drivers/flexram/fsl_flexram.c

0001 /*
0002  * Copyright 2017-2022 NXP
0003  * All rights reserved.
0004  *
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_flexram.h"
0010
0011 /*******************************************************************************
0012  * Definitions
0013  ******************************************************************************/
0014
0015 /* Component ID definition, used by tools. */
0016 #ifndef FSL_COMPONENT_ID
0017 #define FSL_COMPONENT_ID "platform.drivers.flexram"
0018 #endif
0019
0020 /*******************************************************************************
0021  * Prototypes
0022  ******************************************************************************/
0023 /*!
0024  * @brief Gets the instance from the base address to be used to gate or ungate the module clock
0025  *
0026  * @param base FLEXRAM base address
0027  *
0028  * @return The FLEXRAM instance
0029  */
0030 static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
0031
0032 /*******************************************************************************
0033  * Variables
0034  ******************************************************************************/
0035 /*! @brief Pointers to FLEXRAM bases for each instance. */
0036 static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS;
0037
0038 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0039 /*! @brief Pointers to FLEXRAM clocks for each instance. */
0040 static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS;
0041 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0042
0043 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0044 /*! Look-up table to calculate single-bit error bit position for ITCM. */
0045 static const uint8_t ItcmLookUpTable[64] = {
0046     0xC1, 0x43, 0x9E, 0x83, 0x15, 0x4C, 0x4A, 0x8C, 0x31, 0x1C, 0xA2, 0xE0, 0x51, 0x2C, 0xC2, 0xD0,
0047     0x19, 0x1A, 0x26, 0xEA, 0x29, 0x94, 0x16, 0x64, 0x37, 0xA4, 0x0D, 0xC4, 0x75, 0x38, 0x4F, 0x58,
0048     0x46, 0x91, 0x86, 0x61, 0x49, 0x98, 0x89, 0x68, 0x32, 0x34, 0x07, 0xC8, 0x92, 0xA8, 0xA7, 0x54,
0049     0xA1, 0xD9, 0x25, 0xF8, 0x0E, 0x0B, 0x8A, 0x2A, 0x52, 0x45, 0x13, 0x85, 0x62, 0x70, 0x23, 0xB0};
0050 /*! Look-up table to calculate single-bit error bit position for DTCM. */
0051 static const uint8_t DtcmLookUpTable[32] = {0x61, 0x51, 0x19, 0x45, 0x43, 0x31, 0x29, 0x13, 0x62, 0x52, 0x4A,
0052                                             0x46, 0x32, 0x2A, 0x23, 0x1A, 0x2C, 0x64, 0x26, 0x25, 0x34, 0x16,
0053                                             0x15, 0x54, 0x0B, 0x58, 0x1C, 0x4C, 0x38, 0x0E, 0x0D, 0x49};
0054 #endif /* FLEXRAM_ECC_ERROR_DETAILED_INFO */
0055
0056 /*******************************************************************************
0057  * Code
0058  ******************************************************************************/
0059 static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
0060 {
0061     uint32_t instance;
0062
0063     /* Find the instance index from base address mappings. */
0064     for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++)
0065     {
0066         if (s_flexramBases[instance] == base)
0067         {
0068             break;
0069         }
0070     }
0071
0072     assert(instance < ARRAY_SIZE(s_flexramBases));
0073
0074     return instance;
0075 }
0076
0077 /*!
0078  * brief FLEXRAM module initialization function.
0079  *
0080  * param base FLEXRAM base address.
0081  */
0082 void FLEXRAM_Init(FLEXRAM_Type *base)
0083 {
0084 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0085     /* Ungate ENET clock. */
0086     CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
0087 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0088
0089     /* enable all the interrupt status */
0090     base->INT_STAT_EN |= (uint32_t)kFLEXRAM_InterruptStatusAll;
0091     /* clear all the interrupt status */
0092     base->INT_STATUS |= (uint32_t)kFLEXRAM_InterruptStatusAll;
0093     /* disable all the interrpt */
0094     base->INT_SIG_EN = 0U;
0095 }
0096
0097 /*!
0098  * brief Deinitializes the FLEXRAM.
0099  *
0100  */
0101 void FLEXRAM_Deinit(FLEXRAM_Type *base)
0102 {
0103 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0104     /* Ungate ENET clock. */
0105     CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
0106 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0107 }
0108
0109 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
0110 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable)
0111 {
0112     if (true == OcramECCEnable)
0113     {
0114         base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
0115     }
0116     else
0117     {
0118         base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
0119     }
0120
0121     if (true == TcmECCEnable)
0122     {
0123         base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
0124     }
0125     else
0126     {
0127         base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
0128     }
0129 }
0130
0131 void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error)
0132 {
0133     assert(error != NULL);
0134
0135     switch (memory)
0136     {
0137         case kFLEXRAM_OCRAM:
0138             base->OCRAM_ECC_ERROR_INJEC =
0139                 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) |
0140                 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) |
0141                 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) |
0142                 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) |
0143                 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) |
0144                 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion);
0145             break;
0146         case kFLEXRAM_ITCM:
0147             base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) |
0148                                          FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) |
0149                                          FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) |
0150                                          FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) |
0151                                          FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) |
0152                                          FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion);
0153             break;
0154         case kFLEXRAM_D0TCM:
0155             base->D0TCM_ECC_ERROR_INJEC =
0156                 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) |
0157                 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) |
0158                 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) |
0159                 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) |
0160                 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) |
0161                 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion);
0162             break;
0163         case kFLEXRAM_D1TCM:
0164             base->D1TCM_ECC_ERROR_INJEC =
0165                 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) |
0166                 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) |
0167                 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) |
0168                 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) |
0169                 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) |
0170                 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion);
0171             break;
0172         default:
0173             assert(NULL);
0174             break;
0175     }
0176
0177     __DSB();
0178 }
0179
0180 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
0181 {
0182     assert(NULL != info);
0183
0184 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0185     info->OcramSingleErrorECCCipher =
0186         (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) >>
0187                   FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT);
0188     info->OcramSingleErrorECCSyndrome =
0189         (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) >>
0190                   FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT);
0191 #else
0192     info->OcramSingleErrorInfo = base->OCRAM_ECC_SINGLE_ERROR_INFO;
0193 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0194
0195     info->OcramSingleErrorAddr    = base->OCRAM_ECC_SINGLE_ERROR_ADDR;
0196     info->OcramSingleErrorDataLSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_LSB;
0197     info->OcramSingleErrorDataMSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_MSB;
0198 }
0199
0200 void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info)
0201 {
0202     assert(NULL != info);
0203
0204 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0205     info->OcramMultiErrorECCCipher =
0206         (uint8_t)((base->OCRAM_ECC_MULTI_ERROR_INFO & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) >>
0207                   FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT);
0208 #else
0209     info->OcramMultiErrorInfo  = base->OCRAM_ECC_MULTI_ERROR_INFO;
0210 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0211     info->OcramMultiErrorAddr    = base->OCRAM_ECC_MULTI_ERROR_ADDR;
0212     info->OcramMultiErrorDataLSB = base->OCRAM_ECC_MULTI_ERROR_DATA_LSB;
0213     info->OcramMultiErrorDataMSB = base->OCRAM_ECC_MULTI_ERROR_DATA_MSB;
0214 }
0215
0216 void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info)
0217 {
0218     assert(NULL != info);
0219
0220 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0221     /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
0222     uint8_t singleErrorECCSyndrome = 0x00U;
0223
0224     info->ItcmSingleErrorTCMWriteRead =
0225         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
0226                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
0227     info->ItcmSingleErrorTCMAccessSize =
0228         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
0229                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
0230     info->ItcmSingleErrorTCMMaster =
0231         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
0232                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
0233     info->ItcmSingleErrorTCMPrivilege =
0234         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
0235                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
0236     singleErrorECCSyndrome =
0237         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
0238                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
0239
0240     for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
0241     {
0242         if (singleErrorECCSyndrome == ItcmLookUpTable[i])
0243         {
0244             info->ItcmSingleErrorBitPostion = i;
0245             break;
0246         }
0247     }
0248 #else
0249     info->ItcmSingleErrorInfo  = base->ITCM_ECC_SINGLE_ERROR_INFO;
0250 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0251
0252     info->ItcmSingleErrorAddr    = base->ITCM_ECC_SINGLE_ERROR_ADDR;
0253     info->ItcmSingleErrorDataLSB = base->ITCM_ECC_SINGLE_ERROR_DATA_LSB;
0254     info->ItcmSingleErrorDataMSB = base->ITCM_ECC_SINGLE_ERROR_DATA_MSB;
0255 }
0256
0257 void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info)
0258 {
0259     assert(NULL != info);
0260
0261 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0262     info->ItcmMultiErrorTCMWriteRead =
0263         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
0264                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
0265     info->ItcmMultiErrorTCMAccessSize =
0266         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
0267                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
0268     info->ItcmMultiErrorTCMMaster =
0269         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
0270                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
0271     info->ItcmMultiErrorTCMPrivilege =
0272         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
0273                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
0274     info->ItcmMultiErrorECCSyndrome =
0275         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
0276                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
0277 #else
0278     info->ItcmMultiErrorInfo   = base->ITCM_ECC_MULTI_ERROR_INFO;
0279 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0280
0281     info->ItcmMultiErrorAddr    = base->ITCM_ECC_MULTI_ERROR_ADDR;
0282     info->ItcmMultiErrorDataLSB = base->ITCM_ECC_MULTI_ERROR_DATA_LSB;
0283     info->ItcmMultiErrorDataMSB = base->ITCM_ECC_MULTI_ERROR_DATA_MSB;
0284 }
0285
0286 void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank)
0287 {
0288     assert(NULL != info);
0289     assert((0x00U == bank) || (0x01U == bank));
0290
0291     if (0x00U == bank)
0292     {
0293 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0294         /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
0295         uint8_t singleErrorECCSyndrome = 0x00U;
0296
0297         info->DtcmSingleErrorTCMWriteRead =
0298             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
0299                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
0300         info->DtcmSingleErrorTCMAccessSize =
0301             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
0302                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
0303         info->DtcmSingleErrorTCMMaster =
0304             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
0305                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
0306         info->DtcmSingleErrorTCMPrivilege =
0307             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
0308                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
0309         singleErrorECCSyndrome =
0310             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
0311                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
0312
0313         for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
0314         {
0315             if (singleErrorECCSyndrome == ItcmLookUpTable[i])
0316             {
0317                 info->DtcmSingleErrorBitPostion = i;
0318                 break;
0319             }
0320         }
0321 #else
0322         info->DtcmSingleErrorInfo = base->D0TCM_ECC_SINGLE_ERROR_INFO;
0323 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0324
0325         info->DtcmSingleErrorAddr = base->D0TCM_ECC_SINGLE_ERROR_ADDR;
0326         info->DtcmSingleErrorData = base->D0TCM_ECC_SINGLE_ERROR_DATA;
0327     }
0328     else
0329     {
0330 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0331         /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
0332         uint8_t singleErrorECCSyndrome = 0x00U;
0333
0334         info->DtcmSingleErrorTCMWriteRead =
0335             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) >>
0336                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
0337         info->DtcmSingleErrorTCMAccessSize =
0338             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) >>
0339                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
0340         info->DtcmSingleErrorTCMMaster =
0341             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) >>
0342                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
0343         info->DtcmSingleErrorTCMPrivilege =
0344             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) >>
0345                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
0346         singleErrorECCSyndrome =
0347             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) >>
0348                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
0349
0350         for (uint8_t i = 0x00U; i < sizeof(DtcmLookUpTable) / sizeof(DtcmLookUpTable[0]); i++)
0351         {
0352             if (singleErrorECCSyndrome == DtcmLookUpTable[i])
0353             {
0354                 info->DtcmSingleErrorBitPostion = i;
0355                 break;
0356             }
0357         }
0358 #else
0359         info->DtcmSingleErrorInfo = base->D1TCM_ECC_SINGLE_ERROR_INFO;
0360 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0361
0362         info->DtcmSingleErrorAddr = base->D1TCM_ECC_SINGLE_ERROR_ADDR;
0363         info->DtcmSingleErrorData = base->D1TCM_ECC_SINGLE_ERROR_DATA;
0364     }
0365 }
0366
0367 void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank)
0368 {
0369     assert(NULL != info);
0370     assert((0x00U == bank) || (0x01U == bank));
0371
0372     if (0x00U == bank)
0373     {
0374 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0375         info->DtcmMultiErrorTCMWriteRead =
0376             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
0377                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
0378         info->DtcmMultiErrorTCMAccessSize =
0379             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
0380                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
0381         info->DtcmMultiErrorTCMMaster =
0382             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
0383                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
0384         info->DtcmMultiErrorTCMPrivilege =
0385             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
0386                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
0387         info->DtcmMultiErrorECCSyndrome =
0388             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
0389                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
0390 #else
0391         info->DtcmMultiErrorInfo  = base->D0TCM_ECC_MULTI_ERROR_INFO;
0392 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0393
0394         info->DtcmMultiErrorAddr = base->D0TCM_ECC_MULTI_ERROR_ADDR;
0395         info->DtcmMultiErrorData = base->D0TCM_ECC_MULTI_ERROR_DATA;
0396     }
0397     else
0398     {
0399 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0400         info->DtcmMultiErrorTCMWriteRead =
0401             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
0402                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
0403         info->DtcmMultiErrorTCMAccessSize =
0404             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
0405                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
0406         info->DtcmMultiErrorTCMMaster =
0407             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
0408                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
0409         info->DtcmMultiErrorTCMPrivilege =
0410             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
0411                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
0412         info->DtcmMultiErrorECCSyndrome =
0413             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
0414                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
0415 #else
0416         info->DtcmMultiErrorInfo  = base->D1TCM_ECC_MULTI_ERROR_INFO;
0417 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0418
0419         info->DtcmMultiErrorAddr = base->D1TCM_ECC_MULTI_ERROR_ADDR;
0420         info->DtcmMultiErrorData = base->D1TCM_ECC_MULTI_ERROR_DATA;
0421     }
0422 }
0423 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */