drivers/flexio/fsl_flexio_spi.h

0001 /*
0002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2020, 2022 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_FLEXIO_SPI_H_
0010 #define _FSL_FLEXIO_SPI_H_
0011
0012 #include "fsl_common.h"
0013 #include "fsl_flexio.h"
0014
0015 /*!
0016  * @addtogroup flexio_spi
0017  * @{
0018  */
0019
0020 /*******************************************************************************
0021  * Definitions
0022  ******************************************************************************/
0023
0024 /*! @name Driver version */
0025 /*@{*/
0026 /*! @brief FlexIO SPI driver version. */
0027 #define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
0028 /*@}*/
0029
0030 #ifndef FLEXIO_SPI_DUMMYDATA
0031 /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
0032 #define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
0033 #endif
0034
0035 /*! @brief Retry times for waiting flag. */
0036 #ifndef SPI_RETRY_TIMES
0037 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
0038 #endif
0039
0040 /*! @brief Get the transfer data format of width and bit order. */
0041 #define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U))
0042
0043 /*! @brief Error codes for the FlexIO SPI driver. */
0044 enum
0045 {
0046     kStatus_FLEXIO_SPI_Busy  = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
0047     kStatus_FLEXIO_SPI_Idle  = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
0048     kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
0049     kStatus_FLEXIO_SPI_Timeout =
0050         MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 4), /*!< FlexIO SPI timeout polling status flags. */
0051 };
0052
0053 /*! @brief FlexIO SPI clock phase configuration. */
0054 typedef enum _flexio_spi_clock_phase
0055 {
0056     kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U,  /*!< First edge on SPSCK occurs at the middle of the first
0057                                               *   cycle of a data transfer. */
0058     kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
0059                                               *   first cycle of a data transfer. */
0060 } flexio_spi_clock_phase_t;
0061
0062 /*! @brief FlexIO SPI data shifter direction options. */
0063 typedef enum _flexio_spi_shift_direction
0064 {
0065     kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */
0066     kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */
0067 } flexio_spi_shift_direction_t;
0068
0069 /*! @brief FlexIO SPI data length mode options. */
0070 typedef enum _flexio_spi_data_bitcount_mode
0071 {
0072     kFLEXIO_SPI_8BitMode  = 0x08U, /*!< 8-bit data transmission mode. */
0073     kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
0074     kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */
0075 } flexio_spi_data_bitcount_mode_t;
0076
0077 /*! @brief Define FlexIO SPI interrupt mask. */
0078 enum _flexio_spi_interrupt_enable
0079 {
0080     kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
0081     kFLEXIO_SPI_RxFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
0082 };
0083
0084 /*! @brief Define FlexIO SPI status mask. */
0085 enum _flexio_spi_status_flags
0086 {
0087     kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
0088     kFLEXIO_SPI_RxBufferFullFlag  = 0x2U, /*!< Receive buffer full flag. */
0089 };
0090
0091 /*! @brief Define FlexIO SPI DMA mask. */
0092 enum _flexio_spi_dma_enable
0093 {
0094     kFLEXIO_SPI_TxDmaEnable  = 0x1U, /*!< Tx DMA request source */
0095     kFLEXIO_SPI_RxDmaEnable  = 0x2U, /*!< Rx DMA request source */
0096     kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
0097 };
0098
0099 /*! @brief Define FlexIO SPI transfer flags.
0100  *  @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */
0101 enum _flexio_spi_transfer_flags
0102 {
0103     kFLEXIO_SPI_8bitMsb      = 0x0U, /*!< FlexIO SPI 8-bit MSB first */
0104     kFLEXIO_SPI_8bitLsb      = 0x1U, /*!< FlexIO SPI 8-bit LSB first */
0105     kFLEXIO_SPI_16bitMsb     = 0x2U, /*!< FlexIO SPI 16-bit MSB first */
0106     kFLEXIO_SPI_16bitLsb     = 0x3U, /*!< FlexIO SPI 16-bit LSB first */
0107     kFLEXIO_SPI_32bitMsb     = 0x4U, /*!< FlexIO SPI 32-bit MSB first */
0108     kFLEXIO_SPI_32bitLsb     = 0x5U, /*!< FlexIO SPI 32-bit LSB first */
0109     kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */
0110 };
0111
0112 /*! @brief Define FlexIO SPI access structure typedef. */
0113 typedef struct _flexio_spi_type
0114 {
0115     FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
0116     uint8_t SDOPinIndex;     /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as
0117                                 GPIO input and disable all pull up/down in application. */
0118     uint8_t SDIPinIndex;     /*!< Pin select for data input. */
0119     uint8_t SCKPinIndex;     /*!< Pin select for clock. */
0120     uint8_t CSnPinIndex;     /*!< Pin select for enable. */
0121     uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */
0122     uint8_t timerIndex[2];   /*!< Timer index used in FlexIO SPI. */
0123 } FLEXIO_SPI_Type;
0124
0125 /*! @brief Define FlexIO SPI master configuration structure. */
0126 typedef struct _flexio_spi_master_config
0127 {
0128     bool enableMaster;                        /*!< Enable/disable FlexIO SPI master after configuration. */
0129     bool enableInDoze;                        /*!< Enable/disable FlexIO operation in doze mode. */
0130     bool enableInDebug;                       /*!< Enable/disable FlexIO operation in debug mode. */
0131     bool enableFastAccess;                    /*!< Enable/disable fast access to FlexIO registers,
0132                                               fast access requires the FlexIO clock to be at least
0133                                               twice the frequency of the bus clock. */
0134     uint32_t baudRate_Bps;                    /*!< Baud rate in Bps. */
0135     flexio_spi_clock_phase_t phase;           /*!< Clock phase. */
0136     flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
0137 } flexio_spi_master_config_t;
0138
0139 /*! @brief Define FlexIO SPI slave configuration structure. */
0140 typedef struct _flexio_spi_slave_config
0141 {
0142     bool enableSlave;                         /*!< Enable/disable FlexIO SPI slave after configuration. */
0143     bool enableInDoze;                        /*!< Enable/disable FlexIO operation in doze mode. */
0144     bool enableInDebug;                       /*!< Enable/disable FlexIO operation in debug mode. */
0145     bool enableFastAccess;                    /*!< Enable/disable fast access to FlexIO registers,
0146                                               fast access requires the FlexIO clock to be at least
0147                                               twice the frequency of the bus clock. */
0148     flexio_spi_clock_phase_t phase;           /*!< Clock phase. */
0149     flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
0150 } flexio_spi_slave_config_t;
0151
0152 /*! @brief Define FlexIO SPI transfer structure. */
0153 typedef struct _flexio_spi_transfer
0154 {
0155     uint8_t *txData; /*!< Send buffer. */
0156     uint8_t *rxData; /*!< Receive buffer. */
0157     size_t dataSize; /*!< Transfer bytes. */
0158     uint8_t flags;   /*!< FlexIO SPI control flag, MSB first  or LSB first. */
0159 } flexio_spi_transfer_t;
0160
0161 /*! @brief  typedef for flexio_spi_master_handle_t in advance. */
0162 typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t;
0163
0164 /*! @brief  Slave handle is the same with master handle. */
0165 typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t;
0166
0167 /*! @brief FlexIO SPI master callback for finished transmit */
0168 typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base,
0169                                                       flexio_spi_master_handle_t *handle,
0170                                                       status_t status,
0171                                                       void *userData);
0172
0173 /*! @brief FlexIO SPI slave callback for finished transmit */
0174 typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
0175                                                      flexio_spi_slave_handle_t *handle,
0176                                                      status_t status,
0177                                                      void *userData);
0178
0179 /*! @brief Define FlexIO SPI handle structure. */
0180 struct _flexio_spi_master_handle
0181 {
0182     uint8_t *txData;                                /*!< Transfer buffer. */
0183     uint8_t *rxData;                                /*!< Receive buffer. */
0184     size_t transferSize;                            /*!< Total bytes to be transferred. */
0185     volatile size_t txRemainingBytes;               /*!< Send data remaining in bytes. */
0186     volatile size_t rxRemainingBytes;               /*!< Receive data remaining in bytes. */
0187     volatile uint32_t state;                        /*!< FlexIO SPI internal state. */
0188     uint8_t bytePerFrame;                           /*!< SPI mode, 2bytes or 1byte in a frame */
0189     flexio_spi_shift_direction_t direction;         /*!< Shift direction. */
0190     flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */
0191     void *userData;                                 /*!< Callback parameter. */
0192 };
0193
0194 /*******************************************************************************
0195  * API
0196  ******************************************************************************/
0197
0198 #if defined(__cplusplus)
0199 extern "C" {
0200 #endif /*_cplusplus*/
0201
0202 /*!
0203  * @name FlexIO SPI Configuration
0204  * @{
0205  */
0206
0207 /*!
0208  * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
0209  * and configures the FlexIO SPI with FlexIO SPI master configuration. The
0210  * configuration structure can be filled by the user, or be set with default values
0211  * by the FLEXIO_SPI_MasterGetDefaultConfig().
0212  *
0213  * @note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low.
0214  *      2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
0215  *        is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud
0216  *        rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO
0217  *        SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
0218  *
0219  * Example
0220    @code
0221    FLEXIO_SPI_Type spiDev = {
0222    .flexioBase = FLEXIO,
0223    .SDOPinIndex = 0,
0224    .SDIPinIndex = 1,
0225    .SCKPinIndex = 2,
0226    .CSnPinIndex = 3,
0227    .shifterIndex = {0,1},
0228    .timerIndex = {0,1}
0229    };
0230    flexio_spi_master_config_t config = {
0231    .enableMaster = true,
0232    .enableInDoze = false,
0233    .enableInDebug = true,
0234    .enableFastAccess = false,
0235    .baudRate_Bps = 500000,
0236    .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
0237    .direction = kFLEXIO_SPI_MsbFirst,
0238    .dataMode = kFLEXIO_SPI_8BitMode
0239    };
0240    FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
0241    @endcode
0242  *
0243  * @param base Pointer to the FLEXIO_SPI_Type structure.
0244  * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
0245  * @param srcClock_Hz FlexIO source clock in Hz.
0246 */
0247 void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz);
0248
0249 /*!
0250  * @brief Resets the FlexIO SPI timer and shifter config.
0251  *
0252  * @param base Pointer to the FLEXIO_SPI_Type.
0253  */
0254 void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
0255
0256 /*!
0257  * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration
0258  * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
0259  * Example:
0260    @code
0261    flexio_spi_master_config_t masterConfig;
0262    FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
0263    @endcode
0264  * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
0265 */
0266 void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig);
0267
0268 /*!
0269  * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
0270  * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
0271  * configuration structure can be filled by the user, or be set with default values
0272  * by the FLEXIO_SPI_SlaveGetDefaultConfig().
0273  *
0274  * @note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
0275  *      2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
0276  *      3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
0277  *        is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud
0278  *        rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO
0279  *        SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
0280  * Example
0281    @code
0282    FLEXIO_SPI_Type spiDev = {
0283    .flexioBase = FLEXIO,
0284    .SDOPinIndex = 0,
0285    .SDIPinIndex = 1,
0286    .SCKPinIndex = 2,
0287    .CSnPinIndex = 3,
0288    .shifterIndex = {0,1},
0289    .timerIndex = {0}
0290    };
0291    flexio_spi_slave_config_t config = {
0292    .enableSlave = true,
0293    .enableInDoze = false,
0294    .enableInDebug = true,
0295    .enableFastAccess = false,
0296    .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
0297    .direction = kFLEXIO_SPI_MsbFirst,
0298    .dataMode = kFLEXIO_SPI_8BitMode
0299    };
0300    FLEXIO_SPI_SlaveInit(&spiDev, &config);
0301    @endcode
0302  * @param base Pointer to the FLEXIO_SPI_Type structure.
0303  * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
0304 */
0305 void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig);
0306
0307 /*!
0308  * @brief Gates the FlexIO clock.
0309  *
0310  * @param base Pointer to the FLEXIO_SPI_Type.
0311  */
0312 void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
0313
0314 /*!
0315  * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
0316  * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
0317  * Example:
0318    @code
0319    flexio_spi_slave_config_t slaveConfig;
0320    FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
0321    @endcode
0322  * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
0323 */
0324 void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
0325
0326 /*@}*/
0327
0328 /*!
0329  * @name Status
0330  * @{
0331  */
0332
0333 /*!
0334  * @brief Gets FlexIO SPI status flags.
0335  *
0336  * @param base Pointer to the FLEXIO_SPI_Type structure.
0337  * @return status flag; Use the status flag to AND the following flag mask and get the status.
0338  *          @arg kFLEXIO_SPI_TxEmptyFlag
0339  *          @arg kFLEXIO_SPI_RxEmptyFlag
0340  */
0341
0342 uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
0343
0344 /*!
0345  * @brief Clears FlexIO SPI status flags.
0346  *
0347  * @param base Pointer to the FLEXIO_SPI_Type structure.
0348  * @param mask status flag
0349  *      The parameter can be any combination of the following values:
0350  *          @arg kFLEXIO_SPI_TxEmptyFlag
0351  *          @arg kFLEXIO_SPI_RxEmptyFlag
0352  */
0353
0354 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
0355
0356 /*@}*/
0357
0358 /*!
0359  * @name Interrupts
0360  * @{
0361  */
0362
0363 /*!
0364  * @brief Enables the FlexIO SPI interrupt.
0365  *
0366  * This function enables the FlexIO SPI interrupt.
0367  *
0368  * @param base Pointer to the FLEXIO_SPI_Type structure.
0369  * @param mask interrupt source. The parameter can be any combination of the following values:
0370  *        @arg kFLEXIO_SPI_RxFullInterruptEnable
0371  *        @arg kFLEXIO_SPI_TxEmptyInterruptEnable
0372  */
0373 void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
0374
0375 /*!
0376  * @brief Disables the FlexIO SPI interrupt.
0377  *
0378  * This function disables the FlexIO SPI interrupt.
0379  *
0380  * @param base Pointer to the FLEXIO_SPI_Type structure.
0381  * @param mask interrupt source The parameter can be any combination of the following values:
0382  *        @arg kFLEXIO_SPI_RxFullInterruptEnable
0383  *        @arg kFLEXIO_SPI_TxEmptyInterruptEnable
0384  */
0385 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
0386
0387 /*@}*/
0388
0389 /*!
0390  * @name DMA Control
0391  * @{
0392  */
0393
0394 /*!
0395  * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
0396  * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
0397  *
0398  * @param base Pointer to the FLEXIO_SPI_Type structure.
0399  * @param mask SPI DMA source.
0400  * @param enable True means enable DMA, false means disable DMA.
0401  */
0402 void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable);
0403
0404 /*!
0405  * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer.
0406  *
0407  * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
0408  *
0409  * @param base Pointer to the FLEXIO_SPI_Type structure.
0410  * @param direction Shift direction of MSB first or LSB first.
0411  * @return FlexIO SPI transmit data register address.
0412  */
0413 static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base,
0414                                                            flexio_spi_shift_direction_t direction)
0415 {
0416     if (direction == kFLEXIO_SPI_MsbFirst)
0417     {
0418         return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped,
0419                                               base->shifterIndex[0]) +
0420                3U;
0421     }
0422     else
0423     {
0424         return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
0425     }
0426 }
0427
0428 /*!
0429  * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer.
0430  *
0431  * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
0432  *
0433  * @param base Pointer to the FLEXIO_SPI_Type structure.
0434  * @param direction Shift direction of MSB first or LSB first.
0435  * @return FlexIO SPI receive data register address.
0436  */
0437 static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base,
0438                                                            flexio_spi_shift_direction_t direction)
0439 {
0440     if (direction == kFLEXIO_SPI_MsbFirst)
0441     {
0442         return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]);
0443     }
0444     else
0445     {
0446         return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U;
0447     }
0448 }
0449
0450 /*@}*/
0451
0452 /*!
0453  * @name Bus Operations
0454  * @{
0455  */
0456
0457 /*!
0458  * @brief Enables/disables the FlexIO SPI module operation.
0459  *
0460  * @param base Pointer to the FLEXIO_SPI_Type.
0461  * @param enable True to enable, false does not have any effect.
0462  */
0463 static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
0464 {
0465     if (enable)
0466     {
0467         base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
0468     }
0469 }
0470
0471 /*!
0472  * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
0473  *
0474  * @param base Pointer to the FLEXIO_SPI_Type structure.
0475  * @param baudRate_Bps Baud Rate needed in Hz.
0476  * @param srcClockHz SPI source clock frequency in Hz.
0477  */
0478 void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz);
0479
0480 /*!
0481  * @brief Writes one byte of data, which is sent using the MSB method.
0482  *
0483  * @note This is a non-blocking API, which returns directly after the data is put into the
0484  * data register but the data transfer is not finished on the bus. Ensure that
0485  * the TxEmptyFlag is asserted before calling this API.
0486  *
0487  * @param base Pointer to the FLEXIO_SPI_Type structure.
0488  * @param direction Shift direction of MSB first or LSB first.
0489  * @param data 8/16/32 bit data.
0490  */
0491 static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
0492 {
0493     if (direction == kFLEXIO_SPI_MsbFirst)
0494     {
0495         base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
0496     }
0497     else
0498     {
0499         base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data;
0500     }
0501 }
0502
0503 /*!
0504  * @brief Reads 8 bit/16 bit data.
0505  *
0506  * @note This is a non-blocking API, which returns directly after the data is read from the
0507  * data register. Ensure that the RxFullFlag is asserted before calling this API.
0508  *
0509  * @param base Pointer to the FLEXIO_SPI_Type structure.
0510  * @param direction Shift direction of MSB first or LSB first.
0511  * @return 8 bit/16 bit data received.
0512  */
0513 static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
0514 {
0515     if (direction == kFLEXIO_SPI_MsbFirst)
0516     {
0517         return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
0518     }
0519     else
0520     {
0521         return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
0522     }
0523 }
0524
0525 /*!
0526  * @brief Sends a buffer of data bytes.
0527  *
0528  * @note This function blocks using the polling method until all bytes have been sent.
0529  *
0530  * @param base Pointer to the FLEXIO_SPI_Type structure.
0531  * @param direction Shift direction of MSB first or LSB first.
0532  * @param buffer The data bytes to send.
0533  * @param size The number of data bytes to send.
0534  * @retval kStatus_Success Successfully create the handle.
0535  * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
0536  */
0537 status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
0538                                   flexio_spi_shift_direction_t direction,
0539                                   const uint8_t *buffer,
0540                                   size_t size);
0541
0542 /*!
0543  * @brief Receives a buffer of bytes.
0544  *
0545  * @note This function blocks using the polling method until all bytes have been received.
0546  *
0547  * @param base Pointer to the FLEXIO_SPI_Type structure.
0548  * @param direction Shift direction of MSB first or LSB first.
0549  * @param buffer The buffer to store the received bytes.
0550  * @param size The number of data bytes to be received.
0551  * @param direction Shift direction of MSB first or LSB first.
0552  * @retval kStatus_Success Successfully create the handle.
0553  * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
0554  */
0555 status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
0556                                  flexio_spi_shift_direction_t direction,
0557                                  uint8_t *buffer,
0558                                  size_t size);
0559
0560 /*!
0561  * @brief Receives a buffer of bytes.
0562  *
0563  * @note This function blocks via polling until all bytes have been received.
0564  *
0565  * @param base pointer to FLEXIO_SPI_Type structure
0566  * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
0567  * @retval kStatus_Success Successfully create the handle.
0568  * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
0569  */
0570 status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
0571
0572 /*!
0573  * @brief Flush tx/rx shifters.
0574  *
0575  * @param base Pointer to the FLEXIO_SPI_Type structure.
0576  */
0577 void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
0578 /*@}*/
0579
0580 /*Transactional APIs*/
0581
0582 /*!
0583  * @name Transactional
0584  * @{
0585  */
0586
0587 /*!
0588  * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
0589  *
0590  * @param base Pointer to the FLEXIO_SPI_Type structure.
0591  * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
0592  * @param callback The callback function.
0593  * @param userData The parameter of the callback function.
0594  * @retval kStatus_Success Successfully create the handle.
0595  * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
0596  */
0597 status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
0598                                                flexio_spi_master_handle_t *handle,
0599                                                flexio_spi_master_transfer_callback_t callback,
0600                                                void *userData);
0601
0602 /*!
0603  * @brief Master transfer data using IRQ.
0604  *
0605  * This function sends data using IRQ. This is a non-blocking function, which returns
0606  * right away. When all data is sent out/received, the callback function is called.
0607  *
0608  * @param base Pointer to the FLEXIO_SPI_Type structure.
0609  * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
0610  * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
0611  * @retval kStatus_Success Successfully start a transfer.
0612  * @retval kStatus_InvalidArgument Input argument is invalid.
0613  * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
0614  */
0615 status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
0616                                               flexio_spi_master_handle_t *handle,
0617                                               flexio_spi_transfer_t *xfer);
0618
0619 /*!
0620  * @brief Aborts the master data transfer, which used IRQ.
0621  *
0622  * @param base Pointer to the FLEXIO_SPI_Type structure.
0623  * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
0624  */
0625 void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
0626
0627 /*!
0628  * @brief Gets the data transfer status which used IRQ.
0629  *
0630  * @param base Pointer to the FLEXIO_SPI_Type structure.
0631  * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
0632  * @param count Number of bytes transferred so far by the non-blocking transaction.
0633  * @retval kStatus_InvalidArgument count is Invalid.
0634  * @retval kStatus_Success Successfully return the count.
0635  */
0636 status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count);
0637
0638 /*!
0639  * @brief FlexIO SPI master IRQ handler function.
0640  *
0641  * @param spiType Pointer to the FLEXIO_SPI_Type structure.
0642  * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
0643  */
0644 void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle);
0645
0646 /*!
0647  * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
0648  *
0649  * @param base Pointer to the FLEXIO_SPI_Type structure.
0650  * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
0651  * @param callback The callback function.
0652  * @param userData The parameter of the callback function.
0653  * @retval kStatus_Success Successfully create the handle.
0654  * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
0655  */
0656 status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
0657                                               flexio_spi_slave_handle_t *handle,
0658                                               flexio_spi_slave_transfer_callback_t callback,
0659                                               void *userData);
0660
0661 /*!
0662  * @brief Slave transfer data using IRQ.
0663  *
0664  * This function sends data using IRQ. This is a non-blocking function, which returns
0665  * right away. When all data is sent out/received, the callback function is called.
0666  * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
0667  *
0668  * @param base Pointer to the FLEXIO_SPI_Type structure.
0669  * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
0670  * @retval kStatus_Success Successfully start a transfer.
0671  * @retval kStatus_InvalidArgument Input argument is invalid.
0672  * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
0673  */
0674 status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
0675                                              flexio_spi_slave_handle_t *handle,
0676                                              flexio_spi_transfer_t *xfer);
0677
0678 /*!
0679  * @brief Aborts the slave data transfer which used IRQ, share same API with master.
0680  *
0681  * @param base Pointer to the FLEXIO_SPI_Type structure.
0682  * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
0683  */
0684 static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)
0685 {
0686     FLEXIO_SPI_MasterTransferAbort(base, handle);
0687 }
0688 /*!
0689  * @brief Gets the data transfer status which used IRQ, share same API with master.
0690  *
0691  * @param base Pointer to the FLEXIO_SPI_Type structure.
0692  * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
0693  * @param count Number of bytes transferred so far by the non-blocking transaction.
0694  * @retval kStatus_InvalidArgument count is Invalid.
0695  * @retval kStatus_Success Successfully return the count.
0696  */
0697 static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
0698                                                         flexio_spi_slave_handle_t *handle,
0699                                                         size_t *count)
0700 {
0701     return FLEXIO_SPI_MasterTransferGetCount(base, handle, count);
0702 }
0703
0704 /*!
0705  * @brief FlexIO SPI slave IRQ handler function.
0706  *
0707  * @param spiType Pointer to the FLEXIO_SPI_Type structure.
0708  * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
0709  */
0710 void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
0711
0712 /*@}*/
0713
0714 #if defined(__cplusplus)
0715 }
0716 #endif /*_cplusplus*/
0717 /*@}*/
0718
0719 #endif /*_FSL_FLEXIO_SPI_H_*/