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0001 /* 0002 * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. 0003 * Copyright 2016-2022 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 #ifndef _FSL_ENET_H_ 0009 #define _FSL_ENET_H_ 0010 0011 #include "fsl_common.h" 0012 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET 0013 #include "fsl_memory.h" 0014 #endif 0015 /*! 0016 * @addtogroup enet 0017 * @{ 0018 */ 0019 0020 /******************************************************************************* 0021 * Definitions 0022 ******************************************************************************/ 0023 0024 /*! @name Driver version */ 0025 /*@{*/ 0026 /*! @brief Defines the driver version. */ 0027 #define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 6, 3)) 0028 /*@}*/ 0029 0030 /*! @name ENET DESCRIPTOR QUEUE */ 0031 /*@{*/ 0032 /*! @brief Defines the queue number. */ 0033 #ifndef FSL_FEATURE_ENET_QUEUE 0034 #define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */ 0035 #endif 0036 /*@}*/ 0037 0038 /*! @name Control and status region bit masks of the receive buffer descriptor. */ 0039 /*@{*/ 0040 #define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ 0041 #define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ 0042 #define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ 0043 #define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ 0044 #define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ 0045 #define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ 0046 #define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ 0047 #define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ 0048 #define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ 0049 #define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ 0050 #define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ 0051 #define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ 0052 #define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ 0053 /*@}*/ 0054 0055 /*! @name Control and status bit masks of the transmit buffer descriptor. */ 0056 /*@{*/ 0057 #define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ 0058 #define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ 0059 #define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ 0060 #define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ 0061 #define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ 0062 #define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ 0063 /*@}*/ 0064 0065 /* Extended control regions for enhanced buffer descriptors. */ 0066 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0067 /*! @name First extended control region bit masks of the receive buffer descriptor. */ 0068 /*@{*/ 0069 #define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ 0070 #define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ 0071 #define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ 0072 #define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ 0073 #define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ 0074 /*@}*/ 0075 0076 /*! @name Second extended control region bit masks of the receive buffer descriptor. */ 0077 /*@{*/ 0078 #define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ 0079 #define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ 0080 #define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ 0081 #define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ 0082 #define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ 0083 /*@}*/ 0084 0085 /*! @name First extended control region bit masks of the transmit buffer descriptor. */ 0086 /*@{*/ 0087 #define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ 0088 #define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ 0089 #define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ 0090 #define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ 0091 #define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ 0092 #define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ 0093 #define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ 0094 /*@}*/ 0095 0096 /*! @name Second extended control region bit masks of the transmit buffer descriptor. */ 0097 /*@{*/ 0098 #define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ 0099 #define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ 0100 #define ENET_BUFFDESCRIPTOR_TX_PROTOCHECKSUM_MASK 0x1000U /*!< Protocal checksum mask. */ 0101 #define ENET_BUFFDESCRIPTOR_TX_IPCHECKSUM_MASK 0x0800U /*!< IP header checksum flag mask. */ 0102 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0103 #define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U /*!< Use the transmit launch time. */ 0104 #define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U /*!< Frame type mask. */ 0105 #define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U /*!< Frame type shift. */ 0106 #define ENET_BD_FTYPE(n) \ 0107 (((uint32_t)(n) << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK) 0108 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0109 /*@}*/ 0110 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0111 0112 /*! @brief Defines the receive error status flag mask. */ 0113 #define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ 0114 (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ 0115 ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) 0116 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0117 #define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ 0118 (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) 0119 #endif 0120 0121 /*! @name Defines some Ethernet parameters. */ 0122 /*@{*/ 0123 #define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size without VLAN tag. */ 0124 #define ENET_FRAME_VLAN_TAGLEN 4U /*!< Ethernet single VLAN tag size. */ 0125 #define ENET_FRAME_CRC_LEN 4U /*!< CRC size in a frame. */ 0126 #define ENET_FRAME_TX_LEN_LIMITATION(x) \ 0127 ((((x)->RCR & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT) - ENET_FRAME_CRC_LEN) 0128 0129 #define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ 0130 #define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ 0131 #define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) /*!< Maximum PHY address. */ 0132 0133 #if FSL_FEATURE_ENET_QUEUE > 1 0134 #define ENET_TX_INTERRUPT \ 0135 ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt | (uint32_t)kENET_TxFrame1Interrupt | \ 0136 (uint32_t)kENET_TxBuffer1Interrupt | (uint32_t)kENET_TxFrame2Interrupt | \ 0137 (uint32_t)kENET_TxBuffer2Interrupt) /*!< Enet Tx interrupt flag. */ 0138 #define ENET_RX_INTERRUPT \ 0139 ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt | (uint32_t)kENET_RxFrame1Interrupt | \ 0140 (uint32_t)kENET_RxBuffer1Interrupt | (uint32_t)kENET_RxFrame2Interrupt | \ 0141 (uint32_t)kENET_RxBuffer2Interrupt) /*!< Enet Rx interrupt flag. */ 0142 #else 0143 #define ENET_TX_INTERRUPT \ 0144 ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt) /*!< Enet Tx interrupt flag. */ 0145 #define ENET_RX_INTERRUPT \ 0146 ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt) /*!< Enet Rx interrupt flag. */ 0147 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 0148 #define ENET_TS_INTERRUPT \ 0149 ((uint32_t)kENET_TsTimerInterrupt | (uint32_t)kENET_TsAvailInterrupt) /*!< Enet timestamp interrupt flag. */ 0150 #define ENET_ERR_INTERRUPT \ 0151 ((uint32_t)kENET_BabrInterrupt | (uint32_t)kENET_BabtInterrupt | (uint32_t)kENET_EBusERInterrupt | \ 0152 (uint32_t)kENET_LateCollisionInterrupt | (uint32_t)kENET_RetryLimitInterrupt | \ 0153 (uint32_t)kENET_UnderrunInterrupt | (uint32_t)kENET_PayloadRxInterrupt) /*!< Enet error interrupt flag. */ 0154 /*@}*/ 0155 0156 /*! @brief Defines the status return codes for transaction. */ 0157 enum 0158 { 0159 kStatus_ENET_InitMemoryFail = 0160 MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< Init fails since buffer memory is not enough. */ 0161 kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< A frame received but data error happen. */ 0162 kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< Failed to receive a frame. */ 0163 kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< No frame arrive. */ 0164 kStatus_ENET_RxFrameDrop = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Rx frame is dropped since no buffer memory. */ 0165 kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U), /*!< Tx frame over length. */ 0166 kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Tx buffer descriptors are under process. */ 0167 kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 7U), /*!< Transmit frame fail. */ 0168 }; 0169 0170 /*! @brief Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY. */ 0171 typedef enum _enet_mii_mode 0172 { 0173 kENET_MiiMode = 0U, /*!< MII mode for data interface. */ 0174 kENET_RmiiMode = 1U, /*!< RMII mode for data interface. */ 0175 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0176 kENET_RgmiiMode = 2U /*!< RGMII mode for data interface. */ 0177 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0178 } enet_mii_mode_t; 0179 0180 /*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. 0181 * 0182 * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". 0183 */ 0184 typedef enum _enet_mii_speed 0185 { 0186 kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ 0187 kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ 0188 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0189 kENET_MiiSpeed1000M = 2U /*!< Speed 1000M bps. */ 0190 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0191 } enet_mii_speed_t; 0192 0193 /*! @brief Defines the half or full duplex for the MII data interface. */ 0194 typedef enum _enet_mii_duplex 0195 { 0196 kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ 0197 kENET_MiiFullDuplex /*!< Full duplex mode. */ 0198 } enet_mii_duplex_t; 0199 0200 /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ 0201 typedef enum _enet_mii_write 0202 { 0203 kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ 0204 kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ 0205 } enet_mii_write_t; 0206 0207 /*! @brief Defines the read operation for the MII management frame. */ 0208 typedef enum _enet_mii_read 0209 { 0210 kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ 0211 kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ 0212 } enet_mii_read_t; 0213 0214 #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO 0215 /*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ 0216 typedef enum _enet_mii_extend_opcode 0217 { 0218 kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ 0219 kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ 0220 kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ 0221 } enet_mii_extend_opcode; 0222 #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ 0223 0224 /*! @brief Defines a special configuration for ENET MAC controller. 0225 * 0226 * These control flags are provided for special user requirements. 0227 * Normally, these control flags are unused for ENET initialization. 0228 * For special requirements, set the flags to 0229 * macSpecialConfig in the enet_config_t. 0230 * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store 0231 * and forward. FIFO store and forward means that the FIFO read/send is started 0232 * when a complete frame is stored in TX/RX FIFO. If this flag is set, 0233 * configure rxFifoFullThreshold and txFifoWatermark 0234 * in the enet_config_t. 0235 */ 0236 typedef enum _enet_special_control_flag 0237 { 0238 kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ 0239 kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ 0240 kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ 0241 kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ 0242 kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ 0243 kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ 0244 kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ 0245 kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ 0246 kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ 0247 kENET_ControlVLANTagEnable = 0x0200U, /*!< Enable normal VLAN (single vlan tag). */ 0248 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0249 kENET_ControlSVLANEnable = 0x0400U, /*!< Enable S-VLAN. */ 0250 kENET_ControlVLANUseSecondTag = 0x0800U /*!< Enable extracting the second vlan tag for further processing. */ 0251 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0252 } enet_special_control_flag_t; 0253 0254 /*! @brief List of interrupts supported by the peripheral. This 0255 * enumeration uses one-bit encoding to allow a logical OR of multiple 0256 * members. Members usually map to interrupt enable bits in one or more 0257 * peripheral registers. 0258 */ 0259 typedef enum _enet_interrupt_enable 0260 { 0261 kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ 0262 kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ 0263 kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ 0264 kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ 0265 kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ 0266 kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ 0267 kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ 0268 kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ 0269 kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ 0270 kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ 0271 kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ 0272 kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ 0273 kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive error interrupt source */ 0274 kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ 0275 #if FSL_FEATURE_ENET_QUEUE > 1 0276 kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK, /*!< Rx DMA ring2 flush indication. */ 0277 kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK, /*!< Rx DMA ring1 flush indication. */ 0278 kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK, /*!< RX DMA ring0 flush indication. */ 0279 kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK, /*!< Tx frame interrupt for Tx ring/class 2. */ 0280 kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK, /*!< Tx buffer interrupt for Tx ring/class 2. */ 0281 kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK, /*!< Rx frame interrupt for Rx ring/class 2. */ 0282 kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK, /*!< Rx buffer interrupt for Rx ring/class 2. */ 0283 kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK, /*!< Tx frame interrupt for Tx ring/class 1. */ 0284 kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK, /*!< Tx buffer interrupt for Tx ring/class 1. */ 0285 kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK, /*!< Rx frame interrupt for Rx ring/class 1. */ 0286 kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK, /*!< Rx buffer interrupt for Rx ring/class 1. */ 0287 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 0288 kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ 0289 kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ 0290 } enet_interrupt_enable_t; 0291 0292 /*! @brief Defines the common interrupt event for callback use. */ 0293 typedef enum _enet_event 0294 { 0295 kENET_RxEvent, /*!< Receive event. */ 0296 kENET_TxEvent, /*!< Transmit event. */ 0297 kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ 0298 kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ 0299 kENET_TimeStampEvent, /*!< Time stamp event. */ 0300 kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ 0301 } enet_event_t; 0302 0303 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0304 /*! @brief Defines certain idle slope for bandwidth fraction. */ 0305 typedef enum _enet_idle_slope 0306 { 0307 kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ 0308 kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ 0309 kENET_IdleSlope4 = 4U, /*!< The bandwidth fraction is about 0.008. */ 0310 kENET_IdleSlope8 = 8U, /*!< The bandwidth fraction is about 0.02. */ 0311 kENET_IdleSlope16 = 16U, /*!< The bandwidth fraction is about 0.03. */ 0312 kENET_IdleSlope32 = 32U, /*!< The bandwidth fraction is about 0.06. */ 0313 kENET_IdleSlope64 = 64U, /*!< The bandwidth fraction is about 0.11. */ 0314 kENET_IdleSlope128 = 128U, /*!< The bandwidth fraction is about 0.20. */ 0315 kENET_IdleSlope256 = 256U, /*!< The bandwidth fraction is about 0.33. */ 0316 kENET_IdleSlope384 = 384U, /*!< The bandwidth fraction is about 0.43. */ 0317 kENET_IdleSlope512 = 512U, /*!< The bandwidth fraction is about 0.50. */ 0318 kENET_IdleSlope640 = 640U, /*!< The bandwidth fraction is about 0.56. */ 0319 kENET_IdleSlope768 = 768U, /*!< The bandwidth fraction is about 0.60. */ 0320 kENET_IdleSlope896 = 896U, /*!< The bandwidth fraction is about 0.64. */ 0321 kENET_IdleSlope1024 = 1024U, /*!< The bandwidth fraction is about 0.67. */ 0322 kENET_IdleSlope1152 = 1152U, /*!< The bandwidth fraction is about 0.69. */ 0323 kENET_IdleSlope1280 = 1280U, /*!< The bandwidth fraction is about 0.71. */ 0324 kENET_IdleSlope1408 = 1408U, /*!< The bandwidth fraction is about 0.73. */ 0325 kENET_IdleSlope1536 = 1536U /*!< The bandwidth fraction is about 0.75. */ 0326 } enet_idle_slope_t; 0327 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0328 0329 /*! @brief Defines the transmit accelerator configuration. */ 0330 typedef enum _enet_tx_accelerator 0331 { 0332 kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ 0333 kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ 0334 kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ 0335 } enet_tx_accelerator_t; 0336 0337 /*! @brief Defines the receive accelerator configuration. */ 0338 typedef enum _enet_rx_accelerator 0339 { 0340 kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ 0341 kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ 0342 kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ 0343 kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ 0344 kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ 0345 } enet_rx_accelerator_t; 0346 0347 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0348 /*! @brief Defines the ENET PTP message related constant. */ 0349 typedef enum _enet_ptp_event_type 0350 { 0351 kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ 0352 kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ 0353 kENET_PtpEventPort = 319U, /*!< PTP event port number. */ 0354 kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ 0355 } enet_ptp_event_type_t; 0356 0357 /*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ 0358 typedef enum _enet_ptp_timer_channel 0359 { 0360 kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ 0361 kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ 0362 kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ 0363 kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ 0364 } enet_ptp_timer_channel_t; 0365 0366 /*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ 0367 typedef enum _enet_ptp_timer_channel_mode 0368 { 0369 kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ 0370 kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ 0371 kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ 0372 kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ 0373 kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ 0374 kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ 0375 kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ 0376 kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ 0377 kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ 0378 kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ 0379 kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ 0380 kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ 0381 } enet_ptp_timer_channel_mode_t; 0382 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0383 0384 /*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ 0385 typedef struct _enet_rx_bd_struct 0386 { 0387 uint16_t length; /*!< Buffer descriptor data length. */ 0388 uint16_t control; /*!< Buffer descriptor control and status. */ 0389 uint32_t buffer; /*!< Data buffer pointer. */ 0390 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0391 uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ 0392 uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ 0393 uint16_t payloadCheckSum; /*!< Internal payload checksum. */ 0394 uint8_t headerLength; /*!< Header length. */ 0395 uint8_t protocolTyte; /*!< Protocol type. */ 0396 uint16_t reserved0; 0397 uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ 0398 uint32_t timestamp; /*!< Timestamp. */ 0399 uint16_t reserved1; 0400 uint16_t reserved2; 0401 uint16_t reserved3; 0402 uint16_t reserved4; 0403 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0404 } enet_rx_bd_struct_t; 0405 0406 /*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ 0407 typedef struct _enet_tx_bd_struct 0408 { 0409 uint16_t length; /*!< Buffer descriptor data length. */ 0410 uint16_t control; /*!< Buffer descriptor control and status. */ 0411 uint32_t buffer; /*!< Data buffer pointer. */ 0412 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0413 uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ 0414 uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ 0415 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0416 uint16_t txLaunchTimeLow; /*!< Low 16-bits of transmit launch time. */ 0417 uint16_t txLaunchTimeHigh; /*!< High 16-bits of transmit launch time. */ 0418 #else 0419 uint16_t reserved0; 0420 uint16_t reserved1; 0421 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0422 uint16_t reserved2; 0423 uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ 0424 uint32_t timestamp; /*!< Timestamp. */ 0425 uint16_t reserved3; 0426 uint16_t reserved4; 0427 uint16_t reserved5; 0428 uint16_t reserved6; 0429 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0430 } enet_tx_bd_struct_t; 0431 0432 /*! @brief Defines the ENET data error statistics structure. */ 0433 typedef struct _enet_data_error_stats 0434 { 0435 uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ 0436 uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ 0437 uint32_t statsRxFcsErr; /*!< Receive CRC error. */ 0438 uint32_t statsRxOverRunErr; /*!< Receive over run. */ 0439 uint32_t statsRxTruncateErr; /*!< Receive truncate. */ 0440 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0441 uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ 0442 uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ 0443 uint32_t statsRxMacErr; /*!< Receive Mac error. */ 0444 uint32_t statsRxPhyErr; /*!< Receive PHY error. */ 0445 uint32_t statsRxCollisionErr; /*!< Receive collision. */ 0446 uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ 0447 uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ 0448 uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ 0449 uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ 0450 uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ 0451 uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ 0452 uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ 0453 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0454 } enet_data_error_stats_t; 0455 0456 /*! @brief Defines the Rx frame error structure. */ 0457 typedef struct _enet_rx_frame_error 0458 { 0459 bool statsRxTruncateErr : 1; /*!< Receive truncate. */ 0460 bool statsRxOverRunErr : 1; /*!< Receive over run. */ 0461 bool statsRxFcsErr : 1; /*!< Receive CRC error. */ 0462 bool : 1; 0463 bool statsRxAlignErr : 1; /*!< Receive non-octet alignment. */ 0464 bool statsRxLenGreaterErr : 1; /*!< Receive length greater than RCR[MAX_FL]. */ 0465 uint32_t : 19; 0466 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0467 bool statsRxCollisionErr : 1; /*!< Receive collision. */ 0468 bool statsRxPhyErr : 1; /*!< Receive PHY error. */ 0469 uint8_t : 4; 0470 bool statsRxMacErr : 1; /*!< Receive Mac error. */ 0471 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0472 } enet_rx_frame_error_t; 0473 0474 /*! @brief Defines the ENET transfer statistics structure. */ 0475 typedef struct _enet_transfer_stats 0476 { 0477 uint32_t statsRxFrameCount; /*!< Rx frame number. */ 0478 uint32_t statsRxFrameOk; /*!< Good Rx frame number. */ 0479 uint32_t statsRxCrcErr; /*!< Rx frame number with CRC error. */ 0480 uint32_t statsRxAlignErr; /*!< Rx frame number with alignment error. */ 0481 uint32_t statsRxDropInvalidSFD; /*!< Dropped frame number due to invalid SFD. */ 0482 uint32_t statsRxFifoOverflowErr; /*!< Rx FIFO overflow count. */ 0483 uint32_t statsTxFrameCount; /*!< Tx frame number. */ 0484 uint32_t statsTxFrameOk; /*!< Good Tx frame number. */ 0485 uint32_t statsTxCrcAlignErr; /*!< The transmit frame is error. */ 0486 uint32_t statsTxFifoUnderRunErr; /*!< Tx FIFO underrun count. */ 0487 } enet_transfer_stats_t; 0488 0489 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0490 /*! @brief Defines the ENET PTP time stamp structure. */ 0491 typedef struct _enet_ptp_time 0492 { 0493 uint64_t second; /*!< Second. */ 0494 uint32_t nanosecond; /*!< Nanosecond. */ 0495 } enet_ptp_time_t; 0496 0497 /*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ 0498 typedef struct _enet_ptp_time_data 0499 { 0500 uint8_t version; /*!< PTP version. */ 0501 uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ 0502 uint16_t sequenceId; /*!< PTP sequence ID. */ 0503 uint8_t messageType; /*!< PTP message type. */ 0504 enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ 0505 } enet_ptp_time_data_t; 0506 0507 /*! @brief Defines the ENET PTP configuration structure. */ 0508 typedef struct _enet_ptp_config 0509 { 0510 enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ 0511 uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ 0512 } enet_ptp_config_t; 0513 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 0514 0515 /*! @brief Defines the frame info structure. */ 0516 typedef struct enet_frame_info 0517 { 0518 void *context; /*!< User specified data */ 0519 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0520 bool isTsAvail; /*!< Flag indicates timestamp available status */ 0521 enet_ptp_time_t timeStamp; /*!< Timestamp of frame */ 0522 #endif 0523 } enet_frame_info_t; 0524 0525 /*! @brief Defines the ENET transmit dirty addresses ring/queue structure. */ 0526 typedef struct _enet_tx_dirty_ring 0527 { 0528 enet_frame_info_t *txDirtyBase; /*!< Dirty buffer descriptor base address pointer. */ 0529 uint16_t txGenIdx; /*!< tx generate index. */ 0530 uint16_t txConsumIdx; /*!< tx consume index. */ 0531 uint16_t txRingLen; /*!< tx ring length. */ 0532 bool isFull; /*!< tx ring is full flag. */ 0533 } enet_tx_dirty_ring_t; 0534 0535 /*! @brief Defines the ENET Rx memory buffer alloc function pointer. */ 0536 typedef void *(*enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId); 0537 0538 /*! @brief Defines the ENET Rx memory buffer free function pointer. */ 0539 typedef void (*enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId); 0540 0541 /*! @brief Defines the receive buffer descriptor configuration structure. 0542 * 0543 * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. 0544 * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. 0545 * when the data buffers are in cacheable region when cache is enabled, all those size should be 0546 * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. 0547 * 2. The aligned transmit and receive buffer descriptor start address must be at 0548 * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. 0549 * buffer descriptors should be put in non-cacheable region when cache is enabled. 0550 * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. 0551 * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". 0552 * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". 0553 * when the data buffers are in cacheable region when cache is enabled, all those size should be 0554 * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. 0555 */ 0556 typedef struct _enet_buffer_config 0557 { 0558 uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ 0559 uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ 0560 uint16_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ 0561 uint16_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ 0562 volatile enet_rx_bd_struct_t 0563 *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ 0564 volatile enet_tx_bd_struct_t 0565 *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ 0566 uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ 0567 uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ 0568 bool rxMaintainEnable; /*!< Receive buffer cache maintain. */ 0569 bool txMaintainEnable; /*!< Transmit buffer cache maintain. */ 0570 enet_frame_info_t *txFrameInfo; /*!< Transmit frame information start address. */ 0571 } enet_buffer_config_t; 0572 0573 #if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE 0574 /*! @brief Defines the interrupt coalescing configure structure. */ 0575 typedef struct _enet_intcoalesce_config 0576 { 0577 uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ 0578 uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ 0579 uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ 0580 uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ 0581 } enet_intcoalesce_config_t; 0582 #endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ 0583 0584 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 0585 /*! @brief Defines the ENET AVB Configure structure. 0586 * 0587 * This is used for to configure the extended ring 1 and ring 2. 0588 * 1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. 0589 * composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel. 0590 * 0591 * If CMP1,2,3 are not unused, please set them to the same value as CMP0. 0592 * 2. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). 0593 * For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75. 0594 */ 0595 typedef struct _enet_avb_config 0596 { 0597 uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The classification match value for the ring. */ 0598 enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The idle slope for certian bandwidth fraction. */ 0599 } enet_avb_config_t; 0600 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 0601 0602 /* Forward declaration of the handle typedef. */ 0603 typedef struct _enet_handle enet_handle_t; 0604 0605 /*! @brief ENET callback function. */ 0606 typedef void (*enet_callback_t)(ENET_Type *base, 0607 enet_handle_t *handle, 0608 #if FSL_FEATURE_ENET_QUEUE > 1 0609 uint32_t ringId, 0610 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 0611 enet_event_t event, 0612 enet_frame_info_t *frameInfo, 0613 void *userData); 0614 0615 /*! @brief Defines the basic configuration structure for the ENET device. 0616 * 0617 * Note: 0618 * 1. macSpecialConfig is used for a special control configuration, A logical OR of 0619 * "enet_special_control_flag_t". For a special configuration for MAC, 0620 * set this parameter to 0. 0621 * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: 0622 * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. 0623 * 2 - 128 bytes written to TX FIFO .... 0624 * 3 - 192 bytes written to TX FIFO .... 0625 * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... 0626 * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 0627 * or for larger bus access latency 3 or larger due to contention for the system bus. 0628 * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. 0629 * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. 0630 * If the end of the frame is stored in FIFO and the frame size if smaller than the 0631 * txWatermark, the frame is still transmitted. The rule is the 0632 * same for rxFifoFullThreshold in the receive direction. 0633 * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure 0634 * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold 0635 * are set for flow control enabled case. 0636 * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure 0637 * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. 0638 * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator 0639 * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are 0640 * recommended to be used to enable the transmit and receive accelerator. 0641 * After the accelerators are enabled, the store and forward feature should be enabled. 0642 * As a result, kENET_ControlStoreAndFwdDisabled should not be set. 0643 * 7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading. 0644 */ 0645 typedef struct _enet_config 0646 { 0647 uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ 0648 uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ 0649 uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ 0650 enet_mii_mode_t miiMode; /*!< MII mode. */ 0651 enet_mii_speed_t miiSpeed; /*!< MII Speed. */ 0652 enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ 0653 uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ 0654 uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ 0655 uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ 0656 uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, 0657 it makes MAC generate XOFF pause frame. */ 0658 #if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD 0659 uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, 0660 independent of size, that can be accept. If the limit is reached, reception 0661 continues and a pause frame is triggered. */ 0662 #endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ 0663 uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify 0664 the MAC receive ready status. */ 0665 uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO 0666 before a frame transmit start. */ 0667 #if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE 0668 enet_intcoalesce_config_t *intCoalesceCfg; /*!< If the interrupt coalsecence is not required in the ring n(0,1,2), 0669 please set to NULL. */ 0670 #endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ 0671 uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */ 0672 enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback function to alloc memory, must be provided for zero-copy Rx. */ 0673 enet_rx_free_callback_t rxBuffFree; /*!< Callback function to free memory, must be provided for zero-copy Rx. */ 0674 enet_callback_t callback; /*!< General callback function. */ 0675 void *userData; /*!< Callback function parameter.*/ 0676 } enet_config_t; 0677 0678 /*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */ 0679 typedef struct _enet_tx_bd_ring 0680 { 0681 volatile enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */ 0682 uint16_t txGenIdx; /*!< The current available transmit buffer descriptor pointer. */ 0683 uint16_t txConsumIdx; /*!< Transmit consume index. */ 0684 volatile uint16_t txDescUsed; /*!< Transmit descriptor used number. */ 0685 uint16_t txRingLen; /*!< Transmit ring length. */ 0686 } enet_tx_bd_ring_t; 0687 0688 /*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */ 0689 typedef struct _enet_rx_bd_ring 0690 { 0691 volatile enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */ 0692 uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */ 0693 uint16_t rxRingLen; /*!< Receive ring length. */ 0694 } enet_rx_bd_ring_t; 0695 0696 /*! @brief Defines the ENET handler structure. */ 0697 struct _enet_handle 0698 { 0699 enet_rx_bd_ring_t rxBdRing[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer descriptor. */ 0700 enet_tx_bd_ring_t txBdRing[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer descriptor. */ 0701 uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ 0702 uint16_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer size alignment. */ 0703 bool rxMaintainEnable[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer cache maintain. */ 0704 bool txMaintainEnable[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer cache maintain. */ 0705 uint8_t ringNum; /*!< Number of used rings. */ 0706 enet_callback_t callback; /*!< Callback function. */ 0707 void *userData; /*!< Callback function parameter.*/ 0708 enet_tx_dirty_ring_t txDirtyRing[FSL_FEATURE_ENET_QUEUE]; /*!< Ring to store tx frame information.*/ 0709 bool txReclaimEnable[FSL_FEATURE_ENET_QUEUE]; /*!< Tx reclaim enable flag.*/ 0710 enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback function to alloc memory for zero copy Rx. */ 0711 enet_rx_free_callback_t rxBuffFree; /*!< Callback function to free memory for zero copy Rx. */ 0712 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0713 volatile enet_tx_bd_struct_t 0714 *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for error static update. */ 0715 uint64_t msTimerSecond; /*!< The second for Master PTP timer. */ 0716 #endif 0717 uint8_t multicastCount[64]; /*!< Multicast collisions counter */ 0718 #if defined(FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID) && FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID 0719 uint32_t enetClock; /*!< The clock of enet peripheral, to caculate core cycles for PTP timestamp.*/ 0720 uint32_t tsDelayCount; /*!< The count of core cycles for PTP timestamp capture delay.*/ 0721 #endif 0722 }; 0723 0724 typedef struct _enet_buffer_struct 0725 { 0726 void *buffer; /*!< The buffer store the whole or partial frame. */ 0727 uint16_t length; /*!< The byte length of this buffer. */ 0728 } enet_buffer_struct_t; 0729 0730 typedef struct _enet_rx_frame_attribute_struct 0731 { 0732 bool promiscuous; /*!< This frame is received because of promiscuous mode. */ 0733 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0734 uint32_t timestamp; /*!< The nanosecond part timestamp of this Rx frame. */ 0735 #endif 0736 } enet_rx_frame_attribute_t; 0737 0738 typedef struct _enet_rx_frame_struct 0739 { 0740 enet_buffer_struct_t *rxBuffArray; /*!< Rx frame buffer structure. */ 0741 uint16_t totLen; /*!< Rx frame total length. */ 0742 enet_rx_frame_attribute_t rxAttribute; /*!< Rx frame attribute structure. */ 0743 enet_rx_frame_error_t rxFrameError; /*!< Rx frame error. */ 0744 } enet_rx_frame_struct_t; 0745 0746 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0747 typedef struct _enet_tx_config_struct 0748 { 0749 bool intEnable : 1; 0750 bool tsEnable : 1; 0751 bool autoProtocolChecksum : 1; 0752 bool autoIPChecksum : 1; 0753 uint8_t AVBFrameType : 4; /*!< AVB class type. */ 0754 bool tltEnable : 1; /*!< Transmit launch time enable. */ 0755 uint16_t tltLow; /*!< Specifies when frame can be transmitted. */ 0756 uint16_t tltHigh; /*!< Specifies when frame can be transmitted. */ 0757 } enet_tx_config_struct_t; 0758 #endif 0759 0760 typedef struct _enet_tx_frame_struct 0761 { 0762 enet_buffer_struct_t *txBuffArray; /*!< Tx frame buffer structure. */ 0763 uint32_t txBuffNum; /*!< Buffer number of this Tx frame. */ 0764 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 0765 enet_tx_config_struct_t txConfig; /*!< Tx extra configuation. */ 0766 #endif 0767 void *context; /*!< Driver reclaims and gives it in Tx over callback, usually store network packet header. */ 0768 } enet_tx_frame_struct_t; 0769 0770 /*! @brief Define interrupt IRQ handler. */ 0771 #if FSL_FEATURE_ENET_QUEUE > 1 0772 typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); 0773 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 0774 typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); 0775 0776 /*! @brief Pointers to enet clocks for each instance. */ 0777 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) 0778 extern const clock_ip_name_t s_enetClock[]; 0779 #if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE 0780 extern const clock_ip_name_t s_enetExtraClock[]; 0781 #endif 0782 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ 0783 0784 /******************************************************************************* 0785 * API 0786 ******************************************************************************/ 0787 0788 #if defined(__cplusplus) 0789 extern "C" { 0790 #endif 0791 0792 /*! 0793 * @brief Get the ENET instance from peripheral base address. 0794 * 0795 * @param base ENET peripheral base address. 0796 * @return ENET instance. 0797 */ 0798 uint32_t ENET_GetInstance(ENET_Type *base); 0799 0800 /*! 0801 * @name Initialization and De-initialization 0802 * @{ 0803 */ 0804 0805 /*! 0806 * @brief Gets the ENET default configuration structure. 0807 * 0808 * The purpose of this API is to get the default ENET MAC controller 0809 * configure structure for ENET_Init(). User may use the initialized 0810 * structure unchanged in ENET_Init(), or modify some fields of the 0811 * structure before calling ENET_Init(). 0812 * Example: 0813 @code 0814 enet_config_t config; 0815 ENET_GetDefaultConfig(&config); 0816 @endcode 0817 * @param config The ENET mac controller configuration structure pointer. 0818 */ 0819 void ENET_GetDefaultConfig(enet_config_t *config); 0820 0821 /*! 0822 * @brief Initializes the ENET module. 0823 * 0824 * This function initializes the module with the ENET configuration. 0825 * @note ENET has two buffer descriptors legacy buffer descriptors and 0826 * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To 0827 * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor 0828 * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() 0829 * to configure the 1588 feature and related buffers after calling ENET_Up(). 0830 * 0831 * @param base ENET peripheral base address. 0832 * @param handle ENET handler pointer. 0833 * @param config ENET mac configuration structure pointer. 0834 * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig 0835 * can be used directly. It is also possible to verify the Mac configuration using other methods. 0836 * @param bufferConfig ENET buffer configuration structure pointer. 0837 * The buffer configuration should be prepared for ENET Initialization. 0838 * It is the start address of "ringNum" enet_buffer_config structures. 0839 * To support added multi-ring features in some soc and compatible with the previous 0840 * enet driver version. For single ring supported, this bufferConfig is a buffer 0841 * configure structure pointer, for multi-ring supported and used case, this bufferConfig 0842 * pointer should be a buffer configure structure array pointer. 0843 * @param macAddr ENET mac address of Ethernet device. This MAC address should be 0844 * provided. 0845 * @param srcClock_Hz The internal module clock source for MII clock. 0846 * @retval kStatus_Success Succeed to initialize the ethernet driver. 0847 * @retval kStatus_ENET_InitMemoryFail Init fails since buffer memory is not enough. 0848 * 0849 */ 0850 status_t ENET_Up(ENET_Type *base, 0851 enet_handle_t *handle, 0852 const enet_config_t *config, 0853 const enet_buffer_config_t *bufferConfig, 0854 uint8_t *macAddr, 0855 uint32_t srcClock_Hz); 0856 0857 /*! 0858 * @brief Initializes the ENET module. 0859 * 0860 * This function ungates the module clock and initializes it with the ENET configuration. 0861 * @note ENET has two buffer descriptors legacy buffer descriptors and 0862 * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To 0863 * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor 0864 * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() 0865 * to configure the 1588 feature and related buffers after calling ENET_Init(). 0866 * 0867 * @param base ENET peripheral base address. 0868 * @param handle ENET handler pointer. 0869 * @param config ENET mac configuration structure pointer. 0870 * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig 0871 * can be used directly. It is also possible to verify the Mac configuration using other methods. 0872 * @param bufferConfig ENET buffer configuration structure pointer. 0873 * The buffer configuration should be prepared for ENET Initialization. 0874 * It is the start address of "ringNum" enet_buffer_config structures. 0875 * To support added multi-ring features in some soc and compatible with the previous 0876 * enet driver version. For single ring supported, this bufferConfig is a buffer 0877 * configure structure pointer, for multi-ring supported and used case, this bufferConfig 0878 * pointer should be a buffer configure structure array pointer. 0879 * @param macAddr ENET mac address of Ethernet device. This MAC address should be 0880 * provided. 0881 * @param srcClock_Hz The internal module clock source for MII clock. 0882 * @retval kStatus_Success Succeed to initialize the ethernet driver. 0883 * @retval kStatus_ENET_InitMemoryFail Init fails since buffer memory is not enough. 0884 */ 0885 status_t ENET_Init(ENET_Type *base, 0886 enet_handle_t *handle, 0887 const enet_config_t *config, 0888 const enet_buffer_config_t *bufferConfig, 0889 uint8_t *macAddr, 0890 uint32_t srcClock_Hz); 0891 0892 /*! 0893 * @brief Stops the ENET module. 0894 0895 * This function disables the ENET module. 0896 * 0897 * @param base ENET peripheral base address. 0898 */ 0899 void ENET_Down(ENET_Type *base); 0900 0901 /*! 0902 * @brief Deinitializes the ENET module. 0903 0904 * This function gates the module clock, clears ENET interrupts, and disables the ENET module. 0905 * 0906 * @param base ENET peripheral base address. 0907 */ 0908 void ENET_Deinit(ENET_Type *base); 0909 0910 /*! 0911 * @brief Resets the ENET module. 0912 * 0913 * This function restores the ENET module to reset state. 0914 * Note that this function sets all registers to 0915 * reset state. As a result, the ENET module can't work after calling this function. 0916 * 0917 * @param base ENET peripheral base address. 0918 */ 0919 static inline void ENET_Reset(ENET_Type *base) 0920 { 0921 base->ECR |= ENET_ECR_RESET_MASK; 0922 } 0923 0924 /* @} */ 0925 0926 /*! 0927 * @name MII interface operation 0928 * @{ 0929 */ 0930 0931 /*! 0932 * @brief Sets the ENET MII speed and duplex. 0933 * 0934 * This API is provided to dynamically change the speed and dulpex for MAC. 0935 * 0936 * @param base ENET peripheral base address. 0937 * @param speed The speed of the RMII mode. 0938 * @param duplex The duplex of the RMII mode. 0939 */ 0940 void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); 0941 0942 /*! 0943 * @brief Sets the ENET SMI(serial management interface)- MII management interface. 0944 * 0945 * @param base ENET peripheral base address. 0946 * @param srcClock_Hz This is the ENET module clock frequency. See clock distribution. 0947 * @param isPreambleDisabled The preamble disable flag. 0948 * - true Enables the preamble. 0949 * - false Disables the preamble. 0950 */ 0951 void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); 0952 0953 /*! 0954 * @brief Gets the ENET SMI- MII management interface configuration. 0955 * 0956 * This API is used to get the SMI configuration to check whether the MII management 0957 * interface has been set. 0958 * 0959 * @param base ENET peripheral base address. 0960 * @return The SMI setup status true or false. 0961 */ 0962 static inline bool ENET_GetSMI(ENET_Type *base) 0963 { 0964 return (0U != (base->MSCR & 0x7EU)); 0965 } 0966 0967 /*! 0968 * @brief Reads data from the PHY register through an SMI interface. 0969 * 0970 * @param base ENET peripheral base address. 0971 * @return The data read from PHY 0972 */ 0973 static inline uint32_t ENET_ReadSMIData(ENET_Type *base) 0974 { 0975 return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); 0976 } 0977 0978 /*! 0979 * @brief Sends the MDIO IEEE802.3 Clause 22 format write command. 0980 * 0981 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 0982 * For ease of use, encapsulated ENET_MDIOWrite() can be called. For customized requirements, implement 0983 * with combining separated APIs. 0984 * 0985 * @param base ENET peripheral base address. 0986 * @param phyAddr The PHY address. Range from 0 ~ 31. 0987 * @param regAddr The PHY register address. Range from 0 ~ 31. 0988 * @param operation The write operation. 0989 * @param data The data written to PHY. 0990 */ 0991 static inline void ENET_StartSMIWrite( 0992 ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data) 0993 { 0994 base->MMFR = ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | 0995 ENET_MMFR_TA(2U) | data; 0996 } 0997 0998 /*! 0999 * @brief Sends the MDIO IEEE802.3 Clause 22 format read command. 1000 * 1001 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1002 * For ease of use, encapsulated ENET_MDIORead() can be called. For customized requirements, implement 1003 * with combining separated APIs. 1004 * 1005 * @param base ENET peripheral base address. 1006 * @param phyAddr The PHY address. Range from 0 ~ 31. 1007 * @param regAddr The PHY register address. Range from 0 ~ 31. 1008 * @param operation The read operation. 1009 */ 1010 static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_read_t operation) 1011 { 1012 base->MMFR = 1013 ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | ENET_MMFR_TA(2U); 1014 } 1015 1016 /*! 1017 * @brief MDIO write with IEEE802.3 Clause 22 format. 1018 * 1019 * @param base ENET peripheral base address. 1020 * @param phyAddr The PHY address. Range from 0 ~ 31. 1021 * @param regAddr The PHY register. Range from 0 ~ 31. 1022 * @param data The data written to PHY. 1023 * @return kStatus_Success MDIO access succeeds. 1024 * @return kStatus_Timeout MDIO access timeout. 1025 */ 1026 status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data); 1027 1028 /*! 1029 * @brief MDIO read with IEEE802.3 Clause 22 format. 1030 * 1031 * @param base ENET peripheral base address. 1032 * @param phyAddr The PHY address. Range from 0 ~ 31. 1033 * @param regAddr The PHY register. Range from 0 ~ 31. 1034 * @param pData The data read from PHY. 1035 * @return kStatus_Success MDIO access succeeds. 1036 * @return kStatus_Timeout MDIO access timeout. 1037 */ 1038 status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData); 1039 1040 #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO 1041 /*! 1042 * @brief Sends the MDIO IEEE802.3 Clause 45 format write register command. 1043 * 1044 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1045 * For ease of use, encapsulated ENET_MDIOC45Write()/ENET_MDIOC45Read() can be called. For customized 1046 * requirements, implement with combining separated APIs. 1047 * 1048 * @param base ENET peripheral base address. 1049 * @param portAddr The MDIO port address(PHY address). 1050 * @param devAddr The device address. 1051 * @param regAddr The PHY register address. 1052 */ 1053 static inline void ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr) 1054 { 1055 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(portAddr) | 1056 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); 1057 } 1058 1059 /*! 1060 * @brief Sends the MDIO IEEE802.3 Clause 45 format write data command. 1061 * 1062 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1063 * For ease of use, encapsulated ENET_MDIOC45Write() can be called. For customized requirements, implement 1064 * with combining separated APIs. 1065 * 1066 * @param base ENET peripheral base address. 1067 * @param portAddr The MDIO port address(PHY address). 1068 * @param devAddr The device address. 1069 * @param data The data written to PHY. 1070 */ 1071 static inline void ENET_StartExtC45SMIWriteData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t data) 1072 { 1073 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(portAddr) | 1074 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); 1075 } 1076 1077 /*! 1078 * @brief Sends the MDIO IEEE802.3 Clause 45 format read data command. 1079 * 1080 * After calling this function, need to check whether the transmission is over then do next MDIO operation. 1081 * For ease of use, encapsulated ENET_MDIOC45Read() can be called. For customized requirements, implement 1082 * with combining separated APIs. 1083 * 1084 * @param base ENET peripheral base address. 1085 * @param portAddr The MDIO port address(PHY address). 1086 * @param devAddr The device address. 1087 */ 1088 static inline void ENET_StartExtC45SMIReadData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr) 1089 { 1090 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(portAddr) | 1091 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2); 1092 } 1093 1094 /*! 1095 * @brief MDIO write with IEEE802.3 Clause 45 format. 1096 * 1097 * @param base ENET peripheral base address. 1098 * @param portAddr The MDIO port address(PHY address). 1099 * @param devAddr The device address. 1100 * @param regAddr The PHY register address. 1101 * @param data The data written to PHY. 1102 * @return kStatus_Success MDIO access succeeds. 1103 * @return kStatus_Timeout MDIO access timeout. 1104 */ 1105 status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data); 1106 1107 /*! 1108 * @brief MDIO read with IEEE802.3 Clause 45 format. 1109 * 1110 * @param base ENET peripheral base address. 1111 * @param portAddr The MDIO port address(PHY address). 1112 * @param devAddr The device address. 1113 * @param regAddr The PHY register address. 1114 * @param pData The data read from PHY. 1115 * @return kStatus_Success MDIO access succeeds. 1116 * @return kStatus_Timeout MDIO access timeout. 1117 */ 1118 status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData); 1119 #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ 1120 1121 #if ((defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) || \ 1122 (defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY)) 1123 /*! 1124 * @brief Control the usage of the delayed tx/rx RGMII clock. 1125 * 1126 * @param base ENET peripheral base address. 1127 * @param txEnabled Enable or disable to generate the delayed version of RGMII_TXC. 1128 * @param rxEnabled Enable or disable to use the delayed version of RGMII_RXC. 1129 */ 1130 static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled) 1131 { 1132 uint32_t ecrReg = base->ECR; 1133 1134 #if defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY 1135 /* Set for transmit clock delay. */ 1136 if (txEnabled) 1137 { 1138 ecrReg |= ENET_ECR_TXC_DLY_MASK; 1139 } 1140 else 1141 { 1142 ecrReg &= ~ENET_ECR_TXC_DLY_MASK; 1143 } 1144 #endif /* FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY */ 1145 1146 #if defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY 1147 /* Set for receive clock delay. */ 1148 if (rxEnabled) 1149 { 1150 ecrReg |= ENET_ECR_RXC_DLY_MASK; 1151 } 1152 else 1153 { 1154 ecrReg &= ~ENET_ECR_RXC_DLY_MASK; 1155 } 1156 #endif /* FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY */ 1157 base->ECR = ecrReg; 1158 } 1159 #endif 1160 1161 /* @} */ 1162 1163 /*! 1164 * @name MAC Address Filter 1165 * @{ 1166 */ 1167 1168 /*! 1169 * @brief Sets the ENET module Mac address. 1170 * 1171 * @param base ENET peripheral base address. 1172 * @param macAddr The six-byte Mac address pointer. 1173 * The pointer is allocated by application and input into the API. 1174 */ 1175 void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); 1176 1177 /*! 1178 * @brief Gets the ENET module Mac address. 1179 * 1180 * @param base ENET peripheral base address. 1181 * @param macAddr The six-byte Mac address pointer. 1182 * The pointer is allocated by application and input into the API. 1183 */ 1184 void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); 1185 1186 /*! 1187 * @brief Adds the ENET device to a multicast group. 1188 * 1189 * @param base ENET peripheral base address. 1190 * @param address The six-byte multicast group address which is provided by application. 1191 */ 1192 void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); 1193 1194 /*! 1195 * @brief Moves the ENET device from a multicast group. 1196 * 1197 * @param base ENET peripheral base address. 1198 * @param address The six-byte multicast group address which is provided by application. 1199 */ 1200 void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); 1201 1202 /* @} */ 1203 1204 /*! 1205 * @name Other basic operation 1206 * @{ 1207 */ 1208 1209 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1210 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB 1211 /*! 1212 * @brief Sets the ENET AVB feature. 1213 * 1214 * ENET AVB feature configuration, set the Receive classification match and transmit 1215 * bandwidth. This API is called when the AVB feature is required. 1216 * 1217 * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported 1218 * with the Enhanced buffer descriptors. so the AVB configuration should only done with 1219 * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the 1220 * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. 1221 * 1222 * @param base ENET peripheral base address. 1223 * @param handle ENET handler pointer. 1224 * @param config The ENET AVB feature configuration structure. 1225 */ 1226 void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config); 1227 #endif /* FSL_FEATURE_ENET_HAS_AVB */ 1228 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1229 1230 /*! 1231 * @brief Activates frame reception for multiple rings. 1232 * 1233 * This function is to active the enet read process. 1234 * @note This must be called after the MAC configuration and 1235 * state are ready. It must be called after the ENET_Init(). 1236 * This should be called when the frame reception is required. 1237 * 1238 * @param base ENET peripheral base address. 1239 */ 1240 static inline void ENET_ActiveRead(ENET_Type *base) 1241 { 1242 base->RDAR = ENET_RDAR_RDAR_MASK; 1243 #if FSL_FEATURE_ENET_QUEUE > 1 1244 if (FSL_FEATURE_ENET_INSTANCE_QUEUEn(base) > 1) 1245 { 1246 base->RDAR1 = ENET_RDAR1_RDAR_MASK; 1247 base->RDAR2 = ENET_RDAR2_RDAR_MASK; 1248 } 1249 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 1250 } 1251 1252 /*! 1253 * @brief Enables/disables the MAC to enter sleep mode. 1254 * This function is used to set the MAC enter sleep mode. 1255 * When entering sleep mode, the magic frame wakeup interrupt should be enabled 1256 * to wake up MAC from the sleep mode and reset it to normal mode. 1257 * 1258 * @param base ENET peripheral base address. 1259 * @param enable True enable sleep mode, false disable sleep mode. 1260 */ 1261 static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) 1262 { 1263 if (enable) 1264 { 1265 /* When this field is set, MAC enters sleep mode. */ 1266 base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; 1267 } 1268 else 1269 { /* MAC exits sleep mode. */ 1270 base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); 1271 } 1272 } 1273 1274 /*! 1275 * @brief Gets ENET transmit and receive accelerator functions from MAC controller. 1276 * 1277 * @param base ENET peripheral base address. 1278 * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is 1279 * recommended to be used to as the mask to get the exact the accelerator option. 1280 * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is 1281 * recommended to be used to as the mask to get the exact the accelerator option. 1282 */ 1283 static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) 1284 { 1285 assert(txAccelOption != NULL); 1286 assert(txAccelOption != NULL); 1287 1288 *txAccelOption = base->TACC; 1289 *rxAccelOption = base->RACC; 1290 } 1291 1292 /* @} */ 1293 1294 /*! 1295 * @name Interrupts. 1296 * @{ 1297 */ 1298 1299 /*! 1300 * @brief Enables the ENET interrupt. 1301 * 1302 * This function enables the ENET interrupt according to the provided mask. The mask 1303 * is a logical OR of enumeration members. See ::enet_interrupt_enable_t. 1304 * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. 1305 * @code 1306 * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); 1307 * @endcode 1308 * 1309 * @param base ENET peripheral base address. 1310 * @param mask ENET interrupts to enable. This is a logical OR of the 1311 * enumeration ::enet_interrupt_enable_t. 1312 */ 1313 static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) 1314 { 1315 base->EIMR |= mask; 1316 } 1317 1318 /*! 1319 * @brief Disables the ENET interrupt. 1320 * 1321 * This function disables the ENET interrupts according to the provided mask. The mask 1322 * is a logical OR of enumeration members. See ::enet_interrupt_enable_t. 1323 * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. 1324 * @code 1325 * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); 1326 * @endcode 1327 * 1328 * @param base ENET peripheral base address. 1329 * @param mask ENET interrupts to disable. This is a logical OR of the 1330 * enumeration ::enet_interrupt_enable_t. 1331 */ 1332 static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) 1333 { 1334 base->EIMR &= ~mask; 1335 } 1336 1337 /*! 1338 * @brief Gets the ENET interrupt status flag. 1339 * 1340 * @param base ENET peripheral base address. 1341 * @return The event status of the interrupt source. This is the logical OR of members 1342 * of the enumeration ::enet_interrupt_enable_t. 1343 */ 1344 static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) 1345 { 1346 return base->EIR; 1347 } 1348 1349 /*! 1350 * @brief Clears the ENET interrupt events status flag. 1351 * 1352 * This function clears enabled ENET interrupts according to the provided mask. The mask 1353 * is a logical OR of enumeration members. See the ::enet_interrupt_enable_t. 1354 * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. 1355 * @code 1356 * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); 1357 * @endcode 1358 * 1359 * @param base ENET peripheral base address. 1360 * @param mask ENET interrupt source to be cleared. 1361 * This is the logical OR of members of the enumeration ::enet_interrupt_enable_t. 1362 */ 1363 static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) 1364 { 1365 base->EIR = mask; 1366 } 1367 1368 #if FSL_FEATURE_ENET_QUEUE > 1 1369 /*! 1370 * @brief Set the second level Rx IRQ handler 1371 * 1372 * @param base ENET peripheral base address. 1373 * @param ISRHandler The handler to install. 1374 */ 1375 void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler); 1376 1377 /*! 1378 * @brief Set the second level Tx IRQ handler 1379 * 1380 * @param base ENET peripheral base address. 1381 * @param ISRHandler The handler to install. 1382 */ 1383 void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler); 1384 1385 #else 1386 /*! 1387 * @brief Set the second level Rx IRQ handler 1388 * 1389 * @param base ENET peripheral base address. 1390 * @param ISRHandler The handler to install. 1391 */ 1392 void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1393 1394 /*! 1395 * @brief Set the second level Tx IRQ handler 1396 * 1397 * @param base ENET peripheral base address. 1398 * @param ISRHandler The handler to install. 1399 */ 1400 void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1401 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 1402 1403 /*! 1404 * @brief Set the second level Err IRQ handler 1405 * 1406 * @param base ENET peripheral base address. 1407 * @param ISRHandler The handler to install. 1408 */ 1409 void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1410 1411 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1412 /*! 1413 * @brief Set the second level Ts IRQ handler 1414 * 1415 * @param ISRHandler The handler to install. 1416 */ 1417 void ENET_SetTsISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1418 1419 /*! 1420 * @brief Set the second level 1588 Timer IRQ handler 1421 * 1422 * @param ISRHandler The handler to install. 1423 */ 1424 void ENET_Set1588TimerISRHandler(ENET_Type *base, enet_isr_t ISRHandler); 1425 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1426 1427 /* @} */ 1428 1429 /*! 1430 * @name Transactional operation 1431 * @{ 1432 */ 1433 1434 /*! 1435 * @brief Sets the callback function. 1436 * @deprecated Do not use this function. It has been superceded by the config param in @ref ENET_Init. 1437 * This API is provided for the application callback required case when ENET 1438 * interrupt is enabled. This API should be called after calling ENET_Init. 1439 * 1440 * @param handle ENET handler pointer. Should be provided by application. 1441 * @param callback The ENET callback function. 1442 * @param userData The callback function parameter. 1443 */ 1444 void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); 1445 1446 /*! 1447 * @brief Gets the error statistics of a received frame for ENET specified ring. 1448 * 1449 * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). 1450 * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, 1451 * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. 1452 * This is an example. 1453 * @code 1454 * status = ENET_GetRxFrameSize(&g_handle, &length, 0); 1455 * if (status == kStatus_ENET_RxFrameError) 1456 * { 1457 * Comments: Get the error information of the received frame. 1458 * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic, 0); 1459 * Comments: update the receive buffer. 1460 * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); 1461 * } 1462 * @endcode 1463 * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. 1464 * @param eErrorStatic The error statistics structure pointer. 1465 * @param ringId The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1). 1466 */ 1467 void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId); 1468 1469 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1470 /*! 1471 * @brief Gets the ENET transmit frame statistics after the data send for specified ring. 1472 * 1473 * This interface gets the error statistics of the transmit frame. 1474 * Because the error information is reported by the uDMA after the data delivery, this interface 1475 * should be called after the data transmit API. It is recommended to call this function on 1476 * transmit interrupt handler. After calling the ENET_SendFrame, the 1477 * transmit interrupt notifies the transmit completion. 1478 * 1479 * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. 1480 * @param eErrorStatic The error statistics structure pointer. 1481 * @param ringId The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1). 1482 * @return The execute status. 1483 */ 1484 status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId); 1485 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 1486 1487 /*! 1488 * @brief Gets statistical data in transfer. 1489 * 1490 * @param base ENET peripheral base address. 1491 * @param statistics The statistics structure pointer. 1492 */ 1493 void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics); 1494 1495 /*! 1496 * @brief Gets the size of the read frame for specified ring. 1497 * 1498 * This function gets a received frame size from the ENET buffer descriptors. 1499 * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. 1500 * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to receive frame and update the BD 1501 * if the result is not "kStatus_ENET_RxFrameEmpty". 1502 * 1503 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. 1504 * @param length The length of the valid frame received. 1505 * @param ringId The ring index or ring number. 1506 * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. 1507 * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data 1508 * and NULL length to update the receive buffers. 1509 * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame 1510 * should be called with the right data buffer and the captured data length input. 1511 */ 1512 status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId); 1513 1514 /*! 1515 * @brief Reads a frame from the ENET device. 1516 * This function reads a frame (both the data and the length) from the ENET buffer descriptors. 1517 * User can get timestamp through ts pointer if the ts is not NULL. 1518 * @note It doesn't store the timestamp in the receive timestamp queue. 1519 * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. 1520 * This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer 1521 * in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time 1522 * consumption. 1523 * This is an example: 1524 * @code 1525 * uint32_t length; 1526 * enet_handle_t g_handle; 1527 * Comments: Get the received frame size firstly. 1528 * status = ENET_GetRxFrameSize(&g_handle, &length, 0); 1529 * if (length != 0) 1530 * { 1531 * Comments: Allocate memory here with the size of "length" 1532 * uint8_t *data = memory allocate interface; 1533 * if (!data) 1534 * { 1535 * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL); 1536 * Comments: Add the console warning log. 1537 * } 1538 * else 1539 * { 1540 * status = ENET_ReadFrame(ENET, &g_handle, data, length, 0, NULL); 1541 * Comments: Call stack input API to deliver the data to stack 1542 * } 1543 * } 1544 * else if (status == kStatus_ENET_RxFrameError) 1545 * { 1546 * Comments: Update the received buffer when a error frame is received. 1547 * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL); 1548 * } 1549 * @endcode 1550 * @param base ENET peripheral base address. 1551 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. 1552 * @param data The data buffer provided by user to store the frame which memory size should be at least "length". 1553 * @param length The size of the data buffer which is still the length of the received frame. 1554 * @param ringId The ring index or ring number. 1555 * @param ts The timestamp address to store received timestamp. 1556 * @return The execute status, successful or failure. 1557 */ 1558 status_t ENET_ReadFrame( 1559 ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts); 1560 1561 /*! 1562 * @brief Transmits an ENET frame for specified ring. 1563 * @note The CRC is automatically appended to the data. Input the data to send without the CRC. 1564 * This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer 1565 * in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time 1566 * consumption. 1567 * 1568 * 1569 * @param base ENET peripheral base address. 1570 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1571 * @param data The data buffer provided by user to send. 1572 * @param length The length of the data to send. 1573 * @param ringId The ring index or ring number. 1574 * @param tsFlag Timestamp enable flag. 1575 * @param context Used by user to handle some events after transmit over. 1576 * @retval kStatus_Success Send frame succeed. 1577 * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. 1578 * The transmit busy happens when the data send rate is over the MAC capacity. 1579 * The waiting mechanism is recommended to be added after each call return with 1580 * kStatus_ENET_TxFrameBusy. 1581 */ 1582 status_t ENET_SendFrame(ENET_Type *base, 1583 enet_handle_t *handle, 1584 const uint8_t *data, 1585 uint32_t length, 1586 uint8_t ringId, 1587 bool tsFlag, 1588 void *context); 1589 1590 /*! 1591 * @brief Enable or disable tx descriptors reclaim mechanism. 1592 * @note This function must be called when no pending send frame action. 1593 * Set enable if you want to reclaim context or timestamp in interrupt. 1594 * 1595 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1596 * @param isEnable Enable or disable flag. 1597 * @param ringId The ring index or ring number. 1598 * @retval kStatus_Success Succeed to enable/disable Tx reclaim. 1599 * @retval kStatus_Fail Fail to enable/disable Tx reclaim. 1600 */ 1601 status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId); 1602 1603 /*! 1604 * @brief Reclaim tx descriptors. 1605 * This function is used to update the tx descriptor status and 1606 * store the tx timestamp when the 1588 feature is enabled. 1607 * This is called by the transmit interupt IRQ handler after the 1608 * complete of a frame transmission. 1609 * 1610 * @param base ENET peripheral base address. 1611 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1612 * @param ringId The ring index or ring number. 1613 */ 1614 void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId); 1615 1616 /*! 1617 * @brief Get a receive buffer pointer of the ENET device for specified ring. 1618 * @deprecated Do not use this function. It has been superseded by @ref ENET_GetRxFrame. 1619 * 1620 * This function can get the data address which stores frame. Then can analyze these data directly without doing any 1621 * memory copy. When the frame locates in multiple BD buffer, need to repeat calling this function until isLastBuff=true 1622 * (need to store the temp buf pointer everytime call this function). After finishing the analysis of this frame, 1623 * call ENET_ReleaseRxBuffer to release rxbuff memory to DMA. 1624 * This is an example: 1625 * @code 1626 * uint32_t length; 1627 * uint8_t *buf = NULL; 1628 * uint32_t data_len = 0; 1629 * bool isLastBuff = false; 1630 * enet_handle_t g_handle; 1631 * status_t status; 1632 * status = ENET_GetRxFrameSize(&g_handle, &length, 0); 1633 * if (length != 0) 1634 * { 1635 * ENET_GetRxBuffer(EXAMPLE_ENET, &g_handle, &buf, &data_len, 0, &isLastBuff, NULL); 1636 * ENET_ReleaseRxBuffer(EXAMPLE_ENET, &g_handle, buf, 0); 1637 * } 1638 * @endcode 1639 * @param base ENET peripheral base address. 1640 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. 1641 * @param buffer The data buffer pointer to store the frame. 1642 * @param length The size of the data buffer. If isLastBuff=false, it represents data length of this buffer. If 1643 * isLastBuff=true, it represents data length of total frame. 1644 * @param ringId The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1). 1645 * @param isLastBuff The flag represents whether this buffer is the last buffer to store frame. 1646 * @param ts The 1588 timestamp value, vaild in last buffer. 1647 * @retval kStatus_Success Get receive buffer succeed. 1648 * @retval kStatus_ENET_RxFrameFail Get receive buffer fails, it's owned by application, should wait app to release this 1649 * buffer. 1650 */ 1651 status_t ENET_GetRxBuffer(ENET_Type *base, 1652 enet_handle_t *handle, 1653 void **buffer, 1654 uint32_t *length, 1655 uint8_t ringId, 1656 bool *isLastBuff, 1657 uint32_t *ts); 1658 1659 /*! 1660 * @brief Release receive buffer descriptor to DMA. 1661 * @deprecated Do not use this function. It has been superseded by @ref ENET_GetRxFrame. 1662 * 1663 * This function can release specified BD owned by application, meanwhile it may rearrange the BD to let the no-owned 1664 * BDs always in back of the index of DMA transfer. So for the situation that releasing order is not same as the getting 1665 * order, the rearrangement makes all ready BDs can be used by DMA. 1666 * @note This function can't be interrupted by ENET_GetRxBuffer, so in application must make sure ENET_GetRxBuffer is 1667 * called before or after this function. And this function itself isn't thread safe due to BD content exchanging. 1668 * 1669 * @param base ENET peripheral base address. 1670 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. 1671 * @param buffer The buffer address to store frame, using it to find the correspond BD and release it. 1672 * @param ringId The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1). 1673 */ 1674 void ENET_ReleaseRxBuffer(ENET_Type *base, enet_handle_t *handle, void *buffer, uint8_t ringId); 1675 1676 /*! 1677 * @brief Receives one frame in specified BD ring with zero copy. 1678 * 1679 * This function will use the user-defined allocate and free callback. Every time application gets one frame through 1680 * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application. 1681 * @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating 1682 * fails. Application must provide a memory pool including at least BD number + 1 buffers to make this function work 1683 * normally. If user calls this function in Rx interrupt handler, be careful that this function makes Rx BD ready with 1684 * allocating new buffer(normal) or updating current BD(out of memory). If there's always new Rx frame input, Rx 1685 * interrupt will be triggered forever. Application need to disable Rx interrupt according to specific design in this 1686 * case. 1687 * 1688 * @param base ENET peripheral base address. 1689 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1690 * @param rxFrame The received frame information structure provided by user. 1691 * @param ringId The ring index or ring number. 1692 * @retval kStatus_Success Succeed to get one frame and allocate new memory for Rx buffer. 1693 * @retval kStatus_ENET_RxFrameEmpty There's no Rx frame in the BD. 1694 * @retval kStatus_ENET_RxFrameError There's issue in this receiving. 1695 * @retval kStatus_ENET_RxFrameDrop There's no new buffer memory for BD, drop this frame. 1696 */ 1697 status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId); 1698 1699 /*! 1700 * @brief Sends one frame in specified BD ring with zero copy. 1701 * 1702 * This function supports scattered buffer transmit, user needs to provide the buffer array. 1703 * @note Tx reclaim should be enabled to ensure the Tx buffer ownership can be given back to 1704 * application after Tx is over. 1705 * 1706 * @param base ENET peripheral base address. 1707 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1708 * @param txFrame The Tx frame structure. 1709 * @param ringId The ring index or ring number. 1710 * @retval kStatus_Success Succeed to send one frame. 1711 * @retval kStatus_ENET_TxFrameBusy The BD is not ready for Tx or the reclaim operation still not finishs. 1712 * @retval kStatus_ENET_TxFrameOverLen The Tx frame length is over max ethernet frame length. 1713 */ 1714 status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId); 1715 1716 /*! 1717 * @brief Transmits an ENET frame for specified ring with zero-copy. 1718 * @deprecated Do not use this function. It has been superseded by @ref ENET_StartTxFrame. 1719 * @note The CRC is automatically appended to the data. Input the data 1720 * to send without the CRC. The frame must store in continuous memory 1721 * and need to check the buffer start address alignment based on your 1722 * device, otherwise it has issue or can't get highest DMA transmit speed. 1723 * 1724 * 1725 * @param base ENET peripheral base address. 1726 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. 1727 * @param data The data buffer provided by user to send. 1728 * @param length The length of the data to send. 1729 * @param ringId The ring index or ring number. 1730 * @param tsFlag Timestamp enable flag. 1731 * @param context Used by user to handle some events after transmit over. 1732 * @retval kStatus_Success Send frame succeed. 1733 * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. 1734 * The transmit busy happens when the data send rate is over the MAC capacity. 1735 * The waiting mechanism is recommended to be added after each call return with 1736 * kStatus_ENET_TxFrameBusy. 1737 */ 1738 status_t ENET_SendFrameZeroCopy(ENET_Type *base, 1739 enet_handle_t *handle, 1740 const uint8_t *data, 1741 uint32_t length, 1742 uint8_t ringId, 1743 bool tsFlag, 1744 void *context); 1745 1746 #if FSL_FEATURE_ENET_QUEUE > 1 1747 /*! 1748 * @brief The transmit IRQ handler. 1749 * 1750 * @param base ENET peripheral base address. 1751 * @param handle The ENET handler pointer. 1752 * @param ringId The ring id or ring number. 1753 */ 1754 void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); 1755 1756 /*! 1757 * @brief The receive IRQ handler. 1758 * 1759 * @param base ENET peripheral base address. 1760 * @param handle The ENET handler pointer. 1761 * @param ringId The ring id or ring number. 1762 */ 1763 void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); 1764 1765 /*! 1766 * @brief the common IRQ handler for the tx/rx irq handler. 1767 * 1768 * This is used for the combined tx/rx interrupt for multi-ring (frame 1). 1769 * 1770 * @param base ENET peripheral base address. 1771 */ 1772 void ENET_CommonFrame1IRQHandler(ENET_Type *base); 1773 1774 /*! 1775 * @brief the common IRQ handler for the tx/rx irq handler. 1776 * 1777 * This is used for the combined tx/rx interrupt for multi-ring (frame 2). 1778 * 1779 * @param base ENET peripheral base address. 1780 */ 1781 void ENET_CommonFrame2IRQHandler(ENET_Type *base); 1782 #else 1783 /*! 1784 * @brief The transmit IRQ handler. 1785 * 1786 * @param base ENET peripheral base address. 1787 * @param handle The ENET handler pointer. 1788 */ 1789 void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); 1790 1791 /*! 1792 * @brief The receive IRQ handler. 1793 * 1794 * @param base ENET peripheral base address. 1795 * @param handle The ENET handler pointer. 1796 */ 1797 void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); 1798 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */ 1799 1800 /*! 1801 * @brief Some special IRQ handler including the error, mii, wakeup irq handler. 1802 * 1803 * @param base ENET peripheral base address. 1804 * @param handle The ENET handler pointer. 1805 */ 1806 void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); 1807 1808 /*! 1809 * @brief the common IRQ handler for the 1588 irq handler. 1810 * 1811 * This is used for the 1588 timer interrupt. 1812 * 1813 * @param base ENET peripheral base address. 1814 */ 1815 void ENET_Ptp1588IRQHandler(ENET_Type *base); 1816 1817 /*! 1818 * @brief the common IRQ handler for the tx/rx/error etc irq handler. 1819 * 1820 * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). 1821 * 1822 * @param base ENET peripheral base address. 1823 */ 1824 void ENET_CommonFrame0IRQHandler(ENET_Type *base); 1825 /* @} */ 1826 1827 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE 1828 /*! 1829 * @name ENET PTP 1588 function operation 1830 * @{ 1831 */ 1832 void ENET_Ptp1588ConfigureHandler(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); 1833 1834 /*! 1835 * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. 1836 * The function sets the clock for PTP 1588 timer and enables 1837 * time stamp interrupts and transmit interrupts for PTP 1588 features. 1838 * This API should be called when the 1588 feature is enabled 1839 * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. 1840 * ENET_Init should be called before calling this API. 1841 * 1842 * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler 1843 * and the transmit time-stamp store is done through transmit interrupt handler. 1844 * As a result, the TS interrupt and TX interrupt are enabled when you call this API. 1845 * 1846 * @param base ENET peripheral base address. 1847 * @param handle ENET handler pointer. 1848 * @param ptpConfig The ENET PTP1588 configuration. 1849 */ 1850 void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); 1851 1852 /*! 1853 * @brief Starts the ENET PTP 1588 Timer. 1854 * This function is used to initialize the PTP timer. After the PTP starts, 1855 * the PTP timer starts running. 1856 * 1857 * @param base ENET peripheral base address. 1858 * @param ptpClkSrc The clock source of the PTP timer. 1859 */ 1860 void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); 1861 1862 /*! 1863 * @brief Stops the ENET PTP 1588 Timer. 1864 * This function is used to stops the ENET PTP timer. 1865 * 1866 * @param base ENET peripheral base address. 1867 */ 1868 static inline void ENET_Ptp1588StopTimer(ENET_Type *base) 1869 { 1870 /* Disable PTP timer and reset the timer. */ 1871 base->ATCR &= ~ENET_ATCR_EN_MASK; 1872 base->ATCR |= ENET_ATCR_RESTART_MASK; 1873 } 1874 1875 /*! 1876 * @brief Adjusts the ENET PTP 1588 timer. 1877 * 1878 * @param base ENET peripheral base address. 1879 * @param corrIncrease The correction increment value. This value is added every time the correction 1880 * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, 1881 * a value greater than the 1/ptpClkSrc speeds up the timer. 1882 * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how 1883 * many timer clock the correction counter should be reset and trigger a correction 1884 * increment on the timer. A value of 0 disables the correction counter and no correction occurs. 1885 */ 1886 void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); 1887 1888 /*! 1889 * @brief Sets the ENET PTP 1588 timer channel mode. 1890 * 1891 * @param base ENET peripheral base address. 1892 * @param channel The ENET PTP timer channel number. 1893 * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". 1894 * @param intEnable Enables or disables the interrupt. 1895 */ 1896 static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, 1897 enet_ptp_timer_channel_t channel, 1898 enet_ptp_timer_channel_mode_t mode, 1899 bool intEnable) 1900 { 1901 uint32_t tcrReg = 0; 1902 1903 tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0U); 1904 1905 /* Disable channel mode first. */ 1906 base->CHANNEL[channel].TCSR = 0; 1907 base->CHANNEL[channel].TCSR = tcrReg; 1908 } 1909 1910 #if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL 1911 /*! 1912 * @brief Sets ENET PTP 1588 timer channel mode pulse width. 1913 * 1914 * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare 1915 * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. 1916 * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. 1917 * so call this function if you need to set the timer channel mode for 1918 * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare 1919 * with pulse width more than one 1588 clock, 1920 * 1921 * @param base ENET peripheral base address. 1922 * @param channel The ENET PTP timer channel number. 1923 * @param isOutputLow True --- timer channel is configured for output compare 1924 * pulse output low. 1925 * false --- timer channel is configured for output compare 1926 * pulse output high. 1927 * @param pulseWidth The pulse width control value, range from 0 ~ 31. 1928 * 0 --- pulse width is one 1588 clock cycle. 1929 * 31 --- pulse width is thirty two 1588 clock cycles. 1930 * @param intEnable Enables or disables the interrupt. 1931 */ 1932 static inline void ENET_Ptp1588SetChannelOutputPulseWidth( 1933 ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable) 1934 { 1935 uint32_t tcrReg; 1936 1937 tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); 1938 1939 if (isOutputLow) 1940 { 1941 tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); 1942 } 1943 else 1944 { 1945 tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); 1946 } 1947 1948 /* Disable channel mode first. */ 1949 base->CHANNEL[channel].TCSR = 0; 1950 base->CHANNEL[channel].TCSR = tcrReg; 1951 } 1952 #endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ 1953 1954 /*! 1955 * @brief Sets the ENET PTP 1588 timer channel comparison value. 1956 * 1957 * @param base ENET peripheral base address. 1958 * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". 1959 * @param cmpValue The compare value for the compare setting. 1960 */ 1961 static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) 1962 { 1963 base->CHANNEL[channel].TCCR = cmpValue; 1964 } 1965 1966 /*! 1967 * @brief Gets the ENET PTP 1588 timer channel status. 1968 * 1969 * @param base ENET peripheral base address. 1970 * @param channel The IEEE 1588 timer channel number. 1971 * @return True or false, Compare or capture operation status 1972 */ 1973 static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) 1974 { 1975 return (0U != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); 1976 } 1977 1978 /*! 1979 * @brief Clears the ENET PTP 1588 timer channel status. 1980 * 1981 * @param base ENET peripheral base address. 1982 * @param channel The IEEE 1588 timer channel number. 1983 */ 1984 static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) 1985 { 1986 base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; 1987 base->TGSR = (1UL << (uint32_t)channel); 1988 } 1989 1990 /*! 1991 * @brief Get the ENET PTP 1588 timer global status. 1992 * 1993 * @param base ENET peripheral base address. 1994 */ 1995 static inline uint32_t ENET_Ptp1588GetGlobalStatus(ENET_Type *base) 1996 { 1997 return base->TGSR; 1998 } 1999 2000 /*! 2001 * @brief Gets the current ENET time from the PTP 1588 timer. 2002 * A variant of ENET_Ptp1588GetTimer() which does not disable interrupts. 2003 * 2004 * @param base ENET peripheral base address. 2005 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 2006 * @param ptpTime The PTP timer structure. 2007 */ 2008 void ENET_Ptp1588GetTimerNoIrqDisable(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); 2009 2010 /*! 2011 * @brief Gets the current ENET time from the PTP 1588 timer. 2012 * 2013 * @param base ENET peripheral base address. 2014 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 2015 * @param ptpTime The PTP timer structure. 2016 */ 2017 void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); 2018 2019 /*! 2020 * @brief Sets the ENET PTP 1588 timer to the assigned time. 2021 * 2022 * @param base ENET peripheral base address. 2023 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 2024 * @param ptpTime The timer to be set to the PTP timer. 2025 */ 2026 void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); 2027 2028 /*! 2029 * @brief The IEEE 1588 PTP time stamp interrupt handler. 2030 * 2031 * @param base ENET peripheral base address. 2032 * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. 2033 */ 2034 void ENET_TimeStampIRQHandler(ENET_Type *base, enet_handle_t *handle); 2035 2036 /* @} */ 2037 2038 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ 2039 2040 #if defined(__cplusplus) 2041 } 2042 #endif 2043 2044 /*! @}*/ 2045 2046 #endif /* _FSL_ENET_H_ */
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