drivers/dmamux/fsl_dmamux.h

0001 /*
0002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2017 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_DMAMUX_H_
0010 #define _FSL_DMAMUX_H_
0011
0012 #include "fsl_common.h"
0013
0014 /*!
0015  * @addtogroup dmamux
0016  * @{
0017  */
0018
0019 /*******************************************************************************
0020  * Definitions
0021  ******************************************************************************/
0022
0023 /*! @name Driver version */
0024 /*@{*/
0025 /*! @brief DMAMUX driver version 2.0.5. */
0026 #define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
0027 /*@}*/
0028
0029 /*******************************************************************************
0030  * API
0031  ******************************************************************************/
0032
0033 #if defined(__cplusplus)
0034 extern "C" {
0035 #endif /* __cplusplus */
0036
0037 /*!
0038  * @name DMAMUX Initialization and de-initialization
0039  * @{
0040  */
0041
0042 /*!
0043  * @brief Initializes the DMAMUX peripheral.
0044  *
0045  * This function ungates the DMAMUX clock.
0046  *
0047  * @param base DMAMUX peripheral base address.
0048  *
0049  */
0050 void DMAMUX_Init(DMAMUX_Type *base);
0051
0052 /*!
0053  * @brief Deinitializes the DMAMUX peripheral.
0054  *
0055  * This function gates the DMAMUX clock.
0056  *
0057  * @param base DMAMUX peripheral base address.
0058  */
0059 void DMAMUX_Deinit(DMAMUX_Type *base);
0060
0061 /* @} */
0062 /*!
0063  * @name DMAMUX Channel Operation
0064  * @{
0065  */
0066
0067 /*!
0068  * @brief Enables the DMAMUX channel.
0069  *
0070  * This function enables the DMAMUX channel.
0071  *
0072  * @param base DMAMUX peripheral base address.
0073  * @param channel DMAMUX channel number.
0074  */
0075 static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
0076 {
0077     assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
0078
0079     base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
0080 }
0081
0082 /*!
0083  * @brief Disables the DMAMUX channel.
0084  *
0085  * This function disables the DMAMUX channel.
0086  *
0087  * @note The user must disable the DMAMUX channel before configuring it.
0088  * @param base DMAMUX peripheral base address.
0089  * @param channel DMAMUX channel number.
0090  */
0091 static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
0092 {
0093     assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
0094
0095 #if defined FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH && (FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH == 32U)
0096     base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
0097 #else
0098     base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK;
0099 #endif
0100 }
0101
0102 /*!
0103  * @brief Configures the DMAMUX channel source.
0104  *
0105  * @param base DMAMUX peripheral base address.
0106  * @param channel DMAMUX channel number.
0107  * @param source Channel source, which is used to trigger the DMA transfer.
0108  */
0109 static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
0110 {
0111     assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
0112
0113 #if defined FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH && (FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH == 32U)
0114     base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
0115 #else
0116     base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
0117 #endif
0118 }
0119
0120 #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
0121 /*!
0122  * @brief Enables the DMAMUX period trigger.
0123  *
0124  * This function enables the DMAMUX period trigger feature.
0125  *
0126  * @param base DMAMUX peripheral base address.
0127  * @param channel DMAMUX channel number.
0128  */
0129 static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
0130 {
0131     assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
0132
0133     base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
0134 }
0135
0136 /*!
0137  * @brief Disables the DMAMUX period trigger.
0138  *
0139  * This function disables the DMAMUX period trigger.
0140  *
0141  * @param base DMAMUX peripheral base address.
0142  * @param channel DMAMUX channel number.
0143  */
0144 static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
0145 {
0146     assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
0147
0148 #if defined FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH && (FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH == 32U)
0149     base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
0150 #else
0151     base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK;
0152 #endif
0153 }
0154 #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
0155
0156 #if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
0157 /*!
0158  * @brief Enables the DMA channel to be always ON.
0159  *
0160  * This function enables the DMAMUX channel always ON feature.
0161  *
0162  * @param base DMAMUX peripheral base address.
0163  * @param channel DMAMUX channel number.
0164  * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
0165  */
0166 static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
0167 {
0168     assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
0169
0170     if (enable)
0171     {
0172         base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
0173     }
0174     else
0175     {
0176         base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
0177     }
0178 }
0179 #endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
0180
0181 /* @} */
0182
0183 #if defined(__cplusplus)
0184 }
0185 #endif /* __cplusplus */
0186
0187 /* @} */
0188
0189 #endif /* _FSL_DMAMUX_H_ */