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File indexing completed on 2025-05-11 08:22:58

0001 /*
0002  * Copyright 2020-2022 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007 
0008 #ifndef _FSL_DCIC_H_
0009 #define _FSL_DCIC_H_
0010 
0011 #include "fsl_common.h"
0012 
0013 /*!
0014  * @addtogroup DCIC
0015  * @{
0016  */
0017 
0018 /*******************************************************************************
0019  * Definitions
0020  ******************************************************************************/
0021 #ifndef DCIC_REGION_COUNT
0022 #define DCIC_REGION_COUNT DCIC_DCICRCS_COUNT
0023 #endif
0024 
0025 /*! @brief DCIC driver version. */
0026 #define FSL_DCIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
0027 
0028 /*! @brief CRC32 calculation polynomial. */
0029 #define DCIC_CRC32_POLYNOMIAL 0x04C11DB7UL
0030 
0031 /*! @brief CRC32 calculation initialize value. */
0032 #define DCIC_CRC32_INIT_VALUE 0UL
0033 
0034 /*! @brief ROI CRC32 value mismatch status. */
0035 #define DCIC_REGION_MISMATCH_STATUS(region) (1UL << (DCIC_DCICS_ROI_MATCH_STAT_SHIFT + (region)))
0036 
0037 /*!
0038  * @brief DCIC display signal polarity flags
0039  * @anchor _DCIC_polarity_flags
0040  */
0041 enum _DCIC_polarity_flags
0042 {
0043     kDCIC_VsyncActiveHigh           = 0U, /*!< VSYNC active high. */
0044     kDCIC_HsyncActiveHigh           = 0U, /*!< HSYNC active high. */
0045     kDCIC_DataEnableActiveHigh      = 0U, /*!< Data enable line active high. */
0046     kDCIC_DriveDataOnFallingClkEdge = 0U, /*!< Output data on rising clock edge, capture data
0047                                               on falling clock edge. */
0048 
0049     kDCIC_VsyncActiveLow           = DCIC_DCICC_VSYNC_POL_MASK, /*!< VSYNC active low. */
0050     kDCIC_HsyncActiveLow           = DCIC_DCICC_HSYNC_POL_MASK, /*!< HSYNC active low. */
0051     kDCIC_DataEnableActiveLow      = DCIC_DCICC_DE_POL_MASK,    /*!< Data enable line active low. */
0052     kDCIC_DriveDataOnRisingClkEdge = DCIC_DCICC_CLK_POL_MASK,   /*!< Output data on falling clock edge, capture data
0053                                                                     on rising clock edge. */
0054 };
0055 
0056 /*!
0057  * @brief Status flags.
0058  * @anchor _DCIC_status_flags
0059  */
0060 enum _DCIC_status_flags
0061 {
0062     kDCIC_FunctionalInterruptStatus = DCIC_DCICS_FI_STAT_MASK, /*!< Asserted when match results ready. */
0063     kDCIC_ErrorInterruptStatus      = DCIC_DCICS_EI_STAT_MASK, /*!< Asserted when there is a signature mismatch. */
0064     kDCIC_Region0MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(0U),  /*!< Region 0  CRC32 value mismatch. */
0065     kDCIC_Region1MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(1U),  /*!< Region 1  CRC32 value mismatch. */
0066     kDCIC_Region2MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(2U),  /*!< Region 2  CRC32 value mismatch. */
0067     kDCIC_Region3MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(3U),  /*!< Region 3  CRC32 value mismatch. */
0068     kDCIC_Region4MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(4U),  /*!< Region 4  CRC32 value mismatch. */
0069     kDCIC_Region5MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(5U),  /*!< Region 5  CRC32 value mismatch. */
0070     kDCIC_Region6MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(6U),  /*!< Region 6  CRC32 value mismatch. */
0071     kDCIC_Region7MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(7U),  /*!< Region 7  CRC32 value mismatch. */
0072     kDCIC_Region8MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(8U),  /*!< Region 8  CRC32 value mismatch. */
0073     kDCIC_Region9MismatchStatus     = DCIC_REGION_MISMATCH_STATUS(9U),  /*!< Region 9  CRC32 value mismatch. */
0074     kDCIC_Region10MismatchStatus    = DCIC_REGION_MISMATCH_STATUS(10U), /*!< Region 10 CRC32 value mismatch. */
0075     kDCIC_Region11MismatchStatus    = DCIC_REGION_MISMATCH_STATUS(11U), /*!< Region 11 CRC32 value mismatch. */
0076     kDCIC_Region12MismatchStatus    = DCIC_REGION_MISMATCH_STATUS(12U), /*!< Region 12 CRC32 value mismatch. */
0077     kDCIC_Region13MismatchStatus    = DCIC_REGION_MISMATCH_STATUS(13U), /*!< Region 13 CRC32 value mismatch. */
0078     kDCIC_Region14MismatchStatus    = DCIC_REGION_MISMATCH_STATUS(14U), /*!< Region 14 CRC32 value mismatch. */
0079     kDCIC_Region15MismatchStatus    = DCIC_REGION_MISMATCH_STATUS(15U), /*!< Region 15 CRC32 value mismatch. */
0080 };
0081 
0082 /*!
0083  * @brief Interrupts.
0084  * @anchor _dcic_interrupt_enable
0085  */
0086 enum _dcic_interrupt_enable
0087 {
0088     kDCIC_FunctionalInterruptEnable = DCIC_DCICIC_FI_MASK_MASK, /*!< Interrupt when match results ready. */
0089     kDCIC_ErrorInterruptEnable      = DCIC_DCICIC_EI_MASK_MASK, /*!< Interrupt when there is a signature mismatch. */
0090 };
0091 
0092 /*!
0093  * @brief DCIC configuration.
0094  */
0095 typedef struct _dcic_config
0096 {
0097     bool enableExternalSignal; /*!< Enable the mismatch external signal. When enabled, the mismatch status could
0098                                  be monitored from the extern pin. */
0099     uint8_t polarityFlags;     /*!< Display signal polarity, logical OR'ed of @ref _DCIC_polarity_flags. */
0100     uint32_t enableInterrupts; /*!< Interrupts to enable, should be OR'ed of @ref _dcic_interrupt_enable. */
0101 } dcic_config_t;
0102 
0103 /*!
0104  * @brief Region of interest (ROI) configuration.
0105  */
0106 typedef struct _dcic_region_config
0107 {
0108     bool lock;            /*!< Lock the region configuration except reference CRC32 value setting. */
0109     uint16_t upperLeftX;  /*!< X of upper left corner. Range: 0 to 2^13-1. */
0110     uint16_t upperLeftY;  /*!< Y of upper left corner. Range: 0 to 2^12-1. */
0111     uint16_t lowerRightX; /*!< X of lower right corner. Range: 0 to 2^13-1. */
0112     uint16_t lowerRightY; /*!< Y of lower right corner. Range: 0 to 2^12-1. */
0113     uint32_t refCrc;      /*!< Reference CRC32 value. */
0114 } dcic_region_config_t;
0115 
0116 #if defined(__cplusplus)
0117 extern "C" {
0118 #endif
0119 
0120 /*******************************************************************************
0121  * API
0122  ******************************************************************************/
0123 
0124 /*!
0125  * @name Initialization and deinitialization
0126  * @{
0127  */
0128 
0129 /*!
0130  * @brief Initializes the DCIC.
0131  *
0132  * This function resets DCIC registers to default value, then
0133  * set the configurations. This function does not start the
0134  * DCIC to work, application should call @ref DCIC_DisableRegion
0135  * to configure regions, then call @ref DCIC_Enable to start the
0136  * DCIC to work.
0137  *
0138  * @param base   DCIC peripheral base address.
0139  * @param config Pointer to the configuration.
0140  */
0141 void DCIC_Init(DCIC_Type *base, const dcic_config_t *config);
0142 
0143 /*!
0144  * @brief Deinitialize the DCIC.
0145  *
0146  * Disable the DCIC functions.
0147  *
0148  * @param base DCIC peripheral base address.
0149  */
0150 void DCIC_Deinit(DCIC_Type *base);
0151 
0152 /*!
0153  * @brief Get the default configuration to initialize DCIC.
0154  *
0155  * The default configuration is:
0156  *
0157  * @code
0158     config->polarityFlags = kDCIC_VsyncActiveLow | kDCIC_HsyncActiveLow |
0159                             kDCIC_DataEnableActiveLow | kDCIC_DriveDataOnFallingClkEdge;
0160     config->enableExternalSignal = false;
0161     config->enableInterrupts = 0;
0162    @endcode
0163  *
0164  * @param config Pointer to the configuration.
0165  */
0166 void DCIC_GetDefaultConfig(dcic_config_t *config);
0167 
0168 /*!
0169  * @brief Enable or disable the DCIC module.
0170  *
0171  * @param base DCIC peripheral base address.
0172  * @param enable Use true to enable, false to disable.
0173  */
0174 static inline void DCIC_Enable(DCIC_Type *base, bool enable)
0175 {
0176     if (enable)
0177     {
0178         base->DCICC |= DCIC_DCICC_IC_EN_MASK;
0179     }
0180     else
0181     {
0182         base->DCICC &= ~DCIC_DCICC_IC_EN_MASK;
0183     }
0184 }
0185 
0186 /* @} */
0187 
0188 /*!
0189  * @name Status
0190  * @{
0191  */
0192 
0193 /*!
0194  * @brief Get status flags.
0195  *
0196  * The flag @ref kDCIC_ErrorInterruptStatus is asserted if any region mismatch
0197  * flag asserted.
0198  *
0199  * @brief base DCIC peripheral base address.
0200  * @return Masks of asserted status flags, @ref _DCIC_status_flags.
0201  */
0202 static inline uint32_t DCIC_GetStatusFlags(DCIC_Type *base)
0203 {
0204     return base->DCICS;
0205 }
0206 
0207 /*!
0208  * @brief Clear status flags.
0209  *
0210  * The flag @ref kDCIC_ErrorInterruptStatus should be cleared by clearing all
0211  * asserted region mismatch flags.
0212  *
0213  * @brief base DCIC peripheral base address.
0214  * @brief mask Mask of status values that would be cleared, @ref _DCIC_status_flags.
0215  */
0216 static inline void DCIC_ClearStatusFlags(DCIC_Type *base, uint32_t mask)
0217 {
0218     base->DCICS = (mask & (DCIC_DCICS_FI_STAT_MASK | DCIC_DCICS_ROI_MATCH_STAT_MASK));
0219 }
0220 
0221 /* @} */
0222 
0223 /*!
0224  * @name Interrupts
0225  * @{
0226  */
0227 
0228 /*!
0229  * @brief Lock the interrupt enabled status.
0230  *
0231  * Once this function is called, the interrupt enabled status could not be changed
0232  * until reset.
0233  *
0234  * @param base DCIC peripheral base address.
0235  */
0236 static inline void DCIC_LockInterruptEnabledStatus(DCIC_Type *base)
0237 {
0238     base->DCICIC |= DCIC_DCICIC_FREEZE_MASK_MASK;
0239 }
0240 
0241 /*!
0242  * @brief Enable interrupts.
0243  *
0244  * @param base DCIC peripheral base address.
0245  * @param mask Mask of interrupt events that would be enabled. See to "_dcic_interrupt_enable_t".
0246  */
0247 static inline void DCIC_EnableInterrupts(DCIC_Type *base, uint32_t mask)
0248 {
0249     base->DCICIC &= ~mask;
0250 }
0251 
0252 /*!
0253  * @brief Disable interrupts.
0254  *
0255  * @param base DCIC peripheral base address.
0256  * @param mask Mask of interrupt events that would be disabled. See to "_dcic_interrupt_enable_t".
0257  */
0258 static inline void DCIC_DisableInterrupts(DCIC_Type *base, uint32_t mask)
0259 {
0260     base->DCICIC |= mask;
0261 }
0262 
0263 /* @} */
0264 
0265 /*!
0266  * @name Region
0267  * @{
0268  */
0269 
0270 /*!
0271  * @brief Enable the region of interest (ROI) with configuration.
0272  *
0273  * Enable the ROI with configuration. To change the configuration except reference
0274  * CRC value, the region should be disabled first by @ref DCIC_DisableRegion,
0275  * then call this function again. The reference CRC value could be changed by
0276  * @ref DCIC_SetRegionRefCrc without disabling the region.
0277  * If the configuration is locked, only the reference CRC value could be changed,
0278  * the region size and position, enable status could not be changed until reset.
0279  *
0280  * @param base DCIC peripheral base address.
0281  * @param regionIdx Region index, from 0 to (DCIC_REGION_COUNT - 1).
0282  * @param config Pointer to the configuration.
0283  */
0284 void DCIC_EnableRegion(DCIC_Type *base, uint8_t regionIdx, const dcic_region_config_t *config);
0285 
0286 /*!
0287  * @brief Disable the region of interest (ROI).
0288  *
0289  * @param base DCIC peripheral base address.
0290  * @param regionIdx Region index, from 0 to (DCIC_REGION_COUNT - 1).
0291  */
0292 static inline void DCIC_DisableRegion(DCIC_Type *base, uint8_t regionIdx)
0293 {
0294     assert(regionIdx < DCIC_REGION_COUNT);
0295 
0296     if (regionIdx < DCIC_REGION_COUNT)
0297     {
0298         base->REGION[regionIdx].DCICRC &= ~DCIC_DCICRC_ROI_EN_MASK;
0299     }
0300 }
0301 
0302 /*!
0303  * @brief Set the reference CRC of interest (ROI).
0304  *
0305  * @param base DCIC peripheral base address.
0306  * @param regionIdx Region index, from 0 to (DCIC_REGION_COUNT - 1).
0307  * @param crc The reference CRC value.
0308  */
0309 static inline void DCIC_SetRegionRefCrc(DCIC_Type *base, uint8_t regionIdx, uint32_t crc)
0310 {
0311     assert(regionIdx < DCIC_REGION_COUNT);
0312 
0313     if (regionIdx < DCIC_REGION_COUNT)
0314     {
0315         base->REGION[regionIdx].DCICRRS = crc;
0316     }
0317 }
0318 
0319 /*!
0320  * @brief Get the DCIC calculated CRC.
0321  *
0322  * @param base DCIC peripheral base address.
0323  * @param regionIdx Region index, from 0 to (DCIC_REGION_COUNT - 1).
0324  * @return The calculated CRC value.
0325  */
0326 static inline uint32_t DCIC_GetRegionCalculatedCrc(DCIC_Type *base, uint8_t regionIdx)
0327 {
0328     uint32_t localdcicrcs = 0U;
0329 
0330     assert(regionIdx < DCIC_REGION_COUNT);
0331 
0332     if (regionIdx < DCIC_REGION_COUNT)
0333     {
0334         localdcicrcs = base->REGION[regionIdx].DCICRCS;
0335     }
0336 
0337     return localdcicrcs;
0338 }
0339 
0340 /* @} */
0341 
0342 /*!
0343  * @name Misc control.
0344  * @{
0345  */
0346 
0347 /*!
0348  * @brief Enable or disable output the mismatch external signal.
0349  *
0350  * The mismatch status can be output to external pins. If enabled:
0351  *   - If @ref kDCIC_ErrorInterruptStatus asserted, the output signal
0352  *     frequency is DCIC clock / 16.
0353  *   - If @ref kDCIC_ErrorInterruptStatus not asserted, the output signal
0354  *     frequency is DCIC clock / 4.
0355  *   - If integrity check is disabled, the signal is idle.
0356  *
0357  * @param base DCIC peripheral base address.
0358  * @param enable. Use true to enable, false to disable.
0359  */
0360 static inline void DCIC_EnableMismatchExternalSignal(DCIC_Type *base, bool enable)
0361 {
0362     if (enable)
0363     {
0364         base->DCICIC |= DCIC_DCICIC_EXT_SIG_EN_MASK;
0365     }
0366     else
0367     {
0368         base->DCICIC &= ~DCIC_DCICIC_EXT_SIG_EN_MASK;
0369     }
0370 }
0371 
0372 /* @} */
0373 
0374 #if defined(__cplusplus)
0375 }
0376 #endif
0377 /*!
0378  * @}
0379  */
0380 #endif /* _FSL_DCIC_H_ */