drivers/dcic/fsl_dcic.c

0001 /*
0002  * Copyright 2020-2022 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007
0008 #include "fsl_dcic.h"
0009
0010 /*******************************************************************************
0011  * Definitions
0012  ******************************************************************************/
0013
0014 /* Component ID definition, used by tools. */
0015 #ifndef FSL_COMPONENT_ID
0016 #define FSL_COMPONENT_ID "platform.drivers.dcic"
0017 #endif
0018
0019 /*******************************************************************************
0020  * Prototypes
0021  ******************************************************************************/
0022
0023 /*!
0024  * @brief Get instance number for DCIC module.
0025  *
0026  * @param base DCIC peripheral base address.
0027  */
0028 static uint32_t DCIC_GetInstance(const DCIC_Type *base);
0029
0030 static void DCIC_ResetRegister(DCIC_Type *base);
0031
0032 /*******************************************************************************
0033  * Variables
0034  ******************************************************************************/
0035
0036 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0037 /*! @brief Pointers to dcic clocks for each instance. */
0038 static const clock_ip_name_t s_dcicClocks[] = DCIC_CLOCKS;
0039 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0040
0041 /*******************************************************************************
0042  * Code
0043  ******************************************************************************/
0044 static uint32_t DCIC_GetInstance(const DCIC_Type *base)
0045 {
0046     static DCIC_Type *const s_dcicBases[] = DCIC_BASE_PTRS;
0047
0048     uint32_t instance;
0049
0050     /* Find the instance index from base address mappings. */
0051     for (instance = 0; instance < ARRAY_SIZE(s_dcicBases); instance++)
0052     {
0053         if (s_dcicBases[instance] == base)
0054         {
0055             break;
0056         }
0057     }
0058
0059     assert(instance < ARRAY_SIZE(s_dcicBases));
0060
0061     return instance;
0062 }
0063
0064 #define DCIC_DCCIC_RESET_VALUE  (DCIC_DCICC_VSYNC_POL_MASK | DCIC_DCICC_HSYNC_POL_MASK | DCIC_DCICC_DE_POL_MASK)
0065 #define DCIC_DCICIC_RESET_VALUE (DCIC_DCICIC_FI_MASK_MASK | DCIC_DCICIC_EI_MASK_MASK)
0066
0067 static void DCIC_ResetRegister(DCIC_Type *base)
0068 {
0069     uint32_t i;
0070
0071     base->DCICC  = DCIC_DCCIC_RESET_VALUE;
0072     base->DCICIC = DCIC_DCICIC_RESET_VALUE;
0073
0074     /* Reset region registers. */
0075     for (i = 0; i < DCIC_REGION_COUNT; i++)
0076     {
0077         base->REGION[i].DCICRC  = 0UL;
0078         base->REGION[i].DCICRS  = 0UL;
0079         base->REGION[i].DCICRRS = 0UL;
0080     }
0081
0082     /* Clear all status. */
0083     base->DCICS = (DCIC_DCICS_EI_STAT_MASK | DCIC_DCICS_FI_STAT_MASK | DCIC_DCICS_ROI_MATCH_STAT_MASK);
0084 }
0085
0086 /*
0087  * brief Initializes the DCIC.
0088  *
0089  * param base   DCIC peripheral base address.
0090  * param config Pointer to the configuration.
0091  */
0092 void DCIC_Init(DCIC_Type *base, const dcic_config_t *config)
0093 {
0094 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && (0 != FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
0095     /* Enable the clock. */
0096     (void)CLOCK_EnableClock(s_dcicClocks[DCIC_GetInstance(base)]);
0097 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0098
0099     DCIC_ResetRegister(base);
0100
0101     base->DCICC = config->polarityFlags;
0102
0103     DCIC_EnableMismatchExternalSignal(base, config->enableExternalSignal);
0104     DCIC_EnableInterrupts(base, config->enableInterrupts);
0105 }
0106
0107 /*
0108  * brief Disable the DCIC.
0109  *
0110  * param base DCIC peripheral base address.
0111  */
0112 void DCIC_Deinit(DCIC_Type *base)
0113 {
0114     base->DCICC = 0U;
0115
0116 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && (0 != FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
0117     /* Disable the clock. */
0118     (void)CLOCK_DisableClock(s_dcicClocks[DCIC_GetInstance(base)]);
0119 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0120 }
0121
0122 /*!
0123  * Get the default configuration to initialize DCIC.
0124  *
0125  * The default configuration is:
0126  *
0127     config->polarityFlags = kDCIC_VsyncActiveLow | kDCIC_HsyncActiveLow |
0128                             kDCIC_DataEnableActiveLow | kDCIC_DriveDataOnFallingClkEdge;
0129     config->enableExternalSignal = false;
0130     config->enableInterrupts = 0;
0131  *
0132  * param config Pointer to the configuration.
0133  */
0134 void DCIC_GetDefaultConfig(dcic_config_t *config)
0135 {
0136     assert(NULL != config);
0137
0138     config->polarityFlags = (uint8_t)kDCIC_VsyncActiveLow | (uint8_t)kDCIC_HsyncActiveLow |
0139                             (uint8_t)kDCIC_DataEnableActiveLow | (uint8_t)kDCIC_DriveDataOnFallingClkEdge;
0140     config->enableExternalSignal = false;
0141     config->enableInterrupts     = 0;
0142 }
0143
0144 /*
0145  * brief Enable the region of interest (ROI) with configuration.
0146  *
0147  * Enable the ROI with configuration. To change the configuration except reference
0148  * CRC value, the region should be disabled first by ref DCIC_DisableRegion,
0149  * then call this function again. The reference CRC value could be changed by
0150  * ref DCIC_SetRegionRefCrc without disabling the region.
0151  * If the configuration is locked, only the reference CRC value could be changed,
0152  * the region size and position, enable status could not be changed until reset.
0153  *
0154  * param base DCIC peripheral base address.
0155  * param regionIdx Region index, from 0 to (DCIC_REGION_COUNT - 1).
0156  * param config Pointer to the configuration.
0157  */
0158 void DCIC_EnableRegion(DCIC_Type *base, uint8_t regionIdx, const dcic_region_config_t *config)
0159 {
0160     assert(regionIdx < DCIC_REGION_COUNT);
0161     assert(NULL != config);
0162
0163     if (regionIdx < DCIC_REGION_COUNT)
0164     {
0165         base->REGION[regionIdx].DCICRRS = config->refCrc;
0166
0167         base->REGION[regionIdx].DCICRS = (((uint32_t)config->lowerRightX << DCIC_DCICRS_END_OFFSET_X_SHIFT) |
0168                                           ((uint32_t)config->lowerRightY << DCIC_DCICRS_END_OFFSET_Y_SHIFT));
0169
0170         base->REGION[regionIdx].DCICRC = (((uint32_t)config->upperLeftX << DCIC_DCICRC_START_OFFSET_X_SHIFT) |
0171                                           ((uint32_t)config->upperLeftY << DCIC_DCICRC_START_OFFSET_Y_SHIFT) |
0172                                           (config->lock ? DCIC_DCICRC_ROI_FREEZE_MASK : 0UL) | DCIC_DCICRC_ROI_EN_MASK);
0173     }
0174 }