drivers/dcdc_1/fsl_dcdc.h

0001 /*
0002  * Copyright 2017-2021, NXP
0003  * All rights reserved.
0004  *
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef __FSL_DCDC_H__
0010 #define __FSL_DCDC_H__
0011
0012 #include "fsl_common.h"
0013
0014 /*!
0015  * @addtogroup dcdc
0016  * @{
0017  */
0018
0019 /*******************************************************************************
0020  * Definitions
0021  ******************************************************************************/
0022 /*! @brief DCDC driver version. */
0023 #define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */
0024
0025 /*!
0026  * @brief DCDC status flags.
0027  */
0028 enum _dcdc_status_flags_t
0029 {
0030     kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */
0031 };
0032
0033 /*!
0034  * @brief The current bias of low power comparator.
0035  */
0036 typedef enum _dcdc_comparator_current_bias
0037 {
0038     kDCDC_ComparatorCurrentBias50nA  = 0U, /*!< The current bias of low power comparator is 50nA. */
0039     kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */
0040     kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */
0041     kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
0042 } dcdc_comparator_current_bias_t;
0043
0044 /*!
0045  * @brief The threshold of over current detection.
0046  */
0047 typedef enum _dcdc_over_current_threshold
0048 {
0049     kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */
0050     kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */
0051     kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */
0052     kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */
0053 } dcdc_over_current_threshold_t;
0054
0055 /*!
0056  * @brief The threshold if peak current detection.
0057  */
0058 typedef enum _dcdc_peak_current_threshold
0059 {
0060     kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */
0061     kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */
0062     kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */
0063     kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */
0064     kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */
0065     kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */
0066 } dcdc_peak_current_threshold_t;
0067
0068 /*!
0069  * @brief The period of counting the charging times in power save mode.
0070  */
0071 typedef enum _dcdc_count_charging_time_period
0072 {
0073     kDCDC_CountChargingTimePeriod8Cycle  = 0U, /*!< Eight 32k cycle. */
0074     kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */
0075 } dcdc_count_charging_time_period_t;
0076
0077 /*!
0078  * @brief The threshold of the counting number of charging times
0079  */
0080 typedef enum _dcdc_count_charging_time_threshold
0081 {
0082     kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */
0083     kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */
0084     kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */
0085     kDCDC_CountChargingTimeThreshold8  = 3U, /*!< 0x3: 8. */
0086 } dcdc_count_charging_time_threshold_t;
0087
0088 /*!
0089  * @brief Oscillator clock option.
0090  */
0091 typedef enum _dcdc_clock_source
0092 {
0093     kDCDC_ClockAutoSwitch  = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
0094     kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */
0095     kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */
0096 } dcdc_clock_source_t;
0097
0098 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0099 /*!
0100  * @brief Voltage output option.
0101  */
0102 typedef enum _dcdc_voltage_output_sel
0103 {
0104     kDCDC_VoltageOutput1P8 = 0U, /*!< 1.8V output. */
0105     kDCDC_VoltageOutput1P0 = 1U, /*!< 1.0V output. */
0106 } dcdc_voltage_output_sel_t;
0107 #endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
0108
0109 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0110 /*!
0111  * @brief DCDC low power modes.
0112  */
0113 typedef enum _dcdc_low_power_mode
0114 {
0115     kDCDC_StandbyMode            = 0U, /*!< Standby mode. */
0116     kDCDC_LowPowerMode           = 1U, /*!< Low power mode. */
0117     kDCDC_GpcStandbyLowPowerMode = 2U, /*!< low power mode for GPC standby request. */
0118 } dcdc_low_power_mode_t;
0119
0120 /*!
0121  * @brief DCDC control mode.
0122  */
0123 typedef enum _dcdc_control_mode
0124 {
0125     kDCDC_StaticControl   = 0U, /*!< Static control. */
0126     kDCDC_SetPointControl = 1U, /*!< Controlled by GPC set points. */
0127 } dcdc_control_mode_t;
0128
0129 /*!
0130  * @brief DCDC trim input mode.
0131  */
0132 typedef enum _dcdc_trim_input_mode
0133 {
0134     kDCDC_SampleTrimInput = 0U, /*!< Sample trim input. */
0135     kDCDC_HoldTrimInput   = 1U, /*!< Hold trim input. */
0136 } dcdc_trim_input_mode_t;
0137
0138 #if defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK
0139 /*!
0140  * @brief System setpoints enumeration.
0141  */
0142 enum _dcdc_setpoint_map
0143 {
0144     kDCDC_SetPoint0  = 1UL << 0UL,  /*!< Set point 0. */
0145     kDCDC_SetPoint1  = 1UL << 1UL,  /*!< Set point 1. */
0146     kDCDC_SetPoint2  = 1UL << 2UL,  /*!< Set point 2. */
0147     kDCDC_SetPoint3  = 1UL << 3UL,  /*!< Set point 3. */
0148     kDCDC_SetPoint4  = 1UL << 4UL,  /*!< Set point 4. */
0149     kDCDC_SetPoint5  = 1UL << 5UL,  /*!< Set point 5. */
0150     kDCDC_SetPoint6  = 1UL << 6UL,  /*!< Set point 6. */
0151     kDCDC_SetPoint7  = 1UL << 7UL,  /*!< Set point 7. */
0152     kDCDC_SetPoint8  = 1UL << 8UL,  /*!< Set point 8. */
0153     kDCDC_SetPoint9  = 1UL << 9UL,  /*!< Set point 9. */
0154     kDCDC_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */
0155     kDCDC_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */
0156     kDCDC_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */
0157     kDCDC_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */
0158     kDCDC_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */
0159     kDCDC_SetPoint15 = 1UL << 15UL  /*!< Set point 15. */
0160 };
0161 #endif /* DCDC_REG4_ENABLE_SP_MASK */
0162
0163 /*!
0164  * @brief Configuration for DCDC.
0165  */
0166 typedef struct _dcdc_config
0167 {
0168     dcdc_control_mode_t controlMode;      /*!< DCDC control mode. */
0169     dcdc_trim_input_mode_t trimInputMode; /*!< Hold trim input. */
0170     bool enableDcdcTimeout;               /*!< Enable internal count for DCDC_OK timeout. */
0171     bool enableSwitchingConverterOutput;  /*!< Enable the VDDIO switching converter output.*/
0172 } dcdc_config_t;
0173 #endif /* FSL_FEATURE_DCDC_HAS_CTRL_REGp */
0174
0175 /*!
0176  * @brief Configuration for DCDC detection.
0177  */
0178 typedef struct _dcdc_detection_config
0179 {
0180     bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */
0181 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0182     bool powerDownOverVoltageVdd1P8Detection; /*!< Power down over-voltage detection comparator for VDD1P8. */
0183     bool powerDownOverVoltageVdd1P0Detection; /*!< Power down over-voltage detection comparator for VDD1P0. */
0184 #else
0185     bool powerDownOverVoltageDetection; /*!< Power down over-voltage detection comparator. */
0186 #endif                                  /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
0187     bool powerDownLowVlotageDetection;  /*!< Power down low-voltage detection comparator. */
0188     bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */
0189     bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */
0190     bool powerDownZeroCrossDetection;   /*!< Power down the zero cross detection function for discontinuous conductor
0191                                            mode. */
0192     dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */
0193     dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */
0194 } dcdc_detection_config_t;
0195
0196 /*!
0197  * @brief Configuration for the loop control.
0198  */
0199 typedef struct _dcdc_loop_control_config
0200 {
0201     bool enableCommonHysteresis;         /*!< Enable hysteresis in switching converter common mode analog comparators.
0202                                               This feature will improve transient supply ripple and efficiency. */
0203     bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */
0204 #if defined(FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE) && \
0205     FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE
0206     bool enableDifferentialHysteresis;         /*!< Enable hysteresis in switching converter differential mode analog
0207                                                     comparators. This feature will improve transient supply ripple and
0208                                                     efficiency. */
0209     bool enableDifferentialThresholdDetection; /*!< Increase the threshold detection for differential mode analog
0210                                                     comparators. */
0211 #endif                                         /* FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE */
0212     bool enableInvertHysteresisSign;           /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */
0213     bool enableRCThresholdDetection;           /*!< Increase the threshold detection for RC scale circuit. */
0214     uint32_t enableRCScaleCircuit;      /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond
0215                                              faster under transient load conditions. */
0216     uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in
0217                                            the switching DC-DC converter. Each time this field makes a transition from
0218                                            0x0, the loop filter of the DC-DC converter is stepped once by a value
0219                                            proportional to the change. This can be used to force a certain control loop
0220                                            behavior, such as improving response under known heavy load transients. */
0221 } dcdc_loop_control_config_t;
0222 /*!
0223  * @brief Configuration for DCDC low power.
0224  */
0225 typedef struct _dcdc_low_power_config
0226 {
0227 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0228     bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the
0229                                      overloading threshold (typical value is 50 mA), DCDC will switch to the run mode
0230                                      automatically. */
0231 #endif                            /* FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS */
0232     bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */
0233     dcdc_count_charging_time_period_t
0234         countChargingTimePeriod; /*!< The period of counting the charging times in power save mode. */
0235     dcdc_count_charging_time_threshold_t
0236         countChargingTimeThreshold; /*!< the threshold of the counting number of charging times during
0237                                          the period that lp_overload_freq_sel sets in power save mode. */
0238 } dcdc_low_power_config_t;
0239
0240 /*!
0241  * @brief Configuration for DCDC internal regulator.
0242  */
0243 typedef struct _dcdc_internal_regulator_config
0244 {
0245     bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is
0246                                 connected as default "true", and need set to "false" to disconnect the load
0247                                 resistor. */
0248     uint32_t feedbackPoint;  /*!< Available range is 0~3. Select the feedback point of the internal regulator. */
0249 } dcdc_internal_regulator_config_t;
0250
0251 /*!
0252  * @brief Configuration for min power setting.
0253  */
0254 typedef struct _dcdc_min_power_config
0255 {
0256     bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */
0257 } dcdc_min_power_config_t;
0258
0259 #if defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK
0260 /*!
0261  * @brief DCDC configuration in set point mode.
0262  */
0263 typedef struct _dcdc_setpoint_config
0264 {
0265     uint32_t enableDCDCMap;     /*!< The setpoint map that enable the DCDC module. Should be the OR'ed value of @ref
0266                                    _dcdc_setpoint_map. */
0267     uint32_t enableDigLogicMap; /*!< The setpoint map that enable the DCDC dig logic. Should be the OR'ed value of @ref
0268                                    _dcdc_setpoint_map. */
0269     uint32_t lowpowerMap; /*!< The setpoint map that enable the DCDC Low powermode. Should be the OR'ed value of @ref
0270                               _dcdc_setpoint_map. */
0271     uint32_t standbyMap;  /*!< The setpoint map that enable the DCDC standby mode. Should be the OR'ed value of @ref
0272                               _dcdc_setpoint_map. */
0273     uint32_t standbyLowpowerMap; /*!< The setpoint map that enable the DCDC low power mode, when the related setpoint is
0274                                     in standby mode.
0275                                      @ref _dcdc_setpoint_map. */
0276     uint8_t *buckVDD1P8TargetVoltage;    /*!< Point to the array that store the target voltage level of VDD1P8 in buck
0277                                             mode.    Note that the pointed array must have 16 elements. */
0278     uint8_t *buckVDD1P0TargetVoltage;    /*!< Point to the array that store the target voltage level of VDD1P0 in buck
0279                                             mode.    Note that the pointed array must have 16 elements. */
0280     uint8_t *standbyVDD1P8TargetVoltage; /*!< Point to the array that store the target voltage level of VDD1P8 in
0281                                             standby mode. Note that the pointed array must have 16 elements. */
0282     uint8_t *standbyVDD1P0TargetVoltage; /*!< Point to the array that store the target voltage level of VDD1P0 in
0283                                             standby mode. Note that the pointed array must have 16 elements. */
0284 } dcdc_setpoint_config_t;
0285
0286 #endif /* DCDC_REG4_ENABLE_SP_MASK */
0287
0288 #if defined(__cplusplus)
0289 extern "C" {
0290 #endif
0291
0292 /*******************************************************************************
0293  * API
0294  ******************************************************************************/
0295 /*!
0296  * @name Initialization and deinitialization
0297  * @{
0298  */
0299
0300 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0301 /*!
0302  * @brief Enable the access to DCDC registers.
0303  *
0304  * @param base DCDC peripheral base address.
0305  * @param config Pointer to the configuration structure.
0306  */
0307 void DCDC_Init(DCDC_Type *base, dcdc_config_t *config);
0308 #else
0309 /*!
0310  * @brief Enable the access to DCDC registers.
0311  *
0312  * @param base DCDC peripheral base address.
0313  */
0314 void DCDC_Init(DCDC_Type *base);
0315 #endif /* FSL_FEATURE_DCDC_HAS_CTRL_REG */
0316
0317 /*!
0318  * @brief Disable the access to DCDC registers.
0319  *
0320  * @param base DCDC peripheral base address.
0321  */
0322 void DCDC_Deinit(DCDC_Type *base);
0323
0324 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0325 /*!
0326  * brief Get the default setting for DCDC user configuration structure.
0327  *
0328  * This function initializes the user configuration structure to a default value. The default values are:
0329  * code
0330  *   config->controlMode                    = kDCDC_StaticControl;
0331  *   config->trimInputMode                  = kDCDC_SampleTrimInput;
0332  *   config->enableDcdcTimeout              = false;
0333  *   config->enableSwitchingConverterOutput = false;
0334  * endcode
0335  *
0336  * param config Pointer to configuration structure. See to "dcdc_config_t"
0337  */
0338 void DCDC_GetDefaultConfig(DCDC_Type *base, dcdc_config_t *config);
0339 #endif /* FSL_FEATURE_DCDC_HAS_CTRL_REGp */
0340
0341 /* @} */
0342
0343 /*!
0344  * @name Status
0345  * @{
0346  */
0347
0348 /*!
0349  * @brief Get DCDC status flags.
0350  *
0351  * @param base peripheral base address.
0352  * @return Mask of asserted status flags. See to "_dcdc_status_flags_t".
0353  */
0354 uint32_t DCDC_GetstatusFlags(DCDC_Type *base);
0355
0356 /* @} */
0357
0358 /*!
0359  * @name Misc control
0360  * @{
0361  */
0362
0363 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0364 /*!
0365  * @brief Make DCDC enter into low power modes.
0366  *
0367  * @param base DCDC peripheral base address.
0368  * @param mode DCDC low power mode selection. See to "_dcdc_low_power_mode"
0369  */
0370 void DCDC_EnterLowPowerMode(DCDC_Type *base, dcdc_low_power_mode_t mode);
0371 #endif /* FSL_FEATURE_DCDC_HAS_CTRL_REG */
0372
0373 /*!
0374  * @brief Enable the output range comparator.
0375  *
0376  * The output range comparator is disabled by default.
0377  *
0378  * @param base DCDC peripheral base address.
0379  * @param enable Enable the feature or not.
0380  */
0381 static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)
0382 {
0383     if (enable)
0384     {
0385         base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK;
0386     }
0387     else
0388     {
0389         base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
0390     }
0391 }
0392
0393 /*!
0394  * @brief Configure the DCDC clock source.
0395  *
0396  * @param base DCDC peripheral base address.
0397  * @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
0398  */
0399 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
0400
0401 /*!
0402  * @brief Get the default setting for detection configuration.
0403  *
0404  * The default configuration are set according to responding registers' setting when powered on.
0405  * They are:
0406  * @code
0407  *   config->enableXtalokDetection = false;
0408  *   config->powerDownOverVoltageDetection = true;
0409  *   config->powerDownLowVlotageDetection = false;
0410  *   config->powerDownOverCurrentDetection = true;
0411  *   config->powerDownPeakCurrentDetection = true;
0412  *   config->powerDownZeroCrossDetection = true;
0413  *   config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
0414  *   config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
0415  * @endcode
0416  *
0417  * @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
0418  */
0419 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config);
0420
0421 /*!
0422  * @brief Configure the DCDC detection.
0423  *
0424  * @param base DCDC peripheral base address.
0425  * @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
0426  */
0427 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config);
0428
0429 /*!
0430  * @brief Get the default setting for low power configuration.
0431  *
0432  * The default configuration are set according to responding registers' setting when powered on.
0433  * They are:
0434  * @code
0435  *   config->enableOverloadDetection = true;
0436  *   config->enableAdjustHystereticValue = false;
0437  *   config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
0438  *   config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
0439  * @endcode
0440  *
0441  * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
0442  */
0443 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config);
0444
0445 /*!
0446  * @brief Configure the DCDC low power.
0447  *
0448  * @param base DCDC peripheral base address.
0449  * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
0450  */
0451 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config);
0452
0453 /*!
0454  * @brief Reset current alert signal. Alert signal is generate by peak current detection.
0455  *
0456  * @param base DCDC peripheral base address.
0457  * @param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
0458  */
0459 void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable);
0460
0461 /*!
0462  * @brief Set the bangap trim value to trim bandgap voltage.
0463  *
0464  * @param base DCDC peripheral base address.
0465  * @param trimValue The bangap trim value. Available range is 0U-31U.
0466  */
0467 static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
0468 {
0469     base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
0470     base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue);
0471 }
0472
0473 /*!
0474  * @brief Get the default setting for loop control configuration.
0475  *
0476  * The default configuration are set according to responding registers' setting when powered on.
0477  * They are:
0478  * @code
0479  *   config->enableCommonHysteresis = false;
0480  *   config->enableCommonThresholdDetection = false;
0481  *   config->enableInvertHysteresisSign = false;
0482  *   config->enableRCThresholdDetection = false;
0483  *   config->enableRCScaleCircuit = 0U;
0484  *   config->complementFeedForwardStep = 0U;
0485  * @endcode
0486  *
0487  * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
0488  */
0489 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config);
0490
0491 /*!
0492  * @brief Configure the DCDC loop control.
0493  *
0494  * @param base DCDC peripheral base address.
0495  * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
0496  */
0497 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config);
0498
0499 /*!
0500  * @brief Configure for the min power.
0501  *
0502  * @param base DCDC peripheral base address.
0503  * @param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
0504  */
0505 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config);
0506
0507 /*!
0508  * @brief Set the current bias of low power comparator.
0509  *
0510  * @param base DCDC peripheral base address.
0511  * @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t".
0512  */
0513 static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule)
0514 {
0515     base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
0516     base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule);
0517 }
0518
0519 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0520 /*!
0521  * @brief Lock VDD 1P0 target voltage.
0522  *
0523  * @param base DCDC peripheral base address.
0524  */
0525 static inline void DCDC_LockVdd1p0TargetVoltage(DCDC_Type *base)
0526 {
0527     base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0528 }
0529
0530 /*!
0531  * @brief Lock VDD 1P8 target voltage.
0532  *
0533  * @param base DCDC peripheral base address.
0534  */
0535 static inline void DCDC_LockVdd1p8TargetVoltage(DCDC_Type *base)
0536 {
0537     base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0538 }
0539
0540 /*!
0541  * @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
0542  * @deprecated Do not use this function. It has been superceded by @ref DCDC_AdjustRunTargetVoltage
0543  * and @ref DCDC_AdjustLowPowerTargetVoltage
0544  *
0545  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0546  * stabled.
0547  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0548  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0549  *
0550  * @param base DCDC peripheral base address.
0551  * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0552  * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0553  * @param sel sel DCDC target voltage output selection. See to "_dcdc_voltage_output_sel".
0554  */
0555 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel);
0556
0557 /*!
0558  * @brief Adjust the target voltage of VDD_SOC in run mode.
0559  *
0560  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0561  * stabled.
0562  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0563  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0564  *
0565  * @param base DCDC peripheral base address.
0566  * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0567  * @param sel sel DCDC target voltage output selection. See to "_dcdc_voltage_output_sel".
0568  */
0569 void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun, dcdc_voltage_output_sel_t sel);
0570
0571 /*!
0572  * @brief Adjust the target voltage of VDD_SOC in low power mode.
0573  *
0574  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0575  * stabled.
0576  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0577  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0578  *
0579  * @param base DCDC peripheral base address.
0580  * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0581  * @param sel sel DCDC target voltage output selection. See to "_dcdc_voltage_output_sel".
0582  */
0583 void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel);
0584 #else
0585
0586 /*!
0587  * @brief Lock target voltage.
0588  *
0589  * @param base DCDC peripheral base address.
0590  */
0591 static inline void DCDC_LockTargetVoltage(DCDC_Type *base)
0592 {
0593     base->REG3 |= DCDC_REG3_DISABLE_STEP_MASK;
0594 }
0595
0596 /*!
0597  * @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
0598  * @deprecated Do not use this function. It has been superceded by @ref DCDC_AdjustRunTargetVoltage
0599  * and @ref DCDC_AdjustLowPowerTargetVoltage
0600  *
0601  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0602  * stabled.
0603  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0604  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0605  *
0606  * @param base DCDC peripheral base address.
0607  * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0608  * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0609  */
0610 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby);
0611
0612 /*!
0613  * @brief Adjust the target voltage of VDD_SOC in run mode.
0614  *
0615  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0616  * stabled.
0617  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0618  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0619  *
0620  * @param base DCDC peripheral base address.
0621  * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0622  */
0623 void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun);
0624
0625 /*!
0626  * @brief Adjust the target voltage of VDD_SOC in low power mode.
0627  *
0628  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0629  * stabled.
0630  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0631  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0632  *
0633  * @param base DCDC peripheral base address.
0634  * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0635  */
0636 void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby);
0637 #endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
0638
0639 /*!
0640  * @brief Configure the DCDC internal regulator.
0641  *
0642  * @param base DCDC peripheral base address.
0643  * @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
0644  */
0645 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config);
0646
0647 /*!
0648  * @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero
0649  *        cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.
0650  *
0651  * @param base DCDC peripheral base address.
0652  * @param enable Enable the feature or not.
0653  */
0654 static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
0655 {
0656     if (enable)
0657     {
0658         base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK;
0659     }
0660     else
0661     {
0662         base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK;
0663     }
0664 }
0665
0666 /* @} */
0667
0668 #if defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK
0669 /*!
0670  * @name Setpoint mode APIs
0671  */
0672
0673 /*!
0674  * @brief Init DCDC module when the control mode selected as setpoint mode.
0675  *
0676  * @note The function should be invoked in the initial step to config the
0677  *       DCDC via setpoint control mode.
0678  *
0679  * @param base DCDC peripheral base address.
0680  * @param config The pointer to the structure @ref dcdc_setpoint_config_t.
0681  */
0682 void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config);
0683
0684 /*!
0685  * @brief Disable DCDC module when the control mode selected as setpoint mode.
0686  *
0687  * @param base DCDC peripheral base address.
0688  * @param setpointMap. The map of the setpoint to disable the DCDC module.
0689  *                      Should be the OR'ed value of _dcdc_setpoint_map.
0690  */
0691 static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap)
0692 {
0693     base->REG4 &= ~setpointMap;
0694 }
0695
0696 /* @} */
0697 #endif /* DCDC_REG4_ENABLE_SP_MASK */
0698
0699 /*!
0700  * @name Application guideline
0701  * @{
0702  */
0703
0704 /*!
0705  * @brief Boot DCDC into DCM(discontinous conduction mode).
0706  *
0707  *  pwd_zcd=0x0;
0708  *  pwd_cmp_offset=0x0;
0709  *  dcdc_loopctrl_en_rcscale= 0x5;
0710  *  DCM_set_ctrl=1'b1;
0711  *
0712  * @param base DCDC peripheral base address.
0713  */
0714 void DCDC_BootIntoDCM(DCDC_Type *base);
0715
0716 /*!
0717  * @brief Boot DCDC into CCM(continous conduction mode).
0718  *
0719  *  pwd_zcd=0x1;
0720  *  pwd_cmp_offset=0x0;
0721  *  dcdc_loopctrl_en_rcscale=0x3;
0722  *
0723  * @param base DCDC peripheral base address.
0724  */
0725 void DCDC_BootIntoCCM(DCDC_Type *base);
0726
0727 /* @} */
0728
0729 #if defined(__cplusplus)
0730 }
0731 #endif
0732
0733 /* @} */
0734
0735 #endif /* __FSL_DCDC_H__ */