File indexing completed on 2025-05-11 08:22:58
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0009 #include "fsl_dcdc.h"
0010
0011
0012 #ifndef FSL_COMPONENT_ID
0013 #define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
0014 #endif
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024 static uint32_t DCDC_GetInstance(DCDC_Type *base);
0025
0026 #if (defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK)
0027
0028
0029
0030
0031
0032
0033 static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray);
0034 #endif
0035
0036
0037
0038
0039
0040 static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS;
0041
0042 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0043
0044 static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS;
0045 #endif
0046
0047
0048
0049
0050 static uint32_t DCDC_GetInstance(DCDC_Type *base)
0051 {
0052 uint32_t instance;
0053
0054
0055 for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++)
0056 {
0057 if (s_dcdcBases[instance] == base)
0058 {
0059 break;
0060 }
0061 }
0062
0063 assert(instance < ARRAY_SIZE(s_dcdcBases));
0064
0065 return instance;
0066 }
0067
0068 #if (defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK)
0069 static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray)
0070 {
0071 assert(ptrArray != NULL);
0072
0073 uint32_t temp32 = 0UL;
0074 uint8_t index;
0075
0076 for (index = 0U; index < 4U; index++)
0077 {
0078 temp32 |= ptrArray[index] << ((index % 4U) * 8U);
0079 }
0080
0081 return temp32;
0082 }
0083 #endif
0084
0085 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0086
0087
0088
0089
0090
0091
0092 void DCDC_Init(DCDC_Type *base, dcdc_config_t *config)
0093 {
0094 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0095
0096 CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
0097 #endif
0098 uint32_t tmp32 = base->CTRL0;
0099
0100 tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode);
0101
0102 if (config->enableDcdcTimeout)
0103 {
0104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;
0105 }
0106 if (config->enableSwitchingConverterOutput)
0107 {
0108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK;
0109 }
0110 base->CTRL0 |= DCDC_CTRL0_ENABLE_MASK;
0111 base->CTRL0 = tmp32;
0112 }
0113 #else
0114
0115
0116
0117
0118
0119 void DCDC_Init(DCDC_Type *base)
0120 {
0121 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0122
0123 CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
0124 #endif
0125 }
0126 #endif
0127
0128
0129
0130
0131
0132
0133 void DCDC_Deinit(DCDC_Type *base)
0134 {
0135 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0136
0137 CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
0138 #endif
0139 }
0140
0141 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155 void DCDC_GetDefaultConfig(DCDC_Type *base, dcdc_config_t *config)
0156 {
0157 assert(NULL != config);
0158
0159
0160 (void)memset(config, 0, sizeof(*config));
0161
0162 config->controlMode = kDCDC_StaticControl;
0163 config->trimInputMode = kDCDC_SampleTrimInput;
0164 config->enableDcdcTimeout = false;
0165 config->enableSwitchingConverterOutput = false;
0166 }
0167
0168
0169
0170
0171
0172
0173
0174 void DCDC_EnterLowPowerMode(DCDC_Type *base, dcdc_low_power_mode_t mode)
0175 {
0176 switch (mode)
0177 {
0178 case kDCDC_StandbyMode:
0179 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK;
0180 break;
0181 case kDCDC_LowPowerMode:
0182 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK;
0183 break;
0184 case kDCDC_GpcStandbyLowPowerMode:
0185 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
0186 break;
0187 default:
0188 assert(false);
0189 break;
0190 }
0191 }
0192 #endif
0193
0194
0195
0196
0197
0198
0199
0200 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
0201 {
0202 uint32_t tmp32;
0203
0204
0205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
0206 DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
0207 switch (clockSource)
0208 {
0209 case kDCDC_ClockInternalOsc:
0210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;
0211 break;
0212 case kDCDC_ClockExternalOsc:
0213
0214 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK;
0215 break;
0216 case kDCDC_ClockAutoSwitch:
0217
0218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;
0219 break;
0220 default:
0221 assert(false);
0222 break;
0223 }
0224 base->REG0 = tmp32;
0225 }
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244
0245 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
0246 {
0247 assert(NULL != config);
0248
0249
0250 (void)memset(config, 0, sizeof(*config));
0251
0252 config->enableXtalokDetection = false;
0253 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0254 config->powerDownOverVoltageVdd1P8Detection = true;
0255 config->powerDownOverVoltageVdd1P0Detection = true;
0256 #else
0257 config->powerDownOverVoltageDetection = true;
0258 #endif
0259 config->powerDownLowVlotageDetection = false;
0260 config->powerDownOverCurrentDetection = true;
0261 config->powerDownPeakCurrentDetection = true;
0262 config->powerDownZeroCrossDetection = true;
0263 config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
0264 config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
0265 }
0266
0267
0268
0269
0270
0271
0272
0273 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
0274 {
0275 assert(NULL != config);
0276
0277 uint32_t tmp32;
0278
0279 tmp32 = base->REG0 & ~(DCDC_REG0_XTALOK_DISABLE_MASK
0280 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0281 | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK
0282 #else
0283 | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK
0284 #endif
0285 #if defined(FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET) && FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET
0286 | DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK
0287 #else
0288 | DCDC_REG0_PWD_CMP_BATT_DET_MASK
0289 #endif
0290 | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | DCDC_REG0_PWD_ZCD_MASK |
0291 DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK);
0292
0293 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) |
0294 DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold);
0295 if (false == config->enableXtalokDetection)
0296 {
0297 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
0298 }
0299 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0300 if (config->powerDownOverVoltageVdd1P8Detection)
0301 {
0302 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;
0303 }
0304 if (config->powerDownOverVoltageVdd1P0Detection)
0305 {
0306 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;
0307 }
0308 #else
0309 if (config->powerDownOverVoltageDetection)
0310 {
0311 tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK;
0312 }
0313 #endif
0314 if (config->powerDownLowVlotageDetection)
0315 {
0316 #if defined(FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET) && FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET
0317 tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;
0318 #else
0319 tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK;
0320 #endif
0321 }
0322 if (config->powerDownOverCurrentDetection)
0323 {
0324 tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;
0325 }
0326 if (config->powerDownPeakCurrentDetection)
0327 {
0328 tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;
0329 }
0330 if (config->powerDownZeroCrossDetection)
0331 {
0332 tmp32 |= DCDC_REG0_PWD_ZCD_MASK;
0333 }
0334 base->REG0 = tmp32;
0335 }
0336
0337
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
0350
0351 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
0352 {
0353 assert(NULL != config);
0354
0355
0356 (void)memset(config, 0, sizeof(*config));
0357 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0358 config->enableOverloadDetection = true;
0359 #endif
0360 config->enableAdjustHystereticValue = false;
0361 config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
0362 config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
0363 }
0364
0365
0366
0367
0368
0369
0370
0371 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
0372 {
0373 assert(NULL != config);
0374
0375 uint32_t tmp32;
0376
0377 tmp32 = base->REG0 &
0378 ~(DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK
0379 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0380 | DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK
0381 #endif
0382 );
0383 tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |
0384 DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold);
0385 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0386 if (config->enableOverloadDetection)
0387 {
0388 tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK;
0389 }
0390 #endif
0391 if (config->enableAdjustHystereticValue)
0392 {
0393 tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
0394 }
0395 base->REG0 = tmp32;
0396 }
0397
0398
0399
0400
0401
0402
0403
0404 uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
0405 {
0406 uint32_t tmp32 = 0U;
0407
0408 if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0409 {
0410 tmp32 |= (uint32_t)kDCDC_LockedOKStatus;
0411 }
0412
0413 return tmp32;
0414 }
0415
0416 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC) && FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC)
0417
0418
0419
0420
0421
0422
0423 void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
0424 {
0425 if (enable)
0426 {
0427 base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK;
0428 }
0429 else
0430 {
0431 base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK;
0432 }
0433 }
0434 #endif
0435
0436
0437
0438
0439
0440
0441
0442
0443
0444
0445
0446
0447
0448
0449
0450
0451
0452 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
0453 {
0454 assert(NULL != config);
0455
0456
0457 (void)memset(config, 0, sizeof(*config));
0458
0459 config->enableCommonHysteresis = false;
0460 config->enableCommonThresholdDetection = false;
0461 config->enableInvertHysteresisSign = false;
0462 config->enableRCThresholdDetection = false;
0463 config->enableRCScaleCircuit = 0U;
0464 config->complementFeedForwardStep = 0U;
0465 }
0466
0467
0468
0469
0470
0471
0472
0473 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
0474 {
0475 assert(NULL != config);
0476
0477 uint32_t tmp32;
0478
0479
0480 #if defined(FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE) && \
0481 FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE
0482 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |
0483 DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK);
0484 if (config->enableCommonHysteresis)
0485 {
0486 tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;
0487 }
0488 if (config->enableCommonThresholdDetection)
0489 {
0490 tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;
0491 }
0492 if (config->enableDifferentialHysteresis)
0493 {
0494 tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;
0495 }
0496 if (config->enableDifferentialThresholdDetection)
0497 {
0498 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;
0499 }
0500 #else
0501 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK);
0502 if (config->enableCommonHysteresis)
0503 {
0504 tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK;
0505 }
0506 if (config->enableCommonThresholdDetection)
0507 {
0508 tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK;
0509 }
0510 #endif
0511 base->REG1 = tmp32;
0512
0513
0514 tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
0515 DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK);
0516 tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
0517 DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit);
0518 if (config->enableInvertHysteresisSign)
0519 {
0520 tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;
0521 }
0522 if (config->enableRCThresholdDetection)
0523 {
0524 tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;
0525 }
0526 base->REG2 = tmp32;
0527 }
0528
0529
0530
0531
0532
0533
0534
0535 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
0536 {
0537 assert(NULL != config);
0538
0539 uint32_t tmp32;
0540
0541 tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
0542 if (config->enableUseHalfFreqForContinuous)
0543 {
0544 tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
0545 }
0546 base->REG3 = tmp32;
0547 }
0548
0549 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0550
0551
0552
0553
0554
0555
0556
0557
0558
0559
0560
0561
0562
0563
0564
0565 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel)
0566 {
0567 uint32_t tmp32;
0568
0569 if (sel == kDCDC_VoltageOutput1P8)
0570 {
0571
0572 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0573
0574
0575 tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK | DCDC_CTRL1_VDD1P8CTRL_TRG_MASK);
0576
0577 tmp32 |= DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(VDDStandby) | DCDC_CTRL1_VDD1P8CTRL_TRG(VDDRun);
0578 base->CTRL1 = tmp32;
0579 }
0580 else if (sel == kDCDC_VoltageOutput1P0)
0581 {
0582
0583 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0584
0585
0586 tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK | DCDC_CTRL1_VDD1P0CTRL_TRG_MASK);
0587
0588 tmp32 |= DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(VDDStandby) | DCDC_CTRL1_VDD1P0CTRL_TRG(VDDRun);
0589 base->CTRL1 = tmp32;
0590 }
0591 else
0592 {
0593 ;
0594 }
0595
0596
0597
0598 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0599 {
0600 }
0601 }
0602
0603
0604
0605
0606
0607
0608
0609
0610
0611
0612
0613
0614
0615 void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun, dcdc_voltage_output_sel_t sel)
0616 {
0617 uint32_t tmp32;
0618
0619 if (sel == kDCDC_VoltageOutput1P8)
0620 {
0621
0622 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0623
0624
0625 tmp32 = base->CTRL1 & ~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK;
0626
0627 tmp32 |= DCDC_CTRL1_VDD1P8CTRL_TRG(VDDRun);
0628 base->CTRL1 = tmp32;
0629 }
0630 else if (sel == kDCDC_VoltageOutput1P0)
0631 {
0632
0633 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0634
0635
0636 tmp32 = base->CTRL1 & ~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK;
0637
0638 tmp32 |= DCDC_CTRL1_VDD1P0CTRL_TRG(VDDRun);
0639 base->CTRL1 = tmp32;
0640 }
0641 else
0642 {
0643 ;
0644 }
0645
0646
0647
0648 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0649 {
0650 }
0651 }
0652
0653
0654
0655
0656
0657
0658
0659
0660
0661
0662
0663
0664
0665 void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel)
0666 {
0667 uint32_t tmp32;
0668
0669 if (sel == kDCDC_VoltageOutput1P8)
0670 {
0671
0672 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0673
0674
0675 tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK);
0676
0677 tmp32 |= DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(VDDStandby);
0678 base->CTRL1 = tmp32;
0679 }
0680 else if (sel == kDCDC_VoltageOutput1P0)
0681 {
0682
0683 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0684
0685
0686 tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK);
0687
0688 tmp32 |= DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(VDDStandby);
0689 base->CTRL1 = tmp32;
0690 }
0691 else
0692 {
0693 ;
0694 }
0695
0696
0697
0698 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0699 {
0700 }
0701 }
0702 #else
0703
0704
0705
0706
0707
0708
0709
0710
0711
0712
0713
0714
0715
0716
0717
0718 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
0719 {
0720 uint32_t tmp32;
0721
0722
0723 base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
0724
0725
0726 tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK);
0727
0728 tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun);
0729 base->REG3 = tmp32;
0730
0731
0732
0733 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0734 {
0735 }
0736 }
0737
0738
0739
0740
0741
0742
0743
0744
0745
0746
0747
0748
0749 void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun)
0750 {
0751 uint32_t tmp32;
0752
0753
0754 base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
0755
0756
0757 tmp32 = base->REG3 & ~DCDC_REG3_TRG_MASK;
0758
0759 tmp32 |= DCDC_REG3_TRG(VDDRun);
0760 base->REG3 = tmp32;
0761
0762
0763
0764 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0765 {
0766 }
0767 }
0768
0769
0770
0771
0772
0773
0774
0775
0776
0777
0778
0779
0780 void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby)
0781 {
0782 uint32_t tmp32;
0783
0784
0785 base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
0786
0787
0788 tmp32 = base->REG3 & ~DCDC_REG3_TARGET_LP_MASK;
0789
0790 tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby);
0791 base->REG3 = tmp32;
0792
0793
0794
0795 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0796 {
0797 }
0798 }
0799 #endif
0800
0801
0802
0803
0804
0805
0806
0807 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
0808 {
0809 assert(NULL != config);
0810
0811 uint32_t tmp32;
0812
0813 #if (defined(FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL) && FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL)
0814 tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;
0815 tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);
0816 base->REG3 = tmp32;
0817
0818 tmp32 = base->REG1 & ~DCDC_REG1_REG_RLOAD_SW_MASK;
0819 #else
0820
0821 tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK);
0822 tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint);
0823 #endif
0824
0825 if (config->enableLoadResistor)
0826 {
0827 tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK;
0828 }
0829 base->REG1 = tmp32;
0830 }
0831
0832 #if (defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK)
0833
0834
0835
0836
0837
0838
0839
0840
0841
0842 void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
0843 {
0844 assert(config != NULL);
0845
0846
0847 base->REG5 = config->enableDigLogicMap;
0848
0849
0850 base->REG6 = config->lowpowerMap;
0851 base->REG7 = config->standbyMap;
0852 base->REG7P = config->standbyLowpowerMap;
0853
0854
0855 base->REG8 = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage);
0856 base->REG9 = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage + 4U);
0857 base->REG10 = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage + 8U);
0858 base->REG11 = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage + 12U);
0859
0860
0861 base->REG12 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage);
0862 base->REG13 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage + 4U);
0863 base->REG14 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage + 8U);
0864 base->REG15 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage + 12U);
0865
0866
0867 base->REG16 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage);
0868 base->REG17 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage + 4U);
0869 base->REG18 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage + 8U);
0870 base->REG19 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage + 12U);
0871
0872
0873 base->REG20 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage);
0874 base->REG21 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage + 4U);
0875 base->REG22 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage + 8U);
0876 base->REG23 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage + 12U);
0877
0878
0879 base->REG4 = config->enableDCDCMap;
0880 }
0881 #endif
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893 void DCDC_BootIntoDCM(DCDC_Type *base)
0894 {
0895 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
0896 base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U) |
0897 DCDC_REG2_DCM_SET_CTRL_MASK;
0898 }
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908
0909 void DCDC_BootIntoCCM(DCDC_Type *base)
0910 {
0911 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
0912 base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
0913 }