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File indexing completed on 2025-05-11 08:22:58

0001 /*
0002  * Copyright 2017-2021, NXP
0003  * All rights reserved.
0004  *
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008 
0009 #include "fsl_dcdc.h"
0010 
0011 /* Component ID definition, used by tools. */
0012 #ifndef FSL_COMPONENT_ID
0013 #define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
0014 #endif
0015 
0016 /*******************************************************************************
0017  * Prototypes
0018  ******************************************************************************/
0019 /*!
0020  * @brief Get instance number for DCDC module.
0021  *
0022  * @param base DCDC peripheral base address
0023  */
0024 static uint32_t DCDC_GetInstance(DCDC_Type *base);
0025 
0026 #if (defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK)
0027 /*!
0028  * @brief Convert the byte array to word.
0029  *
0030  * @param ptrArray Pointer to the byte array.
0031  * @return The converted result.
0032  */
0033 static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray);
0034 #endif /* DCDC_REG4_ENABLE_SP_MASK */
0035 
0036 /*******************************************************************************
0037  * Variables
0038  ******************************************************************************/
0039 /*! @brief Pointers to DCDC bases for each instance. */
0040 static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS;
0041 
0042 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0043 /*! @brief Pointers to DCDC clocks for each instance. */
0044 static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS;
0045 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0046 
0047 /*******************************************************************************
0048  * Code
0049  ******************************************************************************/
0050 static uint32_t DCDC_GetInstance(DCDC_Type *base)
0051 {
0052     uint32_t instance;
0053 
0054     /* Find the instance index from base address mappings. */
0055     for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++)
0056     {
0057         if (s_dcdcBases[instance] == base)
0058         {
0059             break;
0060         }
0061     }
0062 
0063     assert(instance < ARRAY_SIZE(s_dcdcBases));
0064 
0065     return instance;
0066 }
0067 
0068 #if (defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK)
0069 static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray)
0070 {
0071     assert(ptrArray != NULL);
0072 
0073     uint32_t temp32 = 0UL;
0074     uint8_t index;
0075 
0076     for (index = 0U; index < 4U; index++)
0077     {
0078         temp32 |= ptrArray[index] << ((index % 4U) * 8U);
0079     }
0080 
0081     return temp32;
0082 }
0083 #endif /* DCDC_REG4_ENABLE_SP_MASK */
0084 
0085 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0086 /*!
0087  * brief Enable the access to DCDC registers.
0088  *
0089  * param base DCDC peripheral base address.
0090  * param config Pointer to the configuration structure.
0091  */
0092 void DCDC_Init(DCDC_Type *base, dcdc_config_t *config)
0093 {
0094 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0095     /* Enable the clock. */
0096     CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
0097 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0098     uint32_t tmp32 = base->CTRL0;
0099 
0100     tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode);
0101 
0102     if (config->enableDcdcTimeout)
0103     {
0104         tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;
0105     }
0106     if (config->enableSwitchingConverterOutput)
0107     {
0108         tmp32 |= DCDC_CTRL0_DIG_EN_MASK;
0109     }
0110     base->CTRL0 |= DCDC_CTRL0_ENABLE_MASK;
0111     base->CTRL0 = tmp32;
0112 }
0113 #else
0114 /*!
0115  * brief Enable the access to DCDC registers.
0116  *
0117  * param base DCDC peripheral base address.
0118  */
0119 void DCDC_Init(DCDC_Type *base)
0120 {
0121 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0122     /* Enable the clock. */
0123     CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
0124 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0125 }
0126 #endif /* FSL_FEATURE_DCDC_HAS_CTRL_REG */
0127 
0128 /*!
0129  * brief Disable the access to DCDC registers.
0130  *
0131  * param base DCDC peripheral base address.
0132  */
0133 void DCDC_Deinit(DCDC_Type *base)
0134 {
0135 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0136     /* Disable the clock. */
0137     CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
0138 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0139 }
0140 
0141 #if defined(FSL_FEATURE_DCDC_HAS_CTRL_REG) && FSL_FEATURE_DCDC_HAS_CTRL_REG
0142 /*!
0143  * brief Get the default setting for DCDC user configuration structure.
0144  *
0145  * This function initializes the user configuration structure to a default value. The default values are:
0146  * code
0147  *   config->controlMode                    = kDCDC_StaticControl;
0148  *   config->trimInputMode                  = kDCDC_SampleTrimInput;
0149  *   config->enableDcdcTimeout              = false;
0150  *   config->enableSwitchingConverterOutput = false;
0151  * endcode
0152  *
0153  * param config Pointer to configuration structure. See to "dcdc_config_t"
0154  */
0155 void DCDC_GetDefaultConfig(DCDC_Type *base, dcdc_config_t *config)
0156 {
0157     assert(NULL != config);
0158 
0159     /* Initializes the configure structure to zero. */
0160     (void)memset(config, 0, sizeof(*config));
0161 
0162     config->controlMode                    = kDCDC_StaticControl;
0163     config->trimInputMode                  = kDCDC_SampleTrimInput;
0164     config->enableDcdcTimeout              = false;
0165     config->enableSwitchingConverterOutput = false;
0166 }
0167 
0168 /*!
0169  * @brief Make DCDC enter into low power modes.
0170  *
0171  * @param base DCDC peripheral base address.
0172  * @param mode DCDC low power mode selection. See to "_dcdc_low_power_mode"
0173  */
0174 void DCDC_EnterLowPowerMode(DCDC_Type *base, dcdc_low_power_mode_t mode)
0175 {
0176     switch (mode)
0177     {
0178         case kDCDC_StandbyMode:
0179             base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK;
0180             break;
0181         case kDCDC_LowPowerMode:
0182             base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK;
0183             break;
0184         case kDCDC_GpcStandbyLowPowerMode:
0185             base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
0186             break;
0187         default:
0188             assert(false);
0189             break;
0190     }
0191 }
0192 #endif /* FSL_FEATURE_DCDC_HAS_CTRL_REG */
0193 
0194 /*!
0195  * brief Configure the DCDC clock source.
0196  *
0197  * param base DCDC peripheral base address.
0198  * param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
0199  */
0200 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
0201 {
0202     uint32_t tmp32;
0203 
0204     /* Configure the DCDC_REG0 register. */
0205     tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
0206                            DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
0207     switch (clockSource)
0208     {
0209         case kDCDC_ClockInternalOsc:
0210             tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;
0211             break;
0212         case kDCDC_ClockExternalOsc:
0213             /* Choose the external clock and disable the internal clock. */
0214             tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK;
0215             break;
0216         case kDCDC_ClockAutoSwitch:
0217             /* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */
0218             tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;
0219             break;
0220         default:
0221             assert(false);
0222             break;
0223     }
0224     base->REG0 = tmp32;
0225 }
0226 
0227 /*!
0228  * brief Get the default setting for detection configuration.
0229  *
0230  * The default configuration are set according to responding registers' setting when powered on.
0231  * They are:
0232  * code
0233  *   config->enableXtalokDetection = false;
0234  *   config->powerDownOverVoltageDetection = true;
0235  *   config->powerDownLowVlotageDetection = false;
0236  *   config->powerDownOverCurrentDetection = true;
0237  *   config->powerDownPeakCurrentDetection = true;
0238  *   config->powerDownZeroCrossDetection = true;
0239  *   config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
0240  *   config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
0241  * endcode
0242  *
0243  * param config Pointer to configuration structure. See to "dcdc_detection_config_t"
0244  */
0245 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
0246 {
0247     assert(NULL != config);
0248 
0249     /* Initializes the configure structure to zero. */
0250     (void)memset(config, 0, sizeof(*config));
0251 
0252     config->enableXtalokDetection = false;
0253 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0254     config->powerDownOverVoltageVdd1P8Detection = true;
0255     config->powerDownOverVoltageVdd1P0Detection = true;
0256 #else
0257     config->powerDownOverVoltageDetection = true;
0258 #endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
0259     config->powerDownLowVlotageDetection  = false;
0260     config->powerDownOverCurrentDetection = true;
0261     config->powerDownPeakCurrentDetection = true;
0262     config->powerDownZeroCrossDetection   = true;
0263     config->OverCurrentThreshold          = kDCDC_OverCurrentThresholdAlt0;
0264     config->PeakCurrentThreshold          = kDCDC_PeakCurrentThresholdAlt0;
0265 }
0266 
0267 /*!
0268  * breif Configure the DCDC detection.
0269  *
0270  * param base DCDC peripheral base address.
0271  * param config Pointer to configuration structure. See to "dcdc_detection_config_t"
0272  */
0273 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
0274 {
0275     assert(NULL != config);
0276 
0277     uint32_t tmp32;
0278     /* Configure the DCDC_REG0 register. */
0279     tmp32 = base->REG0 & ~(DCDC_REG0_XTALOK_DISABLE_MASK
0280 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0281                            | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK
0282 #else
0283                            | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK
0284 #endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
0285 #if defined(FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET) && FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET
0286                            | DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK
0287 #else
0288                            | DCDC_REG0_PWD_CMP_BATT_DET_MASK
0289 #endif /* FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET */
0290                            | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | DCDC_REG0_PWD_ZCD_MASK |
0291                            DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK);
0292 
0293     tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) |
0294              DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold);
0295     if (false == config->enableXtalokDetection)
0296     {
0297         tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
0298     }
0299 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0300     if (config->powerDownOverVoltageVdd1P8Detection)
0301     {
0302         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;
0303     }
0304     if (config->powerDownOverVoltageVdd1P0Detection)
0305     {
0306         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;
0307     }
0308 #else
0309     if (config->powerDownOverVoltageDetection)
0310     {
0311         tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK;
0312     }
0313 #endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT */
0314     if (config->powerDownLowVlotageDetection)
0315     {
0316 #if defined(FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET) && FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET
0317         tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;
0318 #else
0319         tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK;
0320 #endif /* FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET */
0321     }
0322     if (config->powerDownOverCurrentDetection)
0323     {
0324         tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;
0325     }
0326     if (config->powerDownPeakCurrentDetection)
0327     {
0328         tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;
0329     }
0330     if (config->powerDownZeroCrossDetection)
0331     {
0332         tmp32 |= DCDC_REG0_PWD_ZCD_MASK;
0333     }
0334     base->REG0 = tmp32;
0335 }
0336 
0337 /*!
0338  * brief Get the default setting for low power configuration.
0339  *
0340  * The default configuration are set according to responding registers' setting when powered on.
0341  * They are:
0342  * code
0343  *   config->enableOverloadDetection = true;
0344  *   config->enableAdjustHystereticValue = false;
0345  *   config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
0346  *   config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
0347  * endcode
0348  *
0349  * param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
0350  */
0351 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
0352 {
0353     assert(NULL != config);
0354 
0355     /* Initializes the configure structure to zero. */
0356     (void)memset(config, 0, sizeof(*config));
0357 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0358     config->enableOverloadDetection = true;
0359 #endif /* FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS */
0360     config->enableAdjustHystereticValue = false;
0361     config->countChargingTimePeriod     = kDCDC_CountChargingTimePeriod8Cycle;
0362     config->countChargingTimeThreshold  = kDCDC_CountChargingTimeThreshold32;
0363 }
0364 
0365 /*!
0366  * brief Configure the DCDC low power.
0367  *
0368  * param base DCDC peripheral base address.
0369  * param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
0370  */
0371 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
0372 {
0373     assert(NULL != config);
0374 
0375     uint32_t tmp32;
0376     /* Configure the DCDC_REG0 register. */
0377     tmp32 = base->REG0 &
0378             ~(DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK
0379 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0380               | DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK
0381 #endif /* FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS */
0382             );
0383     tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |
0384              DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold);
0385 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS) && FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS)
0386     if (config->enableOverloadDetection)
0387     {
0388         tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK;
0389     }
0390 #endif /* FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS */
0391     if (config->enableAdjustHystereticValue)
0392     {
0393         tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
0394     }
0395     base->REG0 = tmp32;
0396 }
0397 
0398 /*!
0399  * brief Get DCDC status flags.
0400  *
0401  * param base peripheral base address.
0402  * return Mask of asserted status flags. See to "_dcdc_status_flags_t".
0403  */
0404 uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
0405 {
0406     uint32_t tmp32 = 0U;
0407 
0408     if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0409     {
0410         tmp32 |= (uint32_t)kDCDC_LockedOKStatus;
0411     }
0412 
0413     return tmp32;
0414 }
0415 
0416 #if !(defined(FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC) && FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC)
0417 /*!
0418  * brief Reset current alert signal. Alert signal is generate by peak current detection.
0419  *
0420  * param base DCDC peripheral base address.
0421  * param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
0422  */
0423 void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
0424 {
0425     if (enable)
0426     {
0427         base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK;
0428     }
0429     else
0430     {
0431         base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK;
0432     }
0433 }
0434 #endif /* FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC */
0435 
0436 /*!
0437  * brief Get the default setting for loop control configuration.
0438  *
0439  * The default configuration are set according to responding registers' setting when powered on.
0440  * They are:
0441  * code
0442  *   config->enableCommonHysteresis = false;
0443  *   config->enableCommonThresholdDetection = false;
0444  *   config->enableInvertHysteresisSign = false;
0445  *   config->enableRCThresholdDetection = false;
0446  *   config->enableRCScaleCircuit = 0U;
0447  *   config->complementFeedForwardStep = 0U;
0448  * endcode
0449  *
0450  * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
0451  */
0452 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
0453 {
0454     assert(NULL != config);
0455 
0456     /* Initializes the configure structure to zero. */
0457     (void)memset(config, 0, sizeof(*config));
0458 
0459     config->enableCommonHysteresis         = false;
0460     config->enableCommonThresholdDetection = false;
0461     config->enableInvertHysteresisSign     = false;
0462     config->enableRCThresholdDetection     = false;
0463     config->enableRCScaleCircuit           = 0U;
0464     config->complementFeedForwardStep      = 0U;
0465 }
0466 
0467 /*!
0468  * brief Configure the DCDC loop control.
0469  *
0470  * param base DCDC peripheral base address.
0471  * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
0472  */
0473 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
0474 {
0475     assert(NULL != config);
0476 
0477     uint32_t tmp32;
0478 
0479     /* Configure the DCDC_REG1 register. */
0480 #if defined(FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE) && \
0481     FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE
0482     tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |
0483                            DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK);
0484     if (config->enableCommonHysteresis)
0485     {
0486         tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;
0487     }
0488     if (config->enableCommonThresholdDetection)
0489     {
0490         tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;
0491     }
0492     if (config->enableDifferentialHysteresis)
0493     {
0494         tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;
0495     }
0496     if (config->enableDifferentialThresholdDetection)
0497     {
0498         tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;
0499     }
0500 #else
0501     tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK);
0502     if (config->enableCommonHysteresis)
0503     {
0504         tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK;
0505     }
0506     if (config->enableCommonThresholdDetection)
0507     {
0508         tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK;
0509     }
0510 #endif /* FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE */
0511     base->REG1 = tmp32;
0512 
0513     /* configure the DCDC_REG2 register. */
0514     tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
0515                            DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK);
0516     tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
0517              DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit);
0518     if (config->enableInvertHysteresisSign)
0519     {
0520         tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;
0521     }
0522     if (config->enableRCThresholdDetection)
0523     {
0524         tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;
0525     }
0526     base->REG2 = tmp32;
0527 }
0528 
0529 /*!
0530  * brief Configure for the min power.
0531  *
0532  * param base DCDC peripheral base address.
0533  * param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
0534  */
0535 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
0536 {
0537     assert(NULL != config);
0538 
0539     uint32_t tmp32;
0540 
0541     tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
0542     if (config->enableUseHalfFreqForContinuous)
0543     {
0544         tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
0545     }
0546     base->REG3 = tmp32;
0547 }
0548 
0549 #if (defined(FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT) && (FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2))
0550 /*!
0551  * brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
0552  * Do not use this function. It has been superceded by DCDC_AdjustRunTargetVoltage
0553  * and DCDC_AdjustLowPowerTargetVoltage.
0554  *
0555  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0556  * stabled.
0557  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0558  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0559  *
0560  * param base DCDC peripheral base address.
0561  * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0562  * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0563  * param sel sel DCDC target voltage output selection. See to "_dcdc_voltage_output_sel".
0564  */
0565 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel)
0566 {
0567     uint32_t tmp32;
0568 
0569     if (sel == kDCDC_VoltageOutput1P8)
0570     {
0571         /* Unlock the step for the VDD 1P8. */
0572         base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0573 
0574         /* Configure the DCDC_CTRL1 register. */
0575         tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK | DCDC_CTRL1_VDD1P8CTRL_TRG_MASK);
0576 
0577         tmp32 |= DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(VDDStandby) | DCDC_CTRL1_VDD1P8CTRL_TRG(VDDRun);
0578         base->CTRL1 = tmp32;
0579     }
0580     else if (sel == kDCDC_VoltageOutput1P0)
0581     {
0582         /* Unlock the step for the VDD 1P0. */
0583         base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0584 
0585         /* Configure the DCDC_CTRL1 register. */
0586         tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK | DCDC_CTRL1_VDD1P0CTRL_TRG_MASK);
0587 
0588         tmp32 |= DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(VDDStandby) | DCDC_CTRL1_VDD1P0CTRL_TRG(VDDRun);
0589         base->CTRL1 = tmp32;
0590     }
0591     else
0592     {
0593         ; /* Intentional empty */
0594     }
0595 
0596     /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage is set to new
0597      * target value, DCDC_STS_DC_OK will be asserted. */
0598     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0599     {
0600     }
0601 }
0602 
0603 /*!
0604  * brief Adjust the target voltage of VDD_SOC in run mode.
0605  *
0606  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0607  * stabled.
0608  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0609  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0610  *
0611  * param base DCDC peripheral base address.
0612  * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0613  * param sel sel DCDC target voltage output selection. See to "_dcdc_voltage_output_sel".
0614  */
0615 void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun, dcdc_voltage_output_sel_t sel)
0616 {
0617     uint32_t tmp32;
0618 
0619     if (sel == kDCDC_VoltageOutput1P8)
0620     {
0621         /* Unlock the step for the VDD 1P8. */
0622         base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0623 
0624         /* Configure the DCDC_CTRL1 register. */
0625         tmp32 = base->CTRL1 & ~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK;
0626 
0627         tmp32 |= DCDC_CTRL1_VDD1P8CTRL_TRG(VDDRun);
0628         base->CTRL1 = tmp32;
0629     }
0630     else if (sel == kDCDC_VoltageOutput1P0)
0631     {
0632         /* Unlock the step for the VDD 1P0. */
0633         base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0634 
0635         /* Configure the DCDC_CTRL1 register. */
0636         tmp32 = base->CTRL1 & ~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK;
0637 
0638         tmp32 |= DCDC_CTRL1_VDD1P0CTRL_TRG(VDDRun);
0639         base->CTRL1 = tmp32;
0640     }
0641     else
0642     {
0643         ; /* Intentional empty */
0644     }
0645 
0646     /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage is set to new
0647      * target value, DCDC_STS_DC_OK will be asserted. */
0648     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0649     {
0650     }
0651 }
0652 
0653 /*!
0654  * brief Adjust the target voltage of VDD_SOC in low power mode.
0655  *
0656  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0657  * stabled.
0658  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0659  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0660  *
0661  * param base DCDC peripheral base address.
0662  * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0663  * param sel sel DCDC target voltage output selection. See to "_dcdc_voltage_output_sel".
0664  */
0665 void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby, dcdc_voltage_output_sel_t sel)
0666 {
0667     uint32_t tmp32;
0668 
0669     if (sel == kDCDC_VoltageOutput1P8)
0670     {
0671         /* Unlock the step for the VDD 1P8. */
0672         base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
0673 
0674         /* Configure the DCDC_CTRL1 register. */
0675         tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK);
0676 
0677         tmp32 |= DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(VDDStandby);
0678         base->CTRL1 = tmp32;
0679     }
0680     else if (sel == kDCDC_VoltageOutput1P0)
0681     {
0682         /* Unlock the step for the VDD 1P0. */
0683         base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
0684 
0685         /* Configure the DCDC_CTRL1 register. */
0686         tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK);
0687 
0688         tmp32 |= DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(VDDStandby);
0689         base->CTRL1 = tmp32;
0690     }
0691     else
0692     {
0693         ; /* Intentional empty */
0694     }
0695 
0696     /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage is set to new
0697      * target value, DCDC_STS_DC_OK will be asserted. */
0698     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0699     {
0700     }
0701 }
0702 #else
0703 
0704 /*!
0705  * brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
0706  * Do not use this function. It has been superceded by DCDC_AdjustRunTargetVoltage
0707  * and DCDC_AdjustLowPowerTargetVoltage
0708  *
0709  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0710  * stabled.
0711  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0712  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0713  *
0714  * param base DCDC peripheral base address.
0715  * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0716  * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0717  */
0718 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
0719 {
0720     uint32_t tmp32;
0721 
0722     /* Unlock the step for the output. */
0723     base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
0724 
0725     /* Configure the DCDC_REG3 register. */
0726     tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK);
0727 
0728     tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun);
0729     base->REG3 = tmp32;
0730 
0731     /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage is set to new
0732      * target value, DCDC_STS_DC_OK will be asserted. */
0733     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0734     {
0735     }
0736 }
0737 
0738 /*!
0739  * brief Adjust the target voltage of VDD_SOC in run mode.
0740  *
0741  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0742  * stabled.
0743  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0744  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0745  *
0746  * param base DCDC peripheral base address.
0747  * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
0748  */
0749 void DCDC_AdjustRunTargetVoltage(DCDC_Type *base, uint32_t VDDRun)
0750 {
0751     uint32_t tmp32;
0752 
0753     /* Unlock the step for the output. */
0754     base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
0755 
0756     /* Configure the DCDC_REG3 register. */
0757     tmp32 = base->REG3 & ~DCDC_REG3_TRG_MASK;
0758 
0759     tmp32 |= DCDC_REG3_TRG(VDDRun);
0760     base->REG3 = tmp32;
0761 
0762     /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage is set to new
0763      * target value, DCDC_STS_DC_OK will be asserted. */
0764     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0765     {
0766     }
0767 }
0768 
0769 /*!
0770  * brief Adjust the target voltage of VDD_SOC in low power mode.
0771  *
0772  * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
0773  * stabled.
0774  * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
0775  * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
0776  *
0777  * param base DCDC peripheral base address.
0778  * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
0779  */
0780 void DCDC_AdjustLowPowerTargetVoltage(DCDC_Type *base, uint32_t VDDStandby)
0781 {
0782     uint32_t tmp32;
0783 
0784     /* Unlock the step for the output. */
0785     base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
0786 
0787     /* Configure the DCDC_REG3 register. */
0788     tmp32 = base->REG3 & ~DCDC_REG3_TARGET_LP_MASK;
0789 
0790     tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby);
0791     base->REG3 = tmp32;
0792 
0793     /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage is set to new
0794      * target value, DCDC_STS_DC_OK will be asserted. */
0795     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
0796     {
0797     }
0798 }
0799 #endif /* FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT == 2 */
0800 
0801 /*!
0802  * brief Configure the DCDC internal regulator.
0803  *
0804  * param base DCDC peripheral base address.
0805  * param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
0806  */
0807 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
0808 {
0809     assert(NULL != config);
0810 
0811     uint32_t tmp32;
0812 
0813 #if (defined(FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL) && FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL)
0814     tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;
0815     tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);
0816     base->REG3 = tmp32;
0817 
0818     tmp32 = base->REG1 & ~DCDC_REG1_REG_RLOAD_SW_MASK;
0819 #else
0820     /* Configure the DCDC_REG1 register. */
0821     tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK);
0822     tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint);
0823 #endif /* FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL */
0824 
0825     if (config->enableLoadResistor)
0826     {
0827         tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK;
0828     }
0829     base->REG1 = tmp32;
0830 }
0831 
0832 #if (defined(DCDC_REG4_ENABLE_SP_MASK) && DCDC_REG4_ENABLE_SP_MASK)
0833 /*!
0834  * brief Init DCDC module when the control mode selected as setpoint mode.
0835  *
0836  * note The function should be invoked in the initial step to config the
0837  *      DCDC via setpoint control mode.
0838  *
0839  * param base DCDC peripheral base address.
0840  * param config The pointer to the structure @ref dcdc_setpoint_config_t.
0841  */
0842 void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
0843 {
0844     assert(config != NULL);
0845 
0846     /* Enable DCDC Dig Logic. */
0847     base->REG5 = config->enableDigLogicMap;
0848 
0849     /* Set DCDC power mode. */
0850     base->REG6  = config->lowpowerMap;
0851     base->REG7  = config->standbyMap;
0852     base->REG7P = config->standbyLowpowerMap;
0853 
0854     /* Set target voltage of VDD1P8 in buck mode. */
0855     base->REG8  = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage);
0856     base->REG9  = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage + 4U);
0857     base->REG10 = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage + 8U);
0858     base->REG11 = DCDC_ConvertByteArrayToWord(config->buckVDD1P8TargetVoltage + 12U);
0859 
0860     /* Set target voltage of VDD1P0 in buck mode. */
0861     base->REG12 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage);
0862     base->REG13 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage + 4U);
0863     base->REG14 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage + 8U);
0864     base->REG15 = DCDC_ConvertByteArrayToWord(config->buckVDD1P0TargetVoltage + 12U);
0865 
0866     /* Set target voltage of VDD1P8 in low power mode. */
0867     base->REG16 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage);
0868     base->REG17 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage + 4U);
0869     base->REG18 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage + 8U);
0870     base->REG19 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P8TargetVoltage + 12U);
0871 
0872     /* Set target voltage of VDD1P0 in low power mode. */
0873     base->REG20 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage);
0874     base->REG21 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage + 4U);
0875     base->REG22 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage + 8U);
0876     base->REG23 = DCDC_ConvertByteArrayToWord(config->standbyVDD1P0TargetVoltage + 12U);
0877 
0878     /* Enable DCDC module. */
0879     base->REG4 = config->enableDCDCMap;
0880 }
0881 #endif /* DCDC_REG4_ENABLE_SP_MASK */
0882 
0883 /*!
0884  * brief Boot DCDC into DCM(discontinous conduction mode).
0885  *
0886  *  pwd_zcd=0x0;
0887  *  pwd_cmp_offset=0x0;
0888  *  dcdc_loopctrl_en_rcscale= 0x5;
0889  *  DCM_set_ctrl=1'b1;
0890  *
0891  * param base DCDC peripheral base address.
0892  */
0893 void DCDC_BootIntoDCM(DCDC_Type *base)
0894 {
0895     base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
0896     base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U) |
0897                  DCDC_REG2_DCM_SET_CTRL_MASK;
0898 }
0899 
0900 /*!
0901  * brief Boot DCDC into CCM(continous conduction mode).
0902  *
0903  *  pwd_zcd=0x1;
0904  *  pwd_cmp_offset=0x0;
0905  *  dcdc_loopctrl_en_rcscale=0x3;
0906  *
0907  * param base DCDC peripheral base address.
0908  */
0909 void DCDC_BootIntoCCM(DCDC_Type *base)
0910 {
0911     base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
0912     base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
0913 }