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File indexing completed on 2025-05-11 08:22:58
0001 /* 0002 * Copyright (c) 2016, Freescale Semiconductor, Inc. 0003 * Copyright 2016-2021 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 0009 #ifndef _FSL_DAC12_H_ 0010 #define _FSL_DAC12_H_ 0011 0012 #include "fsl_common.h" 0013 0014 /*! 0015 * @addtogroup dac12 0016 * @{ 0017 */ 0018 0019 /*! @file */ 0020 0021 /******************************************************************************* 0022 * Definitions 0023 ******************************************************************************/ 0024 0025 /*! @name Driver version */ 0026 /*@{*/ 0027 /*! @brief DAC12 driver version 2.1.0. */ 0028 #define FSL_DAC12_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) 0029 /*@}*/ 0030 0031 /*! @brief Define "write 1 to clear" flags. */ 0032 #define DAC12_CR_W1C_FLAGS_MASK (DAC_CR_OVFF_MASK | DAC_CR_UDFF_MASK) 0033 /*! @brief Define all the flag bits in DACx_CR register. */ 0034 #define DAC12_CR_ALL_FLAGS_MASK (DAC12_CR_W1C_FLAGS_MASK | DAC_CR_WMF_MASK | DAC_CR_NEMPTF_MASK | DAC_CR_FULLF_MASK) 0035 0036 /*! 0037 * @brief DAC12 flags. 0038 */ 0039 enum _dac12_status_flags 0040 { 0041 kDAC12_OverflowFlag = DAC_CR_OVFF_MASK, /*!< FIFO overflow status flag, which indicates that more data has been 0042 written into FIFO than it can hold. */ 0043 kDAC12_UnderflowFlag = DAC_CR_UDFF_MASK, /*!< FIFO underflow status flag, which means that there is a new trigger 0044 after the FIFO is nearly empty. */ 0045 kDAC12_WatermarkFlag = DAC_CR_WMF_MASK, /*!< FIFO wartermark status flag, which indicates the remaining FIFO data is 0046 less than the watermark setting. */ 0047 kDAC12_NearlyEmptyFlag = DAC_CR_NEMPTF_MASK, /*!< FIFO nearly empty flag, which means there is only one data 0048 remaining in FIFO. */ 0049 kDAC12_FullFlag = DAC_CR_FULLF_MASK /*!< FIFO full status flag, which means that the FIFO read pointer equals the 0050 write pointer, as the write pointer increase. */ 0051 }; 0052 0053 /*! 0054 * @brief DAC12 interrupts. 0055 */ 0056 enum _dac12_interrupt_enable 0057 { 0058 kDAC12_UnderOrOverflowInterruptEnable = DAC_CR_UVIE_MASK, /*!< Underflow and overflow interrupt enable. */ 0059 kDAC12_WatermarkInterruptEnable = DAC_CR_WTMIE_MASK, /*!< Watermark interrupt enable. */ 0060 kDAC12_NearlyEmptyInterruptEnable = DAC_CR_EMPTIE_MASK, /*!< Nearly empty interrupt enable. */ 0061 kDAC12_FullInterruptEnable = DAC_CR_FULLIE_MASK /*!< Full interrupt enable. */ 0062 }; 0063 0064 /*! 0065 * @brief DAC12 FIFO size information provided by hardware. 0066 */ 0067 typedef enum _dac12_fifo_size_info 0068 { 0069 kDAC12_FIFOSize2 = 0U, /*!< FIFO depth is 2. */ 0070 kDAC12_FIFOSize4 = 1U, /*!< FIFO depth is 4. */ 0071 kDAC12_FIFOSize8 = 2U, /*!< FIFO depth is 8. */ 0072 kDAC12_FIFOSize16 = 3U, /*!< FIFO depth is 16. */ 0073 kDAC12_FIFOSize32 = 4U, /*!< FIFO depth is 32. */ 0074 kDAC12_FIFOSize64 = 5U, /*!< FIFO depth is 64. */ 0075 kDAC12_FIFOSize128 = 6U, /*!< FIFO depth is 128. */ 0076 kDAC12_FIFOSize256 = 7U, /*!< FIFO depth is 256. */ 0077 } dac12_fifo_size_info_t; 0078 0079 /*! 0080 * @brief DAC12 FIFO work mode. 0081 */ 0082 typedef enum _dac12_fifo_work_mode 0083 { 0084 kDAC12_FIFODisabled = 0U, /*!< FIFO disabled and only one level buffer is enabled. Any data written from this buffer 0085 goes to conversion. */ 0086 kDAC12_FIFOWorkAsNormalMode = 1U, /*!< Data will first read from FIFO to buffer then go to conversion. */ 0087 kDAC12_FIFOWorkAsSwingMode = 2U /*!< In Swing mode, the FIFO must be set up to be full. In Swing back mode, a 0088 trigger changes the read pointer to make it swing between the FIFO Full and 0089 Nearly Empty state. That is, the trigger increases the read pointer till FIFO 0090 is nearly empty and decreases the read pointer till the FIFO is full. */ 0091 } dac12_fifo_work_mode_t; 0092 0093 /*! 0094 * @brief DAC12 reference voltage source. 0095 */ 0096 typedef enum _dac12_reference_voltage_source 0097 { 0098 kDAC12_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ 0099 kDAC12_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ 0100 } dac12_reference_voltage_source_t; 0101 0102 /*! 0103 * @brief DAC12 FIFO trigger mode. 0104 */ 0105 typedef enum _dac12_fifo_trigger_mode 0106 { 0107 kDAC12_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ 0108 kDAC12_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ 0109 } dac12_fifo_trigger_mode_t; 0110 0111 /*! 0112 * @brief DAC internal reference current source. 0113 * 0114 * Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by 0115 * on-chip PMC's "reference part". If no current reference be selected, analog module can’t working normally ,even when 0116 * other register can still be assigned, DAC would waste current but no function. 0117 * To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected. 0118 */ 0119 typedef enum _dac12_reference_current_source 0120 { 0121 kDAC12_ReferenceCurrentSourceDisabled = 0U, /*!< None of reference current source is enabled. */ 0122 kDAC12_ReferenceCurrentSourceAlt0 = 1U, /*!< Use the internal reference current generated by the module itself. */ 0123 kDAC12_ReferenceCurrentSourceAlt1 = 2U, /*!< Use the ZTC(Zero Temperature Coefficient) reference current generated 0124 by on-chip power management module. */ 0125 kDAC12_ReferenceCurrentSourceAlt2 = 3U, /*!< Use the PTAT(Proportional To Absolution Temperature) reference current 0126 generated by power management module. */ 0127 } dac12_reference_current_source_t; 0128 0129 /*! 0130 * @brief DAC analog buffer speed mode for conversion. 0131 */ 0132 typedef enum _dac12_speed_mode 0133 { 0134 kDAC12_SpeedLowMode = 0U, /*!< Low speed mode. */ 0135 kDAC12_SpeedMiddleMode = 1U, /*!< Middle speed mode. */ 0136 kDAC12_SpeedHighMode = 2U, /*!< High speed mode. */ 0137 } dac12_speed_mode_t; 0138 0139 /*! 0140 * @brief DAC12 hardware information. 0141 */ 0142 typedef struct _dac12_hardware_info 0143 { 0144 dac12_fifo_size_info_t fifoSizeInfo; /*!< The number of words in this device's DAC buffer. */ 0145 } dac12_hardware_info_t; 0146 0147 /*! 0148 * @brief DAC12 module configuration. 0149 * 0150 * Actually, the most fields are for FIFO buffer. 0151 */ 0152 typedef struct 0153 { 0154 uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ 0155 dac12_fifo_work_mode_t fifoWorkMode; /*!< FIFI's work mode about pointers. */ 0156 dac12_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ 0157 dac12_fifo_trigger_mode_t fifoTriggerMode; /*! Select the trigger mode for FIFO. */ 0158 0159 /* Analog part configuration. */ 0160 dac12_reference_current_source_t referenceCurrentSource; /*!< Select the reference current source. */ 0161 dac12_speed_mode_t speedMode; /*!< Select the speed mode for conversion. */ 0162 bool enableAnalogBuffer; /*!< Enable analog buffer for high drive. */ 0163 #if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) 0164 uint32_t currentReferenceInternalTrimValue; /*!< Internal reference current trim value. 3-bit value is available.*/ 0165 #endif /* FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER */ 0166 } dac12_config_t; 0167 0168 /******************************************************************************* 0169 * API 0170 ******************************************************************************/ 0171 #if defined(__cplusplus) 0172 extern "C" { 0173 #endif 0174 0175 /*! 0176 * @name Initialization and de-initialization 0177 * @{ 0178 */ 0179 0180 /*! 0181 * @brief Get hardware information about this module. 0182 * 0183 * @param base DAC12 peripheral base address. 0184 * @param info Pointer to info structure, see to #dac12_hardware_info_t. 0185 */ 0186 void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info); 0187 0188 /*! 0189 * @brief Initialize the DAC12 module. 0190 * 0191 * @param base DAC12 peripheral base address. 0192 * @param config Pointer to configuration structure, see to #dac12_config_t. 0193 */ 0194 void DAC12_Init(DAC_Type *base, const dac12_config_t *config); 0195 0196 /*! 0197 * @brief Initializes the DAC12 user configuration structure. 0198 * 0199 * This function initializes the user configuration structure to a default value. The default values are: 0200 * @code 0201 * config->fifoWatermarkLevel = 0U; 0202 * config->fifoWorkMode = kDAC12_FIFODisabled; 0203 * config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1; 0204 * config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode; 0205 * config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0; 0206 * config->speedMode = kDAC12_SpeedLowMode; 0207 * config->speedMode = false; 0208 * config->currentReferenceInternalTrimValue = 0x4; 0209 * @endcode 0210 * @param config Pointer to the configuration structure. See "dac12_config_t". 0211 */ 0212 void DAC12_GetDefaultConfig(dac12_config_t *config); 0213 0214 /*! 0215 * @brief De-initialize the DAC12 module. 0216 * 0217 * @param base DAC12 peripheral base address. 0218 */ 0219 void DAC12_Deinit(DAC_Type *base); 0220 0221 /*! 0222 * @brief Enable the DAC12's converter or not. 0223 * 0224 * @param base DAC12 peripheral base address. 0225 * @param enable Enable the DAC12's converter or not. 0226 */ 0227 static inline void DAC12_Enable(DAC_Type *base, bool enable) 0228 { 0229 if (enable) 0230 { 0231 base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DACEN_MASK; 0232 } 0233 else 0234 { 0235 base->CR &= ~DAC_CR_DACEN_MASK; 0236 } 0237 } 0238 0239 /*! 0240 * @brief Reset all internal logic and registers. 0241 * 0242 * @param base DAC12 peripheral base address. 0243 */ 0244 static inline void DAC12_ResetConfig(DAC_Type *base) 0245 { 0246 base->CR = DAC_CR_SWRST_MASK; 0247 } 0248 0249 /*! 0250 * @brief Reset the FIFO pointers. 0251 * 0252 * FIFO pointers should only be reset when the DAC12 is disabled. This function can be used to configure both pointers 0253 * to the same address to reset the FIFO as empty. 0254 * 0255 * @param base DAC12 peripheral base address. 0256 */ 0257 static inline void DAC12_ResetFIFO(DAC_Type *base) 0258 { 0259 /* FIFO pointers should only be reset when the module is disabled. */ 0260 base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_FIFORST_MASK; 0261 } 0262 0263 /* @} */ 0264 0265 /*! 0266 * @name Status 0267 * @{ 0268 */ 0269 0270 /*! 0271 * @brief Get status flags. 0272 * 0273 * @param base DAC12 peripheral base address. 0274 * @return Mask of current status flags. See to #_dac12_status_flags. 0275 */ 0276 static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base) 0277 { 0278 return (DAC12_CR_ALL_FLAGS_MASK & base->CR); 0279 } 0280 0281 /*! 0282 * @brief Clear status flags. 0283 * 0284 * Note: Not all the flags can be cleared by this API. Several flags need special condition to clear them according to 0285 * target chip's reference manual document. 0286 * 0287 * @param base DAC12 peripheral base address. 0288 * @param flags Mask of status flags to be cleared. See to #_dac12_status_flags. 0289 */ 0290 static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags) 0291 { 0292 base->CR |= (flags & DAC12_CR_W1C_FLAGS_MASK); 0293 } 0294 0295 /* @} */ 0296 0297 /*! 0298 * @name Interrupts 0299 * @{ 0300 */ 0301 0302 /*! 0303 * @brief Enable interrupts. 0304 * 0305 * @param base DAC12 peripheral base address. 0306 * @param mask Mask value of interrupts to be enabled. See to #_dac12_interrupt_enable. 0307 */ 0308 static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask) 0309 { 0310 base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | mask; 0311 } 0312 0313 /*! 0314 * @brief Disable interrupts. 0315 * 0316 * @param base DAC12 peripheral base address. 0317 * @param mask Mask value of interrupts to be disabled. See to #_dac12_interrupt_enable. 0318 */ 0319 static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask) 0320 { 0321 base->CR &= ~mask; 0322 } 0323 0324 /* @} */ 0325 0326 /*! 0327 * @name DMA control 0328 * @{ 0329 */ 0330 0331 /*! 0332 * @brief Enable DMA or not. 0333 * 0334 * When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented 0335 * on this module at the same time. 0336 */ 0337 static inline void DAC12_EnableDMA(DAC_Type *base, bool enable) 0338 { 0339 if (enable) 0340 { 0341 base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DMAEN_MASK; 0342 } 0343 else 0344 { 0345 base->CR &= ~DAC_CR_DMAEN_MASK; 0346 } 0347 } 0348 0349 /* @} */ 0350 0351 /*! 0352 * @name Functional feature 0353 * @{ 0354 */ 0355 0356 /*! 0357 * @brief Set data into the entry of FIFO buffer. 0358 * 0359 * When the DAC FIFO is disabled, and the one entry buffer is enabled, the DAC converts the data in the buffer to analog 0360 * output voltage. Any write to the DATA register will replace the data in the buffer and push data to analog conversion 0361 * without trigger support. 0362 * When the DAC FIFO is enabled. Writing data would increase the write pointer of FIFO. Also, the data would be restored 0363 * into the FIFO buffer. 0364 * 0365 * @param base DAC12 peripheral base address. 0366 * @param value Setting value into FIFO buffer. 0367 */ 0368 static inline void DAC12_SetData(DAC_Type *base, uint32_t value) 0369 { 0370 /* The module is connected internally to a 32-bit interface. 0371 * For the 8-bit or 16-bit, the write might be ignored. */ 0372 base->DATA = DAC_DATA_DATA0(value); 0373 } 0374 0375 /*! 0376 * @brief Do trigger the FIFO by software. 0377 * 0378 * When the DAC FIFO is enabled, and software trigger is used. Doing trigger would increase the read pointer, and the 0379 * data in the entry pointed by read pointer would be converted as new output. 0380 * 0381 * @param base DAC12 peripheral base address. 0382 */ 0383 static inline void DAC12_DoSoftwareTrigger(DAC_Type *base) 0384 { 0385 base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_SWTRG_MASK; 0386 } 0387 0388 /*! 0389 * @brief Get the current read pointer of FIFO. 0390 * 0391 * @param base DAC12 peripheral base address. 0392 * @return Read pointer index of FIFO buffer. 0393 */ 0394 static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base) 0395 { 0396 return (DAC_PTR_DACRFP_MASK & base->PTR) >> DAC_PTR_DACRFP_SHIFT; 0397 } 0398 0399 /*! 0400 * @brief Get the current write pointer of FIFO. 0401 * 0402 * @param base DAC12 peripheral base address. 0403 * @return Write pointer index of FIFO buffer 0404 */ 0405 static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base) 0406 { 0407 return (DAC_PTR_DACWFP_MASK & base->PTR) >> DAC_PTR_DACWFP_SHIFT; 0408 } 0409 0410 /* @} */ 0411 0412 #if defined(__cplusplus) 0413 } 0414 #endif 0415 /*! 0416 * @} 0417 */ 0418 #endif /* _FSL_DAC12_H_ */
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