File indexing completed on 2025-05-11 08:22:58
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0009 #include "fsl_dac12.h"
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0011
0012 #ifndef FSL_COMPONENT_ID
0013 #define FSL_COMPONENT_ID "platform.drivers.dac12"
0014 #endif
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0025 static uint32_t DAC12_GetInstance(DAC_Type *base);
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0031 static DAC_Type *const s_dac12Bases[] = DAC_BASE_PTRS;
0032 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0033
0034 static const clock_ip_name_t s_dac12Clocks[] = DAC_CLOCKS;
0035 #endif
0036
0037
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0039
0040 static uint32_t DAC12_GetInstance(DAC_Type *base)
0041 {
0042 uint32_t instance;
0043
0044
0045 for (instance = 0; instance < ARRAY_SIZE(s_dac12Bases); instance++)
0046 {
0047 if (s_dac12Bases[instance] == base)
0048 {
0049 break;
0050 }
0051 }
0052
0053 assert(instance < ARRAY_SIZE(s_dac12Bases));
0054
0055 return instance;
0056 }
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0063
0064 void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info)
0065 {
0066 assert(NULL != info);
0067
0068 info->fifoSizeInfo =
0069 (dac12_fifo_size_info_t)(uint32_t)((DAC_PARAM_FIFOSZ_MASK & base->PARAM) >> DAC_PARAM_FIFOSZ_SHIFT);
0070 }
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0078 void DAC12_Init(DAC_Type *base, const dac12_config_t *config)
0079 {
0080 assert(NULL != config);
0081
0082 uint32_t tmp32;
0083
0084 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0085
0086 CLOCK_EnableClock(s_dac12Clocks[DAC12_GetInstance(base)]);
0087 #endif
0088
0089 tmp32 = DAC_CR_WML(config->fifoWatermarkLevel);
0090 switch (config->fifoWorkMode)
0091 {
0092 case kDAC12_FIFOWorkAsNormalMode:
0093 tmp32 |= DAC_CR_FIFOEN_MASK;
0094 break;
0095 case kDAC12_FIFOWorkAsSwingMode:
0096 tmp32 |= DAC_CR_FIFOEN_MASK | DAC_CR_SWMD_MASK;
0097 break;
0098 default:
0099 break;
0100 }
0101
0102 tmp32 |= DAC_CR_DACRFS(config->referenceVoltageSource)
0103 | DAC_CR_TRGSEL(config->fifoTriggerMode);
0104
0105 base->CR = tmp32;
0106
0107
0108 tmp32 = 0U;
0109
0110 switch (config->referenceCurrentSource)
0111 {
0112 case kDAC12_ReferenceCurrentSourceAlt0:
0113 tmp32 |= DAC_CR2_IREF_MASK;
0114 break;
0115 case kDAC12_ReferenceCurrentSourceAlt1:
0116 tmp32 |= DAC_CR2_IREF1_MASK;
0117 break;
0118 case kDAC12_ReferenceCurrentSourceAlt2:
0119 tmp32 |= DAC_CR2_IREF2_MASK;
0120 break;
0121 default:
0122 break;
0123 }
0124
0125
0126 switch (config->speedMode)
0127 {
0128 case kDAC12_SpeedMiddleMode:
0129 tmp32 |= DAC_CR2_BFMS_MASK;
0130 break;
0131 case kDAC12_SpeedHighMode:
0132 tmp32 |= DAC_CR2_BFHS_MASK;
0133 break;
0134 default:
0135 break;
0136 }
0137
0138
0139 if (config->enableAnalogBuffer)
0140 {
0141 tmp32 |= DAC_CR2_BFEN_MASK;
0142 }
0143 else
0144 {
0145 tmp32 |= DAC_CR2_OEN_MASK;
0146 }
0147 base->CR2 = tmp32;
0148
0149 #if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER)
0150 base->ITRM = DAC_ITRM_TRIM(config->currentReferenceInternalTrimValue);
0151 #endif
0152 }
0153
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0159 void DAC12_Deinit(DAC_Type *base)
0160 {
0161 DAC12_Enable(base, false);
0162 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0163 CLOCK_DisableClock(s_dac12Clocks[DAC12_GetInstance(base)]);
0164 #endif
0165 }
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0183 void DAC12_GetDefaultConfig(dac12_config_t *config)
0184 {
0185 assert(NULL != config);
0186
0187
0188 (void)memset(config, 0, sizeof(*config));
0189
0190 config->fifoWatermarkLevel = 0U;
0191 config->fifoWorkMode = kDAC12_FIFODisabled;
0192 config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1;
0193 config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode;
0194 config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0;
0195 config->speedMode = kDAC12_SpeedLowMode;
0196 config->enableAnalogBuffer = false;
0197 #if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER)
0198 config->currentReferenceInternalTrimValue = 0x4;
0199 #endif
0200 }