drivers/common/fsl_common_dsp.h

0001 /*
0002  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2020 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_COMMON_DSP_H_
0010 #define _FSL_COMMON_DSP_H_
0011
0012 /*!
0013  * @addtogroup ksdk_common
0014  * @{
0015  */
0016
0017 /*******************************************************************************
0018  * Definitions
0019  ******************************************************************************/
0020
0021 /*! @name Timer utilities */
0022 /* @{ */
0023 /*! Macro to convert a microsecond period to raw count value */
0024 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
0025 /*! Macro to convert a raw count value to microsecond */
0026 #define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz))
0027
0028 /*! Macro to convert a millisecond period to raw count value */
0029 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
0030 /*! Macro to convert a raw count value to millisecond */
0031 #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz))
0032 /* @} */
0033
0034 #define SDK_ISR_EXIT_BARRIER
0035
0036 /*! @name Alignment variable definition macros */
0037 /* @{ */
0038 /*! Macro to define a variable with alignbytes alignment */
0039 #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
0040
0041 /*! Macro to define a variable with L1 d-cache line size alignment */
0042 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
0043 #define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
0044 #endif
0045
0046 /*! Macro to define a variable with L2 cache line size alignment */
0047 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
0048 #define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
0049 #endif
0050
0051 /*! Macro to change a value to a given size aligned value */
0052 #define SDK_SIZEALIGN(var, alignbytes) \
0053     ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
0054 /* @} */
0055
0056 /*! @name Non-cacheable region definition macros */
0057 /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
0058  * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
0059  * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
0060  * will be initialized to zero in system startup.
0061  */
0062 /* @{ */
0063
0064 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
0065 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
0066 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
0067     __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
0068 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
0069     __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
0070
0071 /* @} */
0072
0073 /*!
0074  * @name Time sensitive region
0075  * @{
0076  */
0077 #if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
0078
0079 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
0080 #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
0081
0082 #else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
0083
0084 #define AT_QUICKACCESS_SECTION_CODE(func) func
0085 #define AT_QUICKACCESS_SECTION_DATA(func) func
0086
0087 #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
0088 /* @} */
0089
0090 /* Macros for compatibility. */
0091 #define NVIC_SetPriorityGrouping(value) do {} while(0)
0092 #define NVIC_GetPriorityGrouping() do {} while(0)
0093 #define NVIC_EnableIRQ(value) do {} while(0)
0094 #define NVIC_GetEnableIRQ(value) do {} while(0)
0095 #define NVIC_DisableIRQ(value) do {} while(0)
0096 #define NVIC_GetPendingIRQ(value) do {} while(0)
0097 #define NVIC_SetPendingIRQ(value) do {} while(0)
0098 #define NVIC_ClearPendingIRQ(value) do {} while(0)
0099 #define NVIC_GetActive(value) do {} while(0)
0100
0101 /*
0102  * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
0103  * defined in previous of this file.
0104  */
0105 #include "fsl_clock.h"
0106
0107 /*******************************************************************************
0108  * API
0109  ******************************************************************************/
0110
0111 #if defined(__cplusplus)
0112 extern "C" {
0113 #endif
0114
0115 /*!
0116  * @brief Enable specific interrupt.
0117  *
0118  * Empty function for build compatibility.
0119  *
0120  * @param interrupt The IRQ number.
0121  * @return Always return kStatus_Success.
0122  */
0123 static inline status_t EnableIRQ(IRQn_Type interrupt)
0124 {
0125     return kStatus_Success;
0126 }
0127
0128 /*!
0129  * @brief Disable specific interrupt.
0130  *
0131  * Empty function for build compatibility.
0132  *
0133  * @param interrupt The IRQ number.
0134  * @return Always return kStatus_Success.
0135  */
0136 static inline status_t DisableIRQ(IRQn_Type interrupt)
0137 {
0138     return kStatus_Success;
0139 }
0140
0141 /*!
0142  * @brief Disable the global IRQ
0143  *
0144  * Empty function for build compatibility.
0145  *
0146  * @return Always return 0;
0147  */
0148 static inline uint32_t DisableGlobalIRQ(void)
0149 {
0150     return 0;
0151 }
0152
0153 /*!
0154  * @brief Enable the global IRQ
0155  *
0156  * Empty function for build compatibility.
0157  *
0158  * @param primask Not used.
0159  */
0160 static inline void EnableGlobalIRQ(uint32_t primask)
0161 {
0162 }
0163
0164 #if defined(__cplusplus)
0165 }
0166 #endif
0167
0168 /*! @} */
0169
0170 #endif /* _FSL_COMMON_DSP_H_ */