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0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2021 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008 
0009 #ifndef _FSL_ADC_ETC_H_
0010 #define _FSL_ADC_ETC_H_
0011 
0012 #include "fsl_common.h"
0013 
0014 /*!
0015  *  @addtogroup adc_etc
0016  *  @{
0017  */
0018 
0019 /*******************************************************************************
0020  * Definitions
0021  ******************************************************************************/
0022 /*! @brief ADC_ETC driver version */
0023 #define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
0024 /*! @brief The mask of status flags cleared by writing 1. */
0025 #define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
0026 
0027 /*!
0028  * @brief ADC_ETC customized status flags mask.
0029  */
0030 enum _adc_etc_status_flag_mask
0031 {
0032     kADC_ETC_Done0StatusFlagMask = 1U << 0U,
0033     kADC_ETC_Done1StatusFlagMask = 1U << 1U,
0034     kADC_ETC_Done2StatusFlagMask = 1U << 2U,
0035 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
0036     kADC_ETC_Done3StatusFlagMask = 1U << 3U,
0037     kADC_ETC_ErrorStatusFlagMask = 1U << 4U,
0038 #else
0039     kADC_ETC_ErrorStatusFlagMask  = 1U << 3U,
0040 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
0041 };
0042 
0043 /*!
0044  * @brief External triggers sources.
0045  */
0046 typedef enum _adc_etc_external_trigger_source
0047 {
0048     /* External XBAR sources. Support HW or SW mode. */
0049     kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */
0050     kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */
0051     kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */
0052     kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */
0053     kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */
0054     kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */
0055     kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */
0056     kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */
0057     /* External TSC sources. Only support HW mode. */
0058     kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */
0059     kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */
0060 } adc_etc_external_trigger_source_t;
0061 
0062 /*!
0063  * @brief Interrupt enable/disable mask.
0064  */
0065 typedef enum _adc_etc_interrupt_enable
0066 {
0067 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
0068     kADC_ETC_Done0InterruptEnable = 0U, /* Enable the DONE0 interrupt when ADC conversions complete. */
0069     kADC_ETC_Done1InterruptEnable = 1U, /* Enable the DONE1 interrupt when ADC conversions complete. */
0070     kADC_ETC_Done2InterruptEnable = 2U, /* Enable the DONE2 interrupt when ADC conversions complete. */
0071     kADC_ETC_Done3InterruptEnable = 3U, /* Enable the DONE3 interrupt when ADC conversions complete. */
0072 #else
0073     kADC_ETC_InterruptDisable     = 0U, /* Disable the ADC_ETC interrupt. */
0074     kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
0075     kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
0076     kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
0077 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
0078 } adc_etc_interrupt_enable_t;
0079 
0080 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
0081 /*!
0082  * @brief DMA mode selection.
0083  */
0084 typedef enum _adc_etc_dma_mode_selection
0085 {
0086     kADC_ETC_TrigDMAWithLatchedSignal =
0087         0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
0088     kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
0089 } adc_etc_dma_mode_selection_t;
0090 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
0091 
0092 /*!
0093  * @brief ADC_ETC configuration.
0094  */
0095 typedef struct _adc_etc_config
0096 {
0097 #if ((!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
0098      (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)))
0099     bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
0100                              Otherwise TSC would trigger ADC through ADC_ETC. */
0101 #endif
0102 
0103 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0104     bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
0105 #endif                      /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0106 
0107 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
0108     bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
0109 #endif                      /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
0110 
0111 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
0112     adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
0113 #endif                                    /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
0114 
0115 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0116     uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
0117 #endif                            /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0118 
0119 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
0120     uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
0121 #endif                            /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
0122     uint32_t clockPreDivider;     /* Pre-divider for trig delay and interval. Available range is 0-255.
0123                                     Clock would be divided by (clockPreDivider+1). */
0124     uint32_t XBARtriggerMask;     /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
0125                                      trigger7:0x80
0126                                      For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
0127                                      enabled. */
0128 } adc_etc_config_t;
0129 
0130 /*!
0131  * @brief ADC_ETC trigger chain configuration.
0132  */
0133 typedef struct _adc_etc_trigger_chain_config
0134 {
0135     bool enableB2BMode;           /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
0136                                      wait until interval delay is reached. */
0137     uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */
0138     uint32_t ADCChannelSelect;    /* Select ADC sample channel. */
0139     adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */
0140 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
0141     bool enableIrq; /* Enable IRQ for selected interrupt enable choice in "InterruptEnable" */
0142 #endif              /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
0143 } adc_etc_trigger_chain_config_t;
0144 
0145 /*!
0146  * @brief ADC_ETC trigger configuration.
0147  */
0148 typedef struct _adc_etc_trigger_config
0149 {
0150     bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
0151                             In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */
0152     bool enableSWTriggerMode;     /* Enable the sofware trigger mode. */
0153     uint32_t triggerChainLength;  /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */
0154     uint32_t triggerPriority;     /* External trigger priority, 7 is highest, 0 is lowest. */
0155     uint32_t sampleIntervalDelay; /* Set sampling interval delay. */
0156     uint32_t initialDelay;        /* Set trigger initial delay. */
0157 } adc_etc_trigger_config_t;
0158 
0159 /*******************************************************************************
0160  * API
0161  ******************************************************************************/
0162 #if defined(__cplusplus)
0163 extern "C" {
0164 #endif
0165 
0166 /*!
0167  * @name Initialization
0168  * @{
0169  */
0170 
0171 /*!
0172  * @brief Initialize the ADC_ETC module.
0173  *
0174  * @param base ADC_ETC peripheral base address.
0175  * @param config Pointer to "adc_etc_config_t" structure.
0176  */
0177 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
0178 
0179 /*!
0180  * @brief De-Initialize the ADC_ETC module.
0181  *
0182  * @param base ADC_ETC peripheral base address.
0183  */
0184 void ADC_ETC_Deinit(ADC_ETC_Type *base);
0185 
0186 /*!
0187  * @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
0188  * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
0189  * @code
0190  *   config->enableTSCBypass = true;
0191  *   config->enableTSC0Trigger = false;
0192  *   config->enableTSC1Trigger = false;
0193  *   config->TSC0triggerPriority = 0U;
0194  *   config->TSC1triggerPriority = 0U;
0195  *   config->clockPreDivider = 0U;
0196  *   config->XBARtriggerMask = 0U;
0197  * @endcode
0198  *
0199  * @param config Pointer to "adc_etc_config_t" structure.
0200  */
0201 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
0202 
0203 /*!
0204  * @brief Set the external XBAR trigger configuration.
0205  *
0206  * @param base ADC_ETC peripheral base address.
0207  * @param triggerGroup Trigger group index.
0208  * @param config Pointer to "adc_etc_trigger_config_t" structure.
0209  */
0210 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
0211 
0212 /*!
0213  * @brief Set the external XBAR trigger chain configuration.
0214  * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
0215  * configurated.
0216  *
0217  * @param base ADC_ETC peripheral base address.
0218  * @param triggerGroup Trigger group index. Available number is 0~7.
0219  * @param chainGroup Trigger chain group index. Available number is 0~7.
0220  * @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
0221  */
0222 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
0223                                    uint32_t triggerGroup,
0224                                    uint32_t chainGroup,
0225                                    const adc_etc_trigger_chain_config_t *config);
0226 
0227 /*!
0228  * @brief Gets the interrupt status flags of external XBAR and TSC triggers.
0229  *
0230  * @param base ADC_ETC peripheral base address.
0231  * @param sourceIndex trigger source index.
0232  *
0233  * @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
0234  */
0235 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
0236 
0237 /*!
0238  * @brief Clears the ADC_ETC's interrupt status falgs.
0239  *
0240  * @param base ADC_ETC peripheral base address.
0241  * @param sourceIndex trigger source index.
0242  * @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
0243  */
0244 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
0245                                        adc_etc_external_trigger_source_t sourceIndex,
0246                                        uint32_t mask);
0247 
0248 /*!
0249  * @brief Enable the DMA corresponding to each trigger source.
0250  *
0251  * @param base ADC_ETC peripheral base address.
0252  * @param triggerGroup Trigger group index. Available number is 0~7.
0253  */
0254 static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
0255 {
0256     /* Avoid clearing status flags at the same time. */
0257     base->DMA_CTRL = (base->DMA_CTRL | ((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
0258                      ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
0259 }
0260 
0261 /*!
0262  * @brief Disable the DMA corresponding to each trigger sources.
0263  *
0264  * @param base ADC_ETC peripheral base address.
0265  * @param triggerGroup Trigger group index. Available number is 0~7.
0266  */
0267 static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
0268 {
0269     /* Avoid clearing status flags at the same time. */
0270     base->DMA_CTRL = (base->DMA_CTRL & ~((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
0271                      ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
0272 }
0273 
0274 /*!
0275  * @brief Get the DMA request status falgs. Only external XBAR sources support DMA request.
0276  *
0277  * @param base ADC_ETC peripheral base address.
0278  * @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
0279  * trigger7:0x80.
0280  */
0281 static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)
0282 {
0283     return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
0284 }
0285 
0286 /*!
0287  * @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request.
0288  *
0289  * @param base ADC_ETC peripheral base address.
0290  * @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
0291  * trigger7:0x80.
0292  */
0293 static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)
0294 {
0295     base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
0296 }
0297 
0298 /*!
0299  * @brief When enable, all logical will be reset.
0300  *
0301  * @param base ADC_ETC peripheral base address.
0302  * @param enable Enable/Disable the software reset.
0303  */
0304 static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
0305 {
0306     if (enable)
0307     {
0308         base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK;
0309     }
0310     else
0311     {
0312         base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK;
0313     }
0314 }
0315 
0316 /*!
0317  * @brief Do software trigger corresponding to each XBAR trigger sources.
0318  * Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
0319  * trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
0320  * can only work in hardware trigger mode.
0321  *
0322  * @param base ADC_ETC peripheral base address.
0323  * @param triggerGroup Trigger group index. Available number is 0~7.
0324  */
0325 static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
0326 {
0327     assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
0328 
0329     base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK;
0330 }
0331 
0332 /*!
0333  * @brief Get ADC conversion result from external XBAR sources.
0334  * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
0335  * return Trigger0 source's chain1 conversion result.
0336  *
0337  * @param base ADC_ETC peripheral base address.
0338  * @param triggerGroup Trigger group index. Available number is 0~7.
0339  * @param chainGroup Trigger chain group index. Available number is 0~7.
0340  * @return ADC conversion result value.
0341  */
0342 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
0343 
0344 /* @} */
0345 
0346 #if defined(__cplusplus)
0347 }
0348 #endif
0349 
0350 /* @} */
0351 
0352 #endif /* _FSL_ADC_ETC_H_ */
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