drivers/adc_etc/fsl_adc_etc.c

0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2021 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_adc_etc.h"
0010
0011 /* Component ID definition, used by tools. */
0012 #ifndef FSL_COMPONENT_ID
0013 #define FSL_COMPONENT_ID "platform.drivers.adc_etc"
0014 #endif
0015
0016 /*******************************************************************************
0017  * Prototypes
0018  ******************************************************************************/
0019 #if defined(ADC_ETC_CLOCKS)
0020 /*!
0021  * @brief Get instance number for ADC_ETC module.
0022  *
0023  * @param base ADC_ETC peripheral base address
0024  */
0025 static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
0026
0027 /*******************************************************************************
0028  * Variables
0029  ******************************************************************************/
0030 /*! @brief Pointers to ADC_ETC bases for each instance. */
0031 static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
0032 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0033 /*! @brief Pointers to ADC_ETC clocks for each instance. */
0034 static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
0035 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0036
0037 /*******************************************************************************
0038  * Code
0039  ******************************************************************************/
0040 static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
0041 {
0042     uint32_t instance         = 0U;
0043     uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
0044
0045     /* Find the instance index from base address mappings. */
0046     for (instance = 0; instance < adcetcArrayCount; instance++)
0047     {
0048         if (s_adcetcBases[instance] == base)
0049         {
0050             break;
0051         }
0052     }
0053
0054     assert(instance < adcetcArrayCount);
0055
0056     return instance;
0057 }
0058 #endif /* ADC_ETC_CLOCKS */
0059
0060 /*!
0061  * brief Initialize the ADC_ETC module.
0062  *
0063  * param base ADC_ETC peripheral base address.
0064  * param config Pointer to "adc_etc_config_t" structure.
0065  */
0066 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
0067 {
0068     assert(NULL != config);
0069
0070     uint32_t tmp32 = 0U;
0071
0072 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0073 #if defined(ADC_ETC_CLOCKS)
0074     /* Open clock gate. */
0075     CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
0076 #endif /* ADC_ETC_CLOCKS */
0077 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0078
0079     /* Disable software reset. */
0080     ADC_ETC_DoSoftwareReset(base, false);
0081
0082     /* Set ADC_ETC_CTRL register. */
0083     tmp32 =
0084 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0085         ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
0086 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0087 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0088         ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
0089 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0090         ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
0091 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
0092         | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
0093 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
0094         ;
0095
0096 #if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
0097     (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
0098     if (config->enableTSCBypass)
0099     {
0100         tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
0101     }
0102 #endif
0103 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0104     if (config->enableTSC0Trigger)
0105     {
0106         tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK;
0107     }
0108 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0109 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0110     if (config->enableTSC1Trigger)
0111     {
0112         tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK;
0113     }
0114 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0115     base->CTRL = tmp32;
0116 }
0117
0118 /*!
0119  * brief De-Initialize the ADC_ETC module.
0120  *
0121  * param base ADC_ETC peripheral base address.
0122  */
0123 void ADC_ETC_Deinit(ADC_ETC_Type *base)
0124 {
0125     /* Do software reset to clear all logical. */
0126     ADC_ETC_DoSoftwareReset(base, true);
0127
0128 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0129 #if defined(ADC_ETC_CLOCKS)
0130     /* Close clock gate. */
0131     CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
0132 #endif /* ADC_ETC_CLOCKS */
0133 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0134 }
0135
0136 /*!
0137  * brief Gets an available pre-defined settings for the ADC_ETC's configuration.
0138  * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
0139  * code
0140  *   config->enableTSCBypass = true;
0141  *   config->enableTSC0Trigger = false;
0142  *   config->enableTSC1Trigger = false;
0143  *   config->TSC0triggerPriority = 0U;
0144  *   config->TSC1triggerPriority = 0U;
0145  *   config->clockPreDivider = 0U;
0146  *   config->XBARtriggerMask = 0U;
0147  * endCode
0148  *
0149  * param config Pointer to "adc_etc_config_t" structure.
0150  */
0151 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
0152 {
0153     /* Initializes the configure structure to zero. */
0154     (void)memset(config, 0, sizeof(*config));
0155
0156 #if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
0157     (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
0158     config->enableTSCBypass = true;
0159 #endif
0160
0161 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0162     config->enableTSC0Trigger = false;
0163 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0164
0165 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0166     config->enableTSC1Trigger = false;
0167 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0168
0169 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
0170     config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
0171 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
0172
0173 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0174     config->TSC0triggerPriority = 0U;
0175 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0176
0177 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
0178     config->TSC1triggerPriority = 0U;
0179 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
0180     config->clockPreDivider = 0U;
0181     config->XBARtriggerMask = 0U;
0182 }
0183
0184 /*!
0185  * brief Set the external XBAR trigger configuration.
0186  *
0187  * param base ADC_ETC peripheral base address.
0188  * param triggerGroup Trigger group index.
0189  * param config Pointer to "adc_etc_trigger_config_t" structure.
0190  */
0191 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
0192 {
0193     assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
0194     assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup);
0195
0196     uint32_t tmp32 = 0U;
0197
0198     /* Set ADC_ETC_TRGn_CTRL register. */
0199     tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) |
0200             ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority);
0201     if (config->enableSyncMode)
0202     {
0203         tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK;
0204     }
0205     if (config->enableSWTriggerMode)
0206     {
0207         tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK;
0208     }
0209     base->TRIG[triggerGroup].TRIGn_CTRL = tmp32;
0210
0211     /* Set ADC_ETC_TRGn_COUNTER register. */
0212     tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) |
0213             ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay);
0214     base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
0215 }
0216
0217 /*!
0218  * brief Set the external XBAR trigger chain configuration.
0219  * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
0220  * configurated.
0221  *
0222  * param base ADC_ETC peripheral base address.
0223  * param triggerGroup Trigger group index. Available number is 0~7.
0224  * param chainGroup Trigger chain group index. Available number is 0~7.
0225  * param config Pointer to "adc_etc_trigger_chain_config_t" structure.
0226  */
0227 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
0228                                    uint32_t triggerGroup,
0229                                    uint32_t chainGroup,
0230                                    const adc_etc_trigger_chain_config_t *config)
0231 {
0232     assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
0233
0234     uint32_t tmp32     = 0U;
0235     uint32_t tmpReg    = 0U;
0236     uint8_t mRemainder = (uint8_t)(chainGroup % 2U);
0237
0238     /*  Set ADC_ETC_TRIGn_CHAINm register. */
0239     tmp32 = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) |
0240             ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) |
0241             ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable);
0242     if (true == config->enableB2BMode)
0243     {
0244         tmp32 |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK;
0245     }
0246 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
0247     if (true == config->enableIrq)
0248     {
0249         tmp32 |= ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK;
0250     }
0251 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
0252     switch (chainGroup / 2U)
0253     {
0254         case 0U: /* Configurate trigger chain0 and chain 1. */
0255             tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0;
0256             if (mRemainder == 0U) /* Chain 0. */
0257             {
0258                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK |
0259                             ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK);
0260                 tmpReg |= tmp32;
0261             }
0262             else /* Chain 1. */
0263             {
0264                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK |
0265                             ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK);
0266                 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT);
0267             }
0268             base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmpReg;
0269             break;
0270         case 1U: /* Configurate trigger chain2 and chain 3. */
0271             tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2;
0272             if (mRemainder == 0U) /* Chain 2. */
0273             {
0274                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK |
0275                             ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK);
0276                 tmpReg |= tmp32;
0277             }
0278             else /* Chain 3. */
0279             {
0280                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK |
0281                             ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK);
0282                 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT);
0283             }
0284             base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmpReg;
0285             break;
0286         case 2U: /* Configurate trigger chain4 and chain 5. */
0287             tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4;
0288             if (mRemainder == 0U) /* Chain 4. */
0289             {
0290                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK |
0291                             ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK);
0292                 tmpReg |= tmp32;
0293             }
0294             else /* Chain 5. */
0295             {
0296                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK |
0297                             ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK);
0298                 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT);
0299             }
0300             base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmpReg;
0301             break;
0302         case 3U: /* Configurate trigger chain6 and chain 7. */
0303             tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6;
0304             if (mRemainder == 0U) /* Chain 6. */
0305             {
0306                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK |
0307                             ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK);
0308                 tmpReg |= tmp32;
0309             }
0310             else /* Chain 7. */
0311             {
0312                 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK |
0313                             ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK);
0314                 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT);
0315             }
0316             base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmpReg;
0317             break;
0318         default:
0319             assert(false);
0320             break;
0321     }
0322 }
0323
0324 /*!
0325  * brief Gets the interrupt status flags of external XBAR and TSC triggers.
0326  *
0327  * param base ADC_ETC peripheral base address.
0328  * param sourceIndex trigger source index.
0329  *
0330  * return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
0331  */
0332 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
0333 {
0334     uint32_t tmp32 = 0U;
0335
0336     if (((base->DONE0_1_IRQ) & ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << (uint32_t)sourceIndex)) != 0U)
0337     {
0338         tmp32 |= (uint32_t)kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in
0339                                                   fsl_adc_etc.h file. */
0340     }
0341     if (((base->DONE0_1_IRQ) & ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << (uint32_t)sourceIndex)) != 0U)
0342     {
0343         tmp32 |= (uint32_t)kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in
0344                                                   fsl_adc_etc.h file. */
0345     }
0346     if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex)) != 0U)
0347     {
0348         tmp32 |= (uint32_t)kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in
0349                                                   fsl_adc_etc.h file. */
0350     }
0351 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
0352     if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex)) != 0U)
0353     {
0354         tmp32 |= (uint32_t)kADC_ETC_Done3StatusFlagMask; /* Customized DONE3 status flags mask, which is defined in
0355                                                   fsl_adc_etc.h file. */
0356     }
0357 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
0358     if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex)) != 0U)
0359     {
0360         tmp32 |= (uint32_t)kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in
0361                                                   fsl_adc_etc.h file. */
0362     }
0363     return tmp32;
0364 }
0365
0366 /*!
0367  * brief Clears the ADC_ETC's interrupt status falgs.
0368  *
0369  * param base ADC_ETC peripheral base address.
0370  * param sourceIndex trigger source index.
0371  * param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
0372  */
0373 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
0374 {
0375     if (0U != (mask & (uint32_t)kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
0376     {
0377         base->DONE0_1_IRQ = ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << (uint32_t)sourceIndex);
0378     }
0379     if (0U != (mask & (uint32_t)kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */
0380     {
0381         base->DONE0_1_IRQ = ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << (uint32_t)sourceIndex);
0382     }
0383     if (0U != (mask & (uint32_t)kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */
0384     {
0385         base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex);
0386     }
0387 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
0388     if (0U != (mask & (uint32_t)kADC_ETC_Done3StatusFlagMask)) /* Write 1 to clear DONE3 status flags. */
0389     {
0390         base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex);
0391     }
0392 #endif                                                         /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
0393     if (0U != (mask & (uint32_t)kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */
0394     {
0395         base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex);
0396     }
0397 }
0398
0399 /*!
0400  * brief Get ADC conversion result from external XBAR sources.
0401  * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
0402  * return Trigger0 source's chain1 conversion result.
0403  *
0404  * param base ADC_ETC peripheral base address.
0405  * param triggerGroup Trigger group index. Available number is 0~7.
0406  * param chainGroup Trigger chain group index. Available number is 0~7.
0407  * return ADC conversion result value.
0408  */
0409 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
0410 {
0411     assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);
0412
0413     uint32_t mADCResult;
0414     uint8_t mRemainder = (uint8_t)(chainGroup % 2U);
0415
0416     switch (chainGroup / 2U)
0417     {
0418         case 0U:
0419             if (0U == mRemainder)
0420             {
0421                 mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0);
0422             }
0423             else
0424             {
0425                 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT;
0426             }
0427             break;
0428         case 1U:
0429             if (0U == mRemainder)
0430             {
0431                 mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2);
0432             }
0433             else
0434             {
0435                 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT;
0436             }
0437             break;
0438         case 2U:
0439             if (0U == mRemainder)
0440             {
0441                 mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4);
0442             }
0443             else
0444             {
0445                 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT;
0446             }
0447             break;
0448         case 3U:
0449             if (0U == mRemainder)
0450             {
0451                 mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6);
0452             }
0453             else
0454             {
0455                 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT;
0456             }
0457             break;
0458         default:
0459             mADCResult = 0U;
0460             assert(false);
0461             break;
0462     }
0463     return mADCResult;
0464 }