drivers/acmp/fsl_acmp.c

0001 /*
0002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2019 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_acmp.h"
0010
0011 /*******************************************************************************
0012  * Definitions
0013  ******************************************************************************/
0014
0015 /* Component ID definition, used by tools. */
0016 #ifndef FSL_COMPONENT_ID
0017 #define FSL_COMPONENT_ID "platform.drivers.acmp"
0018 #endif
0019
0020 /*******************************************************************************
0021  * Prototypes
0022  ******************************************************************************/
0023 /*!
0024  * @brief Get the ACMP instance from the peripheral base address.
0025  *
0026  * @param base ACMP peripheral base address.
0027  * @return ACMP instance.
0028  */
0029 static uint32_t ACMP_GetInstance(CMP_Type *base);
0030
0031 /*******************************************************************************
0032  * Variables
0033  ******************************************************************************/
0034 /* Array of ACMP peripheral base address. */
0035 static CMP_Type *const s_acmpBases[] = CMP_BASE_PTRS;
0036 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0037 /* Clock name of ACMP. */
0038 static const clock_ip_name_t s_acmpClock[] = CMP_CLOCKS;
0039 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0040
0041 /*******************************************************************************
0042  * Codes
0043  ******************************************************************************/
0044 static uint32_t ACMP_GetInstance(CMP_Type *base)
0045 {
0046     uint32_t instance = 0U;
0047
0048     /* Find the instance index from base address mappings. */
0049     for (instance = 0; instance < ARRAY_SIZE(s_acmpBases); instance++)
0050     {
0051         if (s_acmpBases[instance] == base)
0052         {
0053             break;
0054         }
0055     }
0056
0057     assert(instance < ARRAY_SIZE(s_acmpBases));
0058
0059     return instance;
0060 }
0061
0062 /*!
0063  * brief Initializes the ACMP.
0064  *
0065  * The default configuration can be got by calling ACMP_GetDefaultConfig().
0066  *
0067  * param base ACMP peripheral base address.
0068  * param config Pointer to ACMP configuration structure.
0069  */
0070 void ACMP_Init(CMP_Type *base, const acmp_config_t *config)
0071 {
0072     assert(NULL != config);
0073
0074     uint32_t tmp32;
0075
0076 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0077     /* Open clock gate. */
0078     CLOCK_EnableClock(s_acmpClock[ACMP_GetInstance(base)]);
0079 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0080
0081     /* Disable the module before configuring it. */
0082     ACMP_Enable(base, false);
0083
0084     /* CMPx_C0
0085      * Set control bit. Avoid clearing status flags at the same time.
0086      */
0087     tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK |
0088                            CMP_C0_HYSTCTR_MASK | CMP_C0_CFx_MASK)));
0089 #if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
0090     tmp32 &= ~CMP_C0_OFFSET_MASK;
0091 #endif /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
0092     if (config->enableHighSpeed)
0093     {
0094         tmp32 |= CMP_C0_PMODE_MASK;
0095     }
0096     if (config->enableInvertOutput)
0097     {
0098         tmp32 |= CMP_C0_INVT_MASK;
0099     }
0100     if (config->useUnfilteredOutput)
0101     {
0102         tmp32 |= CMP_C0_COS_MASK;
0103     }
0104     if (config->enablePinOut)
0105     {
0106         tmp32 |= CMP_C0_OPE_MASK;
0107     }
0108     tmp32 |= CMP_C0_HYSTCTR(config->hysteresisMode);
0109 #if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
0110     tmp32 |= CMP_C0_OFFSET(config->offsetMode);
0111 #endif /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
0112     base->C0 = tmp32;
0113 }
0114
0115 /*!
0116  * brief Deinitializes the ACMP.
0117  *
0118  * param base ACMP peripheral base address.
0119  */
0120 void ACMP_Deinit(CMP_Type *base)
0121 {
0122     /* Disable the module. */
0123     ACMP_Enable(base, false);
0124
0125 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0126     /* Disable clock gate. */
0127     CLOCK_DisableClock(s_acmpClock[ACMP_GetInstance(base)]);
0128 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0129 }
0130
0131 /*!
0132  * brief Gets the default configuration for ACMP.
0133  *
0134  * This function initializes the user configuration structure to default value. The default value are:
0135  *
0136  * Example:
0137    code
0138    config->enableHighSpeed = false;
0139    config->enableInvertOutput = false;
0140    config->useUnfilteredOutput = false;
0141    config->enablePinOut = false;
0142    config->enableHysteresisBothDirections = false;
0143    config->hysteresisMode = kACMP_hysteresisMode0;
0144    endcode
0145  *
0146  * param config Pointer to ACMP configuration structure.
0147  */
0148 void ACMP_GetDefaultConfig(acmp_config_t *config)
0149 {
0150     assert(NULL != config);
0151
0152     /* Initializes the configure structure to zero. */
0153     (void)memset(config, 0, sizeof(*config));
0154
0155     /* Fill default configuration */
0156     config->enableHighSpeed     = false;
0157     config->enableInvertOutput  = false;
0158     config->useUnfilteredOutput = false;
0159     config->enablePinOut        = false;
0160 #if defined(FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT) && (FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT == 1U)
0161     config->offsetMode = kACMP_OffsetLevel0;
0162 #endif /* FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT */
0163     config->hysteresisMode = kACMP_HysteresisLevel0;
0164 }
0165
0166 /*!
0167  * brief Enables or disables the ACMP.
0168  *
0169  * param base ACMP peripheral base address.
0170  * param enable True to enable the ACMP.
0171  */
0172 void ACMP_Enable(CMP_Type *base, bool enable)
0173 {
0174     /* CMPx_C0
0175      * Set control bit. Avoid clearing status flags at the same time.
0176      */
0177     if (enable)
0178     {
0179         base->C0 = ((base->C0 | CMP_C0_EN_MASK) & ~CMP_C0_CFx_MASK);
0180     }
0181     else
0182     {
0183         base->C0 &= ~(CMP_C0_EN_MASK | CMP_C0_CFx_MASK);
0184     }
0185 }
0186
0187 #if defined(FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT) && (FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT == 1U)
0188 /*!
0189  * brief Enables the link from CMP to DAC enable.
0190  *
0191  * When this bit is set, the DAC enable/disable is controlled by the bit CMP_C0[EN] instead of CMP_C1[DACEN].
0192  *
0193  * param base ACMP peripheral base address.
0194  * param enable Enable the feature or not.
0195  */
0196 void ACMP_EnableLinkToDAC(CMP_Type *base, bool enable)
0197 {
0198     /* CMPx_C0_LINKEN
0199      * Set control bit. Avoid clearing status flags at the same time.
0200      */
0201     if (enable)
0202     {
0203         base->C0 = ((base->C0 | CMP_C0_LINKEN_MASK) & ~CMP_C0_CFx_MASK);
0204     }
0205     else
0206     {
0207         base->C0 &= ~(CMP_C0_LINKEN_MASK | CMP_C0_CFx_MASK);
0208     }
0209 }
0210 #endif /* FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT */
0211
0212 /*!
0213  * brief Sets the channel configuration.
0214  *
0215  * Note that the plus/minus mux's setting is only valid when the positive/negative port's input isn't from DAC but
0216  * from channel mux.
0217  *
0218  * Example:
0219    code
0220    acmp_channel_config_t configStruct = {0};
0221    configStruct.positivePortInput = kACMP_PortInputFromDAC;
0222    configStruct.negativePortInput = kACMP_PortInputFromMux;
0223    configStruct.minusMuxInput = 1U;
0224    ACMP_SetChannelConfig(CMP0, &configStruct);
0225    endcode
0226  *
0227  * param base ACMP peripheral base address.
0228  * param config Pointer to channel configuration structure.
0229  */
0230 void ACMP_SetChannelConfig(CMP_Type *base, const acmp_channel_config_t *config)
0231 {
0232     assert(NULL != config);
0233
0234     uint32_t tmp32 = (base->C1 & (~(CMP_C1_PSEL_MASK | CMP_C1_MSEL_MASK)));
0235
0236 /* CMPx_C1
0237  * Set the input of CMP's positive port.
0238  */
0239 #if (defined(FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT == 1U))
0240     tmp32 &= ~CMP_C1_INPSEL_MASK;
0241     tmp32 |= CMP_C1_INPSEL(config->positivePortInput);
0242 #endif /* FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT */
0243
0244 #if (defined(FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT) && (FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT == 1U))
0245     tmp32 &= ~CMP_C1_INNSEL_MASK;
0246     tmp32 |= CMP_C1_INNSEL(config->negativePortInput);
0247 #endif /* FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT */
0248
0249     tmp32 |= CMP_C1_PSEL(config->plusMuxInput) | CMP_C1_MSEL(config->minusMuxInput);
0250
0251     base->C1 = tmp32;
0252 }
0253
0254 /*!
0255  * brief Enables or disables DMA.
0256  *
0257  * param base ACMP peripheral base address.
0258  * param enable True to enable DMA.
0259  */
0260 void ACMP_EnableDMA(CMP_Type *base, bool enable)
0261 {
0262     /* CMPx_C0
0263      * Set control bit. Avoid clearing status flags at the same time.
0264      */
0265     if (enable)
0266     {
0267         base->C0 = ((base->C0 | CMP_C0_DMAEN_MASK) & ~CMP_C0_CFx_MASK);
0268     }
0269     else
0270     {
0271         base->C0 &= ~(CMP_C0_DMAEN_MASK | CMP_C0_CFx_MASK);
0272     }
0273 }
0274
0275 /*!
0276  * brief Enables or disables window mode.
0277  *
0278  * param base ACMP peripheral base address.
0279  * param enable True to enable window mode.
0280  */
0281 void ACMP_EnableWindowMode(CMP_Type *base, bool enable)
0282 {
0283     /* CMPx_C0
0284      * Set control bit. Avoid clearing status flags at the same time.
0285      */
0286     if (enable)
0287     {
0288         base->C0 = ((base->C0 | CMP_C0_WE_MASK) & ~CMP_C0_CFx_MASK);
0289     }
0290     else
0291     {
0292         base->C0 &= ~(CMP_C0_WE_MASK | CMP_C0_CFx_MASK);
0293     }
0294 }
0295
0296 /*!
0297  * brief Configures the filter.
0298  *
0299  * The filter can be enabled when the filter count is bigger than 1, the filter period is greater than 0 and the sample
0300  * clock is from divided bus clock or the filter is bigger than 1 and the sample clock is from external clock. Detailed
0301  * usage can be got from the reference manual.
0302  *
0303  * Example:
0304    code
0305    acmp_filter_config_t configStruct = {0};
0306    configStruct.filterCount = 5U;
0307    configStruct.filterPeriod = 200U;
0308    configStruct.enableSample = false;
0309    ACMP_SetFilterConfig(CMP0, &configStruct);
0310    endcode
0311  *
0312  * param base ACMP peripheral base address.
0313  * param config Pointer to filter configuration structure.
0314  */
0315 void ACMP_SetFilterConfig(CMP_Type *base, const acmp_filter_config_t *config)
0316 {
0317     assert(NULL != config);
0318
0319     /* CMPx_C0
0320      * Set control bit. Avoid clearing status flags at the same time.
0321      */
0322     uint32_t tmp32 = (base->C0 & (~(CMP_C0_FILTER_CNT_MASK | CMP_C0_FPR_MASK | CMP_C0_SE_MASK | CMP_C0_CFx_MASK)));
0323
0324     if (config->enableSample)
0325     {
0326         tmp32 |= CMP_C0_SE_MASK;
0327     }
0328     tmp32 |= (CMP_C0_FILTER_CNT(config->filterCount) | CMP_C0_FPR(config->filterPeriod));
0329     base->C0 = tmp32;
0330 }
0331
0332 /*!
0333  * brief Configures the internal DAC.
0334  *
0335  * Example:
0336    code
0337    acmp_dac_config_t configStruct = {0};
0338    configStruct.referenceVoltageSource = kACMP_VrefSourceVin1;
0339    configStruct.DACValue = 20U;
0340    configStruct.enableOutput = false;
0341    configStruct.workMode = kACMP_DACWorkLowSpeedMode;
0342    ACMP_SetDACConfig(CMP0, &configStruct);
0343    endcode
0344  *
0345  * param base ACMP peripheral base address.
0346  * param config Pointer to DAC configuration structure. "NULL" is for disabling the feature.
0347  */
0348 void ACMP_SetDACConfig(CMP_Type *base, const acmp_dac_config_t *config)
0349 {
0350     uint32_t tmp32;
0351
0352     /* CMPx_C1
0353      * NULL configuration means to disable the feature.
0354      */
0355     if (NULL == config)
0356     {
0357         base->C1 &= ~CMP_C1_DACEN_MASK;
0358         return;
0359     }
0360
0361     tmp32 = (base->C1 & (~(CMP_C1_VRSEL_MASK | CMP_C1_VOSEL_MASK)));
0362     /* Set configuration and enable the feature. */
0363     tmp32 |= (CMP_C1_VRSEL(config->referenceVoltageSource) | CMP_C1_VOSEL(config->DACValue) | CMP_C1_DACEN_MASK);
0364
0365 #if defined(FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT == 1U)
0366     tmp32 &= ~CMP_C1_DACOE_MASK;
0367     if (config->enableOutput)
0368     {
0369         tmp32 |= CMP_C1_DACOE_MASK;
0370     }
0371 #endif /* FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT */
0372
0373 #if defined(FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT == 1U)
0374     switch (config->workMode)
0375     {
0376         case kACMP_DACWorkLowSpeedMode:
0377             tmp32 &= ~CMP_C1_DMODE_MASK;
0378             break;
0379         case kACMP_DACWorkHighSpeedMode:
0380             tmp32 |= CMP_C1_DMODE_MASK;
0381             break;
0382         default:
0383             assert(false);
0384             break;
0385     }
0386 #endif /* FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT */
0387
0388     base->C1 = tmp32;
0389 }
0390
0391 /*!
0392  * brief Configures the round robin mode.
0393  *
0394  * Example:
0395    code
0396    acmp_round_robin_config_t configStruct = {0};
0397    configStruct.fixedPort = kACMP_FixedPlusPort;
0398    configStruct.fixedChannelNumber = 3U;
0399    configStruct.checkerChannelMask = 0xF7U;
0400    configStruct.sampleClockCount = 0U;
0401    configStruct.delayModulus = 0U;
0402    ACMP_SetRoundRobinConfig(CMP0, &configStruct);
0403    endcode
0404  * param base ACMP peripheral base address.
0405  * param config Pointer to round robin mode configuration structure. "NULL" is for disabling the feature.
0406  */
0407 void ACMP_SetRoundRobinConfig(CMP_Type *base, const acmp_round_robin_config_t *config)
0408 {
0409     uint32_t tmp32;
0410
0411     /* CMPx_C2
0412      * Set control bit. Avoid clearing status flags at the same time.
0413      * NULL configuration means to disable the feature.
0414      */
0415     if (NULL == config)
0416     {
0417         tmp32 = CMP_C2_CHnF_MASK;
0418 #if defined(FSL_FEATURE_ACMP_HAS_C2_RRE_BIT) && (FSL_FEATURE_ACMP_HAS_C2_RRE_BIT == 1U)
0419         tmp32 |= CMP_C2_RRE_MASK;
0420 #endif /* FSL_FEATURE_ACMP_HAS_C2_RRE_BIT */
0421         base->C2 &= ~(tmp32);
0422         return;
0423     }
0424
0425     /* CMPx_C1
0426      * Set all channel's round robin checker enable mask.
0427      */
0428     tmp32 = (base->C1 & ~(CMP_C1_CHNn_MASK));
0429     tmp32 |= ((config->checkerChannelMask) << CMP_C1_CHN0_SHIFT);
0430     base->C1 = tmp32;
0431
0432     /* CMPx_C2
0433      * Set configuration and enable the feature.
0434      */
0435     tmp32 = (base->C2 &
0436              (~(CMP_C2_FXMP_MASK | CMP_C2_FXMXCH_MASK | CMP_C2_NSAM_MASK | CMP_C2_INITMOD_MASK | CMP_C2_CHnF_MASK)));
0437     tmp32 |= (CMP_C2_FXMP(config->fixedPort) | CMP_C2_FXMXCH(config->fixedChannelNumber) |
0438               CMP_C2_NSAM(config->sampleClockCount) | CMP_C2_INITMOD(config->delayModulus));
0439 #if defined(FSL_FEATURE_ACMP_HAS_C2_RRE_BIT) && (FSL_FEATURE_ACMP_HAS_C2_RRE_BIT == 1U)
0440     tmp32 |= CMP_C2_RRE_MASK;
0441 #endif /* FSL_FEATURE_ACMP_HAS_C2_RRE_BIT */
0442     base->C2 = tmp32;
0443 }
0444
0445 /*!
0446  * brief Defines the pre-set state of channels in round robin mode.
0447  *
0448  * Note: The pre-state has different circuit with get-round-robin-result in the SOC even though they are same bits.
0449  * So get-round-robin-result can't return the same value as the value are set by pre-state.
0450  *
0451  * param base ACMP peripheral base address.
0452  * param mask Mask of round robin channel index. Available range is channel0:0x01 to channel7:0x80.
0453  */
0454 void ACMP_SetRoundRobinPreState(CMP_Type *base, uint32_t mask)
0455 {
0456     /* CMPx_C2
0457      * Set control bit. Avoid clearing status flags at the same time.
0458      */
0459     uint32_t tmp32 = (base->C2 & ~(CMP_C2_ACOn_MASK | CMP_C2_CHnF_MASK));
0460
0461     tmp32 |= (mask << CMP_C2_ACOn_SHIFT);
0462     base->C2 = tmp32;
0463 }
0464
0465 /*!
0466  * brief Clears the channel input changed flags in round robin mode.
0467  *
0468  * param base ACMP peripheral base address.
0469  * param mask Mask of channel index. Available range is channel0:0x01 to channel7:0x80.
0470  */
0471 void ACMP_ClearRoundRobinStatusFlags(CMP_Type *base, uint32_t mask)
0472 {
0473     /* CMPx_C2 */
0474     uint32_t tmp32 = (base->C2 & (~CMP_C2_CHnF_MASK));
0475
0476     tmp32 |= (mask << CMP_C2_CH0F_SHIFT);
0477     base->C2 = tmp32;
0478 }
0479
0480 /*!
0481  * brief Enables interrupts.
0482  *
0483  * param base ACMP peripheral base address.
0484  * param mask Interrupts mask. See "_acmp_interrupt_enable".
0485  */
0486 void ACMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
0487 {
0488     uint32_t tmp32;
0489
0490     /* CMPx_C0
0491      * Set control bit. Avoid clearing status flags at the same time.
0492      * Set CMP interrupt enable flag.
0493      */
0494     tmp32 = base->C0 & ~CMP_C0_CFx_MASK; /* To protect the W1C flags. */
0495     if ((uint32_t)kACMP_OutputRisingInterruptEnable == (mask & (uint32_t)kACMP_OutputRisingInterruptEnable))
0496     {
0497         tmp32 = ((tmp32 | CMP_C0_IER_MASK) & ~CMP_C0_CFx_MASK);
0498     }
0499     if ((uint32_t)kACMP_OutputFallingInterruptEnable == (mask & (uint32_t)kACMP_OutputFallingInterruptEnable))
0500     {
0501         tmp32 = ((tmp32 | CMP_C0_IEF_MASK) & ~CMP_C0_CFx_MASK);
0502     }
0503     base->C0 = tmp32;
0504
0505     /* CMPx_C2
0506      * Set round robin interrupt enable flag.
0507      */
0508     if ((uint32_t)kACMP_RoundRobinInterruptEnable == (mask & (uint32_t)kACMP_RoundRobinInterruptEnable))
0509     {
0510         tmp32 = base->C2;
0511         /* Set control bit. Avoid clearing status flags at the same time. */
0512         tmp32    = ((tmp32 | CMP_C2_RRIE_MASK) & ~CMP_C2_CHnF_MASK);
0513         base->C2 = tmp32;
0514     }
0515 }
0516
0517 /*!
0518  * brief Disables interrupts.
0519  *
0520  * param base ACMP peripheral base address.
0521  * param mask Interrupts mask. See "_acmp_interrupt_enable".
0522  */
0523 void ACMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
0524 {
0525     uint32_t tmp32;
0526
0527     /* CMPx_C0
0528      * Set control bit. Avoid clearing status flags at the same time.
0529      * Clear CMP interrupt enable flag.
0530      */
0531     tmp32 = base->C0;
0532     if ((uint32_t)kACMP_OutputRisingInterruptEnable == (mask & (uint32_t)kACMP_OutputRisingInterruptEnable))
0533     {
0534         tmp32 &= ~(CMP_C0_IER_MASK | CMP_C0_CFx_MASK);
0535     }
0536     if ((uint32_t)kACMP_OutputFallingInterruptEnable == (mask & (uint32_t)kACMP_OutputFallingInterruptEnable))
0537     {
0538         tmp32 &= ~(CMP_C0_IEF_MASK | CMP_C0_CFx_MASK);
0539     }
0540     base->C0 = tmp32;
0541
0542     /* CMPx_C2
0543      * Clear round robin interrupt enable flag.
0544      */
0545     if ((uint32_t)kACMP_RoundRobinInterruptEnable == (mask & (uint32_t)kACMP_RoundRobinInterruptEnable))
0546     {
0547         tmp32 = base->C2;
0548         /* Set control bit. Avoid clearing status flags at the same time. */
0549         tmp32 &= ~(CMP_C2_RRIE_MASK | CMP_C2_CHnF_MASK);
0550         base->C2 = tmp32;
0551     }
0552 }
0553
0554 /*!
0555  * brief Gets status flags.
0556  *
0557  * param base ACMP peripheral base address.
0558  * return Status flags asserted mask. See "_acmp_status_flags".
0559  */
0560 uint32_t ACMP_GetStatusFlags(CMP_Type *base)
0561 {
0562     uint32_t status = 0U;
0563     uint32_t tmp32  = base->C0;
0564
0565     /* CMPx_C0
0566      * Check if each flag is set.
0567      */
0568     if (CMP_C0_CFR_MASK == (tmp32 & CMP_C0_CFR_MASK))
0569     {
0570         status |= (uint32_t)kACMP_OutputRisingEventFlag;
0571     }
0572     if (CMP_C0_CFF_MASK == (tmp32 & CMP_C0_CFF_MASK))
0573     {
0574         status |= (uint32_t)kACMP_OutputFallingEventFlag;
0575     }
0576     if (CMP_C0_COUT_MASK == (tmp32 & CMP_C0_COUT_MASK))
0577     {
0578         status |= (uint32_t)kACMP_OutputAssertEventFlag;
0579     }
0580
0581     return status;
0582 }
0583
0584 /*!
0585  * brief Clears status flags.
0586  *
0587  * param base ACMP peripheral base address.
0588  * param mask Status flags mask. See "_acmp_status_flags".
0589  */
0590 void ACMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
0591 {
0592     /* CMPx_C0 */
0593     uint32_t tmp32 = (base->C0 & (~(CMP_C0_CFR_MASK | CMP_C0_CFF_MASK)));
0594
0595     /* Clear flag according to mask. */
0596     if ((uint32_t)kACMP_OutputRisingEventFlag == (mask & (uint32_t)kACMP_OutputRisingEventFlag))
0597     {
0598         tmp32 |= CMP_C0_CFR_MASK;
0599     }
0600     if ((uint32_t)kACMP_OutputFallingEventFlag == (mask & (uint32_t)kACMP_OutputFallingEventFlag))
0601     {
0602         tmp32 |= CMP_C0_CFF_MASK;
0603     }
0604     base->C0 = tmp32;
0605 }
0606
0607 #if defined(FSL_FEATURE_ACMP_HAS_C3_REG) && (FSL_FEATURE_ACMP_HAS_C3_REG == 1U)
0608 /*!
0609  * brief Configure the discrete mode.
0610  *
0611  * Configure the discrete mode when supporting 3V domain with 1.8V core.
0612  *
0613  * param base ACMP peripheral base address.
0614  * param config Pointer to configuration structure. See "acmp_discrete_mode_config_t".
0615  */
0616 void ACMP_SetDiscreteModeConfig(CMP_Type *base, const acmp_discrete_mode_config_t *config)
0617 {
0618     uint32_t tmp32 = 0U;
0619
0620     if (!config->enablePositiveChannelDiscreteMode)
0621     {
0622         tmp32 |= CMP_C3_PCHCTEN_MASK;
0623     }
0624     if (!config->enableNegativeChannelDiscreteMode)
0625     {
0626         tmp32 |= CMP_C3_NCHCTEN_MASK;
0627     }
0628     if (config->enableResistorDivider)
0629     {
0630         tmp32 |= CMP_C3_RDIVE_MASK;
0631     }
0632
0633     tmp32 |= CMP_C3_DMCS(config->clockSource)      /* Select the clock. */
0634              | CMP_C3_ACSAT(config->sampleTime)    /* Sample time period. */
0635              | CMP_C3_ACPH1TC(config->phase1Time)  /* Phase 1 sample time. */
0636              | CMP_C3_ACPH2TC(config->phase2Time); /* Phase 2 sample time. */
0637
0638     base->C3 = tmp32;
0639 }
0640
0641 /*!
0642  * brief Get the default configuration for discrete mode setting.
0643  *
0644  * param config Pointer to configuration structure to be restored with the setting values.
0645  */
0646 void ACMP_GetDefaultDiscreteModeConfig(acmp_discrete_mode_config_t *config)
0647 {
0648     assert(NULL != config);
0649
0650     /* Initializes the configure structure to zero. */
0651     (void)memset(config, 0, sizeof(*config));
0652
0653     config->enablePositiveChannelDiscreteMode = false;
0654     config->enableNegativeChannelDiscreteMode = false;
0655     config->enableResistorDivider             = false;
0656     config->clockSource                       = kACMP_DiscreteClockSlow;
0657     config->sampleTime                        = kACMP_DiscreteSampleTimeAs1T;
0658     config->phase1Time                        = kACMP_DiscretePhaseTimeAlt0;
0659     config->phase2Time                        = kACMP_DiscretePhaseTimeAlt0;
0660 }
0661
0662 #endif /* FSL_FEATURE_ACMP_HAS_C3_REG */