devices/MIMXRT1166/system_MIMXRT1166_cm7.c

0001 /*
0002 ** ###################################################################
0003 **     Processors:          MIMXRT1166CVM5A_cm7
0004 **                          MIMXRT1166DVM6A_cm7
0005 **                          MIMXRT1166XVM5A_cm7
0006 **
0007 **     Compilers:           Freescale C/C++ for Embedded ARM
0008 **                          GNU C Compiler
0009 **                          IAR ANSI C/C++ Compiler for ARM
0010 **                          Keil ARM C/C++ Compiler
0011 **                          MCUXpresso Compiler
0012 **
0013 **     Reference manual:    IMXRT1160RM, Rev 0, 03/2021
0014 **     Version:             rev. 0.1, 2020-12-29
0015 **     Build:               b210615
0016 **
0017 **     Abstract:
0018 **         Provides a system configuration function and a global variable that
0019 **         contains the system frequency. It configures the device and initializes
0020 **         the oscillator (PLL) that is part of the microcontroller device.
0021 **
0022 **     Copyright 2016 Freescale Semiconductor, Inc.
0023 **     Copyright 2016-2021 NXP
0024 **     All rights reserved.
0025 **
0026 **     SPDX-License-Identifier: BSD-3-Clause
0027 **
0028 **     http:                 www.nxp.com
0029 **     mail:                 support@nxp.com
0030 **
0031 **     Revisions:
0032 **     - rev. 0.1 (2020-12-29)
0033 **         Initial version.
0034 **
0035 ** ###################################################################
0036 */
0037
0038 /*!
0039  * @file MIMXRT1166_cm7
0040  * @version 1.0
0041  * @date 2021-06-15
0042  * @brief Device specific configuration file for MIMXRT1166_cm7 (implementation
0043  *        file)
0044  *
0045  * Provides a system configuration function and a global variable that contains
0046  * the system frequency. It configures the device and initializes the oscillator
0047  * (PLL) that is part of the microcontroller device.
0048  */
0049
0050 #include <stdint.h>
0051 #include "fsl_device_registers.h"
0052
0053
0054
0055 /* ----------------------------------------------------------------------------
0056    -- Core clock
0057    ---------------------------------------------------------------------------- */
0058
0059 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
0060
0061 /* ----------------------------------------------------------------------------
0062    -- SystemInit()
0063    ---------------------------------------------------------------------------- */
0064
0065 void SystemInit (void) {
0066 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
0067   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
0068 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
0069
0070 #if defined(__MCUXPRESSO)
0071     extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
0072     SCB->VTOR = (uint32_t)g_pfnVectors;
0073 #endif
0074
0075 /* Watchdog disable */
0076
0077 #if (DISABLE_WDOG)
0078     if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
0079     {
0080         WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
0081     }
0082     if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
0083     {
0084         WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
0085     }
0086     if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
0087     {
0088         RTWDOG3->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
0089     }
0090     else
0091     {
0092         RTWDOG3->CNT = 0xC520U;
0093         RTWDOG3->CNT = 0xD928U;
0094     }
0095     RTWDOG3->TOVAL = 0xFFFF;
0096     RTWDOG3->CS = (uint32_t) ((RTWDOG3->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
0097     if ((RTWDOG4->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
0098     {
0099         RTWDOG4->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
0100     }
0101     else
0102     {
0103         RTWDOG4->CNT = 0xC520U;
0104         RTWDOG4->CNT = 0xD928U;
0105     }
0106     RTWDOG4->TOVAL = 0xFFFF;
0107     RTWDOG4->CS = (uint32_t) ((RTWDOG4->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
0108 #endif /* (DISABLE_WDOG) */
0109
0110     /* Disable Systick which might be enabled by bootrom */
0111     if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
0112     {
0113         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
0114     }
0115
0116 /* Enable instruction and data caches */
0117 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
0118     if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
0119         SCB_EnableICache();
0120     }
0121 #endif
0122
0123     /* Clear bit 13 to its reset value since it might be set by ROM. */
0124     IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
0125
0126 #if defined(ROM_ECC_ENABLED)
0127     /* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
0128        Save SRSR to SRC->GPR[10] so that application can still check SRSR value from SRC->GPR[10]. */
0129     SRC->GPR[10] = SRC->SRSR;
0130     /* clear SRSR */
0131     SRC->SRSR = 0xFFFFFFFFU;
0132 #endif
0133
0134     /* Enable entry to thread mode when divide by zero */
0135     SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
0136     __DSB();
0137     __ISB();
0138
0139   SystemInitHook();
0140 }
0141
0142 /* ----------------------------------------------------------------------------
0143    -- SystemCoreClockUpdate()
0144    ---------------------------------------------------------------------------- */
0145
0146 void SystemCoreClockUpdate (void) {
0147
0148 /* TBD */
0149
0150 }
0151
0152 /* ----------------------------------------------------------------------------
0153    -- SystemInitHook()
0154    ---------------------------------------------------------------------------- */
0155
0156 __attribute__ ((weak)) void SystemInitHook (void) {
0157   /* Void implementation of the weak function. */
0158 }
0159