drivers/cm4/fsl_cache.c

0001 /*
0002  * Copyright 2016-2021 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007
0008 #include "fsl_cache.h"
0009 /*******************************************************************************
0010  * Definitions
0011  ******************************************************************************/
0012
0013 /* Component ID definition, used by tools. */
0014 #ifndef FSL_COMPONENT_ID
0015 #define FSL_COMPONENT_ID "platform.drivers.cache_lmem"
0016 #endif
0017
0018 #define L1CACHE_ONEWAYSIZE_BYTE      (4096U)       /*!< Cache size is 4K-bytes one way. */
0019 #define L1CACHE_CODEBUSADDR_BOUNDARY (0x1FFFFFFFU) /*!< The processor code bus address boundary. */
0020
0021 /*******************************************************************************
0022  * Code
0023  ******************************************************************************/
0024 #if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
0025 /*!
0026  * brief Enables the processor code bus cache.
0027  *
0028  */
0029 void L1CACHE_EnableCodeCache(void)
0030 {
0031     if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK))
0032     {
0033         /* First, invalidate the entire cache. */
0034         L1CACHE_InvalidateCodeCache();
0035
0036         /* Now enable the cache. */
0037         LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
0038     }
0039 }
0040
0041 /*!
0042  * brief Disables the processor code bus cache.
0043  *
0044  */
0045 void L1CACHE_DisableCodeCache(void)
0046 {
0047     /* First, push any modified contents. */
0048     L1CACHE_CleanCodeCache();
0049
0050     /* Now disable the cache. */
0051     LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
0052 }
0053
0054 /*!
0055  * brief Invalidates the processor code bus cache.
0056  *
0057  */
0058 void L1CACHE_InvalidateCodeCache(void)
0059 {
0060     /* Enables the processor code bus to invalidate all lines in both ways.
0061     and Initiate the processor code bus code cache command. */
0062     LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
0063
0064     /* Wait until the cache command completes. */
0065     while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
0066     {
0067     }
0068
0069     /* As a precaution clear the bits to avoid inadvertently re-running this command. */
0070     LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
0071 }
0072
0073 /*!
0074  * brief Invalidates processor code bus cache by range.
0075  *
0076  * param address The physical address of cache.
0077  * param size_byte size of the memory to be invalidated.
0078  * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
0079  * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
0080  * startAddr is not aligned. For the size_byte, application should make sure the
0081  * alignment or make sure the right operation order if the size_byte is not aligned.
0082  */
0083 void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)
0084 {
0085     uint32_t endAddr = address + size_byte;
0086     uint32_t pccReg  = 0;
0087     /* Align address to cache line size. */
0088     uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U);
0089
0090     /* Set the invalidate by line command and use the physical address. */
0091     pccReg       = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_MASK;
0092     LMEM->PCCLCR = pccReg;
0093
0094     while (startAddr < endAddr)
0095     {
0096         /* Set the address and initiate the command. */
0097         LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK;
0098
0099         /* Wait until the cache command completes. */
0100         while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U)
0101         {
0102         }
0103         startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE;
0104     }
0105 }
0106
0107 /*!
0108  * brief Cleans the processor code bus cache.
0109  *
0110  */
0111 void L1CACHE_CleanCodeCache(void)
0112 {
0113     /* Enable the processor code bus to push all modified lines. */
0114     LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
0115
0116     /* Wait until the cache command completes. */
0117     while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
0118     {
0119     }
0120
0121     /* As a precaution clear the bits to avoid inadvertently re-running this command. */
0122     LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
0123 }
0124
0125 /*!
0126  * brief Cleans processor code bus cache by range.
0127  *
0128  * param address The physical address of cache.
0129  * param size_byte size of the memory to be cleaned.
0130  * note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
0131  * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
0132  * startAddr is not aligned. For the size_byte, application should make sure the
0133  * alignment or make sure the right operation order if the size_byte is not aligned.
0134  */
0135 void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte)
0136 {
0137     uint32_t endAddr = address + size_byte;
0138     uint32_t pccReg  = 0;
0139     /* Align address to cache line size. */
0140     uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U);
0141
0142     /* Set the push by line command. */
0143     pccReg       = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(2) | LMEM_PCCLCR_LADSEL_MASK;
0144     LMEM->PCCLCR = pccReg;
0145
0146     while (startAddr < endAddr)
0147     {
0148         /* Set the address and initiate the command. */
0149         LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK;
0150
0151         /* Wait until the cache command completes. */
0152         while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U)
0153         {
0154         }
0155         startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE;
0156     }
0157 }
0158
0159 /*!
0160  * brief Cleans and invalidates the processor code bus cache.
0161  *
0162  */
0163 void L1CACHE_CleanInvalidateCodeCache(void)
0164 {
0165     /* Push and invalidate all. */
0166     LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK |
0167                    LMEM_PCCCR_GO_MASK;
0168
0169     /* Wait until the cache command completes. */
0170     while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
0171     {
0172     }
0173
0174     /* As a precaution clear the bits to avoid inadvertently re-running this command. */
0175     LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
0176 }
0177
0178 /*!
0179  * brief Cleans and invalidate processor code bus cache by range.
0180  *
0181  * param address The physical address of cache.
0182  * param size_byte size of the memory to be Cleaned and Invalidated.
0183  * note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
0184  * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
0185  * startAddr is not aligned. For the size_byte, application should make sure the
0186  * alignment or make sure the right operation order if the size_byte is not aligned.
0187  */
0188 void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)
0189 {
0190     uint32_t endAddr = address + size_byte;
0191     uint32_t pccReg  = 0;
0192     /* Align address to cache line size. */
0193     uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U);
0194
0195     /* Set the push by line command. */
0196     pccReg       = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(3) | LMEM_PCCLCR_LADSEL_MASK;
0197     LMEM->PCCLCR = pccReg;
0198
0199     while (startAddr < endAddr)
0200     {
0201         /* Set the address and initiate the command. */
0202         LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK;
0203
0204         /* Wait until the cache command completes. */
0205         while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U)
0206         {
0207         }
0208         startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE;
0209     }
0210 }
0211
0212 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0213 /*!
0214  * brief Enables the processor system bus cache.
0215  *
0216  */
0217 void L1CACHE_EnableSystemCache(void)
0218 {
0219     /* Only enable when not enabled. */
0220     if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK))
0221     {
0222         /* First, invalidate the entire cache. */
0223         L1CACHE_InvalidateSystemCache();
0224
0225         /* Now enable the cache. */
0226         LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
0227     }
0228 }
0229
0230 /*!
0231  * brief Disables the processor system bus cache.
0232  *
0233  */
0234 void L1CACHE_DisableSystemCache(void)
0235 {
0236     /* First, push any modified contents. */
0237     L1CACHE_CleanSystemCache();
0238
0239     /* Now disable the cache. */
0240     LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
0241 }
0242
0243 /*!
0244  * brief Invalidates the processor system bus cache.
0245  *
0246  */
0247 void L1CACHE_InvalidateSystemCache(void)
0248 {
0249     /* Enables the processor system bus to invalidate all lines in both ways.
0250     and Initiate the processor system bus cache command. */
0251     LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
0252
0253     /* Wait until the cache command completes */
0254     while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
0255     {
0256     }
0257
0258     /* As a precaution clear the bits to avoid inadvertently re-running this command. */
0259     LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
0260 }
0261
0262 /*!
0263  * brief Invalidates processor system bus cache by range.
0264  *
0265  * param address The physical address of cache.
0266  * param size_byte size of the memory to be invalidated.
0267  * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
0268  * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
0269  * startAddr is not aligned. For the size_byte, application should make sure the
0270  * alignment or make sure the right operation order if the size_byte is not aligned.
0271  */
0272 void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)
0273 {
0274     uint32_t endAddr = address + size_byte;
0275     uint32_t pscReg  = 0;
0276     uint32_t startAddr =
0277         address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */
0278
0279     /* Set the invalidate by line command and use the physical address. */
0280     pscReg       = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(1) | LMEM_PSCLCR_LADSEL_MASK;
0281     LMEM->PSCLCR = pscReg;
0282
0283     while (startAddr < endAddr)
0284     {
0285         /* Set the address and initiate the command. */
0286         LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK;
0287
0288         /* Wait until the cache command completes. */
0289         while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U)
0290         {
0291         }
0292         startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE;
0293     }
0294 }
0295
0296 /*!
0297  * brief Cleans the processor system bus cache.
0298  *
0299  */
0300 void L1CACHE_CleanSystemCache(void)
0301 {
0302     /* Enable the processor system bus to push all modified lines. */
0303     LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
0304
0305     /* Wait until the cache command completes. */
0306     while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
0307     {
0308     }
0309
0310     /* As a precaution clear the bits to avoid inadvertently re-running this command. */
0311     LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
0312 }
0313
0314 /*!
0315  * brief Cleans processor system bus cache by range.
0316  *
0317  * param address The physical address of cache.
0318  * param size_byte size of the memory to be cleaned.
0319  * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
0320  * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
0321  * startAddr is not aligned. For the size_byte, application should make sure the
0322  * alignment or make sure the right operation order if the size_byte is not aligned.
0323  */
0324 void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte)
0325 {
0326     uint32_t endAddr = address + size_byte;
0327     uint32_t pscReg  = 0;
0328     uint32_t startAddr =
0329         address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */
0330
0331     /* Set the push by line command. */
0332     pscReg       = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(2) | LMEM_PSCLCR_LADSEL_MASK;
0333     LMEM->PSCLCR = pscReg;
0334
0335     while (startAddr < endAddr)
0336     {
0337         /* Set the address and initiate the command. */
0338         LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK;
0339
0340         /* Wait until the cache command completes. */
0341         while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U)
0342         {
0343         }
0344         startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE;
0345     }
0346 }
0347
0348 /*!
0349  * brief Cleans and invalidates the processor system bus cache.
0350  *
0351  */
0352 void L1CACHE_CleanInvalidateSystemCache(void)
0353 {
0354     /* Push and invalidate all. */
0355     LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK |
0356                    LMEM_PSCCR_GO_MASK;
0357
0358     /* Wait until the cache command completes. */
0359     while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
0360     {
0361     }
0362
0363     /* As a precaution clear the bits to avoid inadvertently re-running this command. */
0364     LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
0365 }
0366
0367 /*!
0368  * brief Cleans and Invalidates processor system bus cache by range.
0369  *
0370  * param address The physical address of cache.
0371  * param size_byte size of the memory to be Clean and Invalidated.
0372  * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
0373  * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
0374  * startAddr is not aligned. For the size_byte, application should make sure the
0375  * alignment or make sure the right operation order if the size_byte is not aligned.
0376  */
0377 void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)
0378 {
0379     uint32_t endAddr = address + size_byte;
0380     uint32_t pscReg  = 0;
0381     uint32_t startAddr =
0382         address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */
0383
0384     /* Set the push by line command. */
0385     pscReg       = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(3) | LMEM_PSCLCR_LADSEL_MASK;
0386     LMEM->PSCLCR = pscReg;
0387
0388     while (startAddr < endAddr)
0389     {
0390         /* Set the address and initiate the command. */
0391         LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK;
0392
0393         /* Wait until the cache command completes. */
0394         while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U)
0395         {
0396         }
0397         startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE;
0398     }
0399 }
0400
0401 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0402 #endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
0403
0404 /*!
0405  * brief Invalidates cortex-m4 L1 instrument cache by range.
0406  *
0407  * param address  The start address of the memory to be invalidated.
0408  * param size_byte  The memory size.
0409  * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
0410  */
0411 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
0412 {
0413 #if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
0414     uint32_t endAddr = address + size_byte;
0415     uint32_t size    = size_byte;
0416
0417     if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY)
0418     {
0419         L1CACHE_InvalidateCodeCacheByRange(address, size);
0420     }
0421     else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
0422     {
0423         size = L1CACHE_CODEBUSADDR_BOUNDARY - address;
0424         L1CACHE_InvalidateCodeCacheByRange(address, size);
0425 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0426         size = size_byte - size;
0427         L1CACHE_InvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size);
0428 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0429     }
0430     else
0431     {
0432 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0433         L1CACHE_InvalidateSystemCacheByRange(address, size);
0434 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0435     }
0436 #endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
0437 }
0438
0439 /*!
0440  * brief Cleans cortex-m4 L1 data cache by range.
0441  *
0442  * param address  The start address of the memory to be cleaned.
0443  * param size_byte  The memory size.
0444  * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
0445  */
0446 void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
0447 {
0448 #if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
0449     uint32_t endAddr = address + size_byte;
0450     uint32_t size    = size_byte;
0451
0452     if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY)
0453     {
0454         L1CACHE_CleanCodeCacheByRange(address, size);
0455     }
0456     else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
0457     {
0458         size = L1CACHE_CODEBUSADDR_BOUNDARY - address;
0459         L1CACHE_CleanCodeCacheByRange(address, size);
0460 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0461         size = size_byte - size;
0462         L1CACHE_CleanSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size);
0463 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0464     }
0465     else
0466     {
0467 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0468         L1CACHE_CleanSystemCacheByRange(address, size);
0469 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0470     }
0471 #endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
0472 }
0473
0474 /*!
0475  * brief Cleans and Invalidates cortex-m4 L1 data cache by range.
0476  *
0477  * param address  The start address of the memory to be clean and invalidated.
0478  * param size_byte  The memory size.
0479  * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
0480  */
0481 void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
0482 {
0483 #if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
0484     uint32_t endAddr = address + size_byte;
0485     uint32_t size    = size_byte;
0486
0487     if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY)
0488     {
0489         L1CACHE_CleanInvalidateCodeCacheByRange(address, size);
0490     }
0491     else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY)
0492     {
0493         size = L1CACHE_CODEBUSADDR_BOUNDARY - address;
0494         L1CACHE_CleanInvalidateCodeCacheByRange(address, size);
0495 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0496         size = size_byte - size;
0497         L1CACHE_CleanInvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size);
0498 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0499     }
0500     else
0501     {
0502 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
0503         L1CACHE_CleanInvalidateSystemCacheByRange(address, size);
0504 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
0505     }
0506 #endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
0507 }