devices/MIMXRT1052/system_MIMXRT1052.c

0001 /*
0002 ** ###################################################################
0003 **     Processors:          MIMXRT1052CVJ5B
0004 **                          MIMXRT1052CVL5B
0005 **                          MIMXRT1052DVJ6B
0006 **                          MIMXRT1052DVL6B
0007 **
0008 **     Compilers:           Freescale C/C++ for Embedded ARM
0009 **                          GNU C Compiler
0010 **                          IAR ANSI C/C++ Compiler for ARM
0011 **                          Keil ARM C/C++ Compiler
0012 **                          MCUXpresso Compiler
0013 **
0014 **     Reference manual:    IMXRT1050RM Rev.5, 07/2021 | IMXRT1050SRM Rev.2
0015 **     Version:             rev. 1.4, 2021-08-10
0016 **     Build:               b210811
0017 **
0018 **     Abstract:
0019 **         Provides a system configuration function and a global variable that
0020 **         contains the system frequency. It configures the device and initializes
0021 **         the oscillator (PLL) that is part of the microcontroller device.
0022 **
0023 **     Copyright 2016 Freescale Semiconductor, Inc.
0024 **     Copyright 2016-2021 NXP
0025 **     All rights reserved.
0026 **
0027 **     SPDX-License-Identifier: BSD-3-Clause
0028 **
0029 **     http:                 www.nxp.com
0030 **     mail:                 support@nxp.com
0031 **
0032 **     Revisions:
0033 **     - rev. 0.1 (2017-01-10)
0034 **         Initial version.
0035 **     - rev. 1.0 (2018-09-21)
0036 **         Update interrupt vector table and dma request source.
0037 **         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
0038 **         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
0039 **     - rev. 1.1 (2018-11-16)
0040 **         Update header files to align with IMXRT1050RM Rev.1.
0041 **     - rev. 1.2 (2018-11-27)
0042 **         Update header files to align with IMXRT1050RM Rev.2.1.
0043 **     - rev. 1.3 (2019-04-29)
0044 **         Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
0045 **     - rev. 1.4 (2021-08-10)
0046 **         Update header files to align with IMXRT1050RM Rev.5.
0047 **
0048 ** ###################################################################
0049 */
0050
0051 /*!
0052  * @file MIMXRT1052
0053  * @version 1.4
0054  * @date 2021-08-10
0055  * @brief Device specific configuration file for MIMXRT1052 (implementation file)
0056  *
0057  * Provides a system configuration function and a global variable that contains
0058  * the system frequency. It configures the device and initializes the oscillator
0059  * (PLL) that is part of the microcontroller device.
0060  */
0061
0062 #include <stdint.h>
0063 #include "fsl_device_registers.h"
0064
0065
0066
0067 /* ----------------------------------------------------------------------------
0068    -- Core clock
0069    ---------------------------------------------------------------------------- */
0070
0071 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
0072
0073 /* ----------------------------------------------------------------------------
0074    -- SystemInit()
0075    ---------------------------------------------------------------------------- */
0076
0077 void SystemInit (void) {
0078 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
0079   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
0080 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
0081
0082 #if defined(__MCUXPRESSO)
0083     extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
0084     SCB->VTOR = (uint32_t)g_pfnVectors;
0085 #endif
0086
0087 /* Disable Watchdog Power Down Counter */
0088     WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
0089     WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
0090
0091 /* Watchdog disable */
0092
0093 #if (DISABLE_WDOG)
0094     if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
0095     {
0096         WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
0097     }
0098     if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
0099     {
0100         WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
0101     }
0102     if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
0103     {
0104         RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
0105     }
0106     else
0107     {
0108         RTWDOG->CNT = 0xC520U;
0109         RTWDOG->CNT = 0xD928U;
0110     }
0111     RTWDOG->TOVAL = 0xFFFF;
0112     RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
0113 #endif /* (DISABLE_WDOG) */
0114
0115     /* Disable Systick which might be enabled by bootrom */
0116     if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
0117     {
0118         SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
0119     }
0120
0121 /* Enable instruction and data caches */
0122 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
0123     if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
0124         SCB_EnableICache();
0125     }
0126 #endif
0127
0128   SystemInitHook();
0129 }
0130
0131 /* ----------------------------------------------------------------------------
0132    -- SystemCoreClockUpdate()
0133    ---------------------------------------------------------------------------- */
0134
0135 void SystemCoreClockUpdate (void) {
0136
0137     uint32_t freq;
0138     uint32_t PLL1MainClock;
0139     uint32_t PLL2MainClock;
0140
0141     /* Periph_clk2_clk ---> Periph_clk */
0142     if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
0143     {
0144         switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
0145         {
0146             /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
0147             case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
0148                 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
0149                 {
0150                     freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
0151                            CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
0152                 }
0153                 else
0154                 {
0155                     freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
0156                 }
0157                 break;
0158
0159             /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
0160             case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
0161                 freq = CPU_XTAL_CLK_HZ;
0162                 break;
0163
0164             case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
0165                 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
0166                    CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
0167                 break;
0168
0169             case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
0170             default:
0171                 freq = 0U;
0172                 break;
0173         }
0174
0175         freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
0176     }
0177     /* Pre_Periph_clk ---> Periph_clk */
0178     else
0179     {
0180         /* check if pll is bypassed */
0181         if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U)
0182         {
0183             PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
0184                    CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
0185         }
0186         else
0187         {
0188             PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
0189                                              CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
0190         }
0191
0192         /* check if pll is bypassed */
0193         if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
0194         {
0195             PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
0196                    CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
0197         }
0198         else
0199         {
0200             PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
0201         }
0202         PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
0203
0204         switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
0205         {
0206             /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
0207             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
0208                 freq = PLL2MainClock;
0209                 break;
0210
0211             /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
0212             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
0213                 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
0214                 break;
0215
0216             /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
0217             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
0218                 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
0219                 break;
0220
0221             /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
0222             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
0223                 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
0224                 break;
0225
0226             default:
0227                 freq = 0U;
0228                 break;
0229         }
0230     }
0231
0232     SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
0233
0234 }
0235
0236 /* ----------------------------------------------------------------------------
0237    -- SystemInitHook()
0238    ---------------------------------------------------------------------------- */
0239
0240 __attribute__ ((weak)) void SystemInitHook (void) {
0241   /* Void implementation of the weak function. */
0242 }