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0001 /*
0002 ** ###################################################################
0003 **     Processors:          MIMXRT1052CVJ5B
0004 **                          MIMXRT1052CVL5B
0005 **                          MIMXRT1052DVJ6B
0006 **                          MIMXRT1052DVL6B
0007 **
0008 **     Compilers:           Freescale C/C++ for Embedded ARM
0009 **                          GNU C Compiler
0010 **                          IAR ANSI C/C++ Compiler for ARM
0011 **                          Keil ARM C/C++ Compiler
0012 **                          MCUXpresso Compiler
0013 **
0014 **     Reference manual:    IMXRT1050RM Rev.5, 07/2021 | IMXRT1050SRM Rev.2
0015 **     Version:             rev. 1.4, 2021-08-10
0016 **     Build:               b221010
0017 **
0018 **     Abstract:
0019 **         CMSIS Peripheral Access Layer for MIMXRT1052
0020 **
0021 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
0022 **     Copyright 2016-2022 NXP
0023 **     All rights reserved.
0024 **
0025 **     SPDX-License-Identifier: BSD-3-Clause
0026 **
0027 **     http:                 www.nxp.com
0028 **     mail:                 support@nxp.com
0029 **
0030 **     Revisions:
0031 **     - rev. 0.1 (2017-01-10)
0032 **         Initial version.
0033 **     - rev. 1.0 (2018-09-21)
0034 **         Update interrupt vector table and dma request source.
0035 **         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
0036 **         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
0037 **     - rev. 1.1 (2018-11-16)
0038 **         Update header files to align with IMXRT1050RM Rev.1.
0039 **     - rev. 1.2 (2018-11-27)
0040 **         Update header files to align with IMXRT1050RM Rev.2.1.
0041 **     - rev. 1.3 (2019-04-29)
0042 **         Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
0043 **     - rev. 1.4 (2021-08-10)
0044 **         Update header files to align with IMXRT1050RM Rev.5.
0045 **
0046 ** ###################################################################
0047 */
0048 
0049 /*!
0050  * @file MIMXRT1052.h
0051  * @version 1.4
0052  * @date 2021-08-10
0053  * @brief CMSIS Peripheral Access Layer for MIMXRT1052
0054  *
0055  * CMSIS Peripheral Access Layer for MIMXRT1052
0056  */
0057 
0058 #ifndef _MIMXRT1052_H_
0059 #define _MIMXRT1052_H_                           /**< Symbol preventing repeated inclusion */
0060 
0061 /** Memory map major version (memory maps with equal major version number are
0062  * compatible) */
0063 #define MCU_MEM_MAP_VERSION 0x0100U
0064 /** Memory map minor version */
0065 #define MCU_MEM_MAP_VERSION_MINOR 0x0004U
0066 
0067 
0068 /* ----------------------------------------------------------------------------
0069    -- Interrupt vector numbers
0070    ---------------------------------------------------------------------------- */
0071 
0072 /*!
0073  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
0074  * @{
0075  */
0076 
0077 /** Interrupt Number Definitions */
0078 #define NUMBER_OF_INT_VECTORS 168                /**< Number of interrupts in the Vector table */
0079 
0080 typedef enum IRQn {
0081   /* Auxiliary constants */
0082   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
0083 
0084   /* Core interrupts */
0085   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
0086   HardFault_IRQn               = -13,              /**< Cortex-M7 SV Hard Fault Interrupt */
0087   MemoryManagement_IRQn        = -12,              /**< Cortex-M7 Memory Management Interrupt */
0088   BusFault_IRQn                = -11,              /**< Cortex-M7 Bus Fault Interrupt */
0089   UsageFault_IRQn              = -10,              /**< Cortex-M7 Usage Fault Interrupt */
0090   SVCall_IRQn                  = -5,               /**< Cortex-M7 SV Call Interrupt */
0091   DebugMonitor_IRQn            = -4,               /**< Cortex-M7 Debug Monitor Interrupt */
0092   PendSV_IRQn                  = -2,               /**< Cortex-M7 Pend SV Interrupt */
0093   SysTick_IRQn                 = -1,               /**< Cortex-M7 System Tick Interrupt */
0094 
0095   /* Device specific interrupts */
0096   DMA0_DMA16_IRQn              = 0,                /**< DMA channel 0/16 transfer complete */
0097   DMA1_DMA17_IRQn              = 1,                /**< DMA channel 1/17 transfer complete */
0098   DMA2_DMA18_IRQn              = 2,                /**< DMA channel 2/18 transfer complete */
0099   DMA3_DMA19_IRQn              = 3,                /**< DMA channel 3/19 transfer complete */
0100   DMA4_DMA20_IRQn              = 4,                /**< DMA channel 4/20 transfer complete */
0101   DMA5_DMA21_IRQn              = 5,                /**< DMA channel 5/21 transfer complete */
0102   DMA6_DMA22_IRQn              = 6,                /**< DMA channel 6/22 transfer complete */
0103   DMA7_DMA23_IRQn              = 7,                /**< DMA channel 7/23 transfer complete */
0104   DMA8_DMA24_IRQn              = 8,                /**< DMA channel 8/24 transfer complete */
0105   DMA9_DMA25_IRQn              = 9,                /**< DMA channel 9/25 transfer complete */
0106   DMA10_DMA26_IRQn             = 10,               /**< DMA channel 10/26 transfer complete */
0107   DMA11_DMA27_IRQn             = 11,               /**< DMA channel 11/27 transfer complete */
0108   DMA12_DMA28_IRQn             = 12,               /**< DMA channel 12/28 transfer complete */
0109   DMA13_DMA29_IRQn             = 13,               /**< DMA channel 13/29 transfer complete */
0110   DMA14_DMA30_IRQn             = 14,               /**< DMA channel 14/30 transfer complete */
0111   DMA15_DMA31_IRQn             = 15,               /**< DMA channel 15/31 transfer complete */
0112   DMA_ERROR_IRQn               = 16,               /**< DMA error interrupt channels 0-15 / 16-31 */
0113   CTI0_ERROR_IRQn              = 17,               /**< CTI0_Error */
0114   CTI1_ERROR_IRQn              = 18,               /**< CTI1_Error */
0115   CORE_IRQn                    = 19,               /**< CorePlatform exception IRQ */
0116   LPUART1_IRQn                 = 20,               /**< LPUART1 TX interrupt and RX interrupt */
0117   LPUART2_IRQn                 = 21,               /**< LPUART2 TX interrupt and RX interrupt */
0118   LPUART3_IRQn                 = 22,               /**< LPUART3 TX interrupt and RX interrupt */
0119   LPUART4_IRQn                 = 23,               /**< LPUART4 TX interrupt and RX interrupt */
0120   LPUART5_IRQn                 = 24,               /**< LPUART5 TX interrupt and RX interrupt */
0121   LPUART6_IRQn                 = 25,               /**< LPUART6 TX interrupt and RX interrupt */
0122   LPUART7_IRQn                 = 26,               /**< LPUART7 TX interrupt and RX interrupt */
0123   LPUART8_IRQn                 = 27,               /**< LPUART8 TX interrupt and RX interrupt */
0124   LPI2C1_IRQn                  = 28,               /**< LPI2C1 interrupt */
0125   LPI2C2_IRQn                  = 29,               /**< LPI2C2 interrupt */
0126   LPI2C3_IRQn                  = 30,               /**< LPI2C3 interrupt */
0127   LPI2C4_IRQn                  = 31,               /**< LPI2C4 interrupt */
0128   LPSPI1_IRQn                  = 32,               /**< LPSPI1 single interrupt vector for all sources */
0129   LPSPI2_IRQn                  = 33,               /**< LPSPI2 single interrupt vector for all sources */
0130   LPSPI3_IRQn                  = 34,               /**< LPSPI3 single interrupt vector for all sources */
0131   LPSPI4_IRQn                  = 35,               /**< LPSPI4  single interrupt vector for all sources */
0132   CAN1_IRQn                    = 36,               /**< CAN1 interrupt */
0133   CAN2_IRQn                    = 37,               /**< CAN2 interrupt */
0134   FLEXRAM_IRQn                 = 38,               /**< FlexRAM address out of range Or access hit IRQ */
0135   KPP_IRQn                     = 39,               /**< Keypad nterrupt */
0136   TSC_DIG_IRQn                 = 40,               /**< TSC interrupt */
0137   GPR_IRQ_IRQn                 = 41,               /**< GPR interrupt */
0138   LCDIF_IRQn                   = 42,               /**< LCDIF interrupt */
0139   CSI_IRQn                     = 43,               /**< CSI interrupt */
0140   PXP_IRQn                     = 44,               /**< PXP interrupt */
0141   WDOG2_IRQn                   = 45,               /**< WDOG2 interrupt */
0142   SNVS_HP_WRAPPER_IRQn         = 46,               /**< SRTC Consolidated Interrupt. Non TZ */
0143   SNVS_HP_WRAPPER_TZ_IRQn      = 47,               /**< SRTC Security Interrupt. TZ */
0144   SNVS_LP_WRAPPER_IRQn         = 48,               /**< ON-OFF button press shorter than 5 secs (pulse event) */
0145   CSU_IRQn                     = 49,               /**< CSU interrupt */
0146   DCP_IRQn                     = 50,               /**< DCP_IRQ interrupt */
0147   DCP_VMI_IRQn                 = 51,               /**< DCP_VMI_IRQ interrupt */
0148   Reserved68_IRQn              = 52,               /**< Reserved interrupt */
0149   TRNG_IRQn                    = 53,               /**< TRNG interrupt */
0150   SJC_IRQn                     = 54,               /**< SJC interrupt */
0151   BEE_IRQn                     = 55,               /**< BEE interrupt */
0152   SAI1_IRQn                    = 56,               /**< SAI1 interrupt */
0153   SAI2_IRQn                    = 57,               /**< SAI1 interrupt */
0154   SAI3_RX_IRQn                 = 58,               /**< SAI3 interrupt */
0155   SAI3_TX_IRQn                 = 59,               /**< SAI3 interrupt */
0156   SPDIF_IRQn                   = 60,               /**< SPDIF interrupt */
0157   PMU_EVENT_IRQn               = 61,               /**< Brown-out event interrupt */
0158   Reserved78_IRQn              = 62,               /**< Reserved interrupt */
0159   TEMP_LOW_HIGH_IRQn           = 63,               /**< TempSensor low/high interrupt */
0160   TEMP_PANIC_IRQn              = 64,               /**< TempSensor panic interrupt */
0161   USB_PHY1_IRQn                = 65,               /**< USBPHY (UTMI0), Interrupt */
0162   USB_PHY2_IRQn                = 66,               /**< USBPHY (UTMI0), Interrupt */
0163   ADC1_IRQn                    = 67,               /**< ADC1 interrupt */
0164   ADC2_IRQn                    = 68,               /**< ADC2 interrupt */
0165   DCDC_IRQn                    = 69,               /**< DCDC interrupt */
0166   Reserved86_IRQn              = 70,               /**< Reserved interrupt */
0167   Reserved87_IRQn              = 71,               /**< Reserved interrupt */
0168   GPIO1_INT0_IRQn              = 72,               /**< Active HIGH Interrupt from INT0 from GPIO */
0169   GPIO1_INT1_IRQn              = 73,               /**< Active HIGH Interrupt from INT1 from GPIO */
0170   GPIO1_INT2_IRQn              = 74,               /**< Active HIGH Interrupt from INT2 from GPIO */
0171   GPIO1_INT3_IRQn              = 75,               /**< Active HIGH Interrupt from INT3 from GPIO */
0172   GPIO1_INT4_IRQn              = 76,               /**< Active HIGH Interrupt from INT4 from GPIO */
0173   GPIO1_INT5_IRQn              = 77,               /**< Active HIGH Interrupt from INT5 from GPIO */
0174   GPIO1_INT6_IRQn              = 78,               /**< Active HIGH Interrupt from INT6 from GPIO */
0175   GPIO1_INT7_IRQn              = 79,               /**< Active HIGH Interrupt from INT7 from GPIO */
0176   GPIO1_Combined_0_15_IRQn     = 80,               /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
0177   GPIO1_Combined_16_31_IRQn    = 81,               /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
0178   GPIO2_Combined_0_15_IRQn     = 82,               /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
0179   GPIO2_Combined_16_31_IRQn    = 83,               /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
0180   GPIO3_Combined_0_15_IRQn     = 84,               /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
0181   GPIO3_Combined_16_31_IRQn    = 85,               /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
0182   GPIO4_Combined_0_15_IRQn     = 86,               /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
0183   GPIO4_Combined_16_31_IRQn    = 87,               /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
0184   GPIO5_Combined_0_15_IRQn     = 88,               /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
0185   GPIO5_Combined_16_31_IRQn    = 89,               /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
0186   FLEXIO1_IRQn                 = 90,               /**< FLEXIO1 interrupt */
0187   FLEXIO2_IRQn                 = 91,               /**< FLEXIO2 interrupt */
0188   WDOG1_IRQn                   = 92,               /**< WDOG1 interrupt */
0189   RTWDOG_IRQn                  = 93,               /**< RTWDOG interrupt */
0190   EWM_IRQn                     = 94,               /**< EWM interrupt */
0191   CCM_1_IRQn                   = 95,               /**< CCM IRQ1 interrupt */
0192   CCM_2_IRQn                   = 96,               /**< CCM IRQ2 interrupt */
0193   GPC_IRQn                     = 97,               /**< GPC interrupt */
0194   SRC_IRQn                     = 98,               /**< SRC interrupt */
0195   Reserved115_IRQn             = 99,               /**< Reserved interrupt */
0196   GPT1_IRQn                    = 100,              /**< GPT1 interrupt */
0197   GPT2_IRQn                    = 101,              /**< GPT2 interrupt */
0198   PWM1_0_IRQn                  = 102,              /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
0199   PWM1_1_IRQn                  = 103,              /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
0200   PWM1_2_IRQn                  = 104,              /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
0201   PWM1_3_IRQn                  = 105,              /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
0202   PWM1_FAULT_IRQn              = 106,              /**< PWM1 fault or reload error interrupt */
0203   Reserved123_IRQn             = 107,              /**< Reserved interrupt */
0204   FLEXSPI_IRQn                 = 108,              /**< FlexSPI0 interrupt */
0205   SEMC_IRQn                    = 109,              /**< SEMC interrupt */
0206   USDHC1_IRQn                  = 110,              /**< USDHC1 interrupt */
0207   USDHC2_IRQn                  = 111,              /**< USDHC2 interrupt */
0208   USB_OTG2_IRQn                = 112,              /**< USBO2 USB OTG2 */
0209   USB_OTG1_IRQn                = 113,              /**< USBO2 USB OTG1 */
0210   ENET_IRQn                    = 114,              /**< ENET interrupt */
0211   ENET_1588_Timer_IRQn         = 115,              /**< ENET_1588_Timer interrupt */
0212   XBAR1_IRQ_0_1_IRQn           = 116,              /**< XBARA1 output signal 0, 1 interrupt */
0213   XBAR1_IRQ_2_3_IRQn           = 117,              /**< XBARA1 output signal 2, 3 interrupt */
0214   ADC_ETC_IRQ0_IRQn            = 118,              /**< ADCETC IRQ0 interrupt */
0215   ADC_ETC_IRQ1_IRQn            = 119,              /**< ADCETC IRQ1 interrupt */
0216   ADC_ETC_IRQ2_IRQn            = 120,              /**< ADCETC IRQ2 interrupt */
0217   ADC_ETC_ERROR_IRQ_IRQn       = 121,              /**< ADCETC Error IRQ interrupt */
0218   PIT_IRQn                     = 122,              /**< PIT interrupt */
0219   ACMP1_IRQn                   = 123,              /**< ACMP interrupt */
0220   ACMP2_IRQn                   = 124,              /**< ACMP interrupt */
0221   ACMP3_IRQn                   = 125,              /**< ACMP interrupt */
0222   ACMP4_IRQn                   = 126,              /**< ACMP interrupt */
0223   Reserved143_IRQn             = 127,              /**< Reserved interrupt */
0224   Reserved144_IRQn             = 128,              /**< Reserved interrupt */
0225   ENC1_IRQn                    = 129,              /**< ENC1 interrupt */
0226   ENC2_IRQn                    = 130,              /**< ENC2 interrupt */
0227   ENC3_IRQn                    = 131,              /**< ENC3 interrupt */
0228   ENC4_IRQn                    = 132,              /**< ENC4 interrupt */
0229   TMR1_IRQn                    = 133,              /**< TMR1 interrupt */
0230   TMR2_IRQn                    = 134,              /**< TMR2 interrupt */
0231   TMR3_IRQn                    = 135,              /**< TMR3 interrupt */
0232   TMR4_IRQn                    = 136,              /**< TMR4 interrupt */
0233   PWM2_0_IRQn                  = 137,              /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
0234   PWM2_1_IRQn                  = 138,              /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
0235   PWM2_2_IRQn                  = 139,              /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
0236   PWM2_3_IRQn                  = 140,              /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
0237   PWM2_FAULT_IRQn              = 141,              /**< PWM2 fault or reload error interrupt */
0238   PWM3_0_IRQn                  = 142,              /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
0239   PWM3_1_IRQn                  = 143,              /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
0240   PWM3_2_IRQn                  = 144,              /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
0241   PWM3_3_IRQn                  = 145,              /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
0242   PWM3_FAULT_IRQn              = 146,              /**< PWM3 fault or reload error interrupt */
0243   PWM4_0_IRQn                  = 147,              /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
0244   PWM4_1_IRQn                  = 148,              /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
0245   PWM4_2_IRQn                  = 149,              /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
0246   PWM4_3_IRQn                  = 150,              /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
0247   PWM4_FAULT_IRQn              = 151               /**< PWM4 fault or reload error interrupt */
0248 } IRQn_Type;
0249 
0250 /*!
0251  * @}
0252  */ /* end of group Interrupt_vector_numbers */
0253 
0254 
0255 /* ----------------------------------------------------------------------------
0256    -- Cortex M7 Core Configuration
0257    ---------------------------------------------------------------------------- */
0258 
0259 /*!
0260  * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
0261  * @{
0262  */
0263 
0264 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
0265 #define __ICACHE_PRESENT               1         /**< Defines if an ICACHE is present or not */
0266 #define __DCACHE_PRESENT               1         /**< Defines if an DCACHE is present or not */
0267 #define __DTCM_PRESENT                 1         /**< Defines if an DTCM is present or not */
0268 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
0269 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
0270 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
0271 
0272 #include "core_cm7.h"                  /* Core Peripheral Access Layer */
0273 #include "system_MIMXRT1052.h"         /* Device specific configuration file */
0274 
0275 /*!
0276  * @}
0277  */ /* end of group Cortex_Core_Configuration */
0278 
0279 
0280 /* ----------------------------------------------------------------------------
0281    -- Mapping Information
0282    ---------------------------------------------------------------------------- */
0283 
0284 /*!
0285  * @addtogroup Mapping_Information Mapping Information
0286  * @{
0287  */
0288 
0289 /** Mapping Information */
0290 /*!
0291  * @addtogroup iomuxc_pads
0292  * @{ */
0293 
0294 /*******************************************************************************
0295  * Definitions
0296 *******************************************************************************/
0297 
0298 /*!
0299  * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
0300  *
0301  * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
0302  */
0303 typedef enum _iomuxc_sw_mux_ctl_pad
0304 {
0305     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0306     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0307     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0308     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0309     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0310     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0311     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0312     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0313     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0314     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0315     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0316     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0317     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0318     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0319     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0320     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0321     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0322     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0323     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0324     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0325     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0326     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0327     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0328     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0329     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0330     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0331     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0332     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0333     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0334     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0335     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0336     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0337     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0338     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0339     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0340     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0341     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0342     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0343     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0344     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0345     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0346     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0347     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0348     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0349     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0350     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0351     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0352     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0353     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0354     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0355     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0356     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0357     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0358     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0359     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0360     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0361     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0362     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0363     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0364     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0365     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0366     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0367     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0368     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0369     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0370     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0371     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0372     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0373     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0374     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0375     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0376     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0377     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0378     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U,    /**< IOMUXC SW_MUX_CTL_PAD index */
0379     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0380     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0381     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0382     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0383     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0384     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0385     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0386     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0387     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0388     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0389     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0390     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0391     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0392     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0393     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0394     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0395     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0396     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0397     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0398     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0399     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0400     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0401     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0402     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0403     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0404     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,       /**< IOMUXC SW_MUX_CTL_PAD index */
0405     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0406     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0407     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0408     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0409     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0410     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U,      /**< IOMUXC SW_MUX_CTL_PAD index */
0411     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0412     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0413     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0414     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0415     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0416     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0417     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0418     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0419     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0420     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0421     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0422     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0423     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0424     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0425     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0426     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0427     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0428     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U,   /**< IOMUXC SW_MUX_CTL_PAD index */
0429 } iomuxc_sw_mux_ctl_pad_t;
0430 
0431 /* @} */
0432 
0433 /*!
0434  * @addtogroup iomuxc_pads
0435  * @{ */
0436 
0437 /*******************************************************************************
0438  * Definitions
0439 *******************************************************************************/
0440 
0441 /*!
0442  * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
0443  *
0444  * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
0445  */
0446 typedef enum _iomuxc_sw_pad_ctl_pad
0447 {
0448     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0449     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0450     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0451     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0452     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0453     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0454     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0455     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0456     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0457     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0458     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0459     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0460     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0461     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0462     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0463     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0464     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0465     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0466     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0467     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0468     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0469     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0470     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0471     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0472     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0473     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0474     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0475     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0476     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0477     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0478     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0479     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0480     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0481     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0482     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0483     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0484     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0485     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0486     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0487     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0488     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0489     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0490     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0491     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0492     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0493     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0494     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0495     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0496     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0497     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0498     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0499     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0500     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0501     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0502     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0503     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0504     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0505     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0506     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0507     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0508     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0509     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0510     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0511     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0512     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0513     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0514     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0515     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0516     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0517     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0518     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0519     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0520     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0521     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U,    /**< IOMUXC SW_PAD_CTL_PAD index */
0522     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0523     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0524     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0525     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0526     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0527     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0528     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0529     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0530     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0531     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0532     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0533     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0534     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0535     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0536     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0537     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0538     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0539     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0540     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0541     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0542     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0543     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0544     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0545     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0546     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0547     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,       /**< IOMUXC SW_PAD_CTL_PAD index */
0548     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0549     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0550     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0551     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0552     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0553     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U,      /**< IOMUXC SW_PAD_CTL_PAD index */
0554     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0555     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0556     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0557     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0558     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0559     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0560     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0561     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0562     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0563     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0564     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0565     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0566     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0567     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0568     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0569     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0570     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0571     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U,   /**< IOMUXC SW_PAD_CTL_PAD index */
0572 } iomuxc_sw_pad_ctl_pad_t;
0573 
0574 /* @} */
0575 
0576 /*!
0577  * @brief Enumeration for the IOMUXC select input
0578  *
0579  * Defines the enumeration for the IOMUXC select input collections.
0580  */
0581 typedef enum _iomuxc_select_input
0582 {
0583     kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U,  /**< IOMUXC select input index */
0584     kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U,  /**< IOMUXC select input index */
0585     kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U,      /**< IOMUXC select input index */
0586     kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,          /**< IOMUXC select input index */
0587     kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U,          /**< IOMUXC select input index */
0588     kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U,          /**< IOMUXC select input index */
0589     kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U,          /**< IOMUXC select input index */
0590     kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,          /**< IOMUXC select input index */
0591     kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U,          /**< IOMUXC select input index */
0592     kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U,          /**< IOMUXC select input index */
0593     kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U,         /**< IOMUXC select input index */
0594     kIOMUXC_CSI_HSYNC_SELECT_INPUT  = 11U,         /**< IOMUXC select input index */
0595     kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U,         /**< IOMUXC select input index */
0596     kIOMUXC_CSI_VSYNC_SELECT_INPUT  = 13U,         /**< IOMUXC select input index */
0597     kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U,  /**< IOMUXC select input index */
0598     kIOMUXC_ENET_MDIO_SELECT_INPUT  = 15U,         /**< IOMUXC select input index */
0599     kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U,       /**< IOMUXC select input index */
0600     kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U,       /**< IOMUXC select input index */
0601     kIOMUXC_ENET_RXEN_SELECT_INPUT  = 18U,         /**< IOMUXC select input index */
0602     kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,         /**< IOMUXC select input index */
0603     kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U,        /**< IOMUXC select input index */
0604     kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U,         /**< IOMUXC select input index */
0605     kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U,        /**< IOMUXC select input index */
0606     kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,        /**< IOMUXC select input index */
0607     kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U,     /**< IOMUXC select input index */
0608     kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U,     /**< IOMUXC select input index */
0609     kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U,     /**< IOMUXC select input index */
0610     kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,     /**< IOMUXC select input index */
0611     kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U,     /**< IOMUXC select input index */
0612     kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U,     /**< IOMUXC select input index */
0613     kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U,     /**< IOMUXC select input index */
0614     kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,     /**< IOMUXC select input index */
0615     kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U,     /**< IOMUXC select input index */
0616     kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U,     /**< IOMUXC select input index */
0617     kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U,     /**< IOMUXC select input index */
0618     kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,     /**< IOMUXC select input index */
0619     kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U,     /**< IOMUXC select input index */
0620     kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U,     /**< IOMUXC select input index */
0621     kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U,     /**< IOMUXC select input index */
0622     kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,     /**< IOMUXC select input index */
0623     kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U,     /**< IOMUXC select input index */
0624     kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U,     /**< IOMUXC select input index */
0625     kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U,     /**< IOMUXC select input index */
0626     kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,     /**< IOMUXC select input index */
0627     kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT = 44U,      /**< IOMUXC select input index */
0628     kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 45U,    /**< IOMUXC select input index */
0629     kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 46U,    /**< IOMUXC select input index */
0630     kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 47U,    /**< IOMUXC select input index */
0631     kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 48U,    /**< IOMUXC select input index */
0632     kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT = 49U,    /**< IOMUXC select input index */
0633     kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT = 50U,    /**< IOMUXC select input index */
0634     kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT = 51U,    /**< IOMUXC select input index */
0635     kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT = 52U,    /**< IOMUXC select input index */
0636     kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT = 53U,      /**< IOMUXC select input index */
0637     kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U,         /**< IOMUXC select input index */
0638     kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,         /**< IOMUXC select input index */
0639     kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U,         /**< IOMUXC select input index */
0640     kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U,         /**< IOMUXC select input index */
0641     kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U,         /**< IOMUXC select input index */
0642     kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,         /**< IOMUXC select input index */
0643     kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U,         /**< IOMUXC select input index */
0644     kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U,         /**< IOMUXC select input index */
0645     kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U,        /**< IOMUXC select input index */
0646     kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,         /**< IOMUXC select input index */
0647     kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U,         /**< IOMUXC select input index */
0648     kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U,         /**< IOMUXC select input index */
0649     kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U,        /**< IOMUXC select input index */
0650     kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,         /**< IOMUXC select input index */
0651     kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U,         /**< IOMUXC select input index */
0652     kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U,         /**< IOMUXC select input index */
0653     kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U,        /**< IOMUXC select input index */
0654     kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,         /**< IOMUXC select input index */
0655     kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U,         /**< IOMUXC select input index */
0656     kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U,         /**< IOMUXC select input index */
0657     kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U,        /**< IOMUXC select input index */
0658     kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,         /**< IOMUXC select input index */
0659     kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U,         /**< IOMUXC select input index */
0660     kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U,         /**< IOMUXC select input index */
0661     kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U,         /**< IOMUXC select input index */
0662     kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,         /**< IOMUXC select input index */
0663     kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U,      /**< IOMUXC select input index */
0664     kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U,         /**< IOMUXC select input index */
0665     kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U,         /**< IOMUXC select input index */
0666     kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,         /**< IOMUXC select input index */
0667     kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U,         /**< IOMUXC select input index */
0668     kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U,         /**< IOMUXC select input index */
0669     kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U,         /**< IOMUXC select input index */
0670     kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,         /**< IOMUXC select input index */
0671     kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U,         /**< IOMUXC select input index */
0672     kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U,         /**< IOMUXC select input index */
0673     kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U,         /**< IOMUXC select input index */
0674     kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,         /**< IOMUXC select input index */
0675     kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U,         /**< IOMUXC select input index */
0676     kIOMUXC_NMI_SELECT_INPUT        = 93U,         /**< IOMUXC select input index */
0677     kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U,     /**< IOMUXC select input index */
0678     kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,     /**< IOMUXC select input index */
0679     kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U,     /**< IOMUXC select input index */
0680     kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U,     /**< IOMUXC select input index */
0681     kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U,     /**< IOMUXC select input index */
0682     kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,     /**< IOMUXC select input index */
0683     kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U,    /**< IOMUXC select input index */
0684     kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U,    /**< IOMUXC select input index */
0685     kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U,        /**< IOMUXC select input index */
0686     kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,      /**< IOMUXC select input index */
0687     kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U,     /**< IOMUXC select input index */
0688     kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U,     /**< IOMUXC select input index */
0689     kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U,     /**< IOMUXC select input index */
0690     kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,     /**< IOMUXC select input index */
0691     kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U,      /**< IOMUXC select input index */
0692     kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U,      /**< IOMUXC select input index */
0693     kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U,      /**< IOMUXC select input index */
0694     kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,        /**< IOMUXC select input index */
0695     kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U,      /**< IOMUXC select input index */
0696     kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U,     /**< IOMUXC select input index */
0697     kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U,      /**< IOMUXC select input index */
0698     kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,      /**< IOMUXC select input index */
0699     kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U,      /**< IOMUXC select input index */
0700     kIOMUXC_SPDIF_IN_SELECT_INPUT   = 117U,        /**< IOMUXC select input index */
0701     kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U,       /**< IOMUXC select input index */
0702     kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,       /**< IOMUXC select input index */
0703     kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U,       /**< IOMUXC select input index */
0704     kIOMUXC_USDHC1_WP_SELECT_INPUT  = 121U,        /**< IOMUXC select input index */
0705     kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U,        /**< IOMUXC select input index */
0706     kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,       /**< IOMUXC select input index */
0707     kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U,        /**< IOMUXC select input index */
0708     kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U,      /**< IOMUXC select input index */
0709     kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U,      /**< IOMUXC select input index */
0710     kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,      /**< IOMUXC select input index */
0711     kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U,      /**< IOMUXC select input index */
0712     kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U,      /**< IOMUXC select input index */
0713     kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U,      /**< IOMUXC select input index */
0714     kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,      /**< IOMUXC select input index */
0715     kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U,      /**< IOMUXC select input index */
0716     kIOMUXC_USDHC2_WP_SELECT_INPUT  = 133U,        /**< IOMUXC select input index */
0717     kIOMUXC_XBAR_INOUT02_SELECT_INPUT = 134U,      /**< IOMUXC select input index */
0718     kIOMUXC_XBAR_INOUT03_SELECT_INPUT = 135U,      /**< IOMUXC select input index */
0719     kIOMUXC_XBAR_INOUT04_SELECT_INPUT = 136U,      /**< IOMUXC select input index */
0720     kIOMUXC_XBAR_INOUT05_SELECT_INPUT = 137U,      /**< IOMUXC select input index */
0721     kIOMUXC_XBAR_INOUT06_SELECT_INPUT = 138U,      /**< IOMUXC select input index */
0722     kIOMUXC_XBAR_INOUT07_SELECT_INPUT = 139U,      /**< IOMUXC select input index */
0723     kIOMUXC_XBAR_INOUT08_SELECT_INPUT = 140U,      /**< IOMUXC select input index */
0724     kIOMUXC_XBAR_INOUT09_SELECT_INPUT = 141U,      /**< IOMUXC select input index */
0725     kIOMUXC_XBAR_INOUT17_SELECT_INPUT = 142U,      /**< IOMUXC select input index */
0726     kIOMUXC_XBAR_INOUT18_SELECT_INPUT = 143U,      /**< IOMUXC select input index */
0727     kIOMUXC_XBAR_INOUT20_SELECT_INPUT = 144U,      /**< IOMUXC select input index */
0728     kIOMUXC_XBAR_INOUT22_SELECT_INPUT = 145U,      /**< IOMUXC select input index */
0729     kIOMUXC_XBAR_INOUT23_SELECT_INPUT = 146U,      /**< IOMUXC select input index */
0730     kIOMUXC_XBAR_INOUT24_SELECT_INPUT = 147U,      /**< IOMUXC select input index */
0731     kIOMUXC_XBAR_INOUT14_SELECT_INPUT = 148U,      /**< IOMUXC select input index */
0732     kIOMUXC_XBAR_INOUT15_SELECT_INPUT = 149U,      /**< IOMUXC select input index */
0733     kIOMUXC_XBAR_INOUT16_SELECT_INPUT = 150U,      /**< IOMUXC select input index */
0734     kIOMUXC_XBAR_INOUT25_SELECT_INPUT = 151U,      /**< IOMUXC select input index */
0735     kIOMUXC_XBAR_INOUT19_SELECT_INPUT = 152U,      /**< IOMUXC select input index */
0736     kIOMUXC_XBAR_INOUT21_SELECT_INPUT = 153U,      /**< IOMUXC select input index */
0737 } iomuxc_select_input_t;
0738 
0739 typedef enum _xbar_input_signal
0740 {
0741     kXBARA1_InputLogicLow           = 0|0x100U,    /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
0742     kXBARA1_InputLogicHigh          = 1|0x100U,    /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
0743     kXBARA1_InputIomuxXbarIn02      = 2|0x100U,    /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
0744     kXBARA1_InputIomuxXbarIn03      = 3|0x100U,    /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
0745     kXBARA1_InputIomuxXbarInout04   = 4|0x100U,    /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
0746     kXBARA1_InputIomuxXbarInout05   = 5|0x100U,    /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
0747     kXBARA1_InputIomuxXbarInout06   = 6|0x100U,    /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
0748     kXBARA1_InputIomuxXbarInout07   = 7|0x100U,    /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
0749     kXBARA1_InputIomuxXbarInout08   = 8|0x100U,    /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
0750     kXBARA1_InputIomuxXbarInout09   = 9|0x100U,    /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
0751     kXBARA1_InputIomuxXbarInout10   = 10|0x100U,   /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
0752     kXBARA1_InputIomuxXbarInout11   = 11|0x100U,   /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
0753     kXBARA1_InputIomuxXbarInout12   = 12|0x100U,   /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
0754     kXBARA1_InputIomuxXbarInout13   = 13|0x100U,   /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
0755     kXBARA1_InputIomuxXbarInout14   = 14|0x100U,   /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
0756     kXBARA1_InputIomuxXbarInout15   = 15|0x100U,   /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
0757     kXBARA1_InputIomuxXbarInout16   = 16|0x100U,   /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
0758     kXBARA1_InputIomuxXbarInout17   = 17|0x100U,   /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
0759     kXBARA1_InputIomuxXbarInout18   = 18|0x100U,   /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
0760     kXBARA1_InputIomuxXbarInout19   = 19|0x100U,   /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
0761     kXBARA1_InputIomuxXbarIn20      = 20|0x100U,   /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
0762     kXBARA1_InputIomuxXbarIn21      = 21|0x100U,   /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
0763     kXBARA1_InputIomuxXbarIn22      = 22|0x100U,   /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
0764     kXBARA1_InputIomuxXbarIn23      = 23|0x100U,   /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
0765     kXBARA1_InputIomuxXbarIn24      = 24|0x100U,   /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
0766     kXBARA1_InputIomuxXbarIn25      = 25|0x100U,   /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
0767     kXBARA1_InputAcmp1Out           = 26|0x100U,   /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */
0768     kXBARA1_InputAcmp2Out           = 27|0x100U,   /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */
0769     kXBARA1_InputAcmp3Out           = 28|0x100U,   /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */
0770     kXBARA1_InputAcmp4Out           = 29|0x100U,   /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */
0771     kXBARA1_InputRESERVED30         = 30|0x100U,   /**< XBARA1_IN30 input is reserved. */
0772     kXBARA1_InputRESERVED31         = 31|0x100U,   /**< XBARA1_IN31 input is reserved. */
0773     kXBARA1_InputQtimer3Tmr0Output  = 32|0x100U,   /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
0774     kXBARA1_InputQtimer3Tmr1Output  = 33|0x100U,   /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
0775     kXBARA1_InputQtimer3Tmr2Output  = 34|0x100U,   /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
0776     kXBARA1_InputQtimer3Tmr3Output  = 35|0x100U,   /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
0777     kXBARA1_InputQtimer4Tmr0Output  = 36|0x100U,   /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
0778     kXBARA1_InputQtimer4Tmr1Output  = 37|0x100U,   /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
0779     kXBARA1_InputQtimer4Tmr2Output  = 38|0x100U,   /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
0780     kXBARA1_InputQtimer4Tmr3Output  = 39|0x100U,   /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
0781     kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
0782     kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
0783     kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
0784     kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
0785     kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
0786     kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
0787     kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
0788     kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
0789     kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
0790     kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
0791     kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
0792     kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
0793     kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
0794     kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
0795     kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
0796     kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
0797     kXBARA1_InputPitTrigger0        = 56|0x100U,   /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
0798     kXBARA1_InputPitTrigger1        = 57|0x100U,   /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
0799     kXBARA1_InputPitTrigger2        = 58|0x100U,   /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
0800     kXBARA1_InputPitTrigger3        = 59|0x100U,   /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
0801     kXBARA1_InputEnc1PosMatch       = 60|0x100U,   /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
0802     kXBARA1_InputEnc2PosMatch       = 61|0x100U,   /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
0803     kXBARA1_InputEnc3PosMatch       = 62|0x100U,   /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
0804     kXBARA1_InputEnc4PosMatch       = 63|0x100U,   /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
0805     kXBARA1_InputDmaDone0           = 64|0x100U,   /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */
0806     kXBARA1_InputDmaDone1           = 65|0x100U,   /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */
0807     kXBARA1_InputDmaDone2           = 66|0x100U,   /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */
0808     kXBARA1_InputDmaDone3           = 67|0x100U,   /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */
0809     kXBARA1_InputDmaDone4           = 68|0x100U,   /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */
0810     kXBARA1_InputDmaDone5           = 69|0x100U,   /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */
0811     kXBARA1_InputDmaDone6           = 70|0x100U,   /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */
0812     kXBARA1_InputDmaDone7           = 71|0x100U,   /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */
0813     kXBARA1_InputAoi1Out0           = 72|0x100U,   /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */
0814     kXBARA1_InputAoi1Out1           = 73|0x100U,   /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */
0815     kXBARA1_InputAoi1Out2           = 74|0x100U,   /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */
0816     kXBARA1_InputAoi1Out3           = 75|0x100U,   /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */
0817     kXBARA1_InputAoi2Out0           = 76|0x100U,   /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */
0818     kXBARA1_InputAoi2Out1           = 77|0x100U,   /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */
0819     kXBARA1_InputAoi2Out2           = 78|0x100U,   /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */
0820     kXBARA1_InputAoi2Out3           = 79|0x100U,   /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */
0821     kXBARA1_InputAdcEtcXbar0Coco0   = 80|0x100U,   /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
0822     kXBARA1_InputAdcEtcXbar0Coco1   = 81|0x100U,   /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
0823     kXBARA1_InputAdcEtcXbar0Coco2   = 82|0x100U,   /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
0824     kXBARA1_InputAdcEtcXbar0Coco3   = 83|0x100U,   /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
0825     kXBARA1_InputAdcEtcXbar1Coco0   = 84|0x100U,   /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
0826     kXBARA1_InputAdcEtcXbar1Coco1   = 85|0x100U,   /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
0827     kXBARA1_InputAdcEtcXbar1Coco2   = 86|0x100U,   /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
0828     kXBARA1_InputAdcEtcXbar1Coco3   = 87|0x100U,   /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
0829     kXBARB2_InputLogicLow           = 0|0x200U,    /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
0830     kXBARB2_InputLogicHigh          = 1|0x200U,    /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
0831     kXBARB2_InputRESERVED2          = 2|0x200U,    /**< XBARB2_IN2 input is reserved. */
0832     kXBARB2_InputRESERVED3          = 3|0x200U,    /**< XBARB2_IN3 input is reserved. */
0833     kXBARB2_InputRESERVED4          = 4|0x200U,    /**< XBARB2_IN4 input is reserved. */
0834     kXBARB2_InputRESERVED5          = 5|0x200U,    /**< XBARB2_IN5 input is reserved. */
0835     kXBARB2_InputAcmp1Out           = 6|0x200U,    /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */
0836     kXBARB2_InputAcmp2Out           = 7|0x200U,    /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */
0837     kXBARB2_InputAcmp3Out           = 8|0x200U,    /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */
0838     kXBARB2_InputAcmp4Out           = 9|0x200U,    /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */
0839     kXBARB2_InputRESERVED10         = 10|0x200U,   /**< XBARB2_IN10 input is reserved. */
0840     kXBARB2_InputRESERVED11         = 11|0x200U,   /**< XBARB2_IN11 input is reserved. */
0841     kXBARB2_InputQtimer3Tmr0Output  = 12|0x200U,   /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
0842     kXBARB2_InputQtimer3Tmr1Output  = 13|0x200U,   /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
0843     kXBARB2_InputQtimer3Tmr2Output  = 14|0x200U,   /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
0844     kXBARB2_InputQtimer3Tmr3Output  = 15|0x200U,   /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
0845     kXBARB2_InputQtimer4Tmr0Output  = 16|0x200U,   /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
0846     kXBARB2_InputQtimer4Tmr1Output  = 17|0x200U,   /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
0847     kXBARB2_InputQtimer4Tmr2Output  = 18|0x200U,   /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
0848     kXBARB2_InputQtimer4Tmr3Output  = 19|0x200U,   /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
0849     kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
0850     kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
0851     kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
0852     kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
0853     kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
0854     kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
0855     kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
0856     kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
0857     kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
0858     kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
0859     kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
0860     kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
0861     kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
0862     kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
0863     kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
0864     kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
0865     kXBARB2_InputPitTrigger0        = 36|0x200U,   /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
0866     kXBARB2_InputPitTrigger1        = 37|0x200U,   /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
0867     kXBARB2_InputAdcEtcXbar0Coco0   = 38|0x200U,   /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
0868     kXBARB2_InputAdcEtcXbar0Coco1   = 39|0x200U,   /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
0869     kXBARB2_InputAdcEtcXbar0Coco2   = 40|0x200U,   /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
0870     kXBARB2_InputAdcEtcXbar0Coco3   = 41|0x200U,   /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
0871     kXBARB2_InputAdcEtcXbar1Coco0   = 42|0x200U,   /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
0872     kXBARB2_InputAdcEtcXbar1Coco1   = 43|0x200U,   /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
0873     kXBARB2_InputAdcEtcXbar1Coco2   = 44|0x200U,   /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
0874     kXBARB2_InputAdcEtcXbar1Coco3   = 45|0x200U,   /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
0875     kXBARB2_InputEnc1PosMatch       = 46|0x200U,   /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
0876     kXBARB2_InputEnc2PosMatch       = 47|0x200U,   /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
0877     kXBARB2_InputEnc3PosMatch       = 48|0x200U,   /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
0878     kXBARB2_InputEnc4PosMatch       = 49|0x200U,   /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
0879     kXBARB2_InputDmaDone0           = 50|0x200U,   /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */
0880     kXBARB2_InputDmaDone1           = 51|0x200U,   /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */
0881     kXBARB2_InputDmaDone2           = 52|0x200U,   /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */
0882     kXBARB2_InputDmaDone3           = 53|0x200U,   /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */
0883     kXBARB2_InputDmaDone4           = 54|0x200U,   /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */
0884     kXBARB2_InputDmaDone5           = 55|0x200U,   /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */
0885     kXBARB2_InputDmaDone6           = 56|0x200U,   /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */
0886     kXBARB2_InputDmaDone7           = 57|0x200U,   /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */
0887     kXBARB3_InputLogicLow           = 0|0x300U,    /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
0888     kXBARB3_InputLogicHigh          = 1|0x300U,    /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
0889     kXBARB3_InputRESERVED2          = 2|0x300U,    /**< XBARB3_IN2 input is reserved. */
0890     kXBARB3_InputRESERVED3          = 3|0x300U,    /**< XBARB3_IN3 input is reserved. */
0891     kXBARB3_InputRESERVED4          = 4|0x300U,    /**< XBARB3_IN4 input is reserved. */
0892     kXBARB3_InputRESERVED5          = 5|0x300U,    /**< XBARB3_IN5 input is reserved. */
0893     kXBARB3_InputAcmp1Out           = 6|0x300U,    /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */
0894     kXBARB3_InputAcmp2Out           = 7|0x300U,    /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */
0895     kXBARB3_InputAcmp3Out           = 8|0x300U,    /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */
0896     kXBARB3_InputAcmp4Out           = 9|0x300U,    /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */
0897     kXBARB3_InputRESERVED10         = 10|0x300U,   /**< XBARB3_IN10 input is reserved. */
0898     kXBARB3_InputRESERVED11         = 11|0x300U,   /**< XBARB3_IN11 input is reserved. */
0899     kXBARB3_InputQtimer3Tmr0Output  = 12|0x300U,   /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
0900     kXBARB3_InputQtimer3Tmr1Output  = 13|0x300U,   /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
0901     kXBARB3_InputQtimer3Tmr2Output  = 14|0x300U,   /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
0902     kXBARB3_InputQtimer3Tmr3Output  = 15|0x300U,   /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
0903     kXBARB3_InputQtimer4Tmr0Output  = 16|0x300U,   /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
0904     kXBARB3_InputQtimer4Tmr1Output  = 17|0x300U,   /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
0905     kXBARB3_InputQtimer4Tmr2Output  = 18|0x300U,   /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
0906     kXBARB3_InputQtimer4Tmr3Output  = 19|0x300U,   /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
0907     kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
0908     kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
0909     kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
0910     kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
0911     kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
0912     kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
0913     kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
0914     kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
0915     kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
0916     kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
0917     kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
0918     kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
0919     kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
0920     kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
0921     kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
0922     kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
0923     kXBARB3_InputPitTrigger0        = 36|0x300U,   /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
0924     kXBARB3_InputPitTrigger1        = 37|0x300U,   /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
0925     kXBARB3_InputAdcEtcXbar0Coco0   = 38|0x300U,   /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
0926     kXBARB3_InputAdcEtcXbar0Coco1   = 39|0x300U,   /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
0927     kXBARB3_InputAdcEtcXbar0Coco2   = 40|0x300U,   /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
0928     kXBARB3_InputAdcEtcXbar0Coco3   = 41|0x300U,   /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
0929     kXBARB3_InputAdcEtcXbar1Coco0   = 42|0x300U,   /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
0930     kXBARB3_InputAdcEtcXbar1Coco1   = 43|0x300U,   /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
0931     kXBARB3_InputAdcEtcXbar1Coco2   = 44|0x300U,   /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
0932     kXBARB3_InputAdcEtcXbar1Coco3   = 45|0x300U,   /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
0933     kXBARB3_InputEnc1PosMatch       = 46|0x300U,   /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
0934     kXBARB3_InputEnc2PosMatch       = 47|0x300U,   /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
0935     kXBARB3_InputEnc3PosMatch       = 48|0x300U,   /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
0936     kXBARB3_InputEnc4PosMatch       = 49|0x300U,   /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
0937     kXBARB3_InputDmaDone0           = 50|0x300U,   /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */
0938     kXBARB3_InputDmaDone1           = 51|0x300U,   /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */
0939     kXBARB3_InputDmaDone2           = 52|0x300U,   /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */
0940     kXBARB3_InputDmaDone3           = 53|0x300U,   /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */
0941     kXBARB3_InputDmaDone4           = 54|0x300U,   /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */
0942     kXBARB3_InputDmaDone5           = 55|0x300U,   /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */
0943     kXBARB3_InputDmaDone6           = 56|0x300U,   /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */
0944     kXBARB3_InputDmaDone7           = 57|0x300U,   /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */
0945 } xbar_input_signal_t;
0946 
0947 typedef enum _xbar_output_signal
0948 {
0949     kXBARA1_OutputDmaChMuxReq30     = 0|0x100U,    /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
0950     kXBARA1_OutputDmaChMuxReq31     = 1|0x100U,    /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
0951     kXBARA1_OutputDmaChMuxReq94     = 2|0x100U,    /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
0952     kXBARA1_OutputDmaChMuxReq95     = 3|0x100U,    /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
0953     kXBARA1_OutputIomuxXbarInout04  = 4|0x100U,    /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
0954     kXBARA1_OutputIomuxXbarInout05  = 5|0x100U,    /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
0955     kXBARA1_OutputIomuxXbarInout06  = 6|0x100U,    /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
0956     kXBARA1_OutputIomuxXbarInout07  = 7|0x100U,    /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
0957     kXBARA1_OutputIomuxXbarInout08  = 8|0x100U,    /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
0958     kXBARA1_OutputIomuxXbarInout09  = 9|0x100U,    /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
0959     kXBARA1_OutputIomuxXbarInout10  = 10|0x100U,   /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
0960     kXBARA1_OutputIomuxXbarInout11  = 11|0x100U,   /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
0961     kXBARA1_OutputIomuxXbarInout12  = 12|0x100U,   /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
0962     kXBARA1_OutputIomuxXbarInout13  = 13|0x100U,   /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
0963     kXBARA1_OutputIomuxXbarInout14  = 14|0x100U,   /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
0964     kXBARA1_OutputIomuxXbarInout15  = 15|0x100U,   /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
0965     kXBARA1_OutputIomuxXbarInout16  = 16|0x100U,   /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
0966     kXBARA1_OutputIomuxXbarInout17  = 17|0x100U,   /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
0967     kXBARA1_OutputIomuxXbarInout18  = 18|0x100U,   /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
0968     kXBARA1_OutputIomuxXbarInout19  = 19|0x100U,   /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
0969     kXBARA1_OutputAcmp1Sample       = 20|0x100U,   /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
0970     kXBARA1_OutputAcmp2Sample       = 21|0x100U,   /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
0971     kXBARA1_OutputAcmp3Sample       = 22|0x100U,   /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
0972     kXBARA1_OutputAcmp4Sample       = 23|0x100U,   /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
0973     kXBARA1_OutputRESERVED24        = 24|0x100U,   /**< XBARA1_OUT24 output is reserved. */
0974     kXBARA1_OutputRESERVED25        = 25|0x100U,   /**< XBARA1_OUT25 output is reserved. */
0975     kXBARA1_OutputFlexpwm1Exta0     = 26|0x100U,   /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
0976     kXBARA1_OutputFlexpwm1Exta1     = 27|0x100U,   /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
0977     kXBARA1_OutputFlexpwm1Exta2     = 28|0x100U,   /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
0978     kXBARA1_OutputFlexpwm1Exta3     = 29|0x100U,   /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
0979     kXBARA1_OutputFlexpwm1ExtSync0  = 30|0x100U,   /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
0980     kXBARA1_OutputFlexpwm1ExtSync1  = 31|0x100U,   /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
0981     kXBARA1_OutputFlexpwm1ExtSync2  = 32|0x100U,   /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
0982     kXBARA1_OutputFlexpwm1ExtSync3  = 33|0x100U,   /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
0983     kXBARA1_OutputFlexpwm1ExtClk    = 34|0x100U,   /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
0984     kXBARA1_OutputFlexpwm1Fault0    = 35|0x100U,   /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
0985     kXBARA1_OutputFlexpwm1Fault1    = 36|0x100U,   /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
0986     kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U,   /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
0987     kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U,   /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
0988     kXBARA1_OutputFlexpwm1ExtForce  = 39|0x100U,   /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
0989     kXBARA1_OutputFlexpwm234Exta0   = 40|0x100U,   /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
0990     kXBARA1_OutputFlexpwm234Exta1   = 41|0x100U,   /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
0991     kXBARA1_OutputFlexpwm234Exta2   = 42|0x100U,   /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
0992     kXBARA1_OutputFlexpwm234Exta3   = 43|0x100U,   /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
0993     kXBARA1_OutputFlexpwm2ExtSync0  = 44|0x100U,   /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
0994     kXBARA1_OutputFlexpwm2ExtSync1  = 45|0x100U,   /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
0995     kXBARA1_OutputFlexpwm2ExtSync2  = 46|0x100U,   /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
0996     kXBARA1_OutputFlexpwm2ExtSync3  = 47|0x100U,   /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
0997     kXBARA1_OutputFlexpwm234ExtClk  = 48|0x100U,   /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
0998     kXBARA1_OutputFlexpwm2Fault0    = 49|0x100U,   /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
0999     kXBARA1_OutputFlexpwm2Fault1    = 50|0x100U,   /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
1000     kXBARA1_OutputFlexpwm2ExtForce  = 51|0x100U,   /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
1001     kXBARA1_OutputFlexpwm3ExtSync0  = 52|0x100U,   /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
1002     kXBARA1_OutputFlexpwm3ExtSync1  = 53|0x100U,   /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
1003     kXBARA1_OutputFlexpwm3ExtSync2  = 54|0x100U,   /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
1004     kXBARA1_OutputFlexpwm3ExtSync3  = 55|0x100U,   /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
1005     kXBARA1_OutputFlexpwm3Fault0    = 56|0x100U,   /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
1006     kXBARA1_OutputFlexpwm3Fault1    = 57|0x100U,   /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
1007     kXBARA1_OutputFlexpwm3ExtForce  = 58|0x100U,   /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
1008     kXBARA1_OutputFlexpwm4ExtSync0  = 59|0x100U,   /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
1009     kXBARA1_OutputFlexpwm4ExtSync1  = 60|0x100U,   /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
1010     kXBARA1_OutputFlexpwm4ExtSync2  = 61|0x100U,   /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
1011     kXBARA1_OutputFlexpwm4ExtSync3  = 62|0x100U,   /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
1012     kXBARA1_OutputFlexpwm4Fault0    = 63|0x100U,   /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
1013     kXBARA1_OutputFlexpwm4Fault1    = 64|0x100U,   /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
1014     kXBARA1_OutputFlexpwm4ExtForce  = 65|0x100U,   /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
1015     kXBARA1_OutputEnc1PhaseAInput   = 66|0x100U,   /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */
1016     kXBARA1_OutputEnc1PhaseBInput   = 67|0x100U,   /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */
1017     kXBARA1_OutputEnc1Index         = 68|0x100U,   /**< XBARA1_OUT68 output assigned to ENC1_INDEX */
1018     kXBARA1_OutputEnc1Home          = 69|0x100U,   /**< XBARA1_OUT69 output assigned to ENC1_HOME */
1019     kXBARA1_OutputEnc1Trigger       = 70|0x100U,   /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */
1020     kXBARA1_OutputEnc2PhaseAInput   = 71|0x100U,   /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */
1021     kXBARA1_OutputEnc2PhaseBInput   = 72|0x100U,   /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */
1022     kXBARA1_OutputEnc2Index         = 73|0x100U,   /**< XBARA1_OUT73 output assigned to ENC2_INDEX */
1023     kXBARA1_OutputEnc2Home          = 74|0x100U,   /**< XBARA1_OUT74 output assigned to ENC2_HOME */
1024     kXBARA1_OutputEnc2Trigger       = 75|0x100U,   /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */
1025     kXBARA1_OutputEnc3PhaseAInput   = 76|0x100U,   /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */
1026     kXBARA1_OutputEnc3PhaseBInput   = 77|0x100U,   /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */
1027     kXBARA1_OutputEnc3Index         = 78|0x100U,   /**< XBARA1_OUT78 output assigned to ENC3_INDEX */
1028     kXBARA1_OutputEnc3Home          = 79|0x100U,   /**< XBARA1_OUT79 output assigned to ENC3_HOME */
1029     kXBARA1_OutputEnc3Trigger       = 80|0x100U,   /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */
1030     kXBARA1_OutputEnc4PhaseAInput   = 81|0x100U,   /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */
1031     kXBARA1_OutputEnc4PhaseBInput   = 82|0x100U,   /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */
1032     kXBARA1_OutputEnc4Index         = 83|0x100U,   /**< XBARA1_OUT83 output assigned to ENC4_INDEX */
1033     kXBARA1_OutputEnc4Home          = 84|0x100U,   /**< XBARA1_OUT84 output assigned to ENC4_HOME */
1034     kXBARA1_OutputEnc4Trigger       = 85|0x100U,   /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */
1035     kXBARA1_OutputQtimer1Tmr0Input  = 86|0x100U,   /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */
1036     kXBARA1_OutputQtimer1Tmr1Input  = 87|0x100U,   /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */
1037     kXBARA1_OutputQtimer1Tmr2Input  = 88|0x100U,   /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */
1038     kXBARA1_OutputQtimer1Tmr3Input  = 89|0x100U,   /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */
1039     kXBARA1_OutputQtimer2Tmr0Input  = 90|0x100U,   /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */
1040     kXBARA1_OutputQtimer2Tmr1Input  = 91|0x100U,   /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */
1041     kXBARA1_OutputQtimer2Tmr2Input  = 92|0x100U,   /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */
1042     kXBARA1_OutputQtimer2Tmr3Input  = 93|0x100U,   /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */
1043     kXBARA1_OutputQtimer3Tmr0Input  = 94|0x100U,   /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */
1044     kXBARA1_OutputQtimer3Tmr1Input  = 95|0x100U,   /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */
1045     kXBARA1_OutputQtimer3Tmr2Input  = 96|0x100U,   /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */
1046     kXBARA1_OutputQtimer3Tmr3Input  = 97|0x100U,   /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */
1047     kXBARA1_OutputQtimer4Tmr0Input  = 98|0x100U,   /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */
1048     kXBARA1_OutputQtimer4Tmr1Input  = 99|0x100U,   /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */
1049     kXBARA1_OutputQtimer4Tmr2Input  = 100|0x100U,  /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */
1050     kXBARA1_OutputQtimer4Tmr3Input  = 101|0x100U,  /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */
1051     kXBARA1_OutputEwmEwmIn          = 102|0x100U,  /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */
1052     kXBARA1_OutputAdcEtcXbar0Trig0  = 103|0x100U,  /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
1053     kXBARA1_OutputAdcEtcXbar0Trig1  = 104|0x100U,  /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
1054     kXBARA1_OutputAdcEtcXbar0Trig2  = 105|0x100U,  /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
1055     kXBARA1_OutputAdcEtcXbar0Trig3  = 106|0x100U,  /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
1056     kXBARA1_OutputAdcEtcXbar1Trig0  = 107|0x100U,  /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
1057     kXBARA1_OutputAdcEtcXbar1Trig1  = 108|0x100U,  /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
1058     kXBARA1_OutputAdcEtcXbar1Trig2  = 109|0x100U,  /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
1059     kXBARA1_OutputAdcEtcXbar1Trig3  = 110|0x100U,  /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
1060     kXBARA1_OutputLpi2c1TrgInput    = 111|0x100U,  /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */
1061     kXBARA1_OutputLpi2c2TrgInput    = 112|0x100U,  /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */
1062     kXBARA1_OutputLpi2c3TrgInput    = 113|0x100U,  /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */
1063     kXBARA1_OutputLpi2c4TrgInput    = 114|0x100U,  /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */
1064     kXBARA1_OutputLpspi1TrgInput    = 115|0x100U,  /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */
1065     kXBARA1_OutputLpspi2TrgInput    = 116|0x100U,  /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */
1066     kXBARA1_OutputLpspi3TrgInput    = 117|0x100U,  /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */
1067     kXBARA1_OutputLpspi4TrgInput    = 118|0x100U,  /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */
1068     kXBARA1_OutputLpuart1TrgInput   = 119|0x100U,  /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */
1069     kXBARA1_OutputLpuart2TrgInput   = 120|0x100U,  /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */
1070     kXBARA1_OutputLpuart3TrgInput   = 121|0x100U,  /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */
1071     kXBARA1_OutputLpuart4TrgInput   = 122|0x100U,  /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */
1072     kXBARA1_OutputLpuart5TrgInput   = 123|0x100U,  /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */
1073     kXBARA1_OutputLpuart6TrgInput   = 124|0x100U,  /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */
1074     kXBARA1_OutputLpuart7TrgInput   = 125|0x100U,  /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */
1075     kXBARA1_OutputLpuart8TrgInput   = 126|0x100U,  /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */
1076     kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,  /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
1077     kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U,  /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
1078     kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U,  /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
1079     kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U,  /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
1080     kXBARB2_OutputAoi1In00          = 0|0x200U,    /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
1081     kXBARB2_OutputAoi1In01          = 1|0x200U,    /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
1082     kXBARB2_OutputAoi1In02          = 2|0x200U,    /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
1083     kXBARB2_OutputAoi1In03          = 3|0x200U,    /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
1084     kXBARB2_OutputAoi1In04          = 4|0x200U,    /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
1085     kXBARB2_OutputAoi1In05          = 5|0x200U,    /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
1086     kXBARB2_OutputAoi1In06          = 6|0x200U,    /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
1087     kXBARB2_OutputAoi1In07          = 7|0x200U,    /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
1088     kXBARB2_OutputAoi1In08          = 8|0x200U,    /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
1089     kXBARB2_OutputAoi1In09          = 9|0x200U,    /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
1090     kXBARB2_OutputAoi1In10          = 10|0x200U,   /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
1091     kXBARB2_OutputAoi1In11          = 11|0x200U,   /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
1092     kXBARB2_OutputAoi1In12          = 12|0x200U,   /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
1093     kXBARB2_OutputAoi1In13          = 13|0x200U,   /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
1094     kXBARB2_OutputAoi1In14          = 14|0x200U,   /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
1095     kXBARB2_OutputAoi1In15          = 15|0x200U,   /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
1096     kXBARB3_OutputAoi2In00          = 0|0x300U,    /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
1097     kXBARB3_OutputAoi2In01          = 1|0x300U,    /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
1098     kXBARB3_OutputAoi2In02          = 2|0x300U,    /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
1099     kXBARB3_OutputAoi2In03          = 3|0x300U,    /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
1100     kXBARB3_OutputAoi2In04          = 4|0x300U,    /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
1101     kXBARB3_OutputAoi2In05          = 5|0x300U,    /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
1102     kXBARB3_OutputAoi2In06          = 6|0x300U,    /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
1103     kXBARB3_OutputAoi2In07          = 7|0x300U,    /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
1104     kXBARB3_OutputAoi2In08          = 8|0x300U,    /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
1105     kXBARB3_OutputAoi2In09          = 9|0x300U,    /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
1106     kXBARB3_OutputAoi2In10          = 10|0x300U,   /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
1107     kXBARB3_OutputAoi2In11          = 11|0x300U,   /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
1108     kXBARB3_OutputAoi2In12          = 12|0x300U,   /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
1109     kXBARB3_OutputAoi2In13          = 13|0x300U,   /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
1110     kXBARB3_OutputAoi2In14          = 14|0x300U,   /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
1111     kXBARB3_OutputAoi2In15          = 15|0x300U,   /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
1112 } xbar_output_signal_t;
1113 
1114 /*!
1115  * @addtogroup edma_request
1116  * @{
1117  */
1118 
1119 /*******************************************************************************
1120  * Definitions
1121  ******************************************************************************/
1122 
1123 /*!
1124  * @brief Structure for the DMA hardware request
1125  *
1126  * Defines the structure for the DMA hardware request collections. The user can configure the
1127  * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
1128  * of the hardware request varies according  to the to SoC.
1129  */
1130 typedef enum _dma_request_source
1131 {
1132     kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
1133     kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */
1134     kDmaRequestMuxLPUART1Tx         = 2|0x100U,    /**< LPUART1 Transmit */
1135     kDmaRequestMuxLPUART1Rx         = 3|0x100U,    /**< LPUART1 Receive */
1136     kDmaRequestMuxLPUART3Tx         = 4|0x100U,    /**< LPUART3 Transmit */
1137     kDmaRequestMuxLPUART3Rx         = 5|0x100U,    /**< LPUART3 Receive */
1138     kDmaRequestMuxLPUART5Tx         = 6|0x100U,    /**< LPUART5 Transmit */
1139     kDmaRequestMuxLPUART5Rx         = 7|0x100U,    /**< LPUART5 Receive */
1140     kDmaRequestMuxLPUART7Tx         = 8|0x100U,    /**< LPUART7 Transmit */
1141     kDmaRequestMuxLPUART7Rx         = 9|0x100U,    /**< LPUART7 Receive */
1142     kDmaRequestMuxCSI               = 12|0x100U,   /**< CSI */
1143     kDmaRequestMuxLPSPI1Rx          = 13|0x100U,   /**< LPSPI1 Receive */
1144     kDmaRequestMuxLPSPI1Tx          = 14|0x100U,   /**< LPSPI1 Transmit */
1145     kDmaRequestMuxLPSPI3Rx          = 15|0x100U,   /**< LPSPI3 Receive */
1146     kDmaRequestMuxLPSPI3Tx          = 16|0x100U,   /**< LPSPI3 Transmit */
1147     kDmaRequestMuxLPI2C1            = 17|0x100U,   /**< LPI2C1 */
1148     kDmaRequestMuxLPI2C3            = 18|0x100U,   /**< LPI2C3 */
1149     kDmaRequestMuxSai1Rx            = 19|0x100U,   /**< SAI1 Receive */
1150     kDmaRequestMuxSai1Tx            = 20|0x100U,   /**< SAI1 Transmit */
1151     kDmaRequestMuxSai2Rx            = 21|0x100U,   /**< SAI2 Receive */
1152     kDmaRequestMuxSai2Tx            = 22|0x100U,   /**< SAI2 Transmit */
1153     kDmaRequestMuxADC_ETC           = 23|0x100U,   /**< ADC_ETC */
1154     kDmaRequestMuxADC1              = 24|0x100U,   /**< ADC1 */
1155     kDmaRequestMuxACMP1             = 25|0x100U,   /**< ACMP1 */
1156     kDmaRequestMuxACMP3             = 26|0x100U,   /**< ACMP3 */
1157     kDmaRequestMuxFlexSPIRx         = 28|0x100U,   /**< FlexSPI Receive */
1158     kDmaRequestMuxFlexSPITx         = 29|0x100U,   /**< FlexSPI Transmit */
1159     kDmaRequestMuxXBAR1Request0     = 30|0x100U,   /**< XBAR1 Request 0 */
1160     kDmaRequestMuxXBAR1Request1     = 31|0x100U,   /**< XBAR1 Request 1 */
1161     kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
1162     kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
1163     kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
1164     kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
1165     kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U,   /**< FlexPWM1 Value sub-module0 */
1166     kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,   /**< FlexPWM1 Value sub-module1 */
1167     kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U,   /**< FlexPWM1 Value sub-module2 */
1168     kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U,   /**< FlexPWM1 Value sub-module3 */
1169     kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */
1170     kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */
1171     kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */
1172     kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */
1173     kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U,   /**< FlexPWM3 Value sub-module0 */
1174     kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,   /**< FlexPWM3 Value sub-module1 */
1175     kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U,   /**< FlexPWM3 Value sub-module2 */
1176     kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U,   /**< FlexPWM3 Value sub-module3 */
1177     kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,   /**< TMR1 Capture timer 0 */
1178     kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,   /**< TMR1 Capture timer 1 */
1179     kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,   /**< TMR1 Capture timer 2 */
1180     kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,   /**< TMR1 Capture timer 3 */
1181     kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
1182     kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
1183     kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
1184     kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
1185     kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
1186     kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
1187     kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
1188     kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
1189     kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
1190     kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */
1191     kDmaRequestMuxLPUART2Tx         = 66|0x100U,   /**< LPUART2 Transmit */
1192     kDmaRequestMuxLPUART2Rx         = 67|0x100U,   /**< LPUART2 Receive */
1193     kDmaRequestMuxLPUART4Tx         = 68|0x100U,   /**< LPUART4 Transmit */
1194     kDmaRequestMuxLPUART4Rx         = 69|0x100U,   /**< LPUART4 Receive */
1195     kDmaRequestMuxLPUART6Tx         = 70|0x100U,   /**< LPUART6 Transmit */
1196     kDmaRequestMuxLPUART6Rx         = 71|0x100U,   /**< LPUART6 Receive */
1197     kDmaRequestMuxLPUART8Tx         = 72|0x100U,   /**< LPUART8 Transmit */
1198     kDmaRequestMuxLPUART8Rx         = 73|0x100U,   /**< LPUART8 Receive */
1199     kDmaRequestMuxPxp               = 75|0x100U,   /**< PXP */
1200     kDmaRequestMuxLCDIF             = 76|0x100U,   /**< LCDIF */
1201     kDmaRequestMuxLPSPI2Rx          = 77|0x100U,   /**< LPSPI2 Receive */
1202     kDmaRequestMuxLPSPI2Tx          = 78|0x100U,   /**< LPSPI2 Transmit */
1203     kDmaRequestMuxLPSPI4Rx          = 79|0x100U,   /**< LPSPI4 Receive */
1204     kDmaRequestMuxLPSPI4Tx          = 80|0x100U,   /**< LPSPI4 Transmit */
1205     kDmaRequestMuxLPI2C2            = 81|0x100U,   /**< LPI2C2 */
1206     kDmaRequestMuxLPI2C4            = 82|0x100U,   /**< LPI2C4 */
1207     kDmaRequestMuxSai3Rx            = 83|0x100U,   /**< SAI3 Receive */
1208     kDmaRequestMuxSai3Tx            = 84|0x100U,   /**< SAI3 Transmit */
1209     kDmaRequestMuxSpdifRx           = 85|0x100U,   /**< SPDIF Receive */
1210     kDmaRequestMuxSpdifTx           = 86|0x100U,   /**< SPDIF Transmit */
1211     kDmaRequestMuxADC2              = 88|0x100U,   /**< ADC2 */
1212     kDmaRequestMuxACMP2             = 89|0x100U,   /**< ACMP2 */
1213     kDmaRequestMuxACMP4             = 90|0x100U,   /**< ACMP4 */
1214     kDmaRequestMuxEnetTimer0        = 92|0x100U,   /**< ENET Timer0 */
1215     kDmaRequestMuxEnetTimer1        = 93|0x100U,   /**< ENET Timer1 */
1216     kDmaRequestMuxXBAR1Request2     = 94|0x100U,   /**< XBAR1 Request 2 */
1217     kDmaRequestMuxXBAR1Request3     = 95|0x100U,   /**< XBAR1 Request 3 */
1218     kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
1219     kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
1220     kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
1221     kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
1222     kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U,  /**< FlexPWM2 Value sub-module0 */
1223     kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U,  /**< FlexPWM2 Value sub-module1 */
1224     kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,  /**< FlexPWM2 Value sub-module2 */
1225     kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U,  /**< FlexPWM2 Value sub-module3 */
1226     kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */
1227     kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */
1228     kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */
1229     kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */
1230     kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U,  /**< FlexPWM4 Value sub-module0 */
1231     kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U,  /**< FlexPWM4 Value sub-module1 */
1232     kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,  /**< FlexPWM4 Value sub-module2 */
1233     kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U,  /**< FlexPWM4 Value sub-module3 */
1234     kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,  /**< TMR2 Capture timer 0 */
1235     kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,  /**< TMR2 Capture timer 1 */
1236     kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,  /**< TMR2 Capture timer 2 */
1237     kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,  /**< TMR2 Capture timer 3 */
1238     kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
1239     kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
1240     kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
1241     kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
1242     kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
1243     kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
1244     kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
1245     kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
1246 } dma_request_source_t;
1247 
1248 /* @} */
1249 
1250 
1251 /*!
1252  * @}
1253  */ /* end of group Mapping_Information */
1254 
1255 
1256 /* ----------------------------------------------------------------------------
1257    -- Device Peripheral Access Layer
1258    ---------------------------------------------------------------------------- */
1259 
1260 /*!
1261  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
1262  * @{
1263  */
1264 
1265 
1266 /*
1267 ** Start of section using anonymous unions
1268 */
1269 
1270 #if defined(__ARMCC_VERSION)
1271   #if (__ARMCC_VERSION >= 6010050)
1272     #pragma clang diagnostic push
1273   #else
1274     #pragma push
1275     #pragma anon_unions
1276   #endif
1277 #elif defined(__CWCC__)
1278   #pragma push
1279   #pragma cpp_extensions on
1280 #elif defined(__GNUC__)
1281   /* anonymous unions are enabled by default */
1282 #elif defined(__IAR_SYSTEMS_ICC__)
1283   #pragma language=extended
1284 #else
1285   #error Not supported compiler type
1286 #endif
1287 
1288 /* ----------------------------------------------------------------------------
1289    -- ADC Peripheral Access Layer
1290    ---------------------------------------------------------------------------- */
1291 
1292 /*!
1293  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
1294  * @{
1295  */
1296 
1297 /** ADC - Register Layout Typedef */
1298 typedef struct {
1299   __IO uint32_t HC[8];                             /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
1300   __I  uint32_t HS;                                /**< Status register for HW triggers, offset: 0x20 */
1301   __I  uint32_t R[8];                              /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
1302   __IO uint32_t CFG;                               /**< Configuration register, offset: 0x44 */
1303   __IO uint32_t GC;                                /**< General control register, offset: 0x48 */
1304   __IO uint32_t GS;                                /**< General status register, offset: 0x4C */
1305   __IO uint32_t CV;                                /**< Compare value register, offset: 0x50 */
1306   __IO uint32_t OFS;                               /**< Offset correction value register, offset: 0x54 */
1307   __IO uint32_t CAL;                               /**< Calibration value register, offset: 0x58 */
1308 } ADC_Type;
1309 
1310 /* ----------------------------------------------------------------------------
1311    -- ADC Register Masks
1312    ---------------------------------------------------------------------------- */
1313 
1314 /*!
1315  * @addtogroup ADC_Register_Masks ADC Register Masks
1316  * @{
1317  */
1318 
1319 /*! @name HC - Control register for hardware triggers */
1320 /*! @{ */
1321 
1322 #define ADC_HC_ADCH_MASK                         (0x1FU)
1323 #define ADC_HC_ADCH_SHIFT                        (0U)
1324 /*! ADCH - Input Channel Select
1325  *  0b00000-0b01111..External channels 0 to 15 See External Signals for more information
1326  *  0b10000..External channel selection from ADC_ETC
1327  *  0b10001-0b10111..Reserved
1328  *  0b11000..Reserved.
1329  *  0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
1330  *  0b11010..Reserved.
1331  *  0b11011..Reserved.
1332  *  0b11100-0b11110..Reserved.
1333  *  0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
1334  */
1335 #define ADC_HC_ADCH(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1336 
1337 #define ADC_HC_AIEN_MASK                         (0x80U)
1338 #define ADC_HC_AIEN_SHIFT                        (7U)
1339 /*! AIEN - Conversion Complete Interrupt Enable/Disable Control
1340  *  0b1..Conversion complete interrupt enabled
1341  *  0b0..Conversion complete interrupt disabled
1342  */
1343 #define ADC_HC_AIEN(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1344 /*! @} */
1345 
1346 /* The count of ADC_HC */
1347 #define ADC_HC_COUNT                             (8U)
1348 
1349 /*! @name HS - Status register for HW triggers */
1350 /*! @{ */
1351 
1352 #define ADC_HS_COCO0_MASK                        (0x1U)
1353 #define ADC_HS_COCO0_SHIFT                       (0U)
1354 /*! COCO0 - Conversion Complete Flag
1355  */
1356 #define ADC_HS_COCO0(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1357 
1358 #define ADC_HS_COCO1_MASK                        (0x2U)
1359 #define ADC_HS_COCO1_SHIFT                       (1U)
1360 /*! COCO1 - Conversion Complete Flag
1361  */
1362 #define ADC_HS_COCO1(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK)
1363 
1364 #define ADC_HS_COCO2_MASK                        (0x4U)
1365 #define ADC_HS_COCO2_SHIFT                       (2U)
1366 #define ADC_HS_COCO2(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO2_SHIFT)) & ADC_HS_COCO2_MASK)
1367 
1368 #define ADC_HS_COCO3_MASK                        (0x8U)
1369 #define ADC_HS_COCO3_SHIFT                       (3U)
1370 #define ADC_HS_COCO3(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO3_SHIFT)) & ADC_HS_COCO3_MASK)
1371 
1372 #define ADC_HS_COCO4_MASK                        (0x10U)
1373 #define ADC_HS_COCO4_SHIFT                       (4U)
1374 #define ADC_HS_COCO4(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO4_SHIFT)) & ADC_HS_COCO4_MASK)
1375 
1376 #define ADC_HS_COCO5_MASK                        (0x20U)
1377 #define ADC_HS_COCO5_SHIFT                       (5U)
1378 #define ADC_HS_COCO5(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO5_SHIFT)) & ADC_HS_COCO5_MASK)
1379 
1380 #define ADC_HS_COCO6_MASK                        (0x40U)
1381 #define ADC_HS_COCO6_SHIFT                       (6U)
1382 #define ADC_HS_COCO6(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO6_SHIFT)) & ADC_HS_COCO6_MASK)
1383 
1384 #define ADC_HS_COCO7_MASK                        (0x80U)
1385 #define ADC_HS_COCO7_SHIFT                       (7U)
1386 #define ADC_HS_COCO7(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO7_SHIFT)) & ADC_HS_COCO7_MASK)
1387 /*! @} */
1388 
1389 /*! @name R - Data result register for HW triggers */
1390 /*! @{ */
1391 
1392 #define ADC_R_CDATA_MASK                         (0xFFFU)
1393 #define ADC_R_CDATA_SHIFT                        (0U)
1394 /*! CDATA - Data (result of an ADC conversion)
1395  */
1396 #define ADC_R_CDATA(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1397 /*! @} */
1398 
1399 /* The count of ADC_R */
1400 #define ADC_R_COUNT                              (8U)
1401 
1402 /*! @name CFG - Configuration register */
1403 /*! @{ */
1404 
1405 #define ADC_CFG_ADICLK_MASK                      (0x3U)
1406 #define ADC_CFG_ADICLK_SHIFT                     (0U)
1407 /*! ADICLK - Input Clock Select
1408  *  0b00..IPG clock
1409  *  0b01..IPG clock divided by 2
1410  *  0b10..Reserved
1411  *  0b11..Asynchronous clock (ADACK)
1412  */
1413 #define ADC_CFG_ADICLK(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1414 
1415 #define ADC_CFG_MODE_MASK                        (0xCU)
1416 #define ADC_CFG_MODE_SHIFT                       (2U)
1417 /*! MODE - Conversion Mode Selection
1418  *  0b00..8-bit conversion
1419  *  0b01..10-bit conversion
1420  *  0b10..12-bit conversion
1421  *  0b11..Reserved
1422  */
1423 #define ADC_CFG_MODE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1424 
1425 #define ADC_CFG_ADLSMP_MASK                      (0x10U)
1426 #define ADC_CFG_ADLSMP_SHIFT                     (4U)
1427 /*! ADLSMP - Long Sample Time Configuration
1428  *  0b0..Short sample mode.
1429  *  0b1..Long sample mode.
1430  */
1431 #define ADC_CFG_ADLSMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1432 
1433 #define ADC_CFG_ADIV_MASK                        (0x60U)
1434 #define ADC_CFG_ADIV_SHIFT                       (5U)
1435 /*! ADIV - Clock Divide Select
1436  *  0b00..Input clock
1437  *  0b01..Input clock / 2
1438  *  0b10..Input clock / 4
1439  *  0b11..Input clock / 8
1440  */
1441 #define ADC_CFG_ADIV(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1442 
1443 #define ADC_CFG_ADLPC_MASK                       (0x80U)
1444 #define ADC_CFG_ADLPC_SHIFT                      (7U)
1445 /*! ADLPC - Low-Power Configuration
1446  *  0b0..ADC hard block not in low power mode.
1447  *  0b1..ADC hard block in low power mode.
1448  */
1449 #define ADC_CFG_ADLPC(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1450 
1451 #define ADC_CFG_ADSTS_MASK                       (0x300U)
1452 #define ADC_CFG_ADSTS_SHIFT                      (8U)
1453 /*! ADSTS
1454  *  0b00..Sample period (ADC clocks) = 3 if ADLSMP=0b Sample period (ADC clocks) = 13 if ADLSMP=1b
1455  *  0b01..Sample period (ADC clocks) = 5 if ADLSMP=0b Sample period (ADC clocks) = 17 if ADLSMP=1b
1456  *  0b10..Sample period (ADC clocks) = 7 if ADLSMP=0b Sample period (ADC clocks) = 21 if ADLSMP=1b
1457  *  0b11..Sample period (ADC clocks) = 9 if ADLSMP=0b Sample period (ADC clocks) = 25 if ADLSMP=1b
1458  */
1459 #define ADC_CFG_ADSTS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1460 
1461 #define ADC_CFG_ADHSC_MASK                       (0x400U)
1462 #define ADC_CFG_ADHSC_SHIFT                      (10U)
1463 /*! ADHSC - High Speed Configuration
1464  *  0b0..Normal conversion selected.
1465  *  0b1..High speed conversion selected.
1466  */
1467 #define ADC_CFG_ADHSC(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1468 
1469 #define ADC_CFG_REFSEL_MASK                      (0x1800U)
1470 #define ADC_CFG_REFSEL_SHIFT                     (11U)
1471 /*! REFSEL - Voltage Reference Selection
1472  *  0b00..Selects VREFH/VREFL as reference voltage.
1473  *  0b01..Reserved
1474  *  0b10..Reserved
1475  *  0b11..Reserved
1476  */
1477 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1478 
1479 #define ADC_CFG_ADTRG_MASK                       (0x2000U)
1480 #define ADC_CFG_ADTRG_SHIFT                      (13U)
1481 /*! ADTRG - Conversion Trigger Select
1482  *  0b0..Software trigger selected
1483  *  0b1..Hardware trigger selected
1484  */
1485 #define ADC_CFG_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1486 
1487 #define ADC_CFG_AVGS_MASK                        (0xC000U)
1488 #define ADC_CFG_AVGS_SHIFT                       (14U)
1489 /*! AVGS - Hardware Average select
1490  *  0b00..4 samples averaged
1491  *  0b01..8 samples averaged
1492  *  0b10..16 samples averaged
1493  *  0b11..32 samples averaged
1494  */
1495 #define ADC_CFG_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1496 
1497 #define ADC_CFG_OVWREN_MASK                      (0x10000U)
1498 #define ADC_CFG_OVWREN_SHIFT                     (16U)
1499 /*! OVWREN - Data Overwrite Enable
1500  *  0b1..Enable the overwriting.
1501  *  0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
1502  */
1503 #define ADC_CFG_OVWREN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1504 /*! @} */
1505 
1506 /*! @name GC - General control register */
1507 /*! @{ */
1508 
1509 #define ADC_GC_ADACKEN_MASK                      (0x1U)
1510 #define ADC_GC_ADACKEN_SHIFT                     (0U)
1511 /*! ADACKEN - Asynchronous clock output enable
1512  *  0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
1513  *  0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
1514  */
1515 #define ADC_GC_ADACKEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1516 
1517 #define ADC_GC_DMAEN_MASK                        (0x2U)
1518 #define ADC_GC_DMAEN_SHIFT                       (1U)
1519 /*! DMAEN - DMA Enable
1520  *  0b0..DMA disabled (default)
1521  *  0b1..DMA enabled
1522  */
1523 #define ADC_GC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1524 
1525 #define ADC_GC_ACREN_MASK                        (0x4U)
1526 #define ADC_GC_ACREN_SHIFT                       (2U)
1527 /*! ACREN - Compare Function Range Enable
1528  *  0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
1529  *  0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
1530  */
1531 #define ADC_GC_ACREN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1532 
1533 #define ADC_GC_ACFGT_MASK                        (0x8U)
1534 #define ADC_GC_ACFGT_SHIFT                       (3U)
1535 /*! ACFGT - Compare Function Greater Than Enable
1536  *  0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
1537  *       functionality based on the values placed in the ADC_CV register.
1538  *  0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
1539  *       functionality based on the values placed in the ADC_CV registers.
1540  */
1541 #define ADC_GC_ACFGT(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1542 
1543 #define ADC_GC_ACFE_MASK                         (0x10U)
1544 #define ADC_GC_ACFE_SHIFT                        (4U)
1545 /*! ACFE - Compare Function Enable
1546  *  0b0..Compare function disabled
1547  *  0b1..Compare function enabled
1548  */
1549 #define ADC_GC_ACFE(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1550 
1551 #define ADC_GC_AVGE_MASK                         (0x20U)
1552 #define ADC_GC_AVGE_SHIFT                        (5U)
1553 /*! AVGE - Hardware average enable
1554  *  0b0..Hardware average function disabled
1555  *  0b1..Hardware average function enabled
1556  */
1557 #define ADC_GC_AVGE(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1558 
1559 #define ADC_GC_ADCO_MASK                         (0x40U)
1560 #define ADC_GC_ADCO_SHIFT                        (6U)
1561 /*! ADCO - Continuous Conversion Enable
1562  *  0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1563  *  0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1564  */
1565 #define ADC_GC_ADCO(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1566 
1567 #define ADC_GC_CAL_MASK                          (0x80U)
1568 #define ADC_GC_CAL_SHIFT                         (7U)
1569 /*! CAL - Calibration
1570  */
1571 #define ADC_GC_CAL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1572 /*! @} */
1573 
1574 /*! @name GS - General status register */
1575 /*! @{ */
1576 
1577 #define ADC_GS_ADACT_MASK                        (0x1U)
1578 #define ADC_GS_ADACT_SHIFT                       (0U)
1579 /*! ADACT - Conversion Active
1580  *  0b0..Conversion not in progress.
1581  *  0b1..Conversion in progress.
1582  */
1583 #define ADC_GS_ADACT(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1584 
1585 #define ADC_GS_CALF_MASK                         (0x2U)
1586 #define ADC_GS_CALF_SHIFT                        (1U)
1587 /*! CALF - Calibration Failed Flag
1588  *  0b0..Calibration completed normally.
1589  *  0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
1590  */
1591 #define ADC_GS_CALF(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1592 
1593 #define ADC_GS_AWKST_MASK                        (0x4U)
1594 #define ADC_GS_AWKST_SHIFT                       (2U)
1595 /*! AWKST - Asynchronous wakeup interrupt status
1596  *  0b1..Asynchronous wake up interrupt occurred in stop mode.
1597  *  0b0..No asynchronous interrupt.
1598  */
1599 #define ADC_GS_AWKST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1600 /*! @} */
1601 
1602 /*! @name CV - Compare value register */
1603 /*! @{ */
1604 
1605 #define ADC_CV_CV1_MASK                          (0xFFFU)
1606 #define ADC_CV_CV1_SHIFT                         (0U)
1607 /*! CV1 - Compare Value 1
1608  */
1609 #define ADC_CV_CV1(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1610 
1611 #define ADC_CV_CV2_MASK                          (0xFFF0000U)
1612 #define ADC_CV_CV2_SHIFT                         (16U)
1613 /*! CV2 - Compare Value 2
1614  */
1615 #define ADC_CV_CV2(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1616 /*! @} */
1617 
1618 /*! @name OFS - Offset correction value register */
1619 /*! @{ */
1620 
1621 #define ADC_OFS_OFS_MASK                         (0xFFFU)
1622 #define ADC_OFS_OFS_SHIFT                        (0U)
1623 /*! OFS - Offset value
1624  */
1625 #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1626 
1627 #define ADC_OFS_SIGN_MASK                        (0x1000U)
1628 #define ADC_OFS_SIGN_SHIFT                       (12U)
1629 /*! SIGN - Sign bit
1630  *  0b0..The offset value is added with the raw result
1631  *  0b1..The offset value is subtracted from the raw converted value
1632  */
1633 #define ADC_OFS_SIGN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1634 /*! @} */
1635 
1636 /*! @name CAL - Calibration value register */
1637 /*! @{ */
1638 
1639 #define ADC_CAL_CAL_CODE_MASK                    (0xFU)
1640 #define ADC_CAL_CAL_CODE_SHIFT                   (0U)
1641 /*! CAL_CODE - Calibration Result Value
1642  */
1643 #define ADC_CAL_CAL_CODE(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1644 /*! @} */
1645 
1646 
1647 /*!
1648  * @}
1649  */ /* end of group ADC_Register_Masks */
1650 
1651 
1652 /* ADC - Peripheral instance base addresses */
1653 /** Peripheral ADC1 base address */
1654 #define ADC1_BASE                                (0x400C4000u)
1655 /** Peripheral ADC1 base pointer */
1656 #define ADC1                                     ((ADC_Type *)ADC1_BASE)
1657 /** Peripheral ADC2 base address */
1658 #define ADC2_BASE                                (0x400C8000u)
1659 /** Peripheral ADC2 base pointer */
1660 #define ADC2                                     ((ADC_Type *)ADC2_BASE)
1661 /** Array initializer of ADC peripheral base addresses */
1662 #define ADC_BASE_ADDRS                           { 0u, ADC1_BASE, ADC2_BASE }
1663 /** Array initializer of ADC peripheral base pointers */
1664 #define ADC_BASE_PTRS                            { (ADC_Type *)0u, ADC1, ADC2 }
1665 /** Interrupt vectors for the ADC peripheral type */
1666 #define ADC_IRQS                                 { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1667 
1668 /*!
1669  * @}
1670  */ /* end of group ADC_Peripheral_Access_Layer */
1671 
1672 
1673 /* ----------------------------------------------------------------------------
1674    -- ADC_ETC Peripheral Access Layer
1675    ---------------------------------------------------------------------------- */
1676 
1677 /*!
1678  * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
1679  * @{
1680  */
1681 
1682 /** ADC_ETC - Register Layout Typedef */
1683 typedef struct {
1684   __IO uint32_t CTRL;                              /**< ADC_ETC Global Control Register, offset: 0x0 */
1685   __IO uint32_t DONE0_1_IRQ;                       /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
1686   __IO uint32_t DONE2_3_ERR_IRQ;                   /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
1687   __IO uint32_t DMA_CTRL;                          /**< ETC DMA control Register, offset: 0xC */
1688   struct {                                         /* offset: 0x10, array step: 0x28 */
1689     __IO uint32_t TRIGn_CTRL;                        /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
1690     __IO uint32_t TRIGn_COUNTER;                     /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
1691     __IO uint32_t TRIGn_CHAIN_1_0;                   /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
1692     __IO uint32_t TRIGn_CHAIN_3_2;                   /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
1693     __IO uint32_t TRIGn_CHAIN_5_4;                   /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
1694     __IO uint32_t TRIGn_CHAIN_7_6;                   /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
1695     __I  uint32_t TRIGn_RESULT_1_0;                  /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
1696     __I  uint32_t TRIGn_RESULT_3_2;                  /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
1697     __I  uint32_t TRIGn_RESULT_5_4;                  /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
1698     __I  uint32_t TRIGn_RESULT_7_6;                  /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
1699   } TRIG[8];
1700 } ADC_ETC_Type;
1701 
1702 /* ----------------------------------------------------------------------------
1703    -- ADC_ETC Register Masks
1704    ---------------------------------------------------------------------------- */
1705 
1706 /*!
1707  * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
1708  * @{
1709  */
1710 
1711 /*! @name CTRL - ADC_ETC Global Control Register */
1712 /*! @{ */
1713 
1714 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK            (0xFFU)
1715 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT           (0U)
1716 /*! TRIG_ENABLE
1717  *  0b00000000..disable all 8 external XBAR triggers.
1718  *  0b00000001..enable external XBAR trigger0.
1719  *  0b00000010..enable external XBAR trigger1.
1720  *  0b00000011..enable external XBAR trigger0 and trigger1.
1721  *  0b11111111..enable all 8 external XBAR triggers.
1722  */
1723 #define ADC_ETC_CTRL_TRIG_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1724 
1725 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK       (0x100U)
1726 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT      (8U)
1727 /*! EXT0_TRIG_ENABLE
1728  *  0b0..disable external TSC0 trigger.
1729  *  0b1..enable external TSC0 trigger.
1730  */
1731 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1732 
1733 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK     (0xE00U)
1734 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT    (9U)
1735 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1736 
1737 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK       (0x1000U)
1738 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT      (12U)
1739 /*! EXT1_TRIG_ENABLE
1740  *  0b0..disable external TSC1 trigger.
1741  *  0b1..enable external TSC1 trigger.
1742  */
1743 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1744 
1745 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK     (0xE000U)
1746 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT    (13U)
1747 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1748 
1749 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK            (0xFF0000U)
1750 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT           (16U)
1751 #define ADC_ETC_CTRL_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1752 
1753 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK           (0x20000000U)
1754 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT          (29U)
1755 /*! DMA_MODE_SEL
1756  *  0b0..Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared.
1757  *  0b1..Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only.
1758  */
1759 #define ADC_ETC_CTRL_DMA_MODE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1760 
1761 #define ADC_ETC_CTRL_TSC_BYPASS_MASK             (0x40000000U)
1762 #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT            (30U)
1763 /*! TSC_BYPASS
1764  *  0b0..TSC not bypassed.
1765  *  0b1..TSC is bypassed to ADC2, that means TSC will control ADC2 directly.
1766  */
1767 #define ADC_ETC_CTRL_TSC_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1768 
1769 #define ADC_ETC_CTRL_SOFTRST_MASK                (0x80000000U)
1770 #define ADC_ETC_CTRL_SOFTRST_SHIFT               (31U)
1771 /*! SOFTRST
1772  *  0b0..ADC_ETC works normally.
1773  *  0b1..All registers inside ADC_ETC will be reset to the default value.
1774  */
1775 #define ADC_ETC_CTRL_SOFTRST(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1776 /*! @} */
1777 
1778 /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
1779 /*! @{ */
1780 
1781 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK     (0x1U)
1782 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT    (0U)
1783 /*! TRIG0_DONE0
1784  *  0b0..No TRIG0_DONE0 interrupt detected
1785  *  0b1..TRIG0_DONE0 interrupt detected
1786  */
1787 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1788 
1789 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK     (0x2U)
1790 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT    (1U)
1791 /*! TRIG1_DONE0
1792  *  0b0..No TRIG1_DONE0 interrupt detected
1793  *  0b1..TRIG1_DONE0 interrupt detected
1794  */
1795 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1796 
1797 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK     (0x4U)
1798 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT    (2U)
1799 /*! TRIG2_DONE0
1800  *  0b0..No TRIG2_DONE0 interrupt detected
1801  *  0b1..TRIG2_DONE0 interrupt detected
1802  */
1803 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1804 
1805 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK     (0x8U)
1806 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT    (3U)
1807 /*! TRIG3_DONE0
1808  *  0b0..No TRIG3_DONE0 interrupt detected
1809  *  0b1..TRIG3_DONE0 interrupt detected
1810  */
1811 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1812 
1813 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK     (0x10U)
1814 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT    (4U)
1815 /*! TRIG4_DONE0
1816  *  0b0..No TRIG4_DONE0 interrupt detected
1817  *  0b1..TRIG4_DONE0 interrupt detected
1818  */
1819 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1820 
1821 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK     (0x20U)
1822 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT    (5U)
1823 /*! TRIG5_DONE0
1824  *  0b0..No TRIG5_DONE0 interrupt detected
1825  *  0b1..TRIG5_DONE0 interrupt detected
1826  */
1827 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1828 
1829 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK     (0x40U)
1830 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT    (6U)
1831 /*! TRIG6_DONE0
1832  *  0b0..No TRIG6_DONE0 interrupt detected
1833  *  0b1..TRIG6_DONE0 interrupt detected
1834  */
1835 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1836 
1837 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK     (0x80U)
1838 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT    (7U)
1839 /*! TRIG7_DONE0
1840  *  0b0..No TRIG7_DONE0 interrupt detected
1841  *  0b1..TRIG7_DONE0 interrupt detected
1842  */
1843 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1844 
1845 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK     (0x10000U)
1846 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT    (16U)
1847 /*! TRIG0_DONE1
1848  *  0b0..No TRIG0_DONE1 interrupt detected
1849  *  0b1..TRIG0_DONE1 interrupt detected
1850  */
1851 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1852 
1853 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK     (0x20000U)
1854 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT    (17U)
1855 /*! TRIG1_DONE1
1856  *  0b0..No TRIG1_DONE1 interrupt detected
1857  *  0b1..TRIG1_DONE1 interrupt detected
1858  */
1859 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1860 
1861 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK     (0x40000U)
1862 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT    (18U)
1863 /*! TRIG2_DONE1
1864  *  0b0..No TRIG2_DONE1 interrupt detected
1865  *  0b1..TRIG2_DONE1 interrupt detected
1866  */
1867 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1868 
1869 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK     (0x80000U)
1870 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT    (19U)
1871 /*! TRIG3_DONE1
1872  *  0b0..No TRIG3_DONE1 interrupt detected
1873  *  0b1..TRIG3_DONE1 interrupt detected
1874  */
1875 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1876 
1877 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK     (0x100000U)
1878 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT    (20U)
1879 /*! TRIG4_DONE1
1880  *  0b0..No TRIG4_DONE1 interrupt detected
1881  *  0b1..TRIG4_DONE1 interrupt detected
1882  */
1883 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1884 
1885 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK     (0x200000U)
1886 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT    (21U)
1887 /*! TRIG5_DONE1
1888  *  0b0..No TRIG5_DONE1 interrupt detected
1889  *  0b1..TRIG5_DONE1 interrupt detected
1890  */
1891 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1892 
1893 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK     (0x400000U)
1894 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT    (22U)
1895 /*! TRIG6_DONE1
1896  *  0b0..No TRIG6_DONE1 interrupt detected
1897  *  0b1..TRIG6_DONE1 interrupt detected
1898  */
1899 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1900 
1901 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK     (0x800000U)
1902 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT    (23U)
1903 /*! TRIG7_DONE1
1904  *  0b0..No TRIG7_DONE1 interrupt detected
1905  *  0b1..TRIG7_DONE1 interrupt detected
1906  */
1907 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1908 /*! @} */
1909 
1910 /*! @name DONE2_3_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
1911 /*! @{ */
1912 
1913 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1914 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1915 /*! TRIG0_DONE2
1916  *  0b0..No TRIG0_DONE2 interrupt detected
1917  *  0b1..TRIG0_DONE2 interrupt detected
1918  */
1919 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
1920 
1921 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1922 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1923 /*! TRIG1_DONE2
1924  *  0b0..No TRIG1_DONE2 interrupt detected
1925  *  0b1..TRIG1_DONE2 interrupt detected
1926  */
1927 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
1928 
1929 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1930 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1931 /*! TRIG2_DONE2
1932  *  0b0..No TRIG2_DONE2 interrupt detected
1933  *  0b1..TRIG2_DONE2 interrupt detected
1934  */
1935 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
1936 
1937 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1938 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1939 /*! TRIG3_DONE2
1940  *  0b0..No TRIG3_DONE2 interrupt detected
1941  *  0b1..TRIG3_DONE2 interrupt detected
1942  */
1943 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
1944 
1945 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1946 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1947 /*! TRIG4_DONE2
1948  *  0b0..No TRIG4_DONE2 interrupt detected
1949  *  0b1..TRIG4_DONE2 interrupt detected
1950  */
1951 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
1952 
1953 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1954 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1955 /*! TRIG5_DONE2
1956  *  0b0..No TRIG5_DONE2 interrupt detected
1957  *  0b1..TRIG5_DONE2 interrupt detected
1958  */
1959 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
1960 
1961 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1962 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1963 /*! TRIG6_DONE2
1964  *  0b0..No TRIG6_DONE2 interrupt detected
1965  *  0b1..TRIG6_DONE2 interrupt detected
1966  */
1967 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
1968 
1969 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1970 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1971 /*! TRIG7_DONE2
1972  *  0b0..No TRIG7_DONE2 interrupt detected
1973  *  0b1..TRIG7_DONE2 interrupt detected
1974  */
1975 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
1976 
1977 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK   (0x10000U)
1978 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT  (16U)
1979 /*! TRIG0_ERR
1980  *  0b0..No TRIG0_ERR interrupt detected
1981  *  0b1..TRIG0_ERR interrupt detected
1982  */
1983 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
1984 
1985 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK   (0x20000U)
1986 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT  (17U)
1987 /*! TRIG1_ERR
1988  *  0b0..No TRIG1_ERR interrupt detected
1989  *  0b1..TRIG1_ERR interrupt detected
1990  */
1991 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
1992 
1993 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK   (0x40000U)
1994 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT  (18U)
1995 /*! TRIG2_ERR
1996  *  0b0..No TRIG2_ERR interrupt detected
1997  *  0b1..TRIG2_ERR interrupt detected
1998  */
1999 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
2000 
2001 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK   (0x80000U)
2002 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT  (19U)
2003 /*! TRIG3_ERR
2004  *  0b0..No TRIG3_ERR interrupt detected
2005  *  0b1..TRIG3_ERR interrupt detected
2006  */
2007 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
2008 
2009 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK   (0x100000U)
2010 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT  (20U)
2011 /*! TRIG4_ERR
2012  *  0b0..No TRIG4_ERR interrupt detected
2013  *  0b1..TRIG4_ERR interrupt detected
2014  */
2015 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
2016 
2017 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK   (0x200000U)
2018 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT  (21U)
2019 /*! TRIG5_ERR
2020  *  0b0..No TRIG5_ERR interrupt detected
2021  *  0b1..TRIG5_ERR interrupt detected
2022  */
2023 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
2024 
2025 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK   (0x400000U)
2026 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT  (22U)
2027 /*! TRIG6_ERR
2028  *  0b0..No TRIG6_ERR interrupt detected
2029  *  0b1..TRIG6_ERR interrupt detected
2030  */
2031 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
2032 
2033 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK   (0x800000U)
2034 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT  (23U)
2035 /*! TRIG7_ERR
2036  *  0b0..No TRIG7_ERR interrupt detected
2037  *  0b1..TRIG7_ERR interrupt detected
2038  */
2039 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
2040 /*! @} */
2041 
2042 /*! @name DMA_CTRL - ETC DMA control Register */
2043 /*! @{ */
2044 
2045 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK       (0x1U)
2046 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT      (0U)
2047 /*! TRIG0_ENABLE
2048  *  0b0..TRIG0 DMA request disabled.
2049  *  0b1..TRIG0 DMA request enabled.
2050  */
2051 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
2052 
2053 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK       (0x2U)
2054 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT      (1U)
2055 /*! TRIG1_ENABLE
2056  *  0b0..TRIG1 DMA request disabled.
2057  *  0b1..TRIG1 DMA request enabled.
2058  */
2059 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
2060 
2061 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK       (0x4U)
2062 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT      (2U)
2063 /*! TRIG2_ENABLE
2064  *  0b0..TRIG2 DMA request disabled.
2065  *  0b1..TRIG2 DMA request enabled.
2066  */
2067 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
2068 
2069 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK       (0x8U)
2070 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT      (3U)
2071 /*! TRIG3_ENABLE
2072  *  0b0..TRIG3 DMA request disabled.
2073  *  0b1..TRIG3 DMA request enabled.
2074  */
2075 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
2076 
2077 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK       (0x10U)
2078 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT      (4U)
2079 /*! TRIG4_ENABLE
2080  *  0b0..TRIG4 DMA request disabled.
2081  *  0b1..TRIG4 DMA request enabled.
2082  */
2083 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
2084 
2085 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK       (0x20U)
2086 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT      (5U)
2087 /*! TRIG5_ENABLE
2088  *  0b0..TRIG5 DMA request disabled.
2089  *  0b1..TRIG5 DMA request enabled.
2090  */
2091 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
2092 
2093 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK       (0x40U)
2094 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT      (6U)
2095 /*! TRIG6_ENABLE
2096  *  0b0..TRIG6 DMA request disabled.
2097  *  0b1..TRIG6 DMA request enabled.
2098  */
2099 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
2100 
2101 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK       (0x80U)
2102 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT      (7U)
2103 /*! TRIG7_ENABLE
2104  *  0b0..TRIG7 DMA request disabled.
2105  *  0b1..TRIG7 DMA request enabled.
2106  */
2107 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
2108 
2109 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK          (0x10000U)
2110 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT         (16U)
2111 /*! TRIG0_REQ
2112  *  0b0..TRIG0_REQ not detected.
2113  *  0b1..TRIG0_REQ detected.
2114  */
2115 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
2116 
2117 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK          (0x20000U)
2118 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT         (17U)
2119 /*! TRIG1_REQ
2120  *  0b0..TRIG1_REQ not detected.
2121  *  0b1..TRIG1_REQ detected.
2122  */
2123 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
2124 
2125 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK          (0x40000U)
2126 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT         (18U)
2127 /*! TRIG2_REQ
2128  *  0b0..TRIG2_REQ not detected.
2129  *  0b1..TRIG2_REQ detected.
2130  */
2131 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
2132 
2133 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK          (0x80000U)
2134 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT         (19U)
2135 /*! TRIG3_REQ
2136  *  0b0..TRIG3_REQ not detected.
2137  *  0b1..TRIG3_REQ detected.
2138  */
2139 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
2140 
2141 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK          (0x100000U)
2142 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT         (20U)
2143 /*! TRIG4_REQ
2144  *  0b0..TRIG4_REQ not detected.
2145  *  0b1..TRIG4_REQ detected.
2146  */
2147 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
2148 
2149 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK          (0x200000U)
2150 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT         (21U)
2151 /*! TRIG5_REQ
2152  *  0b0..TRIG5_REQ not detected.
2153  *  0b1..TRIG5_REQ detected.
2154  */
2155 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
2156 
2157 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK          (0x400000U)
2158 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT         (22U)
2159 /*! TRIG6_REQ
2160  *  0b0..TRIG6_REQ not detected.
2161  *  0b1..TRIG6_REQ detected.
2162  */
2163 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
2164 
2165 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK          (0x800000U)
2166 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT         (23U)
2167 /*! TRIG7_REQ
2168  *  0b0..TRIG7_REQ not detected.
2169  *  0b1..TRIG7_REQ detected.
2170  */
2171 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
2172 /*! @} */
2173 
2174 /*! @name TRIGn_CTRL - ETC_TRIG Control Register */
2175 /*! @{ */
2176 
2177 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK          (0x1U)
2178 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT         (0U)
2179 /*! SW_TRIG
2180  *  0b0..No software trigger event generated.
2181  *  0b1..Software trigger event generated.
2182  */
2183 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
2184 
2185 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK        (0x10U)
2186 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT       (4U)
2187 /*! TRIG_MODE
2188  *  0b0..Hardware trigger. The softerware trigger will be ignored.
2189  *  0b1..Software trigger. The hardware trigger will be ignored.
2190  */
2191 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
2192 
2193 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK       (0x700U)
2194 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT      (8U)
2195 /*! TRIG_CHAIN
2196  *  0b000..Trigger chain length is 1
2197  *  0b001..Trigger chain length is 2
2198  *  0b010..Trigger chain length is 3
2199  *  0b011..Trigger chain length is 4
2200  *  0b100..Trigger chain length is 5
2201  *  0b101..Trigger chain length is 6
2202  *  0b110..Trigger chain length is 7
2203  *  0b111..Trigger chain length is 8
2204  */
2205 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
2206 
2207 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK    (0x7000U)
2208 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT   (12U)
2209 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
2210 
2211 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK        (0x10000U)
2212 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT       (16U)
2213 /*! SYNC_MODE
2214  *  0b0..Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently.
2215  *  0b1..Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously.
2216  */
2217 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
2218 /*! @} */
2219 
2220 /* The count of ADC_ETC_TRIGn_CTRL */
2221 #define ADC_ETC_TRIGn_CTRL_COUNT                 (8U)
2222 
2223 /*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
2224 /*! @{ */
2225 
2226 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK    (0xFFFFU)
2227 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT   (0U)
2228 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
2229 
2230 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
2231 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
2232 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
2233 /*! @} */
2234 
2235 /* The count of ADC_ETC_TRIGn_COUNTER */
2236 #define ADC_ETC_TRIGn_COUNTER_COUNT              (8U)
2237 
2238 /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
2239 /*! @{ */
2240 
2241 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK       (0xFU)
2242 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT      (0U)
2243 /*! CSEL0
2244  *  0b0000..ADC Channel 0 selected
2245  *  0b0001..ADC Channel 1 selected.
2246  *  0b0010..ADC Channel 2 selected.
2247  *  0b0011..ADC Channel 3 selected.
2248  *  0b0100..ADC Channel 4 selected.
2249  *  0b0101..ADC Channel 5 selected.
2250  *  0b0110..ADC Channel 6 selected.
2251  *  0b0111..ADC Channel 7 selected.
2252  *  0b1000..ADC Channel 8 selected.
2253  *  0b1001..ADC Channel 9 selected.
2254  *  0b1010..ADC Channel 10 selected.
2255  *  0b1011..ADC Channel 11 selected.
2256  *  0b1100..ADC Channel 12 selected.
2257  *  0b1101..ADC Channel 13 selected.
2258  *  0b1110..ADC Channel 14 selected.
2259  *  0b1111..ADC Channel 15 selected.
2260  */
2261 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
2262 
2263 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK       (0xFF0U)
2264 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT      (4U)
2265 /*! HWTS0
2266  *  0b00000000..no trigger selected
2267  *  0b00000001..ADC TRIG0 selected
2268  *  0b00000010..ADC TRIG1 selected
2269  *  0b00000100..ADC TRIG2 selected
2270  *  0b00001000..ADC TRIG3 selected
2271  *  0b00010000..ADC TRIG4 selected
2272  *  0b00100000..ADC TRIG5 selected
2273  *  0b01000000..ADC TRIG6 selected
2274  *  0b10000000..ADC TRIG7 selected
2275  */
2276 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
2277 
2278 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK        (0x1000U)
2279 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT       (12U)
2280 /*! B2B0
2281  *  0b0..Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached
2282  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2283  */
2284 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
2285 
2286 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK         (0x6000U)
2287 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT        (13U)
2288 /*! IE0
2289  *  0b00..No interrupt when finished
2290  *  0b01..Generate interrupt on Done0 when segment 0 finish.
2291  *  0b10..Generate interrupt on Done1 when segment 0 finish.
2292  *  0b11..Generate interrupt on Done2 when segment 0 finish.
2293  */
2294 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
2295 
2296 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK       (0xF0000U)
2297 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT      (16U)
2298 /*! CSEL1
2299  *  0b0000..ADC Channel 0 selected
2300  *  0b0001..ADC Channel 1 selected.
2301  *  0b0010..ADC Channel 2 selected.
2302  *  0b0011..ADC Channel 3 selected.
2303  *  0b0100..ADC Channel 4 selected.
2304  *  0b0101..ADC Channel 5 selected.
2305  *  0b0110..ADC Channel 6 selected.
2306  *  0b0111..ADC Channel 7 selected.
2307  *  0b1000..ADC Channel 8 selected.
2308  *  0b1001..ADC Channel 9 selected.
2309  *  0b1010..ADC Channel 10 selected.
2310  *  0b1011..ADC Channel 11 selected.
2311  *  0b1100..ADC Channel 12 selected.
2312  *  0b1101..ADC Channel 13 selected.
2313  *  0b1110..ADC Channel 14 selected.
2314  *  0b1111..ADC Channel 15 selected.
2315  */
2316 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
2317 
2318 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK       (0xFF00000U)
2319 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT      (20U)
2320 /*! HWTS1
2321  *  0b00000000..no trigger selected
2322  *  0b00000001..ADC TRIG0 selected
2323  *  0b00000010..ADC TRIG1 selected
2324  *  0b00000100..ADC TRIG2 selected
2325  *  0b00001000..ADC TRIG3 selected
2326  *  0b00010000..ADC TRIG4 selected
2327  *  0b00100000..ADC TRIG5 selected
2328  *  0b01000000..ADC TRIG6 selected
2329  *  0b10000000..ADC TRIG7 selected
2330  */
2331 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
2332 
2333 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK        (0x10000000U)
2334 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT       (28U)
2335 /*! B2B1
2336  *  0b0..Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached
2337  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2338  */
2339 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
2340 
2341 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK         (0x60000000U)
2342 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT        (29U)
2343 /*! IE1
2344  *  0b00..No interrupt when finished
2345  *  0b01..Generate interrupt on Done0 when Segment 1 finish.
2346  *  0b10..Generate interrupt on Done1 when Segment 1 finish.
2347  *  0b11..Generate interrupt on Done2 when Segment 1 finish.
2348  */
2349 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
2350 /*! @} */
2351 
2352 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
2353 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT            (8U)
2354 
2355 /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
2356 /*! @{ */
2357 
2358 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK       (0xFU)
2359 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT      (0U)
2360 /*! CSEL2
2361  *  0b0000..ADC Channel 0 selected
2362  *  0b0001..ADC Channel 1 selected.
2363  *  0b0010..ADC Channel 2 selected.
2364  *  0b0011..ADC Channel 3 selected.
2365  *  0b0100..ADC Channel 4 selected.
2366  *  0b0101..ADC Channel 5 selected.
2367  *  0b0110..ADC Channel 6 selected.
2368  *  0b0111..ADC Channel 7 selected.
2369  *  0b1000..ADC Channel 8 selected.
2370  *  0b1001..ADC Channel 9 selected.
2371  *  0b1010..ADC Channel 10 selected.
2372  *  0b1011..ADC Channel 11 selected.
2373  *  0b1100..ADC Channel 12 selected.
2374  *  0b1101..ADC Channel 13 selected.
2375  *  0b1110..ADC Channel 14 selected.
2376  *  0b1111..ADC Channel 15 selected.
2377  */
2378 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
2379 
2380 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK       (0xFF0U)
2381 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT      (4U)
2382 /*! HWTS2
2383  *  0b00000000..no trigger selected
2384  *  0b00000001..ADC TRIG0 selected
2385  *  0b00000010..ADC TRIG1 selected
2386  *  0b00000100..ADC TRIG2 selected
2387  *  0b00001000..ADC TRIG3 selected
2388  *  0b00010000..ADC TRIG4 selected
2389  *  0b00100000..ADC TRIG5 selected
2390  *  0b01000000..ADC TRIG6 selected
2391  *  0b10000000..ADC TRIG7 selected
2392  */
2393 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
2394 
2395 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK        (0x1000U)
2396 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT       (12U)
2397 /*! B2B2
2398  *  0b0..Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached
2399  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2400  */
2401 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
2402 
2403 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK         (0x6000U)
2404 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT        (13U)
2405 /*! IE2
2406  *  0b00..No interrupt when finished
2407  *  0b01..Generate interrupt on Done0 when segment 2 finish.
2408  *  0b10..Generate interrupt on Done1 when segment 2 finish.
2409  *  0b11..Generate interrupt on Done2 when segment 2 finish.
2410  */
2411 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
2412 
2413 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK       (0xF0000U)
2414 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT      (16U)
2415 /*! CSEL3
2416  *  0b0000..ADC Channel 0 selected
2417  *  0b0001..ADC Channel 1 selected.
2418  *  0b0010..ADC Channel 2 selected.
2419  *  0b0011..ADC Channel 3 selected.
2420  *  0b0100..ADC Channel 4 selected.
2421  *  0b0101..ADC Channel 5 selected.
2422  *  0b0110..ADC Channel 6 selected.
2423  *  0b0111..ADC Channel 7 selected.
2424  *  0b1000..ADC Channel 8 selected.
2425  *  0b1001..ADC Channel 9 selected.
2426  *  0b1010..ADC Channel 10 selected.
2427  *  0b1011..ADC Channel 11 selected.
2428  *  0b1100..ADC Channel 12 selected.
2429  *  0b1101..ADC Channel 13 selected.
2430  *  0b1110..ADC Channel 14 selected.
2431  *  0b1111..ADC Channel 15 selected.
2432  */
2433 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
2434 
2435 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK       (0xFF00000U)
2436 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT      (20U)
2437 /*! HWTS3
2438  *  0b00000000..no trigger selected
2439  *  0b00000001..ADC TRIG0 selected
2440  *  0b00000010..ADC TRIG1 selected
2441  *  0b00000100..ADC TRIG2 selected
2442  *  0b00001000..ADC TRIG3 selected
2443  *  0b00010000..ADC TRIG4 selected
2444  *  0b00100000..ADC TRIG5 selected
2445  *  0b01000000..ADC TRIG6 selected
2446  *  0b10000000..ADC TRIG7 selected
2447  */
2448 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
2449 
2450 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK        (0x10000000U)
2451 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT       (28U)
2452 /*! B2B3
2453  *  0b0..Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached
2454  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2455  */
2456 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
2457 
2458 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK         (0x60000000U)
2459 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT        (29U)
2460 /*! IE3
2461  *  0b00..No interrupt when finished
2462  *  0b01..Generate interrupt on Done0 when segment 3 finish.
2463  *  0b10..Generate interrupt on Done1 when segment 3 finish.
2464  *  0b11..Generate interrupt on Done2 when segment 3 finish.
2465  */
2466 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
2467 /*! @} */
2468 
2469 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
2470 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT            (8U)
2471 
2472 /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
2473 /*! @{ */
2474 
2475 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK       (0xFU)
2476 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT      (0U)
2477 /*! CSEL4
2478  *  0b0000..ADC Channel 0 selected
2479  *  0b0001..ADC Channel 1 selected.
2480  *  0b0010..ADC Channel 2 selected.
2481  *  0b0011..ADC Channel 3 selected.
2482  *  0b0100..ADC Channel 4 selected.
2483  *  0b0101..ADC Channel 5 selected.
2484  *  0b0110..ADC Channel 6 selected.
2485  *  0b0111..ADC Channel 7 selected.
2486  *  0b1000..ADC Channel 8 selected.
2487  *  0b1001..ADC Channel 9 selected.
2488  *  0b1010..ADC Channel 10 selected.
2489  *  0b1011..ADC Channel 11 selected.
2490  *  0b1100..ADC Channel 12 selected.
2491  *  0b1101..ADC Channel 13 selected.
2492  *  0b1110..ADC Channel 14 selected.
2493  *  0b1111..ADC Channel 15 selected.
2494  */
2495 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
2496 
2497 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK       (0xFF0U)
2498 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT      (4U)
2499 /*! HWTS4
2500  *  0b00000000..no trigger selected
2501  *  0b00000001..ADC TRIG0 selected
2502  *  0b00000010..ADC TRIG1 selected
2503  *  0b00000100..ADC TRIG2 selected
2504  *  0b00001000..ADC TRIG3 selected
2505  *  0b00010000..ADC TRIG4 selected
2506  *  0b00100000..ADC TRIG5 selected
2507  *  0b01000000..ADC TRIG6 selected
2508  *  0b10000000..ADC TRIG7 selected
2509  */
2510 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
2511 
2512 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK        (0x1000U)
2513 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT       (12U)
2514 /*! B2B4
2515  *  0b0..Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached
2516  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2517  */
2518 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
2519 
2520 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK         (0x6000U)
2521 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT        (13U)
2522 /*! IE4
2523  *  0b00..No interrupt when finished
2524  *  0b01..Generate interrupt on Done0 when segment 4 finish.
2525  *  0b10..Generate interrupt on Done1 when segment 4 finish.
2526  *  0b11..Generate interrupt on Done2 when segment 4 finish.
2527  */
2528 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
2529 
2530 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK       (0xF0000U)
2531 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT      (16U)
2532 /*! CSEL5
2533  *  0b0000..ADC Channel 0 selected
2534  *  0b0001..ADC Channel 1 selected.
2535  *  0b0010..ADC Channel 2 selected.
2536  *  0b0011..ADC Channel 3 selected.
2537  *  0b0100..ADC Channel 4 selected.
2538  *  0b0101..ADC Channel 5 selected.
2539  *  0b0110..ADC Channel 6 selected.
2540  *  0b0111..ADC Channel 7 selected.
2541  *  0b1000..ADC Channel 8 selected.
2542  *  0b1001..ADC Channel 9 selected.
2543  *  0b1010..ADC Channel 10 selected.
2544  *  0b1011..ADC Channel 11 selected.
2545  *  0b1100..ADC Channel 12 selected.
2546  *  0b1101..ADC Channel 13 selected.
2547  *  0b1110..ADC Channel 14 selected.
2548  *  0b1111..ADC Channel 15 selected.
2549  */
2550 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
2551 
2552 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK       (0xFF00000U)
2553 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT      (20U)
2554 /*! HWTS5
2555  *  0b00000000..no trigger selected
2556  *  0b00000001..ADC TRIG0 selected
2557  *  0b00000010..ADC TRIG1 selected
2558  *  0b00000100..ADC TRIG2 selected
2559  *  0b00001000..ADC TRIG3 selected
2560  *  0b00010000..ADC TRIG4 selected
2561  *  0b00100000..ADC TRIG5 selected
2562  *  0b01000000..ADC TRIG6 selected
2563  *  0b10000000..ADC TRIG7 selected
2564  */
2565 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
2566 
2567 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK        (0x10000000U)
2568 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT       (28U)
2569 /*! B2B5
2570  *  0b0..Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached
2571  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2572  */
2573 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
2574 
2575 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK         (0x60000000U)
2576 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT        (29U)
2577 /*! IE5
2578  *  0b00..No interrupt when finished
2579  *  0b01..Generate interrupt on Done0 when segment 5 finish.
2580  *  0b10..Generate interrupt on Done1 when segment 5 finish.
2581  *  0b11..Generate interrupt on Done2 when segment 5 finish.
2582  */
2583 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
2584 /*! @} */
2585 
2586 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
2587 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT            (8U)
2588 
2589 /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
2590 /*! @{ */
2591 
2592 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK       (0xFU)
2593 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT      (0U)
2594 /*! CSEL6
2595  *  0b0000..ADC Channel 0 selected
2596  *  0b0001..ADC Channel 1 selected.
2597  *  0b0010..ADC Channel 2 selected.
2598  *  0b0011..ADC Channel 3 selected.
2599  *  0b0100..ADC Channel 4 selected.
2600  *  0b0101..ADC Channel 5 selected.
2601  *  0b0110..ADC Channel 6 selected.
2602  *  0b0111..ADC Channel 7 selected.
2603  *  0b1000..ADC Channel 8 selected.
2604  *  0b1001..ADC Channel 9 selected.
2605  *  0b1010..ADC Channel 10 selected.
2606  *  0b1011..ADC Channel 11 selected.
2607  *  0b1100..ADC Channel 12 selected.
2608  *  0b1101..ADC Channel 13 selected.
2609  *  0b1110..ADC Channel 14 selected.
2610  *  0b1111..ADC Channel 15 selected.
2611  */
2612 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
2613 
2614 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK       (0xFF0U)
2615 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT      (4U)
2616 /*! HWTS6
2617  *  0b00000000..no trigger selected
2618  *  0b00000001..ADC TRIG0 selected
2619  *  0b00000010..ADC TRIG1 selected
2620  *  0b00000100..ADC TRIG2 selected
2621  *  0b00001000..ADC TRIG3 selected
2622  *  0b00010000..ADC TRIG4 selected
2623  *  0b00100000..ADC TRIG5 selected
2624  *  0b01000000..ADC TRIG6 selected
2625  *  0b10000000..ADC TRIG7 selected
2626  */
2627 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
2628 
2629 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK        (0x1000U)
2630 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT       (12U)
2631 /*! B2B6
2632  *  0b0..Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached
2633  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2634  */
2635 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
2636 
2637 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK         (0x6000U)
2638 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT        (13U)
2639 /*! IE6
2640  *  0b00..No interrupt when finished
2641  *  0b01..Generate interrupt on Done0 when segment 6 finish.
2642  *  0b10..Generate interrupt on Done1 when segment 6 finish.
2643  *  0b11..Generate interrupt on Done2 when segment 6 finish.
2644  */
2645 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
2646 
2647 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK       (0xF0000U)
2648 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT      (16U)
2649 /*! CSEL7
2650  *  0b0000..ADC Channel 0 selected.
2651  *  0b0001..ADC Channel 1 selected.
2652  *  0b0010..ADC Channel 2 selected.
2653  *  0b0011..ADC Channel 3 selected.
2654  *  0b0100..ADC Channel 4 selected.
2655  *  0b0101..ADC Channel 5 selected.
2656  *  0b0110..ADC Channel 6 selected.
2657  *  0b0111..ADC Channel 7 selected.
2658  *  0b1000..ADC Channel 8 selected.
2659  *  0b1001..ADC Channel 9 selected.
2660  *  0b1010..ADC Channel 10 selected.
2661  *  0b1011..ADC Channel 11 selected.
2662  *  0b1100..ADC Channel 12 selected.
2663  *  0b1101..ADC Channel 13 selected.
2664  *  0b1110..ADC Channel 14 selected.
2665  *  0b1111..ADC Channel 15 selected.
2666  */
2667 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
2668 
2669 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK       (0xFF00000U)
2670 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT      (20U)
2671 /*! HWTS7
2672  *  0b00000000..no trigger selected
2673  *  0b00000001..ADC TRIG0 selected
2674  *  0b00000010..ADC TRIG1 selected
2675  *  0b00000100..ADC TRIG2 selected
2676  *  0b00001000..ADC TRIG3 selected
2677  *  0b00010000..ADC TRIG4 selected
2678  *  0b00100000..ADC TRIG5 selected
2679  *  0b01000000..ADC TRIG6 selected
2680  *  0b10000000..ADC TRIG7 selected
2681  */
2682 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
2683 
2684 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK        (0x10000000U)
2685 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT       (28U)
2686 /*! B2B7
2687  *  0b0..Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached
2688  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
2689  */
2690 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
2691 
2692 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK         (0x60000000U)
2693 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT        (29U)
2694 /*! IE7
2695  *  0b00..No interrupt when finished
2696  *  0b01..Generate interrupt on Done0 when segment 7 finish.
2697  *  0b10..Generate interrupt on Done1 when segment 7 finish.
2698  *  0b11..Generate interrupt on Done2 when segment 7 finish.
2699  */
2700 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
2701 /*! @} */
2702 
2703 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
2704 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT            (8U)
2705 
2706 /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
2707 /*! @{ */
2708 
2709 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK      (0xFFFU)
2710 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT     (0U)
2711 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
2712 
2713 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK      (0xFFF0000U)
2714 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT     (16U)
2715 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
2716 /*! @} */
2717 
2718 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
2719 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT           (8U)
2720 
2721 /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
2722 /*! @{ */
2723 
2724 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK      (0xFFFU)
2725 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT     (0U)
2726 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
2727 
2728 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK      (0xFFF0000U)
2729 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT     (16U)
2730 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
2731 /*! @} */
2732 
2733 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
2734 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT           (8U)
2735 
2736 /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
2737 /*! @{ */
2738 
2739 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK      (0xFFFU)
2740 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT     (0U)
2741 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
2742 
2743 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK      (0xFFF0000U)
2744 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT     (16U)
2745 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
2746 /*! @} */
2747 
2748 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
2749 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT           (8U)
2750 
2751 /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
2752 /*! @{ */
2753 
2754 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK      (0xFFFU)
2755 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT     (0U)
2756 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
2757 
2758 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK      (0xFFF0000U)
2759 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT     (16U)
2760 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
2761 /*! @} */
2762 
2763 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
2764 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT           (8U)
2765 
2766 
2767 /*!
2768  * @}
2769  */ /* end of group ADC_ETC_Register_Masks */
2770 
2771 
2772 /* ADC_ETC - Peripheral instance base addresses */
2773 /** Peripheral ADC_ETC base address */
2774 #define ADC_ETC_BASE                             (0x403B0000u)
2775 /** Peripheral ADC_ETC base pointer */
2776 #define ADC_ETC                                  ((ADC_ETC_Type *)ADC_ETC_BASE)
2777 /** Array initializer of ADC_ETC peripheral base addresses */
2778 #define ADC_ETC_BASE_ADDRS                       { ADC_ETC_BASE }
2779 /** Array initializer of ADC_ETC peripheral base pointers */
2780 #define ADC_ETC_BASE_PTRS                        { ADC_ETC }
2781 /** Interrupt vectors for the ADC_ETC peripheral type */
2782 #define ADC_ETC_IRQS                             { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
2783 #define ADC_ETC_FAULT_IRQS                       { ADC_ETC_ERROR_IRQ_IRQn }
2784 
2785 /*!
2786  * @}
2787  */ /* end of group ADC_ETC_Peripheral_Access_Layer */
2788 
2789 
2790 /* ----------------------------------------------------------------------------
2791    -- AIPSTZ Peripheral Access Layer
2792    ---------------------------------------------------------------------------- */
2793 
2794 /*!
2795  * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
2796  * @{
2797  */
2798 
2799 /** AIPSTZ - Register Layout Typedef */
2800 typedef struct {
2801   __IO uint32_t MPR;                               /**< Master Priviledge Registers, offset: 0x0 */
2802        uint8_t RESERVED_0[60];
2803   __IO uint32_t OPACR;                             /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
2804   __IO uint32_t OPACR1;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
2805   __IO uint32_t OPACR2;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
2806   __IO uint32_t OPACR3;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
2807   __IO uint32_t OPACR4;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
2808 } AIPSTZ_Type;
2809 
2810 /* ----------------------------------------------------------------------------
2811    -- AIPSTZ Register Masks
2812    ---------------------------------------------------------------------------- */
2813 
2814 /*!
2815  * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
2816  * @{
2817  */
2818 
2819 /*! @name MPR - Master Priviledge Registers */
2820 /*! @{ */
2821 
2822 #define AIPSTZ_MPR_MPROT3_MASK                   (0xF0000U)
2823 #define AIPSTZ_MPR_MPROT3_SHIFT                  (16U)
2824 /*! MPROT3
2825  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2826  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2827  *  0bxx0x..This master is not trusted for write accesses.
2828  *  0bxx1x..This master is trusted for write accesses.
2829  *  0bx0xx..This master is not trusted for read accesses.
2830  *  0bx1xx..This master is trusted for read accesses.
2831  *  0b1xxx..Write accesses from this master are allowed to be buffered
2832  */
2833 #define AIPSTZ_MPR_MPROT3(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2834 
2835 #define AIPSTZ_MPR_MPROT2_MASK                   (0xF00000U)
2836 #define AIPSTZ_MPR_MPROT2_SHIFT                  (20U)
2837 /*! MPROT2
2838  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2839  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2840  *  0bxx0x..This master is not trusted for write accesses.
2841  *  0bxx1x..This master is trusted for write accesses.
2842  *  0bx0xx..This master is not trusted for read accesses.
2843  *  0bx1xx..This master is trusted for read accesses.
2844  *  0b1xxx..Write accesses from this master are allowed to be buffered
2845  */
2846 #define AIPSTZ_MPR_MPROT2(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2847 
2848 #define AIPSTZ_MPR_MPROT1_MASK                   (0xF000000U)
2849 #define AIPSTZ_MPR_MPROT1_SHIFT                  (24U)
2850 /*! MPROT1
2851  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2852  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2853  *  0bxx0x..This master is not trusted for write accesses.
2854  *  0bxx1x..This master is trusted for write accesses.
2855  *  0bx0xx..This master is not trusted for read accesses.
2856  *  0bx1xx..This master is trusted for read accesses.
2857  *  0b1xxx..Write accesses from this master are allowed to be buffered
2858  */
2859 #define AIPSTZ_MPR_MPROT1(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2860 
2861 #define AIPSTZ_MPR_MPROT0_MASK                   (0xF0000000U)
2862 #define AIPSTZ_MPR_MPROT0_SHIFT                  (28U)
2863 /*! MPROT0
2864  *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2865  *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2866  *  0bxx0x..This master is not trusted for write accesses.
2867  *  0bxx1x..This master is trusted for write accesses.
2868  *  0bx0xx..This master is not trusted for read accesses.
2869  *  0bx1xx..This master is trusted for read accesses.
2870  *  0b1xxx..Write accesses from this master are allowed to be buffered
2871  */
2872 #define AIPSTZ_MPR_MPROT0(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2873 /*! @} */
2874 
2875 /*! @name OPACR - Off-Platform Peripheral Access Control Registers */
2876 /*! @{ */
2877 
2878 #define AIPSTZ_OPACR_OPAC7_MASK                  (0xFU)
2879 #define AIPSTZ_OPACR_OPAC7_SHIFT                 (0U)
2880 /*! OPAC7
2881  *  0bxxx0..Accesses from an untrusted master are allowed.
2882  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2883  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2884  *  0bxx0x..This peripheral allows write accesses.
2885  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2886  *          error response and no peripheral access is initiated on the IPS bus.
2887  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2888  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2889  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2890  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2891  *          on the IPS bus.
2892  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2893  */
2894 #define AIPSTZ_OPACR_OPAC7(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2895 
2896 #define AIPSTZ_OPACR_OPAC6_MASK                  (0xF0U)
2897 #define AIPSTZ_OPACR_OPAC6_SHIFT                 (4U)
2898 /*! OPAC6
2899  *  0bxxx0..Accesses from an untrusted master are allowed.
2900  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2901  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2902  *  0bxx0x..This peripheral allows write accesses.
2903  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2904  *          error response and no peripheral access is initiated on the IPS bus.
2905  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2906  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2907  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2908  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2909  *          on the IPS bus.
2910  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2911  */
2912 #define AIPSTZ_OPACR_OPAC6(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2913 
2914 #define AIPSTZ_OPACR_OPAC5_MASK                  (0xF00U)
2915 #define AIPSTZ_OPACR_OPAC5_SHIFT                 (8U)
2916 /*! OPAC5
2917  *  0bxxx0..Accesses from an untrusted master are allowed.
2918  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2919  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2920  *  0bxx0x..This peripheral allows write accesses.
2921  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2922  *          error response and no peripheral access is initiated on the IPS bus.
2923  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2924  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2925  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2926  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2927  *          on the IPS bus.
2928  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2929  */
2930 #define AIPSTZ_OPACR_OPAC5(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2931 
2932 #define AIPSTZ_OPACR_OPAC4_MASK                  (0xF000U)
2933 #define AIPSTZ_OPACR_OPAC4_SHIFT                 (12U)
2934 /*! OPAC4
2935  *  0bxxx0..Accesses from an untrusted master are allowed.
2936  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2937  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2938  *  0bxx0x..This peripheral allows write accesses.
2939  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2940  *          error response and no peripheral access is initiated on the IPS bus.
2941  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2942  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2943  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2944  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2945  *          on the IPS bus.
2946  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2947  */
2948 #define AIPSTZ_OPACR_OPAC4(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2949 
2950 #define AIPSTZ_OPACR_OPAC3_MASK                  (0xF0000U)
2951 #define AIPSTZ_OPACR_OPAC3_SHIFT                 (16U)
2952 /*! OPAC3
2953  *  0bxxx0..Accesses from an untrusted master are allowed.
2954  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2955  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2956  *  0bxx0x..This peripheral allows write accesses.
2957  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2958  *          error response and no peripheral access is initiated on the IPS bus.
2959  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2960  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2961  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2962  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2963  *          on the IPS bus.
2964  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2965  */
2966 #define AIPSTZ_OPACR_OPAC3(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2967 
2968 #define AIPSTZ_OPACR_OPAC2_MASK                  (0xF00000U)
2969 #define AIPSTZ_OPACR_OPAC2_SHIFT                 (20U)
2970 /*! OPAC2
2971  *  0bxxx0..Accesses from an untrusted master are allowed.
2972  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2973  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2974  *  0bxx0x..This peripheral allows write accesses.
2975  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2976  *          error response and no peripheral access is initiated on the IPS bus.
2977  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2978  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2979  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2980  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2981  *          on the IPS bus.
2982  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2983  */
2984 #define AIPSTZ_OPACR_OPAC2(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2985 
2986 #define AIPSTZ_OPACR_OPAC1_MASK                  (0xF000000U)
2987 #define AIPSTZ_OPACR_OPAC1_SHIFT                 (24U)
2988 /*! OPAC1
2989  *  0bxxx0..Accesses from an untrusted master are allowed.
2990  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2991  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2992  *  0bxx0x..This peripheral allows write accesses.
2993  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2994  *          error response and no peripheral access is initiated on the IPS bus.
2995  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2996  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2997  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2998  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
2999  *          on the IPS bus.
3000  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3001  */
3002 #define AIPSTZ_OPACR_OPAC1(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
3003 
3004 #define AIPSTZ_OPACR_OPAC0_MASK                  (0xF0000000U)
3005 #define AIPSTZ_OPACR_OPAC0_SHIFT                 (28U)
3006 /*! OPAC0
3007  *  0bxxx0..Accesses from an untrusted master are allowed.
3008  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3009  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3010  *  0bxx0x..This peripheral allows write accesses.
3011  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3012  *          error response and no peripheral access is initiated on the IPS bus.
3013  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3014  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3015  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3016  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3017  *          on the IPS bus.
3018  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3019  */
3020 #define AIPSTZ_OPACR_OPAC0(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
3021 /*! @} */
3022 
3023 /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
3024 /*! @{ */
3025 
3026 #define AIPSTZ_OPACR1_OPAC15_MASK                (0xFU)
3027 #define AIPSTZ_OPACR1_OPAC15_SHIFT               (0U)
3028 /*! OPAC15
3029  *  0bxxx0..Accesses from an untrusted master are allowed.
3030  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3031  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3032  *  0bxx0x..This peripheral allows write accesses.
3033  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3034  *          error response and no peripheral access is initiated on the IPS bus.
3035  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3036  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3037  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3038  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3039  *          on the IPS bus.
3040  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3041  */
3042 #define AIPSTZ_OPACR1_OPAC15(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
3043 
3044 #define AIPSTZ_OPACR1_OPAC14_MASK                (0xF0U)
3045 #define AIPSTZ_OPACR1_OPAC14_SHIFT               (4U)
3046 /*! OPAC14
3047  *  0bxxx0..Accesses from an untrusted master are allowed.
3048  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3049  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3050  *  0bxx0x..This peripheral allows write accesses.
3051  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3052  *          error response and no peripheral access is initiated on the IPS bus.
3053  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3054  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3055  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3056  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3057  *          on the IPS bus.
3058  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3059  */
3060 #define AIPSTZ_OPACR1_OPAC14(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
3061 
3062 #define AIPSTZ_OPACR1_OPAC13_MASK                (0xF00U)
3063 #define AIPSTZ_OPACR1_OPAC13_SHIFT               (8U)
3064 /*! OPAC13
3065  *  0bxxx0..Accesses from an untrusted master are allowed.
3066  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3067  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3068  *  0bxx0x..This peripheral allows write accesses.
3069  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3070  *          error response and no peripheral access is initiated on the IPS bus.
3071  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3072  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3073  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3074  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3075  *          on the IPS bus.
3076  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3077  */
3078 #define AIPSTZ_OPACR1_OPAC13(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
3079 
3080 #define AIPSTZ_OPACR1_OPAC12_MASK                (0xF000U)
3081 #define AIPSTZ_OPACR1_OPAC12_SHIFT               (12U)
3082 /*! OPAC12
3083  *  0bxxx0..Accesses from an untrusted master are allowed.
3084  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3085  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3086  *  0bxx0x..This peripheral allows write accesses.
3087  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3088  *          error response and no peripheral access is initiated on the IPS bus.
3089  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3090  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3091  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3092  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3093  *          on the IPS bus.
3094  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3095  */
3096 #define AIPSTZ_OPACR1_OPAC12(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
3097 
3098 #define AIPSTZ_OPACR1_OPAC11_MASK                (0xF0000U)
3099 #define AIPSTZ_OPACR1_OPAC11_SHIFT               (16U)
3100 /*! OPAC11
3101  *  0bxxx0..Accesses from an untrusted master are allowed.
3102  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3103  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3104  *  0bxx0x..This peripheral allows write accesses.
3105  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3106  *          error response and no peripheral access is initiated on the IPS bus.
3107  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3108  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3109  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3110  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3111  *          on the IPS bus.
3112  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3113  */
3114 #define AIPSTZ_OPACR1_OPAC11(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
3115 
3116 #define AIPSTZ_OPACR1_OPAC10_MASK                (0xF00000U)
3117 #define AIPSTZ_OPACR1_OPAC10_SHIFT               (20U)
3118 /*! OPAC10
3119  *  0bxxx0..Accesses from an untrusted master are allowed.
3120  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3121  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3122  *  0bxx0x..This peripheral allows write accesses.
3123  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3124  *          error response and no peripheral access is initiated on the IPS bus.
3125  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3126  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3127  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3128  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3129  *          on the IPS bus.
3130  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3131  */
3132 #define AIPSTZ_OPACR1_OPAC10(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
3133 
3134 #define AIPSTZ_OPACR1_OPAC9_MASK                 (0xF000000U)
3135 #define AIPSTZ_OPACR1_OPAC9_SHIFT                (24U)
3136 /*! OPAC9
3137  *  0bxxx0..Accesses from an untrusted master are allowed.
3138  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3139  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3140  *  0bxx0x..This peripheral allows write accesses.
3141  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3142  *          error response and no peripheral access is initiated on the IPS bus.
3143  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3144  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3145  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3146  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3147  *          on the IPS bus.
3148  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3149  */
3150 #define AIPSTZ_OPACR1_OPAC9(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
3151 
3152 #define AIPSTZ_OPACR1_OPAC8_MASK                 (0xF0000000U)
3153 #define AIPSTZ_OPACR1_OPAC8_SHIFT                (28U)
3154 /*! OPAC8
3155  *  0bxxx0..Accesses from an untrusted master are allowed.
3156  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3157  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3158  *  0bxx0x..This peripheral allows write accesses.
3159  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3160  *          error response and no peripheral access is initiated on the IPS bus.
3161  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3162  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3163  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3164  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3165  *          on the IPS bus.
3166  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3167  */
3168 #define AIPSTZ_OPACR1_OPAC8(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
3169 /*! @} */
3170 
3171 /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
3172 /*! @{ */
3173 
3174 #define AIPSTZ_OPACR2_OPAC23_MASK                (0xFU)
3175 #define AIPSTZ_OPACR2_OPAC23_SHIFT               (0U)
3176 /*! OPAC23
3177  *  0bxxx0..Accesses from an untrusted master are allowed.
3178  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3179  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3180  *  0bxx0x..This peripheral allows write accesses.
3181  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3182  *          error response and no peripheral access is initiated on the IPS bus.
3183  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3184  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3185  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3186  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3187  *          on the IPS bus.
3188  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3189  */
3190 #define AIPSTZ_OPACR2_OPAC23(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
3191 
3192 #define AIPSTZ_OPACR2_OPAC22_MASK                (0xF0U)
3193 #define AIPSTZ_OPACR2_OPAC22_SHIFT               (4U)
3194 /*! OPAC22
3195  *  0bxxx0..Accesses from an untrusted master are allowed.
3196  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3197  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3198  *  0bxx0x..This peripheral allows write accesses.
3199  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3200  *          error response and no peripheral access is initiated on the IPS bus.
3201  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3202  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3203  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3204  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3205  *          on the IPS bus.
3206  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3207  */
3208 #define AIPSTZ_OPACR2_OPAC22(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
3209 
3210 #define AIPSTZ_OPACR2_OPAC21_MASK                (0xF00U)
3211 #define AIPSTZ_OPACR2_OPAC21_SHIFT               (8U)
3212 /*! OPAC21
3213  *  0bxxx0..Accesses from an untrusted master are allowed.
3214  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3215  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3216  *  0bxx0x..This peripheral allows write accesses.
3217  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3218  *          error response and no peripheral access is initiated on the IPS bus.
3219  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3220  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3221  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3222  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3223  *          on the IPS bus.
3224  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3225  */
3226 #define AIPSTZ_OPACR2_OPAC21(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
3227 
3228 #define AIPSTZ_OPACR2_OPAC20_MASK                (0xF000U)
3229 #define AIPSTZ_OPACR2_OPAC20_SHIFT               (12U)
3230 /*! OPAC20
3231  *  0bxxx0..Accesses from an untrusted master are allowed.
3232  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3233  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3234  *  0bxx0x..This peripheral allows write accesses.
3235  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3236  *          error response and no peripheral access is initiated on the IPS bus.
3237  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3238  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3239  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3240  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3241  *          on the IPS bus.
3242  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3243  */
3244 #define AIPSTZ_OPACR2_OPAC20(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
3245 
3246 #define AIPSTZ_OPACR2_OPAC19_MASK                (0xF0000U)
3247 #define AIPSTZ_OPACR2_OPAC19_SHIFT               (16U)
3248 /*! OPAC19
3249  *  0bxxx0..Accesses from an untrusted master are allowed.
3250  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3251  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3252  *  0bxx0x..This peripheral allows write accesses.
3253  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3254  *          error response and no peripheral access is initiated on the IPS bus.
3255  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3256  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3257  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3258  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3259  *          on the IPS bus.
3260  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3261  */
3262 #define AIPSTZ_OPACR2_OPAC19(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
3263 
3264 #define AIPSTZ_OPACR2_OPAC18_MASK                (0xF00000U)
3265 #define AIPSTZ_OPACR2_OPAC18_SHIFT               (20U)
3266 /*! OPAC18
3267  *  0bxxx0..Accesses from an untrusted master are allowed.
3268  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3269  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3270  *  0bxx0x..This peripheral allows write accesses.
3271  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3272  *          error response and no peripheral access is initiated on the IPS bus.
3273  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3274  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3275  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3276  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3277  *          on the IPS bus.
3278  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3279  */
3280 #define AIPSTZ_OPACR2_OPAC18(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
3281 
3282 #define AIPSTZ_OPACR2_OPAC17_MASK                (0xF000000U)
3283 #define AIPSTZ_OPACR2_OPAC17_SHIFT               (24U)
3284 /*! OPAC17
3285  *  0bxxx0..Accesses from an untrusted master are allowed.
3286  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3287  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3288  *  0bxx0x..This peripheral allows write accesses.
3289  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3290  *          error response and no peripheral access is initiated on the IPS bus.
3291  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3292  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3293  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3294  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3295  *          on the IPS bus.
3296  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3297  */
3298 #define AIPSTZ_OPACR2_OPAC17(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
3299 
3300 #define AIPSTZ_OPACR2_OPAC16_MASK                (0xF0000000U)
3301 #define AIPSTZ_OPACR2_OPAC16_SHIFT               (28U)
3302 /*! OPAC16
3303  *  0bxxx0..Accesses from an untrusted master are allowed.
3304  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3305  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3306  *  0bxx0x..This peripheral allows write accesses.
3307  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3308  *          error response and no peripheral access is initiated on the IPS bus.
3309  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3310  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3311  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3312  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3313  *          on the IPS bus.
3314  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3315  */
3316 #define AIPSTZ_OPACR2_OPAC16(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
3317 /*! @} */
3318 
3319 /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
3320 /*! @{ */
3321 
3322 #define AIPSTZ_OPACR3_OPAC31_MASK                (0xFU)
3323 #define AIPSTZ_OPACR3_OPAC31_SHIFT               (0U)
3324 /*! OPAC31
3325  *  0bxxx0..Accesses from an untrusted master are allowed.
3326  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3327  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3328  *  0bxx0x..This peripheral allows write accesses.
3329  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3330  *          error response and no peripheral access is initiated on the IPS bus.
3331  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3332  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3333  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3334  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3335  *          on the IPS bus.
3336  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3337  */
3338 #define AIPSTZ_OPACR3_OPAC31(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
3339 
3340 #define AIPSTZ_OPACR3_OPAC30_MASK                (0xF0U)
3341 #define AIPSTZ_OPACR3_OPAC30_SHIFT               (4U)
3342 /*! OPAC30
3343  *  0bxxx0..Accesses from an untrusted master are allowed.
3344  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3345  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3346  *  0bxx0x..This peripheral allows write accesses.
3347  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3348  *          error response and no peripheral access is initiated on the IPS bus.
3349  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3350  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3351  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3352  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3353  *          on the IPS bus.
3354  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3355  */
3356 #define AIPSTZ_OPACR3_OPAC30(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
3357 
3358 #define AIPSTZ_OPACR3_OPAC29_MASK                (0xF00U)
3359 #define AIPSTZ_OPACR3_OPAC29_SHIFT               (8U)
3360 /*! OPAC29
3361  *  0bxxx0..Accesses from an untrusted master are allowed.
3362  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3363  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3364  *  0bxx0x..This peripheral allows write accesses.
3365  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3366  *          error response and no peripheral access is initiated on the IPS bus.
3367  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3368  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3369  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3370  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3371  *          on the IPS bus.
3372  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3373  */
3374 #define AIPSTZ_OPACR3_OPAC29(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
3375 
3376 #define AIPSTZ_OPACR3_OPAC28_MASK                (0xF000U)
3377 #define AIPSTZ_OPACR3_OPAC28_SHIFT               (12U)
3378 /*! OPAC28
3379  *  0bxxx0..Accesses from an untrusted master are allowed.
3380  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3381  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3382  *  0bxx0x..This peripheral allows write accesses.
3383  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3384  *          error response and no peripheral access is initiated on the IPS bus.
3385  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3386  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3387  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3388  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3389  *          on the IPS bus.
3390  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3391  */
3392 #define AIPSTZ_OPACR3_OPAC28(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
3393 
3394 #define AIPSTZ_OPACR3_OPAC27_MASK                (0xF0000U)
3395 #define AIPSTZ_OPACR3_OPAC27_SHIFT               (16U)
3396 /*! OPAC27
3397  *  0bxxx0..Accesses from an untrusted master are allowed.
3398  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3399  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3400  *  0bxx0x..This peripheral allows write accesses.
3401  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3402  *          error response and no peripheral access is initiated on the IPS bus.
3403  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3404  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3405  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3406  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3407  *          on the IPS bus.
3408  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3409  */
3410 #define AIPSTZ_OPACR3_OPAC27(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
3411 
3412 #define AIPSTZ_OPACR3_OPAC26_MASK                (0xF00000U)
3413 #define AIPSTZ_OPACR3_OPAC26_SHIFT               (20U)
3414 /*! OPAC26
3415  *  0bxxx0..Accesses from an untrusted master are allowed.
3416  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3417  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3418  *  0bxx0x..This peripheral allows write accesses.
3419  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3420  *          error response and no peripheral access is initiated on the IPS bus.
3421  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3422  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3423  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3424  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3425  *          on the IPS bus.
3426  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3427  */
3428 #define AIPSTZ_OPACR3_OPAC26(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
3429 
3430 #define AIPSTZ_OPACR3_OPAC25_MASK                (0xF000000U)
3431 #define AIPSTZ_OPACR3_OPAC25_SHIFT               (24U)
3432 /*! OPAC25
3433  *  0bxxx0..Accesses from an untrusted master are allowed.
3434  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3435  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3436  *  0bxx0x..This peripheral allows write accesses.
3437  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3438  *          error response and no peripheral access is initiated on the IPS bus.
3439  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3440  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3441  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3442  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3443  *          on the IPS bus.
3444  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3445  */
3446 #define AIPSTZ_OPACR3_OPAC25(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
3447 
3448 #define AIPSTZ_OPACR3_OPAC24_MASK                (0xF0000000U)
3449 #define AIPSTZ_OPACR3_OPAC24_SHIFT               (28U)
3450 /*! OPAC24
3451  *  0bxxx0..Accesses from an untrusted master are allowed.
3452  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3453  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3454  *  0bxx0x..This peripheral allows write accesses.
3455  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3456  *          error response and no peripheral access is initiated on the IPS bus.
3457  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3458  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3459  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3460  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3461  *          on the IPS bus.
3462  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3463  */
3464 #define AIPSTZ_OPACR3_OPAC24(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
3465 /*! @} */
3466 
3467 /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
3468 /*! @{ */
3469 
3470 #define AIPSTZ_OPACR4_OPAC33_MASK                (0xF000000U)
3471 #define AIPSTZ_OPACR4_OPAC33_SHIFT               (24U)
3472 /*! OPAC33
3473  *  0bxxx0..Accesses from an untrusted master are allowed.
3474  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3475  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3476  *  0bxx0x..This peripheral allows write accesses.
3477  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3478  *          error response and no peripheral access is initiated on the IPS bus.
3479  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3480  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3481  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3482  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3483  *          on the IPS bus.
3484  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3485  */
3486 #define AIPSTZ_OPACR4_OPAC33(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
3487 
3488 #define AIPSTZ_OPACR4_OPAC32_MASK                (0xF0000000U)
3489 #define AIPSTZ_OPACR4_OPAC32_SHIFT               (28U)
3490 /*! OPAC32
3491  *  0bxxx0..Accesses from an untrusted master are allowed.
3492  *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
3493  *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3494  *  0bxx0x..This peripheral allows write accesses.
3495  *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
3496  *          error response and no peripheral access is initiated on the IPS bus.
3497  *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
3498  *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
3499  *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
3500  *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
3501  *          on the IPS bus.
3502  *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
3503  */
3504 #define AIPSTZ_OPACR4_OPAC32(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
3505 /*! @} */
3506 
3507 
3508 /*!
3509  * @}
3510  */ /* end of group AIPSTZ_Register_Masks */
3511 
3512 
3513 /* AIPSTZ - Peripheral instance base addresses */
3514 /** Peripheral AIPSTZ1 base address */
3515 #define AIPSTZ1_BASE                             (0x4007C000u)
3516 /** Peripheral AIPSTZ1 base pointer */
3517 #define AIPSTZ1                                  ((AIPSTZ_Type *)AIPSTZ1_BASE)
3518 /** Peripheral AIPSTZ2 base address */
3519 #define AIPSTZ2_BASE                             (0x4017C000u)
3520 /** Peripheral AIPSTZ2 base pointer */
3521 #define AIPSTZ2                                  ((AIPSTZ_Type *)AIPSTZ2_BASE)
3522 /** Peripheral AIPSTZ3 base address */
3523 #define AIPSTZ3_BASE                             (0x4027C000u)
3524 /** Peripheral AIPSTZ3 base pointer */
3525 #define AIPSTZ3                                  ((AIPSTZ_Type *)AIPSTZ3_BASE)
3526 /** Peripheral AIPSTZ4 base address */
3527 #define AIPSTZ4_BASE                             (0x4037C000u)
3528 /** Peripheral AIPSTZ4 base pointer */
3529 #define AIPSTZ4                                  ((AIPSTZ_Type *)AIPSTZ4_BASE)
3530 /** Array initializer of AIPSTZ peripheral base addresses */
3531 #define AIPSTZ_BASE_ADDRS                        { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
3532 /** Array initializer of AIPSTZ peripheral base pointers */
3533 #define AIPSTZ_BASE_PTRS                         { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
3534 
3535 /*!
3536  * @}
3537  */ /* end of group AIPSTZ_Peripheral_Access_Layer */
3538 
3539 
3540 /* ----------------------------------------------------------------------------
3541    -- AOI Peripheral Access Layer
3542    ---------------------------------------------------------------------------- */
3543 
3544 /*!
3545  * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
3546  * @{
3547  */
3548 
3549 /** AOI - Register Layout Typedef */
3550 typedef struct {
3551   struct {                                         /* offset: 0x0, array step: 0x4 */
3552     __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
3553     __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
3554   } BFCRT[4];
3555 } AOI_Type;
3556 
3557 /* ----------------------------------------------------------------------------
3558    -- AOI Register Masks
3559    ---------------------------------------------------------------------------- */
3560 
3561 /*!
3562  * @addtogroup AOI_Register_Masks AOI Register Masks
3563  * @{
3564  */
3565 
3566 /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
3567 /*! @{ */
3568 
3569 #define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
3570 #define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
3571 /*! PT1_DC - Product term 1, D input configuration
3572  *  0b00..Force the D input in this product term to a logical zero
3573  *  0b01..Pass the D input in this product term
3574  *  0b10..Complement the D input in this product term
3575  *  0b11..Force the D input in this product term to a logical one
3576  */
3577 #define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
3578 
3579 #define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
3580 #define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
3581 /*! PT1_CC - Product term 1, C input configuration
3582  *  0b00..Force the C input in this product term to a logical zero
3583  *  0b01..Pass the C input in this product term
3584  *  0b10..Complement the C input in this product term
3585  *  0b11..Force the C input in this product term to a logical one
3586  */
3587 #define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
3588 
3589 #define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
3590 #define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
3591 /*! PT1_BC - Product term 1, B input configuration
3592  *  0b00..Force the B input in this product term to a logical zero
3593  *  0b01..Pass the B input in this product term
3594  *  0b10..Complement the B input in this product term
3595  *  0b11..Force the B input in this product term to a logical one
3596  */
3597 #define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
3598 
3599 #define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
3600 #define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
3601 /*! PT1_AC - Product term 1, A input configuration
3602  *  0b00..Force the A input in this product term to a logical zero
3603  *  0b01..Pass the A input in this product term
3604  *  0b10..Complement the A input in this product term
3605  *  0b11..Force the A input in this product term to a logical one
3606  */
3607 #define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
3608 
3609 #define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
3610 #define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
3611 /*! PT0_DC - Product term 0, D input configuration
3612  *  0b00..Force the D input in this product term to a logical zero
3613  *  0b01..Pass the D input in this product term
3614  *  0b10..Complement the D input in this product term
3615  *  0b11..Force the D input in this product term to a logical one
3616  */
3617 #define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
3618 
3619 #define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
3620 #define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
3621 /*! PT0_CC - Product term 0, C input configuration
3622  *  0b00..Force the C input in this product term to a logical zero
3623  *  0b01..Pass the C input in this product term
3624  *  0b10..Complement the C input in this product term
3625  *  0b11..Force the C input in this product term to a logical one
3626  */
3627 #define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
3628 
3629 #define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
3630 #define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
3631 /*! PT0_BC - Product term 0, B input configuration
3632  *  0b00..Force the B input in this product term to a logical zero
3633  *  0b01..Pass the B input in this product term
3634  *  0b10..Complement the B input in this product term
3635  *  0b11..Force the B input in this product term to a logical one
3636  */
3637 #define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
3638 
3639 #define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
3640 #define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
3641 /*! PT0_AC - Product term 0, A input configuration
3642  *  0b00..Force the A input in this product term to a logical zero
3643  *  0b01..Pass the A input in this product term
3644  *  0b10..Complement the A input in this product term
3645  *  0b11..Force the A input in this product term to a logical one
3646  */
3647 #define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
3648 /*! @} */
3649 
3650 /* The count of AOI_BFCRT01 */
3651 #define AOI_BFCRT01_COUNT                        (4U)
3652 
3653 /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
3654 /*! @{ */
3655 
3656 #define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
3657 #define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
3658 /*! PT3_DC - Product term 3, D input configuration
3659  *  0b00..Force the D input in this product term to a logical zero
3660  *  0b01..Pass the D input in this product term
3661  *  0b10..Complement the D input in this product term
3662  *  0b11..Force the D input in this product term to a logical one
3663  */
3664 #define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
3665 
3666 #define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
3667 #define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
3668 /*! PT3_CC - Product term 3, C input configuration
3669  *  0b00..Force the C input in this product term to a logical zero
3670  *  0b01..Pass the C input in this product term
3671  *  0b10..Complement the C input in this product term
3672  *  0b11..Force the C input in this product term to a logical one
3673  */
3674 #define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
3675 
3676 #define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
3677 #define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
3678 /*! PT3_BC - Product term 3, B input configuration
3679  *  0b00..Force the B input in this product term to a logical zero
3680  *  0b01..Pass the B input in this product term
3681  *  0b10..Complement the B input in this product term
3682  *  0b11..Force the B input in this product term to a logical one
3683  */
3684 #define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
3685 
3686 #define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
3687 #define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
3688 /*! PT3_AC - Product term 3, A input configuration
3689  *  0b00..Force the A input in this product term to a logical zero
3690  *  0b01..Pass the A input in this product term
3691  *  0b10..Complement the A input in this product term
3692  *  0b11..Force the A input in this product term to a logical one
3693  */
3694 #define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
3695 
3696 #define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
3697 #define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
3698 /*! PT2_DC - Product term 2, D input configuration
3699  *  0b00..Force the D input in this product term to a logical zero
3700  *  0b01..Pass the D input in this product term
3701  *  0b10..Complement the D input in this product term
3702  *  0b11..Force the D input in this product term to a logical one
3703  */
3704 #define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
3705 
3706 #define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
3707 #define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
3708 /*! PT2_CC - Product term 2, C input configuration
3709  *  0b00..Force the C input in this product term to a logical zero
3710  *  0b01..Pass the C input in this product term
3711  *  0b10..Complement the C input in this product term
3712  *  0b11..Force the C input in this product term to a logical one
3713  */
3714 #define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
3715 
3716 #define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
3717 #define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
3718 /*! PT2_BC - Product term 2, B input configuration
3719  *  0b00..Force the B input in this product term to a logical zero
3720  *  0b01..Pass the B input in this product term
3721  *  0b10..Complement the B input in this product term
3722  *  0b11..Force the B input in this product term to a logical one
3723  */
3724 #define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
3725 
3726 #define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
3727 #define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
3728 /*! PT2_AC - Product term 2, A input configuration
3729  *  0b00..Force the A input in this product term to a logical zero
3730  *  0b01..Pass the A input in this product term
3731  *  0b10..Complement the A input in this product term
3732  *  0b11..Force the A input in this product term to a logical one
3733  */
3734 #define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
3735 /*! @} */
3736 
3737 /* The count of AOI_BFCRT23 */
3738 #define AOI_BFCRT23_COUNT                        (4U)
3739 
3740 
3741 /*!
3742  * @}
3743  */ /* end of group AOI_Register_Masks */
3744 
3745 
3746 /* AOI - Peripheral instance base addresses */
3747 /** Peripheral AOI1 base address */
3748 #define AOI1_BASE                                (0x403B4000u)
3749 /** Peripheral AOI1 base pointer */
3750 #define AOI1                                     ((AOI_Type *)AOI1_BASE)
3751 /** Peripheral AOI2 base address */
3752 #define AOI2_BASE                                (0x403B8000u)
3753 /** Peripheral AOI2 base pointer */
3754 #define AOI2                                     ((AOI_Type *)AOI2_BASE)
3755 /** Array initializer of AOI peripheral base addresses */
3756 #define AOI_BASE_ADDRS                           { 0u, AOI1_BASE, AOI2_BASE }
3757 /** Array initializer of AOI peripheral base pointers */
3758 #define AOI_BASE_PTRS                            { (AOI_Type *)0u, AOI1, AOI2 }
3759 
3760 /*!
3761  * @}
3762  */ /* end of group AOI_Peripheral_Access_Layer */
3763 
3764 
3765 /* ----------------------------------------------------------------------------
3766    -- BEE Peripheral Access Layer
3767    ---------------------------------------------------------------------------- */
3768 
3769 /*!
3770  * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
3771  * @{
3772  */
3773 
3774 /** BEE - Register Layout Typedef */
3775 typedef struct {
3776   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x0 */
3777   __IO uint32_t ADDR_OFFSET0;                      /**< Offset region 0 Register, offset: 0x4 */
3778   __IO uint32_t ADDR_OFFSET1;                      /**< Offset region 1 Register, offset: 0x8 */
3779   __IO uint32_t AES_KEY0_W0;                       /**< AES Key 0 Register, offset: 0xC */
3780   __IO uint32_t AES_KEY0_W1;                       /**< AES Key 1 Register, offset: 0x10 */
3781   __IO uint32_t AES_KEY0_W2;                       /**< AES Key 2 Register, offset: 0x14 */
3782   __IO uint32_t AES_KEY0_W3;                       /**< AES Key 3 Register, offset: 0x18 */
3783   __IO uint32_t STATUS;                            /**< Status Register, offset: 0x1C */
3784   __O  uint32_t CTR_NONCE0_W0;                     /**< NONCE00 Register, offset: 0x20 */
3785   __O  uint32_t CTR_NONCE0_W1;                     /**< NONCE01 Register, offset: 0x24 */
3786   __O  uint32_t CTR_NONCE0_W2;                     /**< NONCE02 Register, offset: 0x28 */
3787   __O  uint32_t CTR_NONCE0_W3;                     /**< NONCE03 Register, offset: 0x2C */
3788   __O  uint32_t CTR_NONCE1_W0;                     /**< NONCE10 Register, offset: 0x30 */
3789   __O  uint32_t CTR_NONCE1_W1;                     /**< NONCE11 Register, offset: 0x34 */
3790   __O  uint32_t CTR_NONCE1_W2;                     /**< NONCE12 Register, offset: 0x38 */
3791   __O  uint32_t CTR_NONCE1_W3;                     /**< NONCE13 Register, offset: 0x3C */
3792   __IO uint32_t REGION1_TOP;                       /**< Region1 Top Address Register, offset: 0x40 */
3793   __IO uint32_t REGION1_BOT;                       /**< Region1 Bottom Address Register, offset: 0x44 */
3794 } BEE_Type;
3795 
3796 /* ----------------------------------------------------------------------------
3797    -- BEE Register Masks
3798    ---------------------------------------------------------------------------- */
3799 
3800 /*!
3801  * @addtogroup BEE_Register_Masks BEE Register Masks
3802  * @{
3803  */
3804 
3805 /*! @name CTRL - Control Register */
3806 /*! @{ */
3807 
3808 #define BEE_CTRL_BEE_ENABLE_MASK                 (0x1U)
3809 #define BEE_CTRL_BEE_ENABLE_SHIFT                (0U)
3810 /*! BEE_ENABLE
3811  *  0b0..Disable BEE
3812  *  0b1..Enable BEE
3813  */
3814 #define BEE_CTRL_BEE_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
3815 
3816 #define BEE_CTRL_CTRL_CLK_EN_MASK                (0x2U)
3817 #define BEE_CTRL_CTRL_CLK_EN_SHIFT               (1U)
3818 #define BEE_CTRL_CTRL_CLK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
3819 
3820 #define BEE_CTRL_CTRL_SFTRST_N_MASK              (0x4U)
3821 #define BEE_CTRL_CTRL_SFTRST_N_SHIFT             (2U)
3822 #define BEE_CTRL_CTRL_SFTRST_N(x)                (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
3823 
3824 #define BEE_CTRL_KEY_VALID_MASK                  (0x10U)
3825 #define BEE_CTRL_KEY_VALID_SHIFT                 (4U)
3826 #define BEE_CTRL_KEY_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
3827 
3828 #define BEE_CTRL_KEY_REGION_SEL_MASK             (0x20U)
3829 #define BEE_CTRL_KEY_REGION_SEL_SHIFT            (5U)
3830 /*! KEY_REGION_SEL
3831  *  0b0..Load AES key for region0
3832  *  0b1..Load AES key for region1
3833  */
3834 #define BEE_CTRL_KEY_REGION_SEL(x)               (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
3835 
3836 #define BEE_CTRL_AC_PROT_EN_MASK                 (0x40U)
3837 #define BEE_CTRL_AC_PROT_EN_SHIFT                (6U)
3838 #define BEE_CTRL_AC_PROT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
3839 
3840 #define BEE_CTRL_LITTLE_ENDIAN_MASK              (0x80U)
3841 #define BEE_CTRL_LITTLE_ENDIAN_SHIFT             (7U)
3842 /*! LITTLE_ENDIAN
3843  *  0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
3844  *       B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
3845  *       Byte0 to Byte15.
3846  *  0b1..The input and output data of AES core is not swapped.
3847  */
3848 #define BEE_CTRL_LITTLE_ENDIAN(x)                (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
3849 
3850 #define BEE_CTRL_SECURITY_LEVEL_R0_MASK          (0x300U)
3851 #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT         (8U)
3852 #define BEE_CTRL_SECURITY_LEVEL_R0(x)            (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
3853 
3854 #define BEE_CTRL_CTRL_AES_MODE_R0_MASK           (0x400U)
3855 #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT          (10U)
3856 /*! CTRL_AES_MODE_R0
3857  *  0b0..ECB
3858  *  0b1..CTR
3859  */
3860 #define BEE_CTRL_CTRL_AES_MODE_R0(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3861 
3862 #define BEE_CTRL_SECURITY_LEVEL_R1_MASK          (0x3000U)
3863 #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT         (12U)
3864 #define BEE_CTRL_SECURITY_LEVEL_R1(x)            (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3865 
3866 #define BEE_CTRL_CTRL_AES_MODE_R1_MASK           (0x4000U)
3867 #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT          (14U)
3868 /*! CTRL_AES_MODE_R1
3869  *  0b0..ECB
3870  *  0b1..CTR
3871  */
3872 #define BEE_CTRL_CTRL_AES_MODE_R1(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3873 
3874 #define BEE_CTRL_BEE_ENABLE_LOCK_MASK            (0x10000U)
3875 #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT           (16U)
3876 #define BEE_CTRL_BEE_ENABLE_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3877 
3878 #define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK           (0x20000U)
3879 #define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT          (17U)
3880 #define BEE_CTRL_CTRL_CLK_EN_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3881 
3882 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK         (0x40000U)
3883 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT        (18U)
3884 #define BEE_CTRL_CTRL_SFTRST_N_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3885 
3886 #define BEE_CTRL_REGION1_ADDR_LOCK_MASK          (0x80000U)
3887 #define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT         (19U)
3888 #define BEE_CTRL_REGION1_ADDR_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3889 
3890 #define BEE_CTRL_KEY_VALID_LOCK_MASK             (0x100000U)
3891 #define BEE_CTRL_KEY_VALID_LOCK_SHIFT            (20U)
3892 #define BEE_CTRL_KEY_VALID_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3893 
3894 #define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK        (0x200000U)
3895 #define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT       (21U)
3896 #define BEE_CTRL_KEY_REGION_SEL_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3897 
3898 #define BEE_CTRL_AC_PROT_EN_LOCK_MASK            (0x400000U)
3899 #define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT           (22U)
3900 #define BEE_CTRL_AC_PROT_EN_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3901 
3902 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK         (0x800000U)
3903 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT        (23U)
3904 #define BEE_CTRL_LITTLE_ENDIAN_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3905 
3906 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK     (0x3000000U)
3907 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT    (24U)
3908 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3909 
3910 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK      (0x4000000U)
3911 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT     (26U)
3912 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3913 
3914 #define BEE_CTRL_REGION0_KEY_LOCK_MASK           (0x8000000U)
3915 #define BEE_CTRL_REGION0_KEY_LOCK_SHIFT          (27U)
3916 #define BEE_CTRL_REGION0_KEY_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3917 
3918 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK     (0x30000000U)
3919 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT    (28U)
3920 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3921 
3922 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK      (0x40000000U)
3923 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT     (30U)
3924 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3925 
3926 #define BEE_CTRL_REGION1_KEY_LOCK_MASK           (0x80000000U)
3927 #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT          (31U)
3928 #define BEE_CTRL_REGION1_KEY_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3929 /*! @} */
3930 
3931 /*! @name ADDR_OFFSET0 - Offset region 0 Register */
3932 /*! @{ */
3933 
3934 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK       (0xFFFFU)
3935 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT      (0U)
3936 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x)         (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3937 
3938 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK  (0xFFFF0000U)
3939 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3940 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3941 /*! @} */
3942 
3943 /*! @name ADDR_OFFSET1 - Offset region 1 Register */
3944 /*! @{ */
3945 
3946 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK       (0xFFFFU)
3947 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT      (0U)
3948 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x)         (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3949 
3950 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK  (0xFFFF0000U)
3951 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3952 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3953 /*! @} */
3954 
3955 /*! @name AES_KEY0_W0 - AES Key 0 Register */
3956 /*! @{ */
3957 
3958 #define BEE_AES_KEY0_W0_KEY0_MASK                (0xFFFFFFFFU)
3959 #define BEE_AES_KEY0_W0_KEY0_SHIFT               (0U)
3960 /*! KEY0 - AES 128 key from software
3961  */
3962 #define BEE_AES_KEY0_W0_KEY0(x)                  (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3963 /*! @} */
3964 
3965 /*! @name AES_KEY0_W1 - AES Key 1 Register */
3966 /*! @{ */
3967 
3968 #define BEE_AES_KEY0_W1_KEY1_MASK                (0xFFFFFFFFU)
3969 #define BEE_AES_KEY0_W1_KEY1_SHIFT               (0U)
3970 /*! KEY1 - AES 128 key from software
3971  */
3972 #define BEE_AES_KEY0_W1_KEY1(x)                  (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3973 /*! @} */
3974 
3975 /*! @name AES_KEY0_W2 - AES Key 2 Register */
3976 /*! @{ */
3977 
3978 #define BEE_AES_KEY0_W2_KEY2_MASK                (0xFFFFFFFFU)
3979 #define BEE_AES_KEY0_W2_KEY2_SHIFT               (0U)
3980 /*! KEY2 - AES 128 key from software
3981  */
3982 #define BEE_AES_KEY0_W2_KEY2(x)                  (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3983 /*! @} */
3984 
3985 /*! @name AES_KEY0_W3 - AES Key 3 Register */
3986 /*! @{ */
3987 
3988 #define BEE_AES_KEY0_W3_KEY3_MASK                (0xFFFFFFFFU)
3989 #define BEE_AES_KEY0_W3_KEY3_SHIFT               (0U)
3990 /*! KEY3 - AES 128 key from software
3991  */
3992 #define BEE_AES_KEY0_W3_KEY3(x)                  (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3993 /*! @} */
3994 
3995 /*! @name STATUS - Status Register */
3996 /*! @{ */
3997 
3998 #define BEE_STATUS_IRQ_VEC_MASK                  (0xFFU)
3999 #define BEE_STATUS_IRQ_VEC_SHIFT                 (0U)
4000 #define BEE_STATUS_IRQ_VEC(x)                    (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
4001 
4002 #define BEE_STATUS_BEE_IDLE_MASK                 (0x100U)
4003 #define BEE_STATUS_BEE_IDLE_SHIFT                (8U)
4004 #define BEE_STATUS_BEE_IDLE(x)                   (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
4005 /*! @} */
4006 
4007 /*! @name CTR_NONCE0_W0 - NONCE00 Register */
4008 /*! @{ */
4009 
4010 #define BEE_CTR_NONCE0_W0_NONCE00_MASK           (0xFFFFFFFFU)
4011 #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT          (0U)
4012 #define BEE_CTR_NONCE0_W0_NONCE00(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
4013 /*! @} */
4014 
4015 /*! @name CTR_NONCE0_W1 - NONCE01 Register */
4016 /*! @{ */
4017 
4018 #define BEE_CTR_NONCE0_W1_NONCE01_MASK           (0xFFFFFFFFU)
4019 #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT          (0U)
4020 #define BEE_CTR_NONCE0_W1_NONCE01(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
4021 /*! @} */
4022 
4023 /*! @name CTR_NONCE0_W2 - NONCE02 Register */
4024 /*! @{ */
4025 
4026 #define BEE_CTR_NONCE0_W2_NONCE02_MASK           (0xFFFFFFFFU)
4027 #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT          (0U)
4028 #define BEE_CTR_NONCE0_W2_NONCE02(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
4029 /*! @} */
4030 
4031 /*! @name CTR_NONCE0_W3 - NONCE03 Register */
4032 /*! @{ */
4033 
4034 #define BEE_CTR_NONCE0_W3_NONCE03_MASK           (0xFFFFFFFFU)
4035 #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT          (0U)
4036 #define BEE_CTR_NONCE0_W3_NONCE03(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
4037 /*! @} */
4038 
4039 /*! @name CTR_NONCE1_W0 - NONCE10 Register */
4040 /*! @{ */
4041 
4042 #define BEE_CTR_NONCE1_W0_NONCE10_MASK           (0xFFFFFFFFU)
4043 #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT          (0U)
4044 #define BEE_CTR_NONCE1_W0_NONCE10(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
4045 /*! @} */
4046 
4047 /*! @name CTR_NONCE1_W1 - NONCE11 Register */
4048 /*! @{ */
4049 
4050 #define BEE_CTR_NONCE1_W1_NONCE11_MASK           (0xFFFFFFFFU)
4051 #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT          (0U)
4052 #define BEE_CTR_NONCE1_W1_NONCE11(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
4053 /*! @} */
4054 
4055 /*! @name CTR_NONCE1_W2 - NONCE12 Register */
4056 /*! @{ */
4057 
4058 #define BEE_CTR_NONCE1_W2_NONCE12_MASK           (0xFFFFFFFFU)
4059 #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT          (0U)
4060 #define BEE_CTR_NONCE1_W2_NONCE12(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
4061 /*! @} */
4062 
4063 /*! @name CTR_NONCE1_W3 - NONCE13 Register */
4064 /*! @{ */
4065 
4066 #define BEE_CTR_NONCE1_W3_NONCE13_MASK           (0xFFFFFFFFU)
4067 #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT          (0U)
4068 #define BEE_CTR_NONCE1_W3_NONCE13(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
4069 /*! @} */
4070 
4071 /*! @name REGION1_TOP - Region1 Top Address Register */
4072 /*! @{ */
4073 
4074 #define BEE_REGION1_TOP_REGION1_TOP_MASK         (0xFFFFFFFFU)
4075 #define BEE_REGION1_TOP_REGION1_TOP_SHIFT        (0U)
4076 /*! REGION1_TOP - Address upper limit of region1
4077  */
4078 #define BEE_REGION1_TOP_REGION1_TOP(x)           (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
4079 /*! @} */
4080 
4081 /*! @name REGION1_BOT - Region1 Bottom Address Register */
4082 /*! @{ */
4083 
4084 #define BEE_REGION1_BOT_REGION1_BOT_MASK         (0xFFFFFFFFU)
4085 #define BEE_REGION1_BOT_REGION1_BOT_SHIFT        (0U)
4086 /*! REGION1_BOT - Address lower limit of region1
4087  */
4088 #define BEE_REGION1_BOT_REGION1_BOT(x)           (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
4089 /*! @} */
4090 
4091 
4092 /*!
4093  * @}
4094  */ /* end of group BEE_Register_Masks */
4095 
4096 
4097 /* BEE - Peripheral instance base addresses */
4098 /** Peripheral BEE base address */
4099 #define BEE_BASE                                 (0x403EC000u)
4100 /** Peripheral BEE base pointer */
4101 #define BEE                                      ((BEE_Type *)BEE_BASE)
4102 /** Array initializer of BEE peripheral base addresses */
4103 #define BEE_BASE_ADDRS                           { BEE_BASE }
4104 /** Array initializer of BEE peripheral base pointers */
4105 #define BEE_BASE_PTRS                            { BEE }
4106 
4107 /*!
4108  * @}
4109  */ /* end of group BEE_Peripheral_Access_Layer */
4110 
4111 
4112 /* ----------------------------------------------------------------------------
4113    -- CAN Peripheral Access Layer
4114    ---------------------------------------------------------------------------- */
4115 
4116 /*!
4117  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4118  * @{
4119  */
4120 
4121 /** CAN - Register Layout Typedef */
4122 typedef struct {
4123   __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
4124   __IO uint32_t CTRL1;                             /**< Control 1 Register, offset: 0x4 */
4125   __IO uint32_t TIMER;                             /**< Free Running Timer Register, offset: 0x8 */
4126        uint8_t RESERVED_0[4];
4127   __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
4128   __IO uint32_t RX14MASK;                          /**< Rx Buffer 14 Mask Register, offset: 0x14 */
4129   __IO uint32_t RX15MASK;                          /**< Rx Buffer 15 Mask Register, offset: 0x18 */
4130   __IO uint32_t ECR;                               /**< Error Counter Register, offset: 0x1C */
4131   __IO uint32_t ESR1;                              /**< Error and Status 1 Register, offset: 0x20 */
4132   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 Register, offset: 0x24 */
4133   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 Register, offset: 0x28 */
4134   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 Register, offset: 0x2C */
4135   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 Register, offset: 0x30 */
4136   __IO uint32_t CTRL2;                             /**< Control 2 Register, offset: 0x34 */
4137   __I  uint32_t ESR2;                              /**< Error and Status 2 Register, offset: 0x38 */
4138        uint8_t RESERVED_1[8];
4139   __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
4140   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask Register, offset: 0x48 */
4141   __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
4142        uint8_t RESERVED_2[8];
4143   __I  uint32_t DBG1;                              /**< Debug 1 register, offset: 0x58 */
4144   __I  uint32_t DBG2;                              /**< Debug 2 register, offset: 0x5C */
4145        uint8_t RESERVED_3[32];
4146   struct {                                         /* offset: 0x80, array step: 0x10 */
4147     __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
4148     __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
4149     __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
4150     __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4151   } MB[64];
4152        uint8_t RESERVED_4[1024];
4153   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
4154        uint8_t RESERVED_5[96];
4155   __IO uint32_t GFWR;                              /**< Glitch Filter Width Registers, offset: 0x9E0 */
4156 } CAN_Type;
4157 
4158 /* ----------------------------------------------------------------------------
4159    -- CAN Register Masks
4160    ---------------------------------------------------------------------------- */
4161 
4162 /*!
4163  * @addtogroup CAN_Register_Masks CAN Register Masks
4164  * @{
4165  */
4166 
4167 /*! @name MCR - Module Configuration Register */
4168 /*! @{ */
4169 
4170 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
4171 #define CAN_MCR_MAXMB_SHIFT                      (0U)
4172 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4173 
4174 #define CAN_MCR_IDAM_MASK                        (0x300U)
4175 #define CAN_MCR_IDAM_SHIFT                       (8U)
4176 /*! IDAM
4177  *  0b00..Format A One full ID (standard or extended) per ID filter Table element.
4178  *  0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
4179  *  0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
4180  *  0b11..Format D All frames rejected.
4181  */
4182 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4183 
4184 #define CAN_MCR_AEN_MASK                         (0x1000U)
4185 #define CAN_MCR_AEN_SHIFT                        (12U)
4186 /*! AEN
4187  *  0b1..Abort enabled
4188  *  0b0..Abort disabled
4189  */
4190 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4191 
4192 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
4193 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
4194 /*! LPRIOEN
4195  *  0b1..Local Priority enabled
4196  *  0b0..Local Priority disabled
4197  */
4198 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4199 
4200 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
4201 #define CAN_MCR_IRMQ_SHIFT                       (16U)
4202 /*! IRMQ
4203  *  0b1..Individual Rx masking and queue feature are enabled.
4204  *  0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
4205  */
4206 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4207 
4208 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
4209 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
4210 /*! SRXDIS
4211  *  0b1..Self reception disabled
4212  *  0b0..Self reception enabled
4213  */
4214 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4215 
4216 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
4217 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
4218 /*! WAKSRC
4219  *  0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
4220  *  0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
4221  */
4222 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4223 
4224 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
4225 #define CAN_MCR_LPMACK_SHIFT                     (20U)
4226 /*! LPMACK
4227  *  0b1..FLEXCAN is either in Disable Mode, or Stop mode
4228  *  0b0..FLEXCAN not in any of the low power modes
4229  */
4230 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4231 
4232 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
4233 #define CAN_MCR_WRNEN_SHIFT                      (21U)
4234 /*! WRNEN
4235  *  0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
4236  *  0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
4237  */
4238 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4239 
4240 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
4241 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
4242 /*! SLFWAK
4243  *  0b1..FLEXCAN Self Wake Up feature is enabled
4244  *  0b0..FLEXCAN Self Wake Up feature is disabled
4245  */
4246 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4247 
4248 #define CAN_MCR_SUPV_MASK                        (0x800000U)
4249 #define CAN_MCR_SUPV_SHIFT                       (23U)
4250 /*! SUPV
4251  *  0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
4252  *       behaves as though the access was done to an unimplemented register location
4253  *  0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
4254  */
4255 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4256 
4257 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
4258 #define CAN_MCR_FRZACK_SHIFT                     (24U)
4259 /*! FRZACK
4260  *  0b1..FLEXCAN in Freeze Mode, prescaler stopped
4261  *  0b0..FLEXCAN not in Freeze Mode, prescaler running
4262  */
4263 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4264 
4265 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
4266 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
4267 /*! SOFTRST
4268  *  0b1..Reset the registers
4269  *  0b0..No reset request
4270  */
4271 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4272 
4273 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
4274 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
4275 /*! WAKMSK
4276  *  0b1..Wake Up Interrupt is enabled
4277  *  0b0..Wake Up Interrupt is disabled
4278  */
4279 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4280 
4281 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
4282 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
4283 /*! NOTRDY
4284  *  0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
4285  *  0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
4286  */
4287 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4288 
4289 #define CAN_MCR_HALT_MASK                        (0x10000000U)
4290 #define CAN_MCR_HALT_SHIFT                       (28U)
4291 /*! HALT
4292  *  0b1..Enters Freeze Mode if the FRZ bit is asserted.
4293  *  0b0..No Freeze Mode request.
4294  */
4295 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4296 
4297 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
4298 #define CAN_MCR_RFEN_SHIFT                       (29U)
4299 /*! RFEN
4300  *  0b1..FIFO enabled
4301  *  0b0..FIFO not enabled
4302  */
4303 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4304 
4305 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
4306 #define CAN_MCR_FRZ_SHIFT                        (30U)
4307 /*! FRZ
4308  *  0b1..Enabled to enter Freeze Mode
4309  *  0b0..Not enabled to enter Freeze Mode
4310  */
4311 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4312 
4313 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
4314 #define CAN_MCR_MDIS_SHIFT                       (31U)
4315 /*! MDIS
4316  *  0b1..Disable the FLEXCAN module
4317  *  0b0..Enable the FLEXCAN module
4318  */
4319 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4320 /*! @} */
4321 
4322 /*! @name CTRL1 - Control 1 Register */
4323 /*! @{ */
4324 
4325 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
4326 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
4327 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4328 
4329 #define CAN_CTRL1_LOM_MASK                       (0x8U)
4330 #define CAN_CTRL1_LOM_SHIFT                      (3U)
4331 /*! LOM
4332  *  0b1..FLEXCAN module operates in Listen Only Mode
4333  *  0b0..Listen Only Mode is deactivated
4334  */
4335 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4336 
4337 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
4338 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
4339 /*! LBUF
4340  *  0b1..Lowest number buffer is transmitted first
4341  *  0b0..Buffer with highest priority is transmitted first
4342  */
4343 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4344 
4345 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
4346 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
4347 /*! TSYN
4348  *  0b1..Timer Sync feature enabled
4349  *  0b0..Timer Sync feature disabled
4350  */
4351 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4352 
4353 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
4354 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
4355 /*! BOFFREC
4356  *  0b1..Automatic recovering from Bus Off state disabled
4357  *  0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
4358  */
4359 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4360 
4361 #define CAN_CTRL1_SMP_MASK                       (0x80U)
4362 #define CAN_CTRL1_SMP_SHIFT                      (7U)
4363 /*! SMP
4364  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
4365  *       preceding samples, a majority rule is used
4366  *  0b0..Just one sample is used to determine the bit value
4367  */
4368 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4369 
4370 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
4371 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
4372 /*! RWRNMSK
4373  *  0b1..Rx Warning Interrupt enabled
4374  *  0b0..Rx Warning Interrupt disabled
4375  */
4376 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4377 
4378 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
4379 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
4380 /*! TWRNMSK
4381  *  0b1..Tx Warning Interrupt enabled
4382  *  0b0..Tx Warning Interrupt disabled
4383  */
4384 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4385 
4386 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
4387 #define CAN_CTRL1_LPB_SHIFT                      (12U)
4388 /*! LPB
4389  *  0b1..Loop Back enabled
4390  *  0b0..Loop Back disabled
4391  */
4392 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4393 
4394 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
4395 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
4396 /*! ERRMSK
4397  *  0b1..Error interrupt enabled
4398  *  0b0..Error interrupt disabled
4399  */
4400 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4401 
4402 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
4403 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
4404 /*! BOFFMSK
4405  *  0b1..Bus Off interrupt enabled
4406  *  0b0..Bus Off interrupt disabled
4407  */
4408 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4409 
4410 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
4411 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
4412 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4413 
4414 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
4415 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
4416 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4417 
4418 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
4419 #define CAN_CTRL1_RJW_SHIFT                      (22U)
4420 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4421 
4422 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
4423 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
4424 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4425 /*! @} */
4426 
4427 /*! @name TIMER - Free Running Timer Register */
4428 /*! @{ */
4429 
4430 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
4431 #define CAN_TIMER_TIMER_SHIFT                    (0U)
4432 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4433 /*! @} */
4434 
4435 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
4436 /*! @{ */
4437 
4438 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
4439 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
4440 /*! MG
4441  *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
4442  *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
4443  */
4444 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4445 /*! @} */
4446 
4447 /*! @name RX14MASK - Rx Buffer 14 Mask Register */
4448 /*! @{ */
4449 
4450 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
4451 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
4452 /*! RX14M
4453  *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4454  *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
4455  */
4456 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4457 /*! @} */
4458 
4459 /*! @name RX15MASK - Rx Buffer 15 Mask Register */
4460 /*! @{ */
4461 
4462 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
4463 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
4464 /*! RX15M
4465  *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4466  *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
4467  */
4468 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4469 /*! @} */
4470 
4471 /*! @name ECR - Error Counter Register */
4472 /*! @{ */
4473 
4474 #define CAN_ECR_TX_ERR_COUNTER_MASK              (0xFFU)
4475 #define CAN_ECR_TX_ERR_COUNTER_SHIFT             (0U)
4476 #define CAN_ECR_TX_ERR_COUNTER(x)                (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
4477 
4478 #define CAN_ECR_RX_ERR_COUNTER_MASK              (0xFF00U)
4479 #define CAN_ECR_RX_ERR_COUNTER_SHIFT             (8U)
4480 #define CAN_ECR_RX_ERR_COUNTER(x)                (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
4481 /*! @} */
4482 
4483 /*! @name ESR1 - Error and Status 1 Register */
4484 /*! @{ */
4485 
4486 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
4487 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
4488 /*! WAKINT
4489  *  0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
4490  *  0b0..No such occurrence
4491  */
4492 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4493 
4494 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
4495 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
4496 /*! ERRINT
4497  *  0b1..Indicates setting of any Error Bit in the Error and Status Register
4498  *  0b0..No such occurrence
4499  */
4500 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4501 
4502 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
4503 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
4504 /*! BOFFINT
4505  *  0b1..FLEXCAN module entered 'Bus Off' state
4506  *  0b0..No such occurrence
4507  */
4508 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4509 
4510 #define CAN_ESR1_RX_MASK                         (0x8U)
4511 #define CAN_ESR1_RX_SHIFT                        (3U)
4512 /*! RX
4513  *  0b1..FLEXCAN is transmitting a message
4514  *  0b0..FLEXCAN is receiving a message
4515  */
4516 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4517 
4518 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
4519 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
4520 /*! FLTCONF
4521  *  0b00..Error Active
4522  *  0b01..Error Passive
4523  *  0b1x..Bus off
4524  */
4525 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4526 
4527 #define CAN_ESR1_TX_MASK                         (0x40U)
4528 #define CAN_ESR1_TX_SHIFT                        (6U)
4529 /*! TX
4530  *  0b1..FLEXCAN is transmitting a message
4531  *  0b0..FLEXCAN is receiving a message
4532  */
4533 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4534 
4535 #define CAN_ESR1_IDLE_MASK                       (0x80U)
4536 #define CAN_ESR1_IDLE_SHIFT                      (7U)
4537 /*! IDLE
4538  *  0b1..CAN bus is now IDLE
4539  *  0b0..No such occurrence
4540  */
4541 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4542 
4543 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
4544 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
4545 /*! RXWRN
4546  *  0b1..Rx_Err_Counter >= 96
4547  *  0b0..No such occurrence
4548  */
4549 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4550 
4551 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
4552 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
4553 /*! TXWRN
4554  *  0b1..TX_Err_Counter >= 96
4555  *  0b0..No such occurrence
4556  */
4557 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4558 
4559 #define CAN_ESR1_STFERR_MASK                     (0x400U)
4560 #define CAN_ESR1_STFERR_SHIFT                    (10U)
4561 /*! STFERR
4562  *  0b1..A Stuffing Error occurred since last read of this register.
4563  *  0b0..No such occurrence.
4564  */
4565 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4566 
4567 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
4568 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
4569 /*! FRMERR
4570  *  0b1..A Form Error occurred since last read of this register
4571  *  0b0..No such occurrence
4572  */
4573 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4574 
4575 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
4576 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
4577 /*! CRCERR
4578  *  0b1..A CRC error occurred since last read of this register.
4579  *  0b0..No such occurrence
4580  */
4581 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4582 
4583 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
4584 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
4585 /*! ACKERR
4586  *  0b1..An ACK error occurred since last read of this register
4587  *  0b0..No such occurrence
4588  */
4589 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4590 
4591 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
4592 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
4593 /*! BIT0ERR
4594  *  0b1..At least one bit sent as dominant is received as recessive
4595  *  0b0..No such occurrence
4596  */
4597 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4598 
4599 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
4600 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
4601 /*! BIT1ERR
4602  *  0b1..At least one bit sent as recessive is received as dominant
4603  *  0b0..No such occurrence
4604  */
4605 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4606 
4607 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
4608 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
4609 /*! RWRNINT
4610  *  0b1..The Rx error counter transition from < 96 to >= 96
4611  *  0b0..No such occurrence
4612  */
4613 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4614 
4615 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
4616 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
4617 /*! TWRNINT
4618  *  0b1..The Tx error counter transition from < 96 to >= 96
4619  *  0b0..No such occurrence
4620  */
4621 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4622 
4623 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
4624 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
4625 /*! SYNCH
4626  *  0b1..FlexCAN is synchronized to the CAN bus
4627  *  0b0..FlexCAN is not synchronized to the CAN bus
4628  */
4629 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4630 /*! @} */
4631 
4632 /*! @name IMASK2 - Interrupt Masks 2 Register */
4633 /*! @{ */
4634 
4635 #define CAN_IMASK2_BUFHM_MASK                    (0xFFFFFFFFU)
4636 #define CAN_IMASK2_BUFHM_SHIFT                   (0U)
4637 /*! BUFHM
4638  *  0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
4639  *  0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
4640  */
4641 #define CAN_IMASK2_BUFHM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
4642 /*! @} */
4643 
4644 /*! @name IMASK1 - Interrupt Masks 1 Register */
4645 /*! @{ */
4646 
4647 #define CAN_IMASK1_BUFLM_MASK                    (0xFFFFFFFFU)
4648 #define CAN_IMASK1_BUFLM_SHIFT                   (0U)
4649 /*! BUFLM
4650  *  0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
4651  *  0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
4652  */
4653 #define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4654 /*! @} */
4655 
4656 /*! @name IFLAG2 - Interrupt Flags 2 Register */
4657 /*! @{ */
4658 
4659 #define CAN_IFLAG2_BUFHI_MASK                    (0xFFFFFFFFU)
4660 #define CAN_IFLAG2_BUFHI_SHIFT                   (0U)
4661 /*! BUFHI
4662  *  0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
4663  *  0b00000000000000000000000000000000..No such occurrence
4664  */
4665 #define CAN_IFLAG2_BUFHI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
4666 /*! @} */
4667 
4668 /*! @name IFLAG1 - Interrupt Flags 1 Register */
4669 /*! @{ */
4670 
4671 #define CAN_IFLAG1_BUF4TO0I_MASK                 (0x1FU)
4672 #define CAN_IFLAG1_BUF4TO0I_SHIFT                (0U)
4673 /*! BUF4TO0I
4674  *  0b00001..Corresponding MB completed transmission/reception
4675  *  0b00000..No such occurrence
4676  */
4677 #define CAN_IFLAG1_BUF4TO0I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
4678 
4679 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
4680 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
4681 /*! BUF5I
4682  *  0b1..MB5 completed transmission/reception or frames available in the FIFO
4683  *  0b0..No such occurrence
4684  */
4685 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4686 
4687 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
4688 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
4689 /*! BUF6I
4690  *  0b1..MB6 completed transmission/reception or FIFO almost full
4691  *  0b0..No such occurrence
4692  */
4693 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4694 
4695 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
4696 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
4697 /*! BUF7I
4698  *  0b1..MB7 completed transmission/reception or FIFO overflow
4699  *  0b0..No such occurrence
4700  */
4701 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4702 
4703 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
4704 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
4705 /*! BUF31TO8I
4706  *  0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
4707  *  0b000000000000000000000000..No such occurrence
4708  */
4709 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4710 /*! @} */
4711 
4712 /*! @name CTRL2 - Control 2 Register */
4713 /*! @{ */
4714 
4715 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
4716 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
4717 /*! EACEN
4718  *  0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
4719  *       the incoming frame. Mask bits do apply.
4720  *  0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4721  */
4722 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4723 
4724 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
4725 #define CAN_CTRL2_RRS_SHIFT                      (17U)
4726 /*! RRS
4727  *  0b1..Remote Request Frame is stored
4728  *  0b0..Remote Response Frame is generated
4729  */
4730 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4731 
4732 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
4733 #define CAN_CTRL2_MRP_SHIFT                      (18U)
4734 /*! MRP
4735  *  0b1..Matching starts from Mailboxes and continues on Rx FIFO
4736  *  0b0..Matching starts from Rx FIFO and continues on Mailboxes
4737  */
4738 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4739 
4740 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
4741 #define CAN_CTRL2_TASD_SHIFT                     (19U)
4742 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4743 
4744 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
4745 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
4746 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4747 
4748 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
4749 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
4750 /*! WRMFRZ
4751  *  0b1..Enable unrestricted write access to FlexCAN memory
4752  *  0b0..Keep the write access restricted in some regions of FlexCAN memory
4753  */
4754 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4755 /*! @} */
4756 
4757 /*! @name ESR2 - Error and Status 2 Register */
4758 /*! @{ */
4759 
4760 #define CAN_ESR2_IMB_MASK                        (0x2000U)
4761 #define CAN_ESR2_IMB_SHIFT                       (13U)
4762 /*! IMB
4763  *  0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
4764  *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
4765  */
4766 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4767 
4768 #define CAN_ESR2_VPS_MASK                        (0x4000U)
4769 #define CAN_ESR2_VPS_SHIFT                       (14U)
4770 /*! VPS
4771  *  0b1..Contents of IMB and LPTM are valid
4772  *  0b0..Contents of IMB and LPTM are invalid
4773  */
4774 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4775 
4776 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
4777 #define CAN_ESR2_LPTM_SHIFT                      (16U)
4778 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4779 /*! @} */
4780 
4781 /*! @name CRCR - CRC Register */
4782 /*! @{ */
4783 
4784 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
4785 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
4786 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4787 
4788 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
4789 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
4790 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4791 /*! @} */
4792 
4793 /*! @name RXFGMASK - Rx FIFO Global Mask Register */
4794 /*! @{ */
4795 
4796 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
4797 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
4798 /*! FGM
4799  *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4800  *  0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
4801  */
4802 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4803 /*! @} */
4804 
4805 /*! @name RXFIR - Rx FIFO Information Register */
4806 /*! @{ */
4807 
4808 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
4809 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
4810 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4811 /*! @} */
4812 
4813 /*! @name DBG1 - Debug 1 register */
4814 /*! @{ */
4815 
4816 #define CAN_DBG1_CFSM_MASK                       (0x3FU)
4817 #define CAN_DBG1_CFSM_SHIFT                      (0U)
4818 /*! CFSM - CAN Finite State Machine
4819  */
4820 #define CAN_DBG1_CFSM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
4821 
4822 #define CAN_DBG1_CBN_MASK                        (0x1F000000U)
4823 #define CAN_DBG1_CBN_SHIFT                       (24U)
4824 /*! CBN - CAN Bit Number
4825  */
4826 #define CAN_DBG1_CBN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
4827 /*! @} */
4828 
4829 /*! @name DBG2 - Debug 2 register */
4830 /*! @{ */
4831 
4832 #define CAN_DBG2_RMP_MASK                        (0x7FU)
4833 #define CAN_DBG2_RMP_SHIFT                       (0U)
4834 /*! RMP - Rx Matching Pointer
4835  */
4836 #define CAN_DBG2_RMP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
4837 
4838 #define CAN_DBG2_MPP_MASK                        (0x80U)
4839 #define CAN_DBG2_MPP_SHIFT                       (7U)
4840 /*! MPP - Matching Process in Progress
4841  *  0b0..No matching process ongoing.
4842  *  0b1..Matching process is in progress.
4843  */
4844 #define CAN_DBG2_MPP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
4845 
4846 #define CAN_DBG2_TAP_MASK                        (0x7F00U)
4847 #define CAN_DBG2_TAP_SHIFT                       (8U)
4848 /*! TAP - Tx Arbitration Pointer
4849  */
4850 #define CAN_DBG2_TAP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
4851 
4852 #define CAN_DBG2_APP_MASK                        (0x8000U)
4853 #define CAN_DBG2_APP_SHIFT                       (15U)
4854 /*! APP - Arbitration Process in Progress
4855  *  0b0..No matching process ongoing.
4856  *  0b1..Matching process is in progress.
4857  */
4858 #define CAN_DBG2_APP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
4859 /*! @} */
4860 
4861 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
4862 /*! @{ */
4863 
4864 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
4865 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
4866 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
4867  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
4868  *    appears on the CAN bus.
4869  */
4870 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4871 
4872 #define CAN_CS_DLC_MASK                          (0xF0000U)
4873 #define CAN_CS_DLC_SHIFT                         (16U)
4874 /*! DLC - Length of the data to be stored/transmitted.
4875  */
4876 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4877 
4878 #define CAN_CS_RTR_MASK                          (0x100000U)
4879 #define CAN_CS_RTR_SHIFT                         (20U)
4880 /*! RTR - Remote Transmission Request. One/zero for remote/data frame.
4881  */
4882 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4883 
4884 #define CAN_CS_IDE_MASK                          (0x200000U)
4885 #define CAN_CS_IDE_SHIFT                         (21U)
4886 /*! IDE - ID Extended. One/zero for extended/standard format frame.
4887  */
4888 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4889 
4890 #define CAN_CS_SRR_MASK                          (0x400000U)
4891 #define CAN_CS_SRR_SHIFT                         (22U)
4892 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
4893  */
4894 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4895 
4896 #define CAN_CS_CODE_MASK                         (0xF000000U)
4897 #define CAN_CS_CODE_SHIFT                        (24U)
4898 /*! CODE - Reserved
4899  */
4900 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4901 /*! @} */
4902 
4903 /* The count of CAN_CS */
4904 #define CAN_CS_COUNT                             (64U)
4905 
4906 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
4907 /*! @{ */
4908 
4909 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
4910 #define CAN_ID_EXT_SHIFT                         (0U)
4911 /*! EXT - Contains extended (LOW word) identifier of message buffer.
4912  */
4913 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4914 
4915 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
4916 #define CAN_ID_STD_SHIFT                         (18U)
4917 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
4918  */
4919 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4920 
4921 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
4922 #define CAN_ID_PRIO_SHIFT                        (29U)
4923 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
4924  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
4925  *    ID to define the transmission priority.
4926  */
4927 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4928 /*! @} */
4929 
4930 /* The count of CAN_ID */
4931 #define CAN_ID_COUNT                             (64U)
4932 
4933 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
4934 /*! @{ */
4935 
4936 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
4937 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
4938 /*! DATA_BYTE_3 - Data byte 3 of Rx/Tx frame.
4939  */
4940 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4941 
4942 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
4943 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
4944 /*! DATA_BYTE_2 - Data byte 2 of Rx/Tx frame.
4945  */
4946 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4947 
4948 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
4949 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
4950 /*! DATA_BYTE_1 - Data byte 1 of Rx/Tx frame.
4951  */
4952 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4953 
4954 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
4955 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
4956 /*! DATA_BYTE_0 - Data byte 0 of Rx/Tx frame.
4957  */
4958 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4959 /*! @} */
4960 
4961 /* The count of CAN_WORD0 */
4962 #define CAN_WORD0_COUNT                          (64U)
4963 
4964 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
4965 /*! @{ */
4966 
4967 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
4968 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
4969 /*! DATA_BYTE_7 - Data byte 7 of Rx/Tx frame.
4970  */
4971 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4972 
4973 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
4974 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
4975 /*! DATA_BYTE_6 - Data byte 6 of Rx/Tx frame.
4976  */
4977 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4978 
4979 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
4980 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
4981 /*! DATA_BYTE_5 - Data byte 5 of Rx/Tx frame.
4982  */
4983 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4984 
4985 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
4986 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
4987 /*! DATA_BYTE_4 - Data byte 4 of Rx/Tx frame.
4988  */
4989 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4990 /*! @} */
4991 
4992 /* The count of CAN_WORD1 */
4993 #define CAN_WORD1_COUNT                          (64U)
4994 
4995 /*! @name RXIMR - Rx Individual Mask Registers */
4996 /*! @{ */
4997 
4998 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
4999 #define CAN_RXIMR_MI_SHIFT                       (0U)
5000 /*! MI
5001  *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
5002  *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
5003  */
5004 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5005 /*! @} */
5006 
5007 /* The count of CAN_RXIMR */
5008 #define CAN_RXIMR_COUNT                          (64U)
5009 
5010 /*! @name GFWR - Glitch Filter Width Registers */
5011 /*! @{ */
5012 
5013 #define CAN_GFWR_GFWR_MASK                       (0xFFU)
5014 #define CAN_GFWR_GFWR_SHIFT                      (0U)
5015 #define CAN_GFWR_GFWR(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
5016 /*! @} */
5017 
5018 
5019 /*!
5020  * @}
5021  */ /* end of group CAN_Register_Masks */
5022 
5023 
5024 /* CAN - Peripheral instance base addresses */
5025 /** Peripheral CAN1 base address */
5026 #define CAN1_BASE                                (0x401D0000u)
5027 /** Peripheral CAN1 base pointer */
5028 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
5029 /** Peripheral CAN2 base address */
5030 #define CAN2_BASE                                (0x401D4000u)
5031 /** Peripheral CAN2 base pointer */
5032 #define CAN2                                     ((CAN_Type *)CAN2_BASE)
5033 /** Array initializer of CAN peripheral base addresses */
5034 #define CAN_BASE_ADDRS                           { 0u, CAN1_BASE, CAN2_BASE }
5035 /** Array initializer of CAN peripheral base pointers */
5036 #define CAN_BASE_PTRS                            { (CAN_Type *)0u, CAN1, CAN2 }
5037 /** Interrupt vectors for the CAN peripheral type */
5038 #define CAN_Rx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5039 #define CAN_Tx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5040 #define CAN_Wake_Up_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5041 #define CAN_Error_IRQS                           { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5042 #define CAN_Bus_Off_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5043 #define CAN_ORed_Message_buffer_IRQS             { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5044 /* Backward compatibility */
5045 #define CAN_ECR_TXERRCNT_MASK         CAN_ECR_TX_ERR_COUNTER_MASK
5046 #define CAN_ECR_TXERRCNT_SHIFT        CAN_ECR_TX_ERR_COUNTER_SHIFT
5047 #define CAN_ECR_TXERRCNT(x)           CAN_ECR_TX_ERR_COUNTER(x)
5048 #define CAN_ECR_RXERRCNT_MASK         CAN_ECR_RX_ERR_COUNTER_MASK
5049 #define CAN_ECR_RXERRCNT_SHIFT        CAN_ECR_RX_ERR_COUNTER_SHIFT
5050 #define CAN_ECR_RXERRCNT(x)           CAN_ECR_RX_ERR_COUNTER(x)
5051 
5052 
5053 /*!
5054  * @}
5055  */ /* end of group CAN_Peripheral_Access_Layer */
5056 
5057 
5058 /* ----------------------------------------------------------------------------
5059    -- CCM Peripheral Access Layer
5060    ---------------------------------------------------------------------------- */
5061 
5062 /*!
5063  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
5064  * @{
5065  */
5066 
5067 /** CCM - Register Layout Typedef */
5068 typedef struct {
5069   __IO uint32_t CCR;                               /**< CCM Control Register, offset: 0x0 */
5070        uint8_t RESERVED_0[4];
5071   __I  uint32_t CSR;                               /**< CCM Status Register, offset: 0x8 */
5072   __IO uint32_t CCSR;                              /**< CCM Clock Switcher Register, offset: 0xC */
5073   __IO uint32_t CACRR;                             /**< CCM Arm Clock Root Register, offset: 0x10 */
5074   __IO uint32_t CBCDR;                             /**< CCM Bus Clock Divider Register, offset: 0x14 */
5075   __IO uint32_t CBCMR;                             /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
5076   __IO uint32_t CSCMR1;                            /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
5077   __IO uint32_t CSCMR2;                            /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
5078   __IO uint32_t CSCDR1;                            /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
5079   __IO uint32_t CS1CDR;                            /**< CCM Clock Divider Register, offset: 0x28 */
5080   __IO uint32_t CS2CDR;                            /**< CCM Clock Divider Register, offset: 0x2C */
5081   __IO uint32_t CDCDR;                             /**< CCM D1 Clock Divider Register, offset: 0x30 */
5082        uint8_t RESERVED_1[4];
5083   __IO uint32_t CSCDR2;                            /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
5084   __IO uint32_t CSCDR3;                            /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
5085        uint8_t RESERVED_2[8];
5086   __I  uint32_t CDHIPR;                            /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
5087        uint8_t RESERVED_3[8];
5088   __IO uint32_t CLPCR;                             /**< CCM Low Power Control Register, offset: 0x54 */
5089   __IO uint32_t CISR;                              /**< CCM Interrupt Status Register, offset: 0x58 */
5090   __IO uint32_t CIMR;                              /**< CCM Interrupt Mask Register, offset: 0x5C */
5091   __IO uint32_t CCOSR;                             /**< CCM Clock Output Source Register, offset: 0x60 */
5092   __IO uint32_t CGPR;                              /**< CCM General Purpose Register, offset: 0x64 */
5093   __IO uint32_t CCGR0;                             /**< CCM Clock Gating Register 0, offset: 0x68 */
5094   __IO uint32_t CCGR1;                             /**< CCM Clock Gating Register 1, offset: 0x6C */
5095   __IO uint32_t CCGR2;                             /**< CCM Clock Gating Register 2, offset: 0x70 */
5096   __IO uint32_t CCGR3;                             /**< CCM Clock Gating Register 3, offset: 0x74 */
5097   __IO uint32_t CCGR4;                             /**< CCM Clock Gating Register 4, offset: 0x78 */
5098   __IO uint32_t CCGR5;                             /**< CCM Clock Gating Register 5, offset: 0x7C */
5099   __IO uint32_t CCGR6;                             /**< CCM Clock Gating Register 6, offset: 0x80 */
5100        uint8_t RESERVED_4[4];
5101   __IO uint32_t CMEOR;                             /**< CCM Module Enable Overide Register, offset: 0x88 */
5102 } CCM_Type;
5103 
5104 /* ----------------------------------------------------------------------------
5105    -- CCM Register Masks
5106    ---------------------------------------------------------------------------- */
5107 
5108 /*!
5109  * @addtogroup CCM_Register_Masks CCM Register Masks
5110  * @{
5111  */
5112 
5113 /*! @name CCR - CCM Control Register */
5114 /*! @{ */
5115 
5116 #define CCM_CCR_OSCNT_MASK                       (0xFFU)
5117 #define CCM_CCR_OSCNT_SHIFT                      (0U)
5118 /*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as
5119  *    counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time.
5120  *    Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from
5121  *    stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for
5122  *    the dpll_ip to use and only then the gate in dpll_ip can be opened.
5123  */
5124 #define CCM_CCR_OSCNT(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
5125 
5126 #define CCM_CCR_COSC_EN_MASK                     (0x1000U)
5127 #define CCM_CCR_COSC_EN_SHIFT                    (12U)
5128 /*! COSC_EN
5129  *  0b0..disable on chip oscillator
5130  *  0b1..enable on chip oscillator
5131  */
5132 #define CCM_CCR_COSC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
5133 
5134 #define CCM_CCR_REG_BYPASS_COUNT_MASK            (0x7E00000U)
5135 #define CCM_CCR_REG_BYPASS_COUNT_SHIFT           (21U)
5136 /*! REG_BYPASS_COUNT
5137  *  0b000000..no delay
5138  *  0b000001..1 CKIL clock period delay
5139  *  0b111111..63 CKIL clock periods delay
5140  */
5141 #define CCM_CCR_REG_BYPASS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
5142 
5143 #define CCM_CCR_RBC_EN_MASK                      (0x8000000U)
5144 #define CCM_CCR_RBC_EN_SHIFT                     (27U)
5145 /*! RBC_EN
5146  *  0b1..REG_BYPASS_COUNTER enabled.
5147  *  0b0..REG_BYPASS_COUNTER disabled
5148  */
5149 #define CCM_CCR_RBC_EN(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
5150 /*! @} */
5151 
5152 /*! @name CSR - CCM Status Register */
5153 /*! @{ */
5154 
5155 #define CCM_CSR_REF_EN_B_MASK                    (0x1U)
5156 #define CCM_CSR_REF_EN_B_SHIFT                   (0U)
5157 /*! REF_EN_B
5158  *  0b0..value of CCM_REF_EN_B is '0'
5159  *  0b1..value of CCM_REF_EN_B is '1'
5160  */
5161 #define CCM_CSR_REF_EN_B(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
5162 
5163 #define CCM_CSR_CAMP2_READY_MASK                 (0x8U)
5164 #define CCM_CSR_CAMP2_READY_SHIFT                (3U)
5165 /*! CAMP2_READY
5166  *  0b0..CAMP2 is not ready.
5167  *  0b1..CAMP2 is ready.
5168  */
5169 #define CCM_CSR_CAMP2_READY(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
5170 
5171 #define CCM_CSR_COSC_READY_MASK                  (0x20U)
5172 #define CCM_CSR_COSC_READY_SHIFT                 (5U)
5173 /*! COSC_READY
5174  *  0b0..on board oscillator is not ready.
5175  *  0b1..on board oscillator is ready.
5176  */
5177 #define CCM_CSR_COSC_READY(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
5178 /*! @} */
5179 
5180 /*! @name CCSR - CCM Clock Switcher Register */
5181 /*! @{ */
5182 
5183 #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK            (0x1U)
5184 #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT           (0U)
5185 /*! PLL3_SW_CLK_SEL
5186  *  0b0..pll3_main_clk
5187  *  0b1..pll3 bypass clock
5188  */
5189 #define CCM_CCSR_PLL3_SW_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
5190 /*! @} */
5191 
5192 /*! @name CACRR - CCM Arm Clock Root Register */
5193 /*! @{ */
5194 
5195 #define CCM_CACRR_ARM_PODF_MASK                  (0x7U)
5196 #define CCM_CACRR_ARM_PODF_SHIFT                 (0U)
5197 /*! ARM_PODF
5198  *  0b000..divide by 1
5199  *  0b001..divide by 2
5200  *  0b010..divide by 3
5201  *  0b011..divide by 4
5202  *  0b100..divide by 5
5203  *  0b101..divide by 6
5204  *  0b110..divide by 7
5205  *  0b111..divide by 8
5206  */
5207 #define CCM_CACRR_ARM_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
5208 /*! @} */
5209 
5210 /*! @name CBCDR - CCM Bus Clock Divider Register */
5211 /*! @{ */
5212 
5213 #define CCM_CBCDR_SEMC_CLK_SEL_MASK              (0x40U)
5214 #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT             (6U)
5215 /*! SEMC_CLK_SEL
5216  *  0b0..Periph_clk output will be used as SEMC clock root
5217  *  0b1..SEMC alternative clock will be used as SEMC clock root
5218  */
5219 #define CCM_CBCDR_SEMC_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
5220 
5221 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK          (0x80U)
5222 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT         (7U)
5223 /*! SEMC_ALT_CLK_SEL
5224  *  0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
5225  *  0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
5226  */
5227 #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
5228 
5229 #define CCM_CBCDR_IPG_PODF_MASK                  (0x300U)
5230 #define CCM_CBCDR_IPG_PODF_SHIFT                 (8U)
5231 /*! IPG_PODF
5232  *  0b00..divide by 1
5233  *  0b01..divide by 2
5234  *  0b10..divide by 3
5235  *  0b11..divide by 4
5236  */
5237 #define CCM_CBCDR_IPG_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
5238 
5239 #define CCM_CBCDR_AHB_PODF_MASK                  (0x1C00U)
5240 #define CCM_CBCDR_AHB_PODF_SHIFT                 (10U)
5241 /*! AHB_PODF
5242  *  0b000..divide by 1
5243  *  0b001..divide by 2
5244  *  0b010..divide by 3
5245  *  0b011..divide by 4
5246  *  0b100..divide by 5
5247  *  0b101..divide by 6
5248  *  0b110..divide by 7
5249  *  0b111..divide by 8
5250  */
5251 #define CCM_CBCDR_AHB_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
5252 
5253 #define CCM_CBCDR_SEMC_PODF_MASK                 (0x70000U)
5254 #define CCM_CBCDR_SEMC_PODF_SHIFT                (16U)
5255 /*! SEMC_PODF
5256  *  0b000..divide by 1
5257  *  0b001..divide by 2
5258  *  0b010..divide by 3
5259  *  0b011..divide by 4
5260  *  0b100..divide by 5
5261  *  0b101..divide by 6
5262  *  0b110..divide by 7
5263  *  0b111..divide by 8
5264  */
5265 #define CCM_CBCDR_SEMC_PODF(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
5266 
5267 #define CCM_CBCDR_PERIPH_CLK_SEL_MASK            (0x2000000U)
5268 #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT           (25U)
5269 /*! PERIPH_CLK_SEL
5270  *  0b0..derive clock from pre_periph_clk_sel
5271  *  0b1..derive clock from periph_clk2_clk_divided
5272  */
5273 #define CCM_CBCDR_PERIPH_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
5274 
5275 #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK          (0x38000000U)
5276 #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT         (27U)
5277 /*! PERIPH_CLK2_PODF
5278  *  0b000..divide by 1
5279  *  0b001..divide by 2
5280  *  0b010..divide by 3
5281  *  0b011..divide by 4
5282  *  0b100..divide by 5
5283  *  0b101..divide by 6
5284  *  0b110..divide by 7
5285  *  0b111..divide by 8
5286  */
5287 #define CCM_CBCDR_PERIPH_CLK2_PODF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
5288 /*! @} */
5289 
5290 /*! @name CBCMR - CCM Bus Clock Multiplexer Register */
5291 /*! @{ */
5292 
5293 #define CCM_CBCMR_LPSPI_CLK_SEL_MASK             (0x30U)
5294 #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT            (4U)
5295 /*! LPSPI_CLK_SEL
5296  *  0b00..derive clock from PLL3 PFD1 clk
5297  *  0b01..derive clock from PLL3 PFD0
5298  *  0b10..derive clock from PLL2
5299  *  0b11..derive clock from PLL2 PFD2
5300  */
5301 #define CCM_CBCMR_LPSPI_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
5302 
5303 #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK           (0x3000U)
5304 #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT          (12U)
5305 /*! PERIPH_CLK2_SEL
5306  *  0b00..derive clock from pll3_sw_clk
5307  *  0b01..derive clock from osc_clk (pll1_ref_clk)
5308  *  0b10..derive clock from pll2_bypass_clk
5309  *  0b11..reserved
5310  */
5311 #define CCM_CBCMR_PERIPH_CLK2_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
5312 
5313 #define CCM_CBCMR_TRACE_CLK_SEL_MASK             (0xC000U)
5314 #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT            (14U)
5315 /*! TRACE_CLK_SEL
5316  *  0b00..derive clock from PLL2
5317  *  0b01..derive clock from PLL2 PFD2
5318  *  0b10..derive clock from PLL2 PFD0
5319  *  0b11..derive clock from PLL2 PFD1
5320  */
5321 #define CCM_CBCMR_TRACE_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
5322 
5323 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK        (0xC0000U)
5324 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT       (18U)
5325 /*! PRE_PERIPH_CLK_SEL
5326  *  0b00..derive clock from PLL2
5327  *  0b01..derive clock from PLL2 PFD2
5328  *  0b10..derive clock from PLL2 PFD0
5329  *  0b11..derive clock from divided PLL1
5330  */
5331 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
5332 
5333 #define CCM_CBCMR_LCDIF_PODF_MASK                (0x3800000U)
5334 #define CCM_CBCMR_LCDIF_PODF_SHIFT               (23U)
5335 /*! LCDIF_PODF
5336  *  0b000..divide by 1
5337  *  0b001..divide by 2
5338  *  0b010..divide by 3
5339  *  0b011..divide by 4
5340  *  0b100..divide by 5
5341  *  0b101..divide by 6
5342  *  0b110..divide by 7
5343  *  0b111..divide by 8
5344  */
5345 #define CCM_CBCMR_LCDIF_PODF(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
5346 
5347 #define CCM_CBCMR_LPSPI_PODF_MASK                (0x1C000000U)
5348 #define CCM_CBCMR_LPSPI_PODF_SHIFT               (26U)
5349 /*! LPSPI_PODF
5350  *  0b000..divide by 1
5351  *  0b001..divide by 2
5352  *  0b010..divide by 3
5353  *  0b011..divide by 4
5354  *  0b100..divide by 5
5355  *  0b101..divide by 6
5356  *  0b110..divide by 7
5357  *  0b111..divide by 8
5358  */
5359 #define CCM_CBCMR_LPSPI_PODF(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
5360 /*! @} */
5361 
5362 /*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
5363 /*! @{ */
5364 
5365 #define CCM_CSCMR1_PERCLK_PODF_MASK              (0x3FU)
5366 #define CCM_CSCMR1_PERCLK_PODF_SHIFT             (0U)
5367 /*! PERCLK_PODF - Divider for perclk podf.
5368  *  0b000000..Divide by 1
5369  *  0b000001..Divide by 2
5370  *  0b000010..Divide by 3
5371  *  0b000011..Divide by 4
5372  *  0b000100..Divide by 5
5373  *  0b000101..Divide by 6
5374  *  0b000110..Divide by 7
5375  *  0b000111..Divide by 8
5376  *  0b001000..Divide by 9
5377  *  0b001001..Divide by 10
5378  *  0b001010..Divide by 11
5379  *  0b001011..Divide by 12
5380  *  0b001100..Divide by 13
5381  *  0b001101..Divide by 14
5382  *  0b001110..Divide by 15
5383  *  0b001111..Divide by 16
5384  *  0b010000..Divide by 17
5385  *  0b010001..Divide by 18
5386  *  0b010010..Divide by 19
5387  *  0b010011..Divide by 20
5388  *  0b010100..Divide by 21
5389  *  0b010101..Divide by 22
5390  *  0b010110..Divide by 23
5391  *  0b010111..Divide by 24
5392  *  0b011000..Divide by 25
5393  *  0b011001..Divide by 26
5394  *  0b011010..Divide by 27
5395  *  0b011011..Divide by 28
5396  *  0b011100..Divide by 29
5397  *  0b011101..Divide by 30
5398  *  0b011110..Divide by 31
5399  *  0b011111..Divide by 32
5400  *  0b100000..Divide by 33
5401  *  0b100001..Divide by 34
5402  *  0b100010..Divide by 35
5403  *  0b100011..Divide by 36
5404  *  0b100100..Divide by 37
5405  *  0b100101..Divide by 38
5406  *  0b100110..Divide by 39
5407  *  0b100111..Divide by 40
5408  *  0b101000..Divide by 41
5409  *  0b101001..Divide by 42
5410  *  0b101010..Divide by 43
5411  *  0b101011..Divide by 44
5412  *  0b101100..Divide by 45
5413  *  0b101101..Divide by 46
5414  *  0b101110..Divide by 47
5415  *  0b101111..Divide by 48
5416  *  0b110000..Divide by 49
5417  *  0b110001..Divide by 50
5418  *  0b110010..Divide by 51
5419  *  0b110011..Divide by 52
5420  *  0b110100..Divide by 53
5421  *  0b110101..Divide by 54
5422  *  0b110110..Divide by 55
5423  *  0b110111..Divide by 56
5424  *  0b111000..Divide by 57
5425  *  0b111001..Divide by 58
5426  *  0b111010..Divide by 59
5427  *  0b111011..Divide by 60
5428  *  0b111100..Divide by 61
5429  *  0b111101..Divide by 62
5430  *  0b111110..Divide by 63
5431  *  0b111111..Divide by 64
5432  */
5433 #define CCM_CSCMR1_PERCLK_PODF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
5434 
5435 #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK           (0x40U)
5436 #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT          (6U)
5437 /*! PERCLK_CLK_SEL
5438  *  0b0..derive clock from ipg clk root
5439  *  0b1..derive clock from osc_clk
5440  */
5441 #define CCM_CSCMR1_PERCLK_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
5442 
5443 #define CCM_CSCMR1_SAI1_CLK_SEL_MASK             (0xC00U)
5444 #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT            (10U)
5445 /*! SAI1_CLK_SEL
5446  *  0b00..derive clock from PLL3 PFD2
5447  *  0b01..derive clock from PLL5
5448  *  0b10..derive clock from PLL4
5449  *  0b11..Reserved
5450  */
5451 #define CCM_CSCMR1_SAI1_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
5452 
5453 #define CCM_CSCMR1_SAI2_CLK_SEL_MASK             (0x3000U)
5454 #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT            (12U)
5455 /*! SAI2_CLK_SEL
5456  *  0b00..derive clock from PLL3 PFD2
5457  *  0b01..derive clock from PLL5
5458  *  0b10..derive clock from PLL4
5459  *  0b11..Reserved
5460  */
5461 #define CCM_CSCMR1_SAI2_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
5462 
5463 #define CCM_CSCMR1_SAI3_CLK_SEL_MASK             (0xC000U)
5464 #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT            (14U)
5465 /*! SAI3_CLK_SEL
5466  *  0b00..derive clock from PLL3 PFD2
5467  *  0b01..derive clock from PLL5
5468  *  0b10..derive clock from PLL4
5469  *  0b11..Reserved
5470  */
5471 #define CCM_CSCMR1_SAI3_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
5472 
5473 #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK           (0x10000U)
5474 #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT          (16U)
5475 /*! USDHC1_CLK_SEL
5476  *  0b0..derive clock from PLL2 PFD2
5477  *  0b1..derive clock from PLL2 PFD0
5478  */
5479 #define CCM_CSCMR1_USDHC1_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
5480 
5481 #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK           (0x20000U)
5482 #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT          (17U)
5483 /*! USDHC2_CLK_SEL
5484  *  0b0..derive clock from PLL2 PFD2
5485  *  0b1..derive clock from PLL2 PFD0
5486  */
5487 #define CCM_CSCMR1_USDHC2_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
5488 
5489 #define CCM_CSCMR1_FLEXSPI_PODF_MASK             (0x3800000U)
5490 #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT            (23U)
5491 /*! FLEXSPI_PODF
5492  *  0b000..divide by 1
5493  *  0b001..divide by 2
5494  *  0b010..divide by 3
5495  *  0b011..divide by 4
5496  *  0b100..divide by 5
5497  *  0b101..divide by 6
5498  *  0b110..divide by 7
5499  *  0b111..divide by 8
5500  */
5501 #define CCM_CSCMR1_FLEXSPI_PODF(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
5502 
5503 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK          (0x60000000U)
5504 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT         (29U)
5505 /*! FLEXSPI_CLK_SEL
5506  *  0b00..derive clock from semc_clk_root_pre
5507  *  0b01..derive clock from pll3_sw_clk
5508  *  0b10..derive clock from PLL2 PFD2
5509  *  0b11..derive clock from PLL3 PFD0
5510  */
5511 #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
5512 /*! @} */
5513 
5514 /*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
5515 /*! @{ */
5516 
5517 #define CCM_CSCMR2_CAN_CLK_PODF_MASK             (0xFCU)
5518 #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT            (2U)
5519 /*! CAN_CLK_PODF - Divider for CAN clock podf.
5520  *  0b000000..Divide by 1
5521  *  0b000001..Divide by 2
5522  *  0b000010..Divide by 3
5523  *  0b000011..Divide by 4
5524  *  0b000100..Divide by 5
5525  *  0b000101..Divide by 6
5526  *  0b000110..Divide by 7
5527  *  0b000111..Divide by 8
5528  *  0b001000..Divide by 9
5529  *  0b001001..Divide by 10
5530  *  0b001010..Divide by 11
5531  *  0b001011..Divide by 12
5532  *  0b001100..Divide by 13
5533  *  0b001101..Divide by 14
5534  *  0b001110..Divide by 15
5535  *  0b001111..Divide by 16
5536  *  0b010000..Divide by 17
5537  *  0b010001..Divide by 18
5538  *  0b010010..Divide by 19
5539  *  0b010011..Divide by 20
5540  *  0b010100..Divide by 21
5541  *  0b010101..Divide by 22
5542  *  0b010110..Divide by 23
5543  *  0b010111..Divide by 24
5544  *  0b011000..Divide by 25
5545  *  0b011001..Divide by 26
5546  *  0b011010..Divide by 27
5547  *  0b011011..Divide by 28
5548  *  0b011100..Divide by 29
5549  *  0b011101..Divide by 30
5550  *  0b011110..Divide by 31
5551  *  0b011111..Divide by 32
5552  *  0b100000..Divide by 33
5553  *  0b100001..Divide by 34
5554  *  0b100010..Divide by 35
5555  *  0b100011..Divide by 36
5556  *  0b100100..Divide by 37
5557  *  0b100101..Divide by 38
5558  *  0b100110..Divide by 39
5559  *  0b100111..Divide by 40
5560  *  0b101000..Divide by 41
5561  *  0b101001..Divide by 42
5562  *  0b101010..Divide by 43
5563  *  0b101011..Divide by 44
5564  *  0b101100..Divide by 45
5565  *  0b101101..Divide by 46
5566  *  0b101110..Divide by 47
5567  *  0b101111..Divide by 48
5568  *  0b110000..Divide by 49
5569  *  0b110001..Divide by 50
5570  *  0b110010..Divide by 51
5571  *  0b110011..Divide by 52
5572  *  0b110100..Divide by 53
5573  *  0b110101..Divide by 54
5574  *  0b110110..Divide by 55
5575  *  0b110111..Divide by 56
5576  *  0b111000..Divide by 57
5577  *  0b111001..Divide by 58
5578  *  0b111010..Divide by 59
5579  *  0b111011..Divide by 60
5580  *  0b111100..Divide by 61
5581  *  0b111101..Divide by 62
5582  *  0b111110..Divide by 63
5583  *  0b111111..Divide by 64
5584  */
5585 #define CCM_CSCMR2_CAN_CLK_PODF(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
5586 
5587 #define CCM_CSCMR2_CAN_CLK_SEL_MASK              (0x300U)
5588 #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT             (8U)
5589 /*! CAN_CLK_SEL
5590  *  0b00..derive clock from pll3_sw_clk divided clock (60M)
5591  *  0b01..derive clock from osc_clk (24M)
5592  *  0b10..derive clock from pll3_sw_clk divided clock (80M)
5593  *  0b11..Disable FlexCAN clock
5594  */
5595 #define CCM_CSCMR2_CAN_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
5596 
5597 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK          (0x180000U)
5598 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT         (19U)
5599 /*! FLEXIO2_CLK_SEL
5600  *  0b00..derive clock from PLL4 divided clock
5601  *  0b01..derive clock from PLL3 PFD2 clock
5602  *  0b10..derive clock from PLL5 clock
5603  *  0b11..derive clock from pll3_sw_clk
5604  */
5605 #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
5606 /*! @} */
5607 
5608 /*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
5609 /*! @{ */
5610 
5611 #define CCM_CSCDR1_UART_CLK_PODF_MASK            (0x3FU)
5612 #define CCM_CSCDR1_UART_CLK_PODF_SHIFT           (0U)
5613 /*! UART_CLK_PODF - Divider for uart clock podf.
5614  *  0b000000..Divide by 1
5615  *  0b000001..Divide by 2
5616  *  0b000010..Divide by 3
5617  *  0b000011..Divide by 4
5618  *  0b000100..Divide by 5
5619  *  0b000101..Divide by 6
5620  *  0b000110..Divide by 7
5621  *  0b000111..Divide by 8
5622  *  0b001000..Divide by 9
5623  *  0b001001..Divide by 10
5624  *  0b001010..Divide by 11
5625  *  0b001011..Divide by 12
5626  *  0b001100..Divide by 13
5627  *  0b001101..Divide by 14
5628  *  0b001110..Divide by 15
5629  *  0b001111..Divide by 16
5630  *  0b010000..Divide by 17
5631  *  0b010001..Divide by 18
5632  *  0b010010..Divide by 19
5633  *  0b010011..Divide by 20
5634  *  0b010100..Divide by 21
5635  *  0b010101..Divide by 22
5636  *  0b010110..Divide by 23
5637  *  0b010111..Divide by 24
5638  *  0b011000..Divide by 25
5639  *  0b011001..Divide by 26
5640  *  0b011010..Divide by 27
5641  *  0b011011..Divide by 28
5642  *  0b011100..Divide by 29
5643  *  0b011101..Divide by 30
5644  *  0b011110..Divide by 31
5645  *  0b011111..Divide by 32
5646  *  0b100000..Divide by 33
5647  *  0b100001..Divide by 34
5648  *  0b100010..Divide by 35
5649  *  0b100011..Divide by 36
5650  *  0b100100..Divide by 37
5651  *  0b100101..Divide by 38
5652  *  0b100110..Divide by 39
5653  *  0b100111..Divide by 40
5654  *  0b101000..Divide by 41
5655  *  0b101001..Divide by 42
5656  *  0b101010..Divide by 43
5657  *  0b101011..Divide by 44
5658  *  0b101100..Divide by 45
5659  *  0b101101..Divide by 46
5660  *  0b101110..Divide by 47
5661  *  0b101111..Divide by 48
5662  *  0b110000..Divide by 49
5663  *  0b110001..Divide by 50
5664  *  0b110010..Divide by 51
5665  *  0b110011..Divide by 52
5666  *  0b110100..Divide by 53
5667  *  0b110101..Divide by 54
5668  *  0b110110..Divide by 55
5669  *  0b110111..Divide by 56
5670  *  0b111000..Divide by 57
5671  *  0b111001..Divide by 58
5672  *  0b111010..Divide by 59
5673  *  0b111011..Divide by 60
5674  *  0b111100..Divide by 61
5675  *  0b111101..Divide by 62
5676  *  0b111110..Divide by 63
5677  *  0b111111..Divide by 64
5678  */
5679 #define CCM_CSCDR1_UART_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
5680 
5681 #define CCM_CSCDR1_UART_CLK_SEL_MASK             (0x40U)
5682 #define CCM_CSCDR1_UART_CLK_SEL_SHIFT            (6U)
5683 /*! UART_CLK_SEL
5684  *  0b0..derive clock from pll3_80m
5685  *  0b1..derive clock from osc_clk
5686  */
5687 #define CCM_CSCDR1_UART_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
5688 
5689 #define CCM_CSCDR1_USDHC1_PODF_MASK              (0x3800U)
5690 #define CCM_CSCDR1_USDHC1_PODF_SHIFT             (11U)
5691 /*! USDHC1_PODF
5692  *  0b000..divide by 1
5693  *  0b001..divide by 2
5694  *  0b010..divide by 3
5695  *  0b011..divide by 4
5696  *  0b100..divide by 5
5697  *  0b101..divide by 6
5698  *  0b110..divide by 7
5699  *  0b111..divide by 8
5700  */
5701 #define CCM_CSCDR1_USDHC1_PODF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
5702 
5703 #define CCM_CSCDR1_USDHC2_PODF_MASK              (0x70000U)
5704 #define CCM_CSCDR1_USDHC2_PODF_SHIFT             (16U)
5705 /*! USDHC2_PODF
5706  *  0b000..divide by 1
5707  *  0b001..divide by 2
5708  *  0b010..divide by 3
5709  *  0b011..divide by 4
5710  *  0b100..divide by 5
5711  *  0b101..divide by 6
5712  *  0b110..divide by 7
5713  *  0b111..divide by 8
5714  */
5715 #define CCM_CSCDR1_USDHC2_PODF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
5716 
5717 #define CCM_CSCDR1_TRACE_PODF_MASK               (0x6000000U)
5718 #define CCM_CSCDR1_TRACE_PODF_SHIFT              (25U)
5719 /*! TRACE_PODF
5720  *  0b00..divide by 1
5721  *  0b01..divide by 2
5722  *  0b10..divide by 3
5723  *  0b11..divide by 4
5724  */
5725 #define CCM_CSCDR1_TRACE_PODF(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
5726 /*! @} */
5727 
5728 /*! @name CS1CDR - CCM Clock Divider Register */
5729 /*! @{ */
5730 
5731 #define CCM_CS1CDR_SAI1_CLK_PODF_MASK            (0x3FU)
5732 #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT           (0U)
5733 /*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
5734  *    than 300Mhz, the predivider can be used to achieve this.
5735  *  0b000000..Divide by 1
5736  *  0b000001..Divide by 2
5737  *  0b000010..Divide by 3
5738  *  0b000011..Divide by 4
5739  *  0b000100..Divide by 5
5740  *  0b000101..Divide by 6
5741  *  0b000110..Divide by 7
5742  *  0b000111..Divide by 8
5743  *  0b001000..Divide by 9
5744  *  0b001001..Divide by 10
5745  *  0b001010..Divide by 11
5746  *  0b001011..Divide by 12
5747  *  0b001100..Divide by 13
5748  *  0b001101..Divide by 14
5749  *  0b001110..Divide by 15
5750  *  0b001111..Divide by 16
5751  *  0b010000..Divide by 17
5752  *  0b010001..Divide by 18
5753  *  0b010010..Divide by 19
5754  *  0b010011..Divide by 20
5755  *  0b010100..Divide by 21
5756  *  0b010101..Divide by 22
5757  *  0b010110..Divide by 23
5758  *  0b010111..Divide by 24
5759  *  0b011000..Divide by 25
5760  *  0b011001..Divide by 26
5761  *  0b011010..Divide by 27
5762  *  0b011011..Divide by 28
5763  *  0b011100..Divide by 29
5764  *  0b011101..Divide by 30
5765  *  0b011110..Divide by 31
5766  *  0b011111..Divide by 32
5767  *  0b100000..Divide by 33
5768  *  0b100001..Divide by 34
5769  *  0b100010..Divide by 35
5770  *  0b100011..Divide by 36
5771  *  0b100100..Divide by 37
5772  *  0b100101..Divide by 38
5773  *  0b100110..Divide by 39
5774  *  0b100111..Divide by 40
5775  *  0b101000..Divide by 41
5776  *  0b101001..Divide by 42
5777  *  0b101010..Divide by 43
5778  *  0b101011..Divide by 44
5779  *  0b101100..Divide by 45
5780  *  0b101101..Divide by 46
5781  *  0b101110..Divide by 47
5782  *  0b101111..Divide by 48
5783  *  0b110000..Divide by 49
5784  *  0b110001..Divide by 50
5785  *  0b110010..Divide by 51
5786  *  0b110011..Divide by 52
5787  *  0b110100..Divide by 53
5788  *  0b110101..Divide by 54
5789  *  0b110110..Divide by 55
5790  *  0b110111..Divide by 56
5791  *  0b111000..Divide by 57
5792  *  0b111001..Divide by 58
5793  *  0b111010..Divide by 59
5794  *  0b111011..Divide by 60
5795  *  0b111100..Divide by 61
5796  *  0b111101..Divide by 62
5797  *  0b111110..Divide by 63
5798  *  0b111111..Divide by 64
5799  */
5800 #define CCM_CS1CDR_SAI1_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
5801 
5802 #define CCM_CS1CDR_SAI1_CLK_PRED_MASK            (0x1C0U)
5803 #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT           (6U)
5804 /*! SAI1_CLK_PRED
5805  *  0b000..divide by 1
5806  *  0b001..divide by 2
5807  *  0b010..divide by 3
5808  *  0b011..divide by 4
5809  *  0b100..divide by 5
5810  *  0b101..divide by 6
5811  *  0b110..divide by 7
5812  *  0b111..divide by 8
5813  */
5814 #define CCM_CS1CDR_SAI1_CLK_PRED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
5815 
5816 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK         (0xE00U)
5817 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT        (9U)
5818 /*! FLEXIO2_CLK_PRED
5819  *  0b000..divide by 1
5820  *  0b001..divide by 2
5821  *  0b010..divide by 3
5822  *  0b011..divide by 4
5823  *  0b100..divide by 5
5824  *  0b101..divide by 6
5825  *  0b110..divide by 7
5826  *  0b111..divide by 8
5827  */
5828 #define CCM_CS1CDR_FLEXIO2_CLK_PRED(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
5829 
5830 #define CCM_CS1CDR_SAI3_CLK_PODF_MASK            (0x3F0000U)
5831 #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT           (16U)
5832 /*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
5833  *    than 300Mhz, the predivider can be used to achieve this.
5834  *  0b000000..Divide by 1
5835  *  0b000001..Divide by 2
5836  *  0b000010..Divide by 3
5837  *  0b000011..Divide by 4
5838  *  0b000100..Divide by 5
5839  *  0b000101..Divide by 6
5840  *  0b000110..Divide by 7
5841  *  0b000111..Divide by 8
5842  *  0b001000..Divide by 9
5843  *  0b001001..Divide by 10
5844  *  0b001010..Divide by 11
5845  *  0b001011..Divide by 12
5846  *  0b001100..Divide by 13
5847  *  0b001101..Divide by 14
5848  *  0b001110..Divide by 15
5849  *  0b001111..Divide by 16
5850  *  0b010000..Divide by 17
5851  *  0b010001..Divide by 18
5852  *  0b010010..Divide by 19
5853  *  0b010011..Divide by 20
5854  *  0b010100..Divide by 21
5855  *  0b010101..Divide by 22
5856  *  0b010110..Divide by 23
5857  *  0b010111..Divide by 24
5858  *  0b011000..Divide by 25
5859  *  0b011001..Divide by 26
5860  *  0b011010..Divide by 27
5861  *  0b011011..Divide by 28
5862  *  0b011100..Divide by 29
5863  *  0b011101..Divide by 30
5864  *  0b011110..Divide by 31
5865  *  0b011111..Divide by 32
5866  *  0b100000..Divide by 33
5867  *  0b100001..Divide by 34
5868  *  0b100010..Divide by 35
5869  *  0b100011..Divide by 36
5870  *  0b100100..Divide by 37
5871  *  0b100101..Divide by 38
5872  *  0b100110..Divide by 39
5873  *  0b100111..Divide by 40
5874  *  0b101000..Divide by 41
5875  *  0b101001..Divide by 42
5876  *  0b101010..Divide by 43
5877  *  0b101011..Divide by 44
5878  *  0b101100..Divide by 45
5879  *  0b101101..Divide by 46
5880  *  0b101110..Divide by 47
5881  *  0b101111..Divide by 48
5882  *  0b110000..Divide by 49
5883  *  0b110001..Divide by 50
5884  *  0b110010..Divide by 51
5885  *  0b110011..Divide by 52
5886  *  0b110100..Divide by 53
5887  *  0b110101..Divide by 54
5888  *  0b110110..Divide by 55
5889  *  0b110111..Divide by 56
5890  *  0b111000..Divide by 57
5891  *  0b111001..Divide by 58
5892  *  0b111010..Divide by 59
5893  *  0b111011..Divide by 60
5894  *  0b111100..Divide by 61
5895  *  0b111101..Divide by 62
5896  *  0b111110..Divide by 63
5897  *  0b111111..Divide by 64
5898  */
5899 #define CCM_CS1CDR_SAI3_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
5900 
5901 #define CCM_CS1CDR_SAI3_CLK_PRED_MASK            (0x1C00000U)
5902 #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT           (22U)
5903 /*! SAI3_CLK_PRED
5904  *  0b000..divide by 1
5905  *  0b001..divide by 2
5906  *  0b010..divide by 3
5907  *  0b011..divide by 4
5908  *  0b100..divide by 5
5909  *  0b101..divide by 6
5910  *  0b110..divide by 7
5911  *  0b111..divide by 8
5912  */
5913 #define CCM_CS1CDR_SAI3_CLK_PRED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
5914 
5915 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK         (0xE000000U)
5916 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT        (25U)
5917 /*! FLEXIO2_CLK_PODF - Divider for flexio2 clock. Divider should be updated when output clock is gated.
5918  *  0b000..Divide by 1
5919  *  0b001..Divide by 2
5920  *  0b010..Divide by 3
5921  *  0b011..Divide by 4
5922  *  0b100..Divide by 5
5923  *  0b101..Divide by 6
5924  *  0b110..Divide by 7
5925  *  0b111..Divide by 8
5926  */
5927 #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
5928 /*! @} */
5929 
5930 /*! @name CS2CDR - CCM Clock Divider Register */
5931 /*! @{ */
5932 
5933 #define CCM_CS2CDR_SAI2_CLK_PODF_MASK            (0x3FU)
5934 #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT           (0U)
5935 /*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
5936  *    than 300Mhz, the predivider can be used to achieve this.
5937  *  0b000000..Divide by 1
5938  *  0b000001..Divide by 2
5939  *  0b000010..Divide by 3
5940  *  0b000011..Divide by 4
5941  *  0b000100..Divide by 5
5942  *  0b000101..Divide by 6
5943  *  0b000110..Divide by 7
5944  *  0b000111..Divide by 8
5945  *  0b001000..Divide by 9
5946  *  0b001001..Divide by 10
5947  *  0b001010..Divide by 11
5948  *  0b001011..Divide by 12
5949  *  0b001100..Divide by 13
5950  *  0b001101..Divide by 14
5951  *  0b001110..Divide by 15
5952  *  0b001111..Divide by 16
5953  *  0b010000..Divide by 17
5954  *  0b010001..Divide by 18
5955  *  0b010010..Divide by 19
5956  *  0b010011..Divide by 20
5957  *  0b010100..Divide by 21
5958  *  0b010101..Divide by 22
5959  *  0b010110..Divide by 23
5960  *  0b010111..Divide by 24
5961  *  0b011000..Divide by 25
5962  *  0b011001..Divide by 26
5963  *  0b011010..Divide by 27
5964  *  0b011011..Divide by 28
5965  *  0b011100..Divide by 29
5966  *  0b011101..Divide by 30
5967  *  0b011110..Divide by 31
5968  *  0b011111..Divide by 32
5969  *  0b100000..Divide by 33
5970  *  0b100001..Divide by 34
5971  *  0b100010..Divide by 35
5972  *  0b100011..Divide by 36
5973  *  0b100100..Divide by 37
5974  *  0b100101..Divide by 38
5975  *  0b100110..Divide by 39
5976  *  0b100111..Divide by 40
5977  *  0b101000..Divide by 41
5978  *  0b101001..Divide by 42
5979  *  0b101010..Divide by 43
5980  *  0b101011..Divide by 44
5981  *  0b101100..Divide by 45
5982  *  0b101101..Divide by 46
5983  *  0b101110..Divide by 47
5984  *  0b101111..Divide by 48
5985  *  0b110000..Divide by 49
5986  *  0b110001..Divide by 50
5987  *  0b110010..Divide by 51
5988  *  0b110011..Divide by 52
5989  *  0b110100..Divide by 53
5990  *  0b110101..Divide by 54
5991  *  0b110110..Divide by 55
5992  *  0b110111..Divide by 56
5993  *  0b111000..Divide by 57
5994  *  0b111001..Divide by 58
5995  *  0b111010..Divide by 59
5996  *  0b111011..Divide by 60
5997  *  0b111100..Divide by 61
5998  *  0b111101..Divide by 62
5999  *  0b111110..Divide by 63
6000  *  0b111111..Divide by 64
6001  */
6002 #define CCM_CS2CDR_SAI2_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
6003 
6004 #define CCM_CS2CDR_SAI2_CLK_PRED_MASK            (0x1C0U)
6005 #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT           (6U)
6006 /*! SAI2_CLK_PRED
6007  *  0b000..divide by 1
6008  *  0b001..divide by 2
6009  *  0b010..divide by 3
6010  *  0b011..divide by 4
6011  *  0b100..divide by 5
6012  *  0b101..divide by 6
6013  *  0b110..divide by 7
6014  *  0b111..divide by 8
6015  */
6016 #define CCM_CS2CDR_SAI2_CLK_PRED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
6017 /*! @} */
6018 
6019 /*! @name CDCDR - CCM D1 Clock Divider Register */
6020 /*! @{ */
6021 
6022 #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK           (0x180U)
6023 #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT          (7U)
6024 /*! FLEXIO1_CLK_SEL
6025  *  0b00..derive clock from PLL4
6026  *  0b01..derive clock from PLL3 PFD2
6027  *  0b10..derive clock from PLL5
6028  *  0b11..derive clock from pll3_sw_clk
6029  */
6030 #define CCM_CDCDR_FLEXIO1_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
6031 
6032 #define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK          (0xE00U)
6033 #define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT         (9U)
6034 /*! FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
6035  *  0b000..Divide by 1
6036  *  0b001..Divide by 2
6037  *  0b010..Divide by 3
6038  *  0b011..Divide by 4
6039  *  0b100..Divide by 5
6040  *  0b101..Divide by 6
6041  *  0b110..Divide by 7
6042  *  0b111..Divide by 8
6043  */
6044 #define CCM_CDCDR_FLEXIO1_CLK_PODF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
6045 
6046 #define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK          (0x7000U)
6047 #define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT         (12U)
6048 /*! FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
6049  *  0b000..Divide by 1
6050  *  0b001..Divide by 2
6051  *  0b010..Divide by 3
6052  *  0b011..Divide by 4
6053  *  0b100..Divide by 5
6054  *  0b101..Divide by 6
6055  *  0b110..Divide by 7
6056  *  0b111..Divide by 8
6057  */
6058 #define CCM_CDCDR_FLEXIO1_CLK_PRED(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
6059 
6060 #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK            (0x300000U)
6061 #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT           (20U)
6062 /*! SPDIF0_CLK_SEL
6063  *  0b00..derive clock from PLL4
6064  *  0b01..derive clock from PLL3 PFD2
6065  *  0b10..derive clock from PLL5
6066  *  0b11..derive clock from pll3_sw_clk
6067  */
6068 #define CCM_CDCDR_SPDIF0_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
6069 
6070 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK           (0x1C00000U)
6071 #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT          (22U)
6072 /*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
6073  *  0b000..Divide by 1
6074  *  0b001..Divide by 2
6075  *  0b010..Divide by 3
6076  *  0b011..Divide by 4
6077  *  0b100..Divide by 5
6078  *  0b101..Divide by 6
6079  *  0b110..Divide by 7
6080  *  0b111..Divide by 8
6081  */
6082 #define CCM_CDCDR_SPDIF0_CLK_PODF(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
6083 
6084 #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK           (0xE000000U)
6085 #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT          (25U)
6086 /*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
6087  *  0b000..Divide by 1
6088  *  0b001..Divide by 2
6089  *  0b010..Divide by 3
6090  *  0b011..Divide by 4
6091  *  0b100..Divide by 5
6092  *  0b101..Divide by 6
6093  *  0b110..Divide by 7
6094  *  0b111..Divide by 8
6095  */
6096 #define CCM_CDCDR_SPDIF0_CLK_PRED(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
6097 /*! @} */
6098 
6099 /*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
6100 /*! @{ */
6101 
6102 #define CCM_CSCDR2_LCDIF_PRED_MASK               (0x7000U)
6103 #define CCM_CSCDR2_LCDIF_PRED_SHIFT              (12U)
6104 /*! LCDIF_PRED
6105  *  0b000..divide by 1
6106  *  0b001..divide by 2
6107  *  0b010..divide by 3
6108  *  0b011..divide by 4
6109  *  0b100..divide by 5
6110  *  0b101..divide by 6
6111  *  0b110..divide by 7
6112  *  0b111..divide by 8
6113  */
6114 #define CCM_CSCDR2_LCDIF_PRED(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
6115 
6116 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK        (0x38000U)
6117 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT       (15U)
6118 /*! LCDIF_PRE_CLK_SEL
6119  *  0b000..derive clock from PLL2
6120  *  0b001..derive clock from PLL3 PFD3
6121  *  0b010..derive clock from PLL5
6122  *  0b011..derive clock from PLL2 PFD0
6123  *  0b100..derive clock from PLL2 PFD1
6124  *  0b101..derive clock from PLL3 PFD1
6125  *  0b110-0b111..Reserved
6126  */
6127 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
6128 
6129 #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK            (0x40000U)
6130 #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT           (18U)
6131 /*! LPI2C_CLK_SEL
6132  *  0b0..derive clock from pll3_60m
6133  *  0b1..derive clock from osc_clk
6134  */
6135 #define CCM_CSCDR2_LPI2C_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
6136 
6137 #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK           (0x1F80000U)
6138 #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT          (19U)
6139 /*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
6140  *    gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
6141  *    to achieve this.
6142  *  0b000000..Divide by 1
6143  *  0b000001..Divide by 2
6144  *  0b000010..Divide by 3
6145  *  0b000011..Divide by 4
6146  *  0b000100..Divide by 5
6147  *  0b000101..Divide by 6
6148  *  0b000110..Divide by 7
6149  *  0b000111..Divide by 8
6150  *  0b001000..Divide by 9
6151  *  0b001001..Divide by 10
6152  *  0b001010..Divide by 11
6153  *  0b001011..Divide by 12
6154  *  0b001100..Divide by 13
6155  *  0b001101..Divide by 14
6156  *  0b001110..Divide by 15
6157  *  0b001111..Divide by 16
6158  *  0b010000..Divide by 17
6159  *  0b010001..Divide by 18
6160  *  0b010010..Divide by 19
6161  *  0b010011..Divide by 20
6162  *  0b010100..Divide by 21
6163  *  0b010101..Divide by 22
6164  *  0b010110..Divide by 23
6165  *  0b010111..Divide by 24
6166  *  0b011000..Divide by 25
6167  *  0b011001..Divide by 26
6168  *  0b011010..Divide by 27
6169  *  0b011011..Divide by 28
6170  *  0b011100..Divide by 29
6171  *  0b011101..Divide by 30
6172  *  0b011110..Divide by 31
6173  *  0b011111..Divide by 32
6174  *  0b100000..Divide by 33
6175  *  0b100001..Divide by 34
6176  *  0b100010..Divide by 35
6177  *  0b100011..Divide by 36
6178  *  0b100100..Divide by 37
6179  *  0b100101..Divide by 38
6180  *  0b100110..Divide by 39
6181  *  0b100111..Divide by 40
6182  *  0b101000..Divide by 41
6183  *  0b101001..Divide by 42
6184  *  0b101010..Divide by 43
6185  *  0b101011..Divide by 44
6186  *  0b101100..Divide by 45
6187  *  0b101101..Divide by 46
6188  *  0b101110..Divide by 47
6189  *  0b101111..Divide by 48
6190  *  0b110000..Divide by 49
6191  *  0b110001..Divide by 50
6192  *  0b110010..Divide by 51
6193  *  0b110011..Divide by 52
6194  *  0b110100..Divide by 53
6195  *  0b110101..Divide by 54
6196  *  0b110110..Divide by 55
6197  *  0b110111..Divide by 56
6198  *  0b111000..Divide by 57
6199  *  0b111001..Divide by 58
6200  *  0b111010..Divide by 59
6201  *  0b111011..Divide by 60
6202  *  0b111100..Divide by 61
6203  *  0b111101..Divide by 62
6204  *  0b111110..Divide by 63
6205  *  0b111111..Divide by 64
6206  */
6207 #define CCM_CSCDR2_LPI2C_CLK_PODF(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
6208 /*! @} */
6209 
6210 /*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */
6211 /*! @{ */
6212 
6213 #define CCM_CSCDR3_CSI_CLK_SEL_MASK              (0x600U)
6214 #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT             (9U)
6215 /*! CSI_CLK_SEL
6216  *  0b00..derive clock from osc_clk (24M)
6217  *  0b01..derive clock from PLL2 PFD2
6218  *  0b10..derive clock from pll3_120M
6219  *  0b11..derive clock from PLL3 PFD1
6220  */
6221 #define CCM_CSCDR3_CSI_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
6222 
6223 #define CCM_CSCDR3_CSI_PODF_MASK                 (0x3800U)
6224 #define CCM_CSCDR3_CSI_PODF_SHIFT                (11U)
6225 /*! CSI_PODF
6226  *  0b000..divide by 1
6227  *  0b001..divide by 2
6228  *  0b010..divide by 3
6229  *  0b011..divide by 4
6230  *  0b100..divide by 5
6231  *  0b101..divide by 6
6232  *  0b110..divide by 7
6233  *  0b111..divide by 8
6234  */
6235 #define CCM_CSCDR3_CSI_PODF(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
6236 /*! @} */
6237 
6238 /*! @name CDHIPR - CCM Divider Handshake In-Process Register */
6239 /*! @{ */
6240 
6241 #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK           (0x1U)
6242 #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT          (0U)
6243 /*! SEMC_PODF_BUSY
6244  *  0b0..divider is not busy and its value represents the actual division.
6245  *  0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
6246  *       value of the division factor, and after the handshake the written value of the semc_podf will be applied.
6247  */
6248 #define CCM_CDHIPR_SEMC_PODF_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
6249 
6250 #define CCM_CDHIPR_AHB_PODF_BUSY_MASK            (0x2U)
6251 #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT           (1U)
6252 /*! AHB_PODF_BUSY
6253  *  0b0..divider is not busy and its value represents the actual division.
6254  *  0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
6255  *       value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
6256  */
6257 #define CCM_CDHIPR_AHB_PODF_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
6258 
6259 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK     (0x8U)
6260 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT    (3U)
6261 /*! PERIPH2_CLK_SEL_BUSY
6262  *  0b0..mux is not busy and its value represents the actual division.
6263  *  0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
6264  *       previous value of select, and after the handshake periph2_clk_sel value will be applied.
6265  */
6266 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
6267 
6268 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK      (0x20U)
6269 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT     (5U)
6270 /*! PERIPH_CLK_SEL_BUSY
6271  *  0b0..mux is not busy and its value represents the actual division.
6272  *  0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
6273  *       previous value of select, and after the handshake periph_clk_sel value will be applied.
6274  */
6275 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
6276 
6277 #define CCM_CDHIPR_ARM_PODF_BUSY_MASK            (0x10000U)
6278 #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT           (16U)
6279 /*! ARM_PODF_BUSY
6280  *  0b0..divider is not busy and its value represents the actual division.
6281  *  0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
6282  *       value of the division factor, and after the handshake the written value of the arm_podf will be applied.
6283  */
6284 #define CCM_CDHIPR_ARM_PODF_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
6285 /*! @} */
6286 
6287 /*! @name CLPCR - CCM Low Power Control Register */
6288 /*! @{ */
6289 
6290 #define CCM_CLPCR_LPM_MASK                       (0x3U)
6291 #define CCM_CLPCR_LPM_SHIFT                      (0U)
6292 /*! LPM
6293  *  0b00..Remain in run mode
6294  *  0b01..Transfer to wait mode
6295  *  0b10..Transfer to stop mode
6296  *  0b11..Reserved
6297  */
6298 #define CCM_CLPCR_LPM(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
6299 
6300 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK        (0x20U)
6301 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT       (5U)
6302 /*! ARM_CLK_DIS_ON_LPM
6303  *  0b0..Arm clock enabled on wait mode.
6304  *  0b1..Arm clock disabled on wait mode. .
6305  */
6306 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
6307 
6308 #define CCM_CLPCR_SBYOS_MASK                     (0x40U)
6309 #define CCM_CLPCR_SBYOS_SHIFT                    (6U)
6310 /*! SBYOS
6311  *  0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
6312  *       asserted - '0' and cosc_pwrdown will remain de asserted - '0')
6313  *  0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
6314  *       deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
6315  *       be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
6316  *       continue with the exit from the STOP mode process.
6317  */
6318 #define CCM_CLPCR_SBYOS(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
6319 
6320 #define CCM_CLPCR_DIS_REF_OSC_MASK               (0x80U)
6321 #define CCM_CLPCR_DIS_REF_OSC_SHIFT              (7U)
6322 /*! DIS_REF_OSC
6323  *  0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
6324  *  0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
6325  */
6326 #define CCM_CLPCR_DIS_REF_OSC(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
6327 
6328 #define CCM_CLPCR_VSTBY_MASK                     (0x100U)
6329 #define CCM_CLPCR_VSTBY_SHIFT                    (8U)
6330 /*! VSTBY
6331  *  0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
6332  *  0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
6333  */
6334 #define CCM_CLPCR_VSTBY(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
6335 
6336 #define CCM_CLPCR_STBY_COUNT_MASK                (0x600U)
6337 #define CCM_CLPCR_STBY_COUNT_SHIFT               (9U)
6338 /*! STBY_COUNT
6339  *  0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
6340  *  0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
6341  *  0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
6342  *  0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
6343  */
6344 #define CCM_CLPCR_STBY_COUNT(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
6345 
6346 #define CCM_CLPCR_COSC_PWRDOWN_MASK              (0x800U)
6347 #define CCM_CLPCR_COSC_PWRDOWN_SHIFT             (11U)
6348 /*! COSC_PWRDOWN
6349  *  0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
6350  *  0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
6351  */
6352 #define CCM_CLPCR_COSC_PWRDOWN(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
6353 
6354 #define CCM_CLPCR_BYPASS_LPM_HS1_MASK            (0x80000U)
6355 #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT           (19U)
6356 #define CCM_CLPCR_BYPASS_LPM_HS1(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
6357 
6358 #define CCM_CLPCR_BYPASS_LPM_HS0_MASK            (0x200000U)
6359 #define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT           (21U)
6360 #define CCM_CLPCR_BYPASS_LPM_HS0(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
6361 
6362 #define CCM_CLPCR_MASK_CORE0_WFI_MASK            (0x400000U)
6363 #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT           (22U)
6364 /*! MASK_CORE0_WFI
6365  *  0b0..WFI of core0 is not masked
6366  *  0b1..WFI of core0 is masked
6367  */
6368 #define CCM_CLPCR_MASK_CORE0_WFI(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
6369 
6370 #define CCM_CLPCR_MASK_SCU_IDLE_MASK             (0x4000000U)
6371 #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT            (26U)
6372 /*! MASK_SCU_IDLE
6373  *  0b1..SCU IDLE is masked
6374  *  0b0..SCU IDLE is not masked
6375  */
6376 #define CCM_CLPCR_MASK_SCU_IDLE(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
6377 
6378 #define CCM_CLPCR_MASK_L2CC_IDLE_MASK            (0x8000000U)
6379 #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT           (27U)
6380 /*! MASK_L2CC_IDLE
6381  *  0b1..L2CC IDLE is masked
6382  *  0b0..L2CC IDLE is not masked
6383  */
6384 #define CCM_CLPCR_MASK_L2CC_IDLE(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
6385 /*! @} */
6386 
6387 /*! @name CISR - CCM Interrupt Status Register */
6388 /*! @{ */
6389 
6390 #define CCM_CISR_LRF_PLL_MASK                    (0x1U)
6391 #define CCM_CISR_LRF_PLL_SHIFT                   (0U)
6392 /*! LRF_PLL
6393  *  0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
6394  *  0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
6395  */
6396 #define CCM_CISR_LRF_PLL(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
6397 
6398 #define CCM_CISR_COSC_READY_MASK                 (0x40U)
6399 #define CCM_CISR_COSC_READY_SHIFT                (6U)
6400 /*! COSC_READY
6401  *  0b0..interrupt is not generated due to on board oscillator ready
6402  *  0b1..interrupt generated due to on board oscillator ready
6403  */
6404 #define CCM_CISR_COSC_READY(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
6405 
6406 #define CCM_CISR_SEMC_PODF_LOADED_MASK           (0x20000U)
6407 #define CCM_CISR_SEMC_PODF_LOADED_SHIFT          (17U)
6408 /*! SEMC_PODF_LOADED
6409  *  0b0..interrupt is not generated due to frequency change of semc_podf
6410  *  0b1..interrupt generated due to frequency change of semc_podf
6411  */
6412 #define CCM_CISR_SEMC_PODF_LOADED(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
6413 
6414 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK     (0x80000U)
6415 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT    (19U)
6416 /*! PERIPH2_CLK_SEL_LOADED
6417  *  0b0..interrupt is not generated due to frequency change of periph2_clk_sel
6418  *  0b1..interrupt generated due to frequency change of periph2_clk_sel
6419  */
6420 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
6421 
6422 #define CCM_CISR_AHB_PODF_LOADED_MASK            (0x100000U)
6423 #define CCM_CISR_AHB_PODF_LOADED_SHIFT           (20U)
6424 /*! AHB_PODF_LOADED
6425  *  0b0..interrupt is not generated due to frequency change of ahb_podf
6426  *  0b1..interrupt generated due to frequency change of ahb_podf
6427  */
6428 #define CCM_CISR_AHB_PODF_LOADED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
6429 
6430 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK      (0x400000U)
6431 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT     (22U)
6432 /*! PERIPH_CLK_SEL_LOADED
6433  *  0b0..interrupt is not generated due to update of periph_clk_sel.
6434  *  0b1..interrupt generated due to update of periph_clk_sel.
6435  */
6436 #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
6437 
6438 #define CCM_CISR_ARM_PODF_LOADED_MASK            (0x4000000U)
6439 #define CCM_CISR_ARM_PODF_LOADED_SHIFT           (26U)
6440 /*! ARM_PODF_LOADED
6441  *  0b0..interrupt is not generated due to frequency change of arm_podf
6442  *  0b1..interrupt generated due to frequency change of arm_podf
6443  */
6444 #define CCM_CISR_ARM_PODF_LOADED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
6445 /*! @} */
6446 
6447 /*! @name CIMR - CCM Interrupt Mask Register */
6448 /*! @{ */
6449 
6450 #define CCM_CIMR_MASK_LRF_PLL_MASK               (0x1U)
6451 #define CCM_CIMR_MASK_LRF_PLL_SHIFT              (0U)
6452 /*! MASK_LRF_PLL
6453  *  0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
6454  *  0b1..mask interrupt due to lrf of PLLs
6455  */
6456 #define CCM_CIMR_MASK_LRF_PLL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
6457 
6458 #define CCM_CIMR_MASK_COSC_READY_MASK            (0x40U)
6459 #define CCM_CIMR_MASK_COSC_READY_SHIFT           (6U)
6460 /*! MASK_COSC_READY
6461  *  0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
6462  *  0b1..mask interrupt due to on board oscillator ready
6463  */
6464 #define CCM_CIMR_MASK_COSC_READY(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
6465 
6466 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK      (0x20000U)
6467 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT     (17U)
6468 /*! MASK_SEMC_PODF_LOADED
6469  *  0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
6470  *  0b1..mask interrupt due to frequency change of semc_podf
6471  */
6472 #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
6473 
6474 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6475 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6476 /*! MASK_PERIPH2_CLK_SEL_LOADED
6477  *  0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
6478  *  0b1..mask interrupt due to update of periph2_clk_sel
6479  */
6480 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
6481 
6482 #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK       (0x100000U)
6483 #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT      (20U)
6484 /*! MASK_AHB_PODF_LOADED
6485  *  0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
6486  *  0b1..mask interrupt due to frequency change of ahb_podf
6487  */
6488 #define CCM_CIMR_MASK_AHB_PODF_LOADED(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
6489 
6490 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6491 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6492 /*! MASK_PERIPH_CLK_SEL_LOADED
6493  *  0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
6494  *  0b1..mask interrupt due to update of periph_clk_sel
6495  */
6496 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
6497 
6498 #define CCM_CIMR_ARM_PODF_LOADED_MASK            (0x4000000U)
6499 #define CCM_CIMR_ARM_PODF_LOADED_SHIFT           (26U)
6500 /*! ARM_PODF_LOADED
6501  *  0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
6502  *  0b1..mask interrupt due to frequency change of arm_podf
6503  */
6504 #define CCM_CIMR_ARM_PODF_LOADED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
6505 /*! @} */
6506 
6507 /*! @name CCOSR - CCM Clock Output Source Register */
6508 /*! @{ */
6509 
6510 #define CCM_CCOSR_CLKO1_SEL_MASK                 (0xFU)
6511 #define CCM_CCOSR_CLKO1_SEL_SHIFT                (0U)
6512 /*! CLKO1_SEL
6513  *  0b0000..USB1 PLL clock (divided by 2)
6514  *  0b0001..SYS PLL clock (divided by 2)
6515  *  0b0011..VIDEO PLL clock (divided by 2)
6516  *  0b0101..semc_clk_root
6517  *  0b0110..Reserved
6518  *  0b1010..lcdif_pix_clk_root
6519  *  0b1011..ahb_clk_root
6520  *  0b1100..ipg_clk_root
6521  *  0b1101..perclk_root
6522  *  0b1110..ckil_sync_clk_root
6523  *  0b1111..pll4_main_clk
6524  */
6525 #define CCM_CCOSR_CLKO1_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
6526 
6527 #define CCM_CCOSR_CLKO1_DIV_MASK                 (0x70U)
6528 #define CCM_CCOSR_CLKO1_DIV_SHIFT                (4U)
6529 /*! CLKO1_DIV
6530  *  0b000..divide by 1
6531  *  0b001..divide by 2
6532  *  0b010..divide by 3
6533  *  0b011..divide by 4
6534  *  0b100..divide by 5
6535  *  0b101..divide by 6
6536  *  0b110..divide by 7
6537  *  0b111..divide by 8
6538  */
6539 #define CCM_CCOSR_CLKO1_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
6540 
6541 #define CCM_CCOSR_CLKO1_EN_MASK                  (0x80U)
6542 #define CCM_CCOSR_CLKO1_EN_SHIFT                 (7U)
6543 /*! CLKO1_EN
6544  *  0b0..CCM_CLKO1 disabled.
6545  *  0b1..CCM_CLKO1 enabled.
6546  */
6547 #define CCM_CCOSR_CLKO1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
6548 
6549 #define CCM_CCOSR_CLK_OUT_SEL_MASK               (0x100U)
6550 #define CCM_CCOSR_CLK_OUT_SEL_SHIFT              (8U)
6551 /*! CLK_OUT_SEL
6552  *  0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
6553  *  0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
6554  */
6555 #define CCM_CCOSR_CLK_OUT_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
6556 
6557 #define CCM_CCOSR_CLKO2_SEL_MASK                 (0x1F0000U)
6558 #define CCM_CCOSR_CLKO2_SEL_SHIFT                (16U)
6559 /*! CLKO2_SEL
6560  *  0b00011..usdhc1_clk_root
6561  *  0b00110..lpi2c_clk_root
6562  *  0b01011..csi_clk_root
6563  *  0b01110..osc_clk
6564  *  0b10001..usdhc2_clk_root
6565  *  0b10010..sai1_clk_root
6566  *  0b10011..sai2_clk_root
6567  *  0b10100..sai3_clk_root
6568  *  0b10111..can_clk_root
6569  *  0b11011..flexspi_clk_root
6570  *  0b11100..uart_clk_root
6571  *  0b11101..spdif0_clk_root
6572  *  0b11111..Reserved
6573  */
6574 #define CCM_CCOSR_CLKO2_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
6575 
6576 #define CCM_CCOSR_CLKO2_DIV_MASK                 (0xE00000U)
6577 #define CCM_CCOSR_CLKO2_DIV_SHIFT                (21U)
6578 /*! CLKO2_DIV
6579  *  0b000..divide by 1
6580  *  0b001..divide by 2
6581  *  0b010..divide by 3
6582  *  0b011..divide by 4
6583  *  0b100..divide by 5
6584  *  0b101..divide by 6
6585  *  0b110..divide by 7
6586  *  0b111..divide by 8
6587  */
6588 #define CCM_CCOSR_CLKO2_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
6589 
6590 #define CCM_CCOSR_CLKO2_EN_MASK                  (0x1000000U)
6591 #define CCM_CCOSR_CLKO2_EN_SHIFT                 (24U)
6592 /*! CLKO2_EN
6593  *  0b0..CCM_CLKO2 disabled.
6594  *  0b1..CCM_CLKO2 enabled.
6595  */
6596 #define CCM_CCOSR_CLKO2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
6597 /*! @} */
6598 
6599 /*! @name CGPR - CCM General Purpose Register */
6600 /*! @{ */
6601 
6602 #define CCM_CGPR_PMIC_DELAY_SCALER_MASK          (0x1U)
6603 #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT         (0U)
6604 /*! PMIC_DELAY_SCALER
6605  *  0b0..clock is not divided
6606  *  0b1..clock is divided /8
6607  */
6608 #define CCM_CGPR_PMIC_DELAY_SCALER(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
6609 
6610 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK     (0x10U)
6611 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT    (4U)
6612 /*! EFUSE_PROG_SUPPLY_GATE
6613  *  0b0..fuse programing supply voltage is gated off to the efuse module
6614  *  0b1..allow fuse programing.
6615  */
6616 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
6617 
6618 #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK            (0xC000U)
6619 #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT           (14U)
6620 /*! SYS_MEM_DS_CTRL
6621  *  0b00..Disable memory DS mode always
6622  *  0b01..Enable memory (outside Arm platform) DS mode when system STOP and PLL are disabled
6623  *  0b1x..enable memory (outside Arm platform) DS mode when system is in STOP mode
6624  */
6625 #define CCM_CGPR_SYS_MEM_DS_CTRL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
6626 
6627 #define CCM_CGPR_FPL_MASK                        (0x10000U)
6628 #define CCM_CGPR_FPL_SHIFT                       (16U)
6629 /*! FPL - Fast PLL enable.
6630  *  0b0..Engage PLL enable default way.
6631  *  0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
6632  */
6633 #define CCM_CGPR_FPL(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
6634 
6635 #define CCM_CGPR_INT_MEM_CLK_LPM_MASK            (0x20000U)
6636 #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT           (17U)
6637 /*! INT_MEM_CLK_LPM
6638  *  0b0..Disable the clock to the Arm platform memories when entering Low Power Mode
6639  *  0b1..Keep the clocks to the Arm platform memories enabled only if an interrupt is pending when entering Low
6640  *       Power Modes (WAIT and STOP without power gating)
6641  */
6642 #define CCM_CGPR_INT_MEM_CLK_LPM(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
6643 /*! @} */
6644 
6645 /*! @name CCGR0 - CCM Clock Gating Register 0 */
6646 /*! @{ */
6647 
6648 #define CCM_CCGR0_CG0_MASK                       (0x3U)
6649 #define CCM_CCGR0_CG0_SHIFT                      (0U)
6650 #define CCM_CCGR0_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
6651 
6652 #define CCM_CCGR0_CG1_MASK                       (0xCU)
6653 #define CCM_CCGR0_CG1_SHIFT                      (2U)
6654 #define CCM_CCGR0_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
6655 
6656 #define CCM_CCGR0_CG2_MASK                       (0x30U)
6657 #define CCM_CCGR0_CG2_SHIFT                      (4U)
6658 #define CCM_CCGR0_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
6659 
6660 #define CCM_CCGR0_CG3_MASK                       (0xC0U)
6661 #define CCM_CCGR0_CG3_SHIFT                      (6U)
6662 #define CCM_CCGR0_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
6663 
6664 #define CCM_CCGR0_CG4_MASK                       (0x300U)
6665 #define CCM_CCGR0_CG4_SHIFT                      (8U)
6666 #define CCM_CCGR0_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
6667 
6668 #define CCM_CCGR0_CG5_MASK                       (0xC00U)
6669 #define CCM_CCGR0_CG5_SHIFT                      (10U)
6670 #define CCM_CCGR0_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
6671 
6672 #define CCM_CCGR0_CG6_MASK                       (0x3000U)
6673 #define CCM_CCGR0_CG6_SHIFT                      (12U)
6674 #define CCM_CCGR0_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
6675 
6676 #define CCM_CCGR0_CG7_MASK                       (0xC000U)
6677 #define CCM_CCGR0_CG7_SHIFT                      (14U)
6678 #define CCM_CCGR0_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
6679 
6680 #define CCM_CCGR0_CG8_MASK                       (0x30000U)
6681 #define CCM_CCGR0_CG8_SHIFT                      (16U)
6682 #define CCM_CCGR0_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
6683 
6684 #define CCM_CCGR0_CG9_MASK                       (0xC0000U)
6685 #define CCM_CCGR0_CG9_SHIFT                      (18U)
6686 #define CCM_CCGR0_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
6687 
6688 #define CCM_CCGR0_CG10_MASK                      (0x300000U)
6689 #define CCM_CCGR0_CG10_SHIFT                     (20U)
6690 #define CCM_CCGR0_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
6691 
6692 #define CCM_CCGR0_CG11_MASK                      (0xC00000U)
6693 #define CCM_CCGR0_CG11_SHIFT                     (22U)
6694 #define CCM_CCGR0_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
6695 
6696 #define CCM_CCGR0_CG12_MASK                      (0x3000000U)
6697 #define CCM_CCGR0_CG12_SHIFT                     (24U)
6698 #define CCM_CCGR0_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
6699 
6700 #define CCM_CCGR0_CG13_MASK                      (0xC000000U)
6701 #define CCM_CCGR0_CG13_SHIFT                     (26U)
6702 #define CCM_CCGR0_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
6703 
6704 #define CCM_CCGR0_CG14_MASK                      (0x30000000U)
6705 #define CCM_CCGR0_CG14_SHIFT                     (28U)
6706 #define CCM_CCGR0_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
6707 
6708 #define CCM_CCGR0_CG15_MASK                      (0xC0000000U)
6709 #define CCM_CCGR0_CG15_SHIFT                     (30U)
6710 #define CCM_CCGR0_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
6711 /*! @} */
6712 
6713 /*! @name CCGR1 - CCM Clock Gating Register 1 */
6714 /*! @{ */
6715 
6716 #define CCM_CCGR1_CG0_MASK                       (0x3U)
6717 #define CCM_CCGR1_CG0_SHIFT                      (0U)
6718 #define CCM_CCGR1_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
6719 
6720 #define CCM_CCGR1_CG1_MASK                       (0xCU)
6721 #define CCM_CCGR1_CG1_SHIFT                      (2U)
6722 #define CCM_CCGR1_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
6723 
6724 #define CCM_CCGR1_CG2_MASK                       (0x30U)
6725 #define CCM_CCGR1_CG2_SHIFT                      (4U)
6726 #define CCM_CCGR1_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
6727 
6728 #define CCM_CCGR1_CG3_MASK                       (0xC0U)
6729 #define CCM_CCGR1_CG3_SHIFT                      (6U)
6730 #define CCM_CCGR1_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
6731 
6732 #define CCM_CCGR1_CG4_MASK                       (0x300U)
6733 #define CCM_CCGR1_CG4_SHIFT                      (8U)
6734 #define CCM_CCGR1_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
6735 
6736 #define CCM_CCGR1_CG5_MASK                       (0xC00U)
6737 #define CCM_CCGR1_CG5_SHIFT                      (10U)
6738 #define CCM_CCGR1_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
6739 
6740 #define CCM_CCGR1_CG6_MASK                       (0x3000U)
6741 #define CCM_CCGR1_CG6_SHIFT                      (12U)
6742 #define CCM_CCGR1_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
6743 
6744 #define CCM_CCGR1_CG7_MASK                       (0xC000U)
6745 #define CCM_CCGR1_CG7_SHIFT                      (14U)
6746 #define CCM_CCGR1_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
6747 
6748 #define CCM_CCGR1_CG8_MASK                       (0x30000U)
6749 #define CCM_CCGR1_CG8_SHIFT                      (16U)
6750 #define CCM_CCGR1_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
6751 
6752 #define CCM_CCGR1_CG9_MASK                       (0xC0000U)
6753 #define CCM_CCGR1_CG9_SHIFT                      (18U)
6754 #define CCM_CCGR1_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
6755 
6756 #define CCM_CCGR1_CG10_MASK                      (0x300000U)
6757 #define CCM_CCGR1_CG10_SHIFT                     (20U)
6758 #define CCM_CCGR1_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
6759 
6760 #define CCM_CCGR1_CG11_MASK                      (0xC00000U)
6761 #define CCM_CCGR1_CG11_SHIFT                     (22U)
6762 #define CCM_CCGR1_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
6763 
6764 #define CCM_CCGR1_CG12_MASK                      (0x3000000U)
6765 #define CCM_CCGR1_CG12_SHIFT                     (24U)
6766 #define CCM_CCGR1_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
6767 
6768 #define CCM_CCGR1_CG13_MASK                      (0xC000000U)
6769 #define CCM_CCGR1_CG13_SHIFT                     (26U)
6770 #define CCM_CCGR1_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
6771 
6772 #define CCM_CCGR1_CG14_MASK                      (0x30000000U)
6773 #define CCM_CCGR1_CG14_SHIFT                     (28U)
6774 #define CCM_CCGR1_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
6775 
6776 #define CCM_CCGR1_CG15_MASK                      (0xC0000000U)
6777 #define CCM_CCGR1_CG15_SHIFT                     (30U)
6778 #define CCM_CCGR1_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
6779 /*! @} */
6780 
6781 /*! @name CCGR2 - CCM Clock Gating Register 2 */
6782 /*! @{ */
6783 
6784 #define CCM_CCGR2_CG0_MASK                       (0x3U)
6785 #define CCM_CCGR2_CG0_SHIFT                      (0U)
6786 #define CCM_CCGR2_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
6787 
6788 #define CCM_CCGR2_CG1_MASK                       (0xCU)
6789 #define CCM_CCGR2_CG1_SHIFT                      (2U)
6790 #define CCM_CCGR2_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
6791 
6792 #define CCM_CCGR2_CG2_MASK                       (0x30U)
6793 #define CCM_CCGR2_CG2_SHIFT                      (4U)
6794 #define CCM_CCGR2_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
6795 
6796 #define CCM_CCGR2_CG3_MASK                       (0xC0U)
6797 #define CCM_CCGR2_CG3_SHIFT                      (6U)
6798 #define CCM_CCGR2_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
6799 
6800 #define CCM_CCGR2_CG4_MASK                       (0x300U)
6801 #define CCM_CCGR2_CG4_SHIFT                      (8U)
6802 #define CCM_CCGR2_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
6803 
6804 #define CCM_CCGR2_CG5_MASK                       (0xC00U)
6805 #define CCM_CCGR2_CG5_SHIFT                      (10U)
6806 #define CCM_CCGR2_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
6807 
6808 #define CCM_CCGR2_CG6_MASK                       (0x3000U)
6809 #define CCM_CCGR2_CG6_SHIFT                      (12U)
6810 #define CCM_CCGR2_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
6811 
6812 #define CCM_CCGR2_CG7_MASK                       (0xC000U)
6813 #define CCM_CCGR2_CG7_SHIFT                      (14U)
6814 #define CCM_CCGR2_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
6815 
6816 #define CCM_CCGR2_CG8_MASK                       (0x30000U)
6817 #define CCM_CCGR2_CG8_SHIFT                      (16U)
6818 #define CCM_CCGR2_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
6819 
6820 #define CCM_CCGR2_CG9_MASK                       (0xC0000U)
6821 #define CCM_CCGR2_CG9_SHIFT                      (18U)
6822 #define CCM_CCGR2_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
6823 
6824 #define CCM_CCGR2_CG10_MASK                      (0x300000U)
6825 #define CCM_CCGR2_CG10_SHIFT                     (20U)
6826 #define CCM_CCGR2_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
6827 
6828 #define CCM_CCGR2_CG11_MASK                      (0xC00000U)
6829 #define CCM_CCGR2_CG11_SHIFT                     (22U)
6830 #define CCM_CCGR2_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
6831 
6832 #define CCM_CCGR2_CG12_MASK                      (0x3000000U)
6833 #define CCM_CCGR2_CG12_SHIFT                     (24U)
6834 #define CCM_CCGR2_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
6835 
6836 #define CCM_CCGR2_CG13_MASK                      (0xC000000U)
6837 #define CCM_CCGR2_CG13_SHIFT                     (26U)
6838 #define CCM_CCGR2_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
6839 
6840 #define CCM_CCGR2_CG14_MASK                      (0x30000000U)
6841 #define CCM_CCGR2_CG14_SHIFT                     (28U)
6842 #define CCM_CCGR2_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
6843 
6844 #define CCM_CCGR2_CG15_MASK                      (0xC0000000U)
6845 #define CCM_CCGR2_CG15_SHIFT                     (30U)
6846 #define CCM_CCGR2_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
6847 /*! @} */
6848 
6849 /*! @name CCGR3 - CCM Clock Gating Register 3 */
6850 /*! @{ */
6851 
6852 #define CCM_CCGR3_CG0_MASK                       (0x3U)
6853 #define CCM_CCGR3_CG0_SHIFT                      (0U)
6854 #define CCM_CCGR3_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
6855 
6856 #define CCM_CCGR3_CG1_MASK                       (0xCU)
6857 #define CCM_CCGR3_CG1_SHIFT                      (2U)
6858 #define CCM_CCGR3_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
6859 
6860 #define CCM_CCGR3_CG2_MASK                       (0x30U)
6861 #define CCM_CCGR3_CG2_SHIFT                      (4U)
6862 #define CCM_CCGR3_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
6863 
6864 #define CCM_CCGR3_CG3_MASK                       (0xC0U)
6865 #define CCM_CCGR3_CG3_SHIFT                      (6U)
6866 #define CCM_CCGR3_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
6867 
6868 #define CCM_CCGR3_CG4_MASK                       (0x300U)
6869 #define CCM_CCGR3_CG4_SHIFT                      (8U)
6870 #define CCM_CCGR3_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
6871 
6872 #define CCM_CCGR3_CG5_MASK                       (0xC00U)
6873 #define CCM_CCGR3_CG5_SHIFT                      (10U)
6874 #define CCM_CCGR3_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
6875 
6876 #define CCM_CCGR3_CG6_MASK                       (0x3000U)
6877 #define CCM_CCGR3_CG6_SHIFT                      (12U)
6878 #define CCM_CCGR3_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
6879 
6880 #define CCM_CCGR3_CG7_MASK                       (0xC000U)
6881 #define CCM_CCGR3_CG7_SHIFT                      (14U)
6882 #define CCM_CCGR3_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
6883 
6884 #define CCM_CCGR3_CG8_MASK                       (0x30000U)
6885 #define CCM_CCGR3_CG8_SHIFT                      (16U)
6886 #define CCM_CCGR3_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
6887 
6888 #define CCM_CCGR3_CG9_MASK                       (0xC0000U)
6889 #define CCM_CCGR3_CG9_SHIFT                      (18U)
6890 #define CCM_CCGR3_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
6891 
6892 #define CCM_CCGR3_CG10_MASK                      (0x300000U)
6893 #define CCM_CCGR3_CG10_SHIFT                     (20U)
6894 #define CCM_CCGR3_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
6895 
6896 #define CCM_CCGR3_CG11_MASK                      (0xC00000U)
6897 #define CCM_CCGR3_CG11_SHIFT                     (22U)
6898 #define CCM_CCGR3_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
6899 
6900 #define CCM_CCGR3_CG12_MASK                      (0x3000000U)
6901 #define CCM_CCGR3_CG12_SHIFT                     (24U)
6902 #define CCM_CCGR3_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
6903 
6904 #define CCM_CCGR3_CG13_MASK                      (0xC000000U)
6905 #define CCM_CCGR3_CG13_SHIFT                     (26U)
6906 #define CCM_CCGR3_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
6907 
6908 #define CCM_CCGR3_CG14_MASK                      (0x30000000U)
6909 #define CCM_CCGR3_CG14_SHIFT                     (28U)
6910 /*! CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device.
6911  */
6912 #define CCM_CCGR3_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
6913 
6914 #define CCM_CCGR3_CG15_MASK                      (0xC0000000U)
6915 #define CCM_CCGR3_CG15_SHIFT                     (30U)
6916 #define CCM_CCGR3_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
6917 /*! @} */
6918 
6919 /*! @name CCGR4 - CCM Clock Gating Register 4 */
6920 /*! @{ */
6921 
6922 #define CCM_CCGR4_CG0_MASK                       (0x3U)
6923 #define CCM_CCGR4_CG0_SHIFT                      (0U)
6924 #define CCM_CCGR4_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
6925 
6926 #define CCM_CCGR4_CG1_MASK                       (0xCU)
6927 #define CCM_CCGR4_CG1_SHIFT                      (2U)
6928 #define CCM_CCGR4_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
6929 
6930 #define CCM_CCGR4_CG2_MASK                       (0x30U)
6931 #define CCM_CCGR4_CG2_SHIFT                      (4U)
6932 #define CCM_CCGR4_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
6933 
6934 #define CCM_CCGR4_CG3_MASK                       (0xC0U)
6935 #define CCM_CCGR4_CG3_SHIFT                      (6U)
6936 #define CCM_CCGR4_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
6937 
6938 #define CCM_CCGR4_CG4_MASK                       (0x300U)
6939 #define CCM_CCGR4_CG4_SHIFT                      (8U)
6940 #define CCM_CCGR4_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
6941 
6942 #define CCM_CCGR4_CG5_MASK                       (0xC00U)
6943 #define CCM_CCGR4_CG5_SHIFT                      (10U)
6944 #define CCM_CCGR4_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
6945 
6946 #define CCM_CCGR4_CG6_MASK                       (0x3000U)
6947 #define CCM_CCGR4_CG6_SHIFT                      (12U)
6948 #define CCM_CCGR4_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
6949 
6950 #define CCM_CCGR4_CG7_MASK                       (0xC000U)
6951 #define CCM_CCGR4_CG7_SHIFT                      (14U)
6952 #define CCM_CCGR4_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
6953 
6954 #define CCM_CCGR4_CG8_MASK                       (0x30000U)
6955 #define CCM_CCGR4_CG8_SHIFT                      (16U)
6956 #define CCM_CCGR4_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
6957 
6958 #define CCM_CCGR4_CG9_MASK                       (0xC0000U)
6959 #define CCM_CCGR4_CG9_SHIFT                      (18U)
6960 #define CCM_CCGR4_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
6961 
6962 #define CCM_CCGR4_CG10_MASK                      (0x300000U)
6963 #define CCM_CCGR4_CG10_SHIFT                     (20U)
6964 #define CCM_CCGR4_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
6965 
6966 #define CCM_CCGR4_CG11_MASK                      (0xC00000U)
6967 #define CCM_CCGR4_CG11_SHIFT                     (22U)
6968 #define CCM_CCGR4_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
6969 
6970 #define CCM_CCGR4_CG12_MASK                      (0x3000000U)
6971 #define CCM_CCGR4_CG12_SHIFT                     (24U)
6972 #define CCM_CCGR4_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
6973 
6974 #define CCM_CCGR4_CG13_MASK                      (0xC000000U)
6975 #define CCM_CCGR4_CG13_SHIFT                     (26U)
6976 #define CCM_CCGR4_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
6977 
6978 #define CCM_CCGR4_CG14_MASK                      (0x30000000U)
6979 #define CCM_CCGR4_CG14_SHIFT                     (28U)
6980 #define CCM_CCGR4_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
6981 
6982 #define CCM_CCGR4_CG15_MASK                      (0xC0000000U)
6983 #define CCM_CCGR4_CG15_SHIFT                     (30U)
6984 #define CCM_CCGR4_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
6985 /*! @} */
6986 
6987 /*! @name CCGR5 - CCM Clock Gating Register 5 */
6988 /*! @{ */
6989 
6990 #define CCM_CCGR5_CG0_MASK                       (0x3U)
6991 #define CCM_CCGR5_CG0_SHIFT                      (0U)
6992 #define CCM_CCGR5_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
6993 
6994 #define CCM_CCGR5_CG1_MASK                       (0xCU)
6995 #define CCM_CCGR5_CG1_SHIFT                      (2U)
6996 #define CCM_CCGR5_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
6997 
6998 #define CCM_CCGR5_CG2_MASK                       (0x30U)
6999 #define CCM_CCGR5_CG2_SHIFT                      (4U)
7000 #define CCM_CCGR5_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
7001 
7002 #define CCM_CCGR5_CG3_MASK                       (0xC0U)
7003 #define CCM_CCGR5_CG3_SHIFT                      (6U)
7004 #define CCM_CCGR5_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
7005 
7006 #define CCM_CCGR5_CG4_MASK                       (0x300U)
7007 #define CCM_CCGR5_CG4_SHIFT                      (8U)
7008 #define CCM_CCGR5_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
7009 
7010 #define CCM_CCGR5_CG5_MASK                       (0xC00U)
7011 #define CCM_CCGR5_CG5_SHIFT                      (10U)
7012 #define CCM_CCGR5_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
7013 
7014 #define CCM_CCGR5_CG6_MASK                       (0x3000U)
7015 #define CCM_CCGR5_CG6_SHIFT                      (12U)
7016 #define CCM_CCGR5_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
7017 
7018 #define CCM_CCGR5_CG7_MASK                       (0xC000U)
7019 #define CCM_CCGR5_CG7_SHIFT                      (14U)
7020 #define CCM_CCGR5_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
7021 
7022 #define CCM_CCGR5_CG8_MASK                       (0x30000U)
7023 #define CCM_CCGR5_CG8_SHIFT                      (16U)
7024 #define CCM_CCGR5_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
7025 
7026 #define CCM_CCGR5_CG9_MASK                       (0xC0000U)
7027 #define CCM_CCGR5_CG9_SHIFT                      (18U)
7028 #define CCM_CCGR5_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
7029 
7030 #define CCM_CCGR5_CG10_MASK                      (0x300000U)
7031 #define CCM_CCGR5_CG10_SHIFT                     (20U)
7032 #define CCM_CCGR5_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
7033 
7034 #define CCM_CCGR5_CG11_MASK                      (0xC00000U)
7035 #define CCM_CCGR5_CG11_SHIFT                     (22U)
7036 #define CCM_CCGR5_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
7037 
7038 #define CCM_CCGR5_CG12_MASK                      (0x3000000U)
7039 #define CCM_CCGR5_CG12_SHIFT                     (24U)
7040 #define CCM_CCGR5_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
7041 
7042 #define CCM_CCGR5_CG13_MASK                      (0xC000000U)
7043 #define CCM_CCGR5_CG13_SHIFT                     (26U)
7044 #define CCM_CCGR5_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
7045 
7046 #define CCM_CCGR5_CG14_MASK                      (0x30000000U)
7047 #define CCM_CCGR5_CG14_SHIFT                     (28U)
7048 #define CCM_CCGR5_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
7049 
7050 #define CCM_CCGR5_CG15_MASK                      (0xC0000000U)
7051 #define CCM_CCGR5_CG15_SHIFT                     (30U)
7052 #define CCM_CCGR5_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
7053 /*! @} */
7054 
7055 /*! @name CCGR6 - CCM Clock Gating Register 6 */
7056 /*! @{ */
7057 
7058 #define CCM_CCGR6_CG0_MASK                       (0x3U)
7059 #define CCM_CCGR6_CG0_SHIFT                      (0U)
7060 #define CCM_CCGR6_CG0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
7061 
7062 #define CCM_CCGR6_CG1_MASK                       (0xCU)
7063 #define CCM_CCGR6_CG1_SHIFT                      (2U)
7064 #define CCM_CCGR6_CG1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
7065 
7066 #define CCM_CCGR6_CG2_MASK                       (0x30U)
7067 #define CCM_CCGR6_CG2_SHIFT                      (4U)
7068 #define CCM_CCGR6_CG2(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
7069 
7070 #define CCM_CCGR6_CG3_MASK                       (0xC0U)
7071 #define CCM_CCGR6_CG3_SHIFT                      (6U)
7072 #define CCM_CCGR6_CG3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
7073 
7074 #define CCM_CCGR6_CG4_MASK                       (0x300U)
7075 #define CCM_CCGR6_CG4_SHIFT                      (8U)
7076 #define CCM_CCGR6_CG4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
7077 
7078 #define CCM_CCGR6_CG5_MASK                       (0xC00U)
7079 #define CCM_CCGR6_CG5_SHIFT                      (10U)
7080 #define CCM_CCGR6_CG5(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
7081 
7082 #define CCM_CCGR6_CG6_MASK                       (0x3000U)
7083 #define CCM_CCGR6_CG6_SHIFT                      (12U)
7084 #define CCM_CCGR6_CG6(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
7085 
7086 #define CCM_CCGR6_CG7_MASK                       (0xC000U)
7087 #define CCM_CCGR6_CG7_SHIFT                      (14U)
7088 #define CCM_CCGR6_CG7(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
7089 
7090 #define CCM_CCGR6_CG8_MASK                       (0x30000U)
7091 #define CCM_CCGR6_CG8_SHIFT                      (16U)
7092 #define CCM_CCGR6_CG8(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
7093 
7094 #define CCM_CCGR6_CG9_MASK                       (0xC0000U)
7095 #define CCM_CCGR6_CG9_SHIFT                      (18U)
7096 #define CCM_CCGR6_CG9(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
7097 
7098 #define CCM_CCGR6_CG10_MASK                      (0x300000U)
7099 #define CCM_CCGR6_CG10_SHIFT                     (20U)
7100 #define CCM_CCGR6_CG10(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
7101 
7102 #define CCM_CCGR6_CG11_MASK                      (0xC00000U)
7103 #define CCM_CCGR6_CG11_SHIFT                     (22U)
7104 #define CCM_CCGR6_CG11(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
7105 
7106 #define CCM_CCGR6_CG12_MASK                      (0x3000000U)
7107 #define CCM_CCGR6_CG12_SHIFT                     (24U)
7108 #define CCM_CCGR6_CG12(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
7109 
7110 #define CCM_CCGR6_CG13_MASK                      (0xC000000U)
7111 #define CCM_CCGR6_CG13_SHIFT                     (26U)
7112 #define CCM_CCGR6_CG13(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
7113 
7114 #define CCM_CCGR6_CG14_MASK                      (0x30000000U)
7115 #define CCM_CCGR6_CG14_SHIFT                     (28U)
7116 #define CCM_CCGR6_CG14(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
7117 
7118 #define CCM_CCGR6_CG15_MASK                      (0xC0000000U)
7119 #define CCM_CCGR6_CG15_SHIFT                     (30U)
7120 #define CCM_CCGR6_CG15(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
7121 /*! @} */
7122 
7123 /*! @name CMEOR - CCM Module Enable Overide Register */
7124 /*! @{ */
7125 
7126 #define CCM_CMEOR_MOD_EN_OV_GPT_MASK             (0x20U)
7127 #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT            (5U)
7128 /*! MOD_EN_OV_GPT
7129  *  0b0..don't override module enable signal
7130  *  0b1..override module enable signal
7131  */
7132 #define CCM_CMEOR_MOD_EN_OV_GPT(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
7133 
7134 #define CCM_CMEOR_MOD_EN_OV_PIT_MASK             (0x40U)
7135 #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT            (6U)
7136 /*! MOD_EN_OV_PIT
7137  *  0b0..don't override module enable signal
7138  *  0b1..override module enable signal
7139  */
7140 #define CCM_CMEOR_MOD_EN_OV_PIT(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
7141 
7142 #define CCM_CMEOR_MOD_EN_USDHC_MASK              (0x80U)
7143 #define CCM_CMEOR_MOD_EN_USDHC_SHIFT             (7U)
7144 /*! MOD_EN_USDHC
7145  *  0b0..don't override module enable signal
7146  *  0b1..override module enable signal
7147  */
7148 #define CCM_CMEOR_MOD_EN_USDHC(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
7149 
7150 #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK            (0x200U)
7151 #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT           (9U)
7152 /*! MOD_EN_OV_TRNG
7153  *  0b0..don't override module enable signal
7154  *  0b1..override module enable signal
7155  */
7156 #define CCM_CMEOR_MOD_EN_OV_TRNG(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
7157 
7158 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK        (0x10000000U)
7159 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT       (28U)
7160 /*! MOD_EN_OV_CAN2_CPI
7161  *  0b0..don't override module enable signal
7162  *  0b1..override module enable signal
7163  */
7164 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
7165 
7166 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK        (0x40000000U)
7167 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT       (30U)
7168 /*! MOD_EN_OV_CAN1_CPI
7169  *  0b0..don't overide module enable signal
7170  *  0b1..overide module enable signal
7171  */
7172 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
7173 /*! @} */
7174 
7175 
7176 /*!
7177  * @}
7178  */ /* end of group CCM_Register_Masks */
7179 
7180 
7181 /* CCM - Peripheral instance base addresses */
7182 /** Peripheral CCM base address */
7183 #define CCM_BASE                                 (0x400FC000u)
7184 /** Peripheral CCM base pointer */
7185 #define CCM                                      ((CCM_Type *)CCM_BASE)
7186 /** Array initializer of CCM peripheral base addresses */
7187 #define CCM_BASE_ADDRS                           { CCM_BASE }
7188 /** Array initializer of CCM peripheral base pointers */
7189 #define CCM_BASE_PTRS                            { CCM }
7190 /** Interrupt vectors for the CCM peripheral type */
7191 #define CCM_IRQS                                 { CCM_1_IRQn, CCM_2_IRQn }
7192 
7193 /*!
7194  * @}
7195  */ /* end of group CCM_Peripheral_Access_Layer */
7196 
7197 
7198 /* ----------------------------------------------------------------------------
7199    -- CCM_ANALOG Peripheral Access Layer
7200    ---------------------------------------------------------------------------- */
7201 
7202 /*!
7203  * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
7204  * @{
7205  */
7206 
7207 /** CCM_ANALOG - Register Layout Typedef */
7208 typedef struct {
7209   __IO uint32_t PLL_ARM;                           /**< Analog ARM PLL control Register, offset: 0x0 */
7210   __IO uint32_t PLL_ARM_SET;                       /**< Analog ARM PLL control Register, offset: 0x4 */
7211   __IO uint32_t PLL_ARM_CLR;                       /**< Analog ARM PLL control Register, offset: 0x8 */
7212   __IO uint32_t PLL_ARM_TOG;                       /**< Analog ARM PLL control Register, offset: 0xC */
7213   __IO uint32_t PLL_USB1;                          /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
7214   __IO uint32_t PLL_USB1_SET;                      /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
7215   __IO uint32_t PLL_USB1_CLR;                      /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
7216   __IO uint32_t PLL_USB1_TOG;                      /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
7217   __IO uint32_t PLL_USB2;                          /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */
7218   __IO uint32_t PLL_USB2_SET;                      /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */
7219   __IO uint32_t PLL_USB2_CLR;                      /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */
7220   __IO uint32_t PLL_USB2_TOG;                      /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */
7221   __IO uint32_t PLL_SYS;                           /**< Analog System PLL Control Register, offset: 0x30 */
7222   __IO uint32_t PLL_SYS_SET;                       /**< Analog System PLL Control Register, offset: 0x34 */
7223   __IO uint32_t PLL_SYS_CLR;                       /**< Analog System PLL Control Register, offset: 0x38 */
7224   __IO uint32_t PLL_SYS_TOG;                       /**< Analog System PLL Control Register, offset: 0x3C */
7225   __IO uint32_t PLL_SYS_SS;                        /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
7226        uint8_t RESERVED_0[12];
7227   __IO uint32_t PLL_SYS_NUM;                       /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
7228        uint8_t RESERVED_1[12];
7229   __IO uint32_t PLL_SYS_DENOM;                     /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
7230        uint8_t RESERVED_2[12];
7231   __IO uint32_t PLL_AUDIO;                         /**< Analog Audio PLL control Register, offset: 0x70 */
7232   __IO uint32_t PLL_AUDIO_SET;                     /**< Analog Audio PLL control Register, offset: 0x74 */
7233   __IO uint32_t PLL_AUDIO_CLR;                     /**< Analog Audio PLL control Register, offset: 0x78 */
7234   __IO uint32_t PLL_AUDIO_TOG;                     /**< Analog Audio PLL control Register, offset: 0x7C */
7235   __IO uint32_t PLL_AUDIO_NUM;                     /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
7236        uint8_t RESERVED_3[12];
7237   __IO uint32_t PLL_AUDIO_DENOM;                   /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
7238        uint8_t RESERVED_4[12];
7239   __IO uint32_t PLL_VIDEO;                         /**< Analog Video PLL control Register, offset: 0xA0 */
7240   __IO uint32_t PLL_VIDEO_SET;                     /**< Analog Video PLL control Register, offset: 0xA4 */
7241   __IO uint32_t PLL_VIDEO_CLR;                     /**< Analog Video PLL control Register, offset: 0xA8 */
7242   __IO uint32_t PLL_VIDEO_TOG;                     /**< Analog Video PLL control Register, offset: 0xAC */
7243   __IO uint32_t PLL_VIDEO_NUM;                     /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */
7244        uint8_t RESERVED_5[12];
7245   __IO uint32_t PLL_VIDEO_DENOM;                   /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */
7246        uint8_t RESERVED_6[28];
7247   __IO uint32_t PLL_ENET;                          /**< Analog ENET PLL Control Register, offset: 0xE0 */
7248   __IO uint32_t PLL_ENET_SET;                      /**< Analog ENET PLL Control Register, offset: 0xE4 */
7249   __IO uint32_t PLL_ENET_CLR;                      /**< Analog ENET PLL Control Register, offset: 0xE8 */
7250   __IO uint32_t PLL_ENET_TOG;                      /**< Analog ENET PLL Control Register, offset: 0xEC */
7251   __IO uint32_t PFD_480;                           /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
7252   __IO uint32_t PFD_480_SET;                       /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
7253   __IO uint32_t PFD_480_CLR;                       /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
7254   __IO uint32_t PFD_480_TOG;                       /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
7255   __IO uint32_t PFD_528;                           /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
7256   __IO uint32_t PFD_528_SET;                       /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
7257   __IO uint32_t PFD_528_CLR;                       /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
7258   __IO uint32_t PFD_528_TOG;                       /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
7259        uint8_t RESERVED_7[64];
7260   __IO uint32_t MISC0;                             /**< Miscellaneous Register 0, offset: 0x150 */
7261   __IO uint32_t MISC0_SET;                         /**< Miscellaneous Register 0, offset: 0x154 */
7262   __IO uint32_t MISC0_CLR;                         /**< Miscellaneous Register 0, offset: 0x158 */
7263   __IO uint32_t MISC0_TOG;                         /**< Miscellaneous Register 0, offset: 0x15C */
7264   __IO uint32_t MISC1;                             /**< Miscellaneous Register 1, offset: 0x160 */
7265   __IO uint32_t MISC1_SET;                         /**< Miscellaneous Register 1, offset: 0x164 */
7266   __IO uint32_t MISC1_CLR;                         /**< Miscellaneous Register 1, offset: 0x168 */
7267   __IO uint32_t MISC1_TOG;                         /**< Miscellaneous Register 1, offset: 0x16C */
7268   __IO uint32_t MISC2;                             /**< Miscellaneous Register 2, offset: 0x170 */
7269   __IO uint32_t MISC2_SET;                         /**< Miscellaneous Register 2, offset: 0x174 */
7270   __IO uint32_t MISC2_CLR;                         /**< Miscellaneous Register 2, offset: 0x178 */
7271   __IO uint32_t MISC2_TOG;                         /**< Miscellaneous Register 2, offset: 0x17C */
7272 } CCM_ANALOG_Type;
7273 
7274 /* ----------------------------------------------------------------------------
7275    -- CCM_ANALOG Register Masks
7276    ---------------------------------------------------------------------------- */
7277 
7278 /*!
7279  * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
7280  * @{
7281  */
7282 
7283 /*! @name PLL_ARM - Analog ARM PLL control Register */
7284 /*! @{ */
7285 
7286 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK       (0x7FU)
7287 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT      (0U)
7288 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
7289 
7290 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK        (0x1000U)
7291 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT       (12U)
7292 #define CCM_ANALOG_PLL_ARM_POWERDOWN(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
7293 
7294 #define CCM_ANALOG_PLL_ARM_ENABLE_MASK           (0x2000U)
7295 #define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT          (13U)
7296 #define CCM_ANALOG_PLL_ARM_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
7297 
7298 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK   (0xC000U)
7299 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT  (14U)
7300 /*! BYPASS_CLK_SRC
7301  *  0b00..Select the 24MHz oscillator as source.
7302  *  0b01..Select the CLK1_N / CLK1_P as source.
7303  *  0b10..Reserved1
7304  *  0b11..Reserved2
7305  */
7306 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
7307 
7308 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK           (0x10000U)
7309 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT          (16U)
7310 #define CCM_ANALOG_PLL_ARM_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
7311 
7312 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK          (0x80000U)
7313 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT         (19U)
7314 #define CCM_ANALOG_PLL_ARM_PLL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
7315 
7316 #define CCM_ANALOG_PLL_ARM_LOCK_MASK             (0x80000000U)
7317 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT            (31U)
7318 #define CCM_ANALOG_PLL_ARM_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
7319 /*! @} */
7320 
7321 /*! @name PLL_ARM_SET - Analog ARM PLL control Register */
7322 /*! @{ */
7323 
7324 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK   (0x7FU)
7325 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT  (0U)
7326 #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
7327 
7328 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK    (0x1000U)
7329 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT   (12U)
7330 #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
7331 
7332 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK       (0x2000U)
7333 #define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT      (13U)
7334 #define CCM_ANALOG_PLL_ARM_SET_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
7335 
7336 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7337 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
7338 /*! BYPASS_CLK_SRC
7339  *  0b00..Select the 24MHz oscillator as source.
7340  *  0b01..Select the CLK1_N / CLK1_P as source.
7341  *  0b10..Reserved1
7342  *  0b11..Reserved2
7343  */
7344 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
7345 
7346 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK       (0x10000U)
7347 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT      (16U)
7348 #define CCM_ANALOG_PLL_ARM_SET_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
7349 
7350 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK      (0x80000U)
7351 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT     (19U)
7352 #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
7353 
7354 #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK         (0x80000000U)
7355 #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT        (31U)
7356 #define CCM_ANALOG_PLL_ARM_SET_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
7357 /*! @} */
7358 
7359 /*! @name PLL_ARM_CLR - Analog ARM PLL control Register */
7360 /*! @{ */
7361 
7362 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK   (0x7FU)
7363 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT  (0U)
7364 #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
7365 
7366 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK    (0x1000U)
7367 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT   (12U)
7368 #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
7369 
7370 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK       (0x2000U)
7371 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT      (13U)
7372 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
7373 
7374 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7375 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7376 /*! BYPASS_CLK_SRC
7377  *  0b00..Select the 24MHz oscillator as source.
7378  *  0b01..Select the CLK1_N / CLK1_P as source.
7379  *  0b10..Reserved1
7380  *  0b11..Reserved2
7381  */
7382 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
7383 
7384 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK       (0x10000U)
7385 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT      (16U)
7386 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
7387 
7388 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK      (0x80000U)
7389 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT     (19U)
7390 #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
7391 
7392 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK         (0x80000000U)
7393 #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT        (31U)
7394 #define CCM_ANALOG_PLL_ARM_CLR_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
7395 /*! @} */
7396 
7397 /*! @name PLL_ARM_TOG - Analog ARM PLL control Register */
7398 /*! @{ */
7399 
7400 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK   (0x7FU)
7401 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT  (0U)
7402 #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
7403 
7404 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK    (0x1000U)
7405 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT   (12U)
7406 #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
7407 
7408 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK       (0x2000U)
7409 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT      (13U)
7410 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
7411 
7412 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7413 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7414 /*! BYPASS_CLK_SRC
7415  *  0b00..Select the 24MHz oscillator as source.
7416  *  0b01..Select the CLK1_N / CLK1_P as source.
7417  *  0b10..Reserved1
7418  *  0b11..Reserved2
7419  */
7420 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
7421 
7422 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK       (0x10000U)
7423 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT      (16U)
7424 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
7425 
7426 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK      (0x80000U)
7427 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT     (19U)
7428 #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
7429 
7430 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK         (0x80000000U)
7431 #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT        (31U)
7432 #define CCM_ANALOG_PLL_ARM_TOG_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
7433 /*! @} */
7434 
7435 /*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
7436 /*! @{ */
7437 
7438 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK      (0x2U)
7439 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT     (1U)
7440 #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
7441 
7442 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK     (0x40U)
7443 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT    (6U)
7444 /*! EN_USB_CLKS
7445  *  0b0..PLL outputs for USBPHYn off.
7446  *  0b1..PLL outputs for USBPHYn on.
7447  */
7448 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
7449 
7450 #define CCM_ANALOG_PLL_USB1_POWER_MASK           (0x1000U)
7451 #define CCM_ANALOG_PLL_USB1_POWER_SHIFT          (12U)
7452 #define CCM_ANALOG_PLL_USB1_POWER(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
7453 
7454 #define CCM_ANALOG_PLL_USB1_ENABLE_MASK          (0x2000U)
7455 #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT         (13U)
7456 #define CCM_ANALOG_PLL_USB1_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
7457 
7458 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK  (0xC000U)
7459 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
7460 /*! BYPASS_CLK_SRC
7461  *  0b00..Select the 24MHz oscillator as source.
7462  *  0b01..Select the CLK1_N / CLK1_P as source.
7463  */
7464 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
7465 
7466 #define CCM_ANALOG_PLL_USB1_BYPASS_MASK          (0x10000U)
7467 #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT         (16U)
7468 #define CCM_ANALOG_PLL_USB1_BYPASS(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
7469 
7470 #define CCM_ANALOG_PLL_USB1_LOCK_MASK            (0x80000000U)
7471 #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT           (31U)
7472 #define CCM_ANALOG_PLL_USB1_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
7473 /*! @} */
7474 
7475 /*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
7476 /*! @{ */
7477 
7478 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK  (0x2U)
7479 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
7480 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
7481 
7482 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
7483 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
7484 /*! EN_USB_CLKS
7485  *  0b0..PLL outputs for USBPHYn off.
7486  *  0b1..PLL outputs for USBPHYn on.
7487  */
7488 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
7489 
7490 #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK       (0x1000U)
7491 #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT      (12U)
7492 #define CCM_ANALOG_PLL_USB1_SET_POWER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
7493 
7494 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK      (0x2000U)
7495 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT     (13U)
7496 #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
7497 
7498 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7499 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
7500 /*! BYPASS_CLK_SRC
7501  *  0b00..Select the 24MHz oscillator as source.
7502  *  0b01..Select the CLK1_N / CLK1_P as source.
7503  */
7504 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
7505 
7506 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK      (0x10000U)
7507 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT     (16U)
7508 #define CCM_ANALOG_PLL_USB1_SET_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
7509 
7510 #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK        (0x80000000U)
7511 #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT       (31U)
7512 #define CCM_ANALOG_PLL_USB1_SET_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
7513 /*! @} */
7514 
7515 /*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
7516 /*! @{ */
7517 
7518 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK  (0x2U)
7519 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
7520 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
7521 
7522 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
7523 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
7524 /*! EN_USB_CLKS
7525  *  0b0..PLL outputs for USBPHYn off.
7526  *  0b1..PLL outputs for USBPHYn on.
7527  */
7528 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
7529 
7530 #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK       (0x1000U)
7531 #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT      (12U)
7532 #define CCM_ANALOG_PLL_USB1_CLR_POWER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
7533 
7534 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK      (0x2000U)
7535 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT     (13U)
7536 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
7537 
7538 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7539 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7540 /*! BYPASS_CLK_SRC
7541  *  0b00..Select the 24MHz oscillator as source.
7542  *  0b01..Select the CLK1_N / CLK1_P as source.
7543  */
7544 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
7545 
7546 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK      (0x10000U)
7547 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT     (16U)
7548 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
7549 
7550 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK        (0x80000000U)
7551 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT       (31U)
7552 #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
7553 /*! @} */
7554 
7555 /*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
7556 /*! @{ */
7557 
7558 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK  (0x2U)
7559 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
7560 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
7561 
7562 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
7563 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
7564 /*! EN_USB_CLKS
7565  *  0b0..PLL outputs for USBPHYn off.
7566  *  0b1..PLL outputs for USBPHYn on.
7567  */
7568 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
7569 
7570 #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK       (0x1000U)
7571 #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT      (12U)
7572 #define CCM_ANALOG_PLL_USB1_TOG_POWER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
7573 
7574 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK      (0x2000U)
7575 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT     (13U)
7576 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
7577 
7578 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7579 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7580 /*! BYPASS_CLK_SRC
7581  *  0b00..Select the 24MHz oscillator as source.
7582  *  0b01..Select the CLK1_N / CLK1_P as source.
7583  */
7584 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
7585 
7586 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK      (0x10000U)
7587 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT     (16U)
7588 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
7589 
7590 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK        (0x80000000U)
7591 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT       (31U)
7592 #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
7593 /*! @} */
7594 
7595 /*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */
7596 /*! @{ */
7597 
7598 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK      (0x2U)
7599 #define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT     (1U)
7600 #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
7601 
7602 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK     (0x40U)
7603 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT    (6U)
7604 #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
7605 
7606 #define CCM_ANALOG_PLL_USB2_POWER_MASK           (0x1000U)
7607 #define CCM_ANALOG_PLL_USB2_POWER_SHIFT          (12U)
7608 #define CCM_ANALOG_PLL_USB2_POWER(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
7609 
7610 #define CCM_ANALOG_PLL_USB2_ENABLE_MASK          (0x2000U)
7611 #define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT         (13U)
7612 #define CCM_ANALOG_PLL_USB2_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
7613 
7614 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK  (0xC000U)
7615 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
7616 /*! BYPASS_CLK_SRC
7617  *  0b00..Select the 24MHz oscillator as source.
7618  *  0b01..Select the CLK1_N / CLK1_P as source.
7619  *  0b10..Reserved1
7620  *  0b11..Reserved2
7621  */
7622 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
7623 
7624 #define CCM_ANALOG_PLL_USB2_BYPASS_MASK          (0x10000U)
7625 #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT         (16U)
7626 #define CCM_ANALOG_PLL_USB2_BYPASS(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
7627 
7628 #define CCM_ANALOG_PLL_USB2_LOCK_MASK            (0x80000000U)
7629 #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT           (31U)
7630 #define CCM_ANALOG_PLL_USB2_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
7631 /*! @} */
7632 
7633 /*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */
7634 /*! @{ */
7635 
7636 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK  (0x2U)
7637 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
7638 #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
7639 
7640 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
7641 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
7642 #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
7643 
7644 #define CCM_ANALOG_PLL_USB2_SET_POWER_MASK       (0x1000U)
7645 #define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT      (12U)
7646 #define CCM_ANALOG_PLL_USB2_SET_POWER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
7647 
7648 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK      (0x2000U)
7649 #define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT     (13U)
7650 #define CCM_ANALOG_PLL_USB2_SET_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
7651 
7652 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7653 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
7654 /*! BYPASS_CLK_SRC
7655  *  0b00..Select the 24MHz oscillator as source.
7656  *  0b01..Select the CLK1_N / CLK1_P as source.
7657  *  0b10..Reserved1
7658  *  0b11..Reserved2
7659  */
7660 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
7661 
7662 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK      (0x10000U)
7663 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT     (16U)
7664 #define CCM_ANALOG_PLL_USB2_SET_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
7665 
7666 #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK        (0x80000000U)
7667 #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT       (31U)
7668 #define CCM_ANALOG_PLL_USB2_SET_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
7669 /*! @} */
7670 
7671 /*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */
7672 /*! @{ */
7673 
7674 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK  (0x2U)
7675 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
7676 #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
7677 
7678 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
7679 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
7680 #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
7681 
7682 #define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK       (0x1000U)
7683 #define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT      (12U)
7684 #define CCM_ANALOG_PLL_USB2_CLR_POWER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
7685 
7686 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK      (0x2000U)
7687 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT     (13U)
7688 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
7689 
7690 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7691 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7692 /*! BYPASS_CLK_SRC
7693  *  0b00..Select the 24MHz oscillator as source.
7694  *  0b01..Select the CLK1_N / CLK1_P as source.
7695  *  0b10..Reserved1
7696  *  0b11..Reserved2
7697  */
7698 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
7699 
7700 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK      (0x10000U)
7701 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT     (16U)
7702 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
7703 
7704 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK        (0x80000000U)
7705 #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT       (31U)
7706 #define CCM_ANALOG_PLL_USB2_CLR_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
7707 /*! @} */
7708 
7709 /*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */
7710 /*! @{ */
7711 
7712 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK  (0x2U)
7713 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
7714 #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
7715 
7716 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
7717 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
7718 #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
7719 
7720 #define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK       (0x1000U)
7721 #define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT      (12U)
7722 #define CCM_ANALOG_PLL_USB2_TOG_POWER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
7723 
7724 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK      (0x2000U)
7725 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT     (13U)
7726 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
7727 
7728 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7729 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7730 /*! BYPASS_CLK_SRC
7731  *  0b00..Select the 24MHz oscillator as source.
7732  *  0b01..Select the CLK1_N / CLK1_P as source.
7733  *  0b10..Reserved1
7734  *  0b11..Reserved2
7735  */
7736 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
7737 
7738 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK      (0x10000U)
7739 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT     (16U)
7740 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
7741 
7742 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK        (0x80000000U)
7743 #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT       (31U)
7744 #define CCM_ANALOG_PLL_USB2_TOG_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
7745 /*! @} */
7746 
7747 /*! @name PLL_SYS - Analog System PLL Control Register */
7748 /*! @{ */
7749 
7750 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK       (0x1U)
7751 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT      (0U)
7752 #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
7753 
7754 #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK        (0x1000U)
7755 #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT       (12U)
7756 #define CCM_ANALOG_PLL_SYS_POWERDOWN(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
7757 
7758 #define CCM_ANALOG_PLL_SYS_ENABLE_MASK           (0x2000U)
7759 #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT          (13U)
7760 #define CCM_ANALOG_PLL_SYS_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
7761 
7762 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK   (0xC000U)
7763 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT  (14U)
7764 /*! BYPASS_CLK_SRC
7765  *  0b00..Select the 24MHz oscillator as source.
7766  *  0b01..Select the CLK1_N / CLK1_P as source.
7767  */
7768 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
7769 
7770 #define CCM_ANALOG_PLL_SYS_BYPASS_MASK           (0x10000U)
7771 #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT          (16U)
7772 #define CCM_ANALOG_PLL_SYS_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
7773 
7774 #define CCM_ANALOG_PLL_SYS_LOCK_MASK             (0x80000000U)
7775 #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT            (31U)
7776 #define CCM_ANALOG_PLL_SYS_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
7777 /*! @} */
7778 
7779 /*! @name PLL_SYS_SET - Analog System PLL Control Register */
7780 /*! @{ */
7781 
7782 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK   (0x1U)
7783 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT  (0U)
7784 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
7785 
7786 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK    (0x1000U)
7787 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT   (12U)
7788 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
7789 
7790 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK       (0x2000U)
7791 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT      (13U)
7792 #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
7793 
7794 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7795 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
7796 /*! BYPASS_CLK_SRC
7797  *  0b00..Select the 24MHz oscillator as source.
7798  *  0b01..Select the CLK1_N / CLK1_P as source.
7799  */
7800 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
7801 
7802 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK       (0x10000U)
7803 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT      (16U)
7804 #define CCM_ANALOG_PLL_SYS_SET_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
7805 
7806 #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK         (0x80000000U)
7807 #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT        (31U)
7808 #define CCM_ANALOG_PLL_SYS_SET_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
7809 /*! @} */
7810 
7811 /*! @name PLL_SYS_CLR - Analog System PLL Control Register */
7812 /*! @{ */
7813 
7814 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK   (0x1U)
7815 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT  (0U)
7816 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
7817 
7818 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK    (0x1000U)
7819 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT   (12U)
7820 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
7821 
7822 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK       (0x2000U)
7823 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT      (13U)
7824 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
7825 
7826 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7827 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7828 /*! BYPASS_CLK_SRC
7829  *  0b00..Select the 24MHz oscillator as source.
7830  *  0b01..Select the CLK1_N / CLK1_P as source.
7831  */
7832 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
7833 
7834 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK       (0x10000U)
7835 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT      (16U)
7836 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
7837 
7838 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK         (0x80000000U)
7839 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT        (31U)
7840 #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
7841 /*! @} */
7842 
7843 /*! @name PLL_SYS_TOG - Analog System PLL Control Register */
7844 /*! @{ */
7845 
7846 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK   (0x1U)
7847 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT  (0U)
7848 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
7849 
7850 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK    (0x1000U)
7851 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT   (12U)
7852 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
7853 
7854 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK       (0x2000U)
7855 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT      (13U)
7856 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
7857 
7858 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7859 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7860 /*! BYPASS_CLK_SRC
7861  *  0b00..Select the 24MHz oscillator as source.
7862  *  0b01..Select the CLK1_N / CLK1_P as source.
7863  */
7864 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
7865 
7866 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK       (0x10000U)
7867 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT      (16U)
7868 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
7869 
7870 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK         (0x80000000U)
7871 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT        (31U)
7872 #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
7873 /*! @} */
7874 
7875 /*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
7876 /*! @{ */
7877 
7878 #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK          (0x7FFFU)
7879 #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT         (0U)
7880 #define CCM_ANALOG_PLL_SYS_SS_STEP(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
7881 
7882 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK        (0x8000U)
7883 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT       (15U)
7884 /*! ENABLE - Enable bit
7885  *  0b0..Spread spectrum modulation disabled
7886  *  0b1..Soread spectrum modulation enabled
7887  */
7888 #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
7889 
7890 #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK          (0xFFFF0000U)
7891 #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT         (16U)
7892 #define CCM_ANALOG_PLL_SYS_SS_STOP(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
7893 /*! @} */
7894 
7895 /*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
7896 /*! @{ */
7897 
7898 #define CCM_ANALOG_PLL_SYS_NUM_A_MASK            (0x3FFFFFFFU)
7899 #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT           (0U)
7900 #define CCM_ANALOG_PLL_SYS_NUM_A(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
7901 /*! @} */
7902 
7903 /*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
7904 /*! @{ */
7905 
7906 #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK          (0x3FFFFFFFU)
7907 #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT         (0U)
7908 #define CCM_ANALOG_PLL_SYS_DENOM_B(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
7909 /*! @} */
7910 
7911 /*! @name PLL_AUDIO - Analog Audio PLL control Register */
7912 /*! @{ */
7913 
7914 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK     (0x7FU)
7915 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT    (0U)
7916 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
7917 
7918 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK      (0x1000U)
7919 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT     (12U)
7920 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
7921 
7922 #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK         (0x2000U)
7923 #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT        (13U)
7924 #define CCM_ANALOG_PLL_AUDIO_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
7925 
7926 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
7927 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
7928 /*! BYPASS_CLK_SRC
7929  *  0b00..Select the 24MHz oscillator as source.
7930  *  0b01..Select the CLK1_N / CLK1_P as source.
7931  *  0b10..Reserved1
7932  *  0b11..Reserved2
7933  */
7934 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
7935 
7936 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK         (0x10000U)
7937 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT        (16U)
7938 #define CCM_ANALOG_PLL_AUDIO_BYPASS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
7939 
7940 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
7941 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
7942 /*! POST_DIV_SELECT
7943  *  0b00..Divide by 4.
7944  *  0b01..Divide by 2.
7945  *  0b10..Divide by 1.
7946  *  0b11..Reserved
7947  */
7948 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
7949 
7950 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK           (0x80000000U)
7951 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT          (31U)
7952 #define CCM_ANALOG_PLL_AUDIO_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
7953 /*! @} */
7954 
7955 /*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
7956 /*! @{ */
7957 
7958 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
7959 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
7960 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
7961 
7962 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK  (0x1000U)
7963 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
7964 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
7965 
7966 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK     (0x2000U)
7967 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT    (13U)
7968 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
7969 
7970 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7971 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
7972 /*! BYPASS_CLK_SRC
7973  *  0b00..Select the 24MHz oscillator as source.
7974  *  0b01..Select the CLK1_N / CLK1_P as source.
7975  *  0b10..Reserved1
7976  *  0b11..Reserved2
7977  */
7978 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
7979 
7980 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK     (0x10000U)
7981 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT    (16U)
7982 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
7983 
7984 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
7985 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
7986 /*! POST_DIV_SELECT
7987  *  0b00..Divide by 4.
7988  *  0b01..Divide by 2.
7989  *  0b10..Divide by 1.
7990  *  0b11..Reserved
7991  */
7992 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
7993 
7994 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK       (0x80000000U)
7995 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT      (31U)
7996 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
7997 /*! @} */
7998 
7999 /*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
8000 /*! @{ */
8001 
8002 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
8003 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
8004 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
8005 
8006 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK  (0x1000U)
8007 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
8008 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
8009 
8010 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK     (0x2000U)
8011 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT    (13U)
8012 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
8013 
8014 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8015 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8016 /*! BYPASS_CLK_SRC
8017  *  0b00..Select the 24MHz oscillator as source.
8018  *  0b01..Select the CLK1_N / CLK1_P as source.
8019  *  0b10..Reserved1
8020  *  0b11..Reserved2
8021  */
8022 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
8023 
8024 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK     (0x10000U)
8025 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT    (16U)
8026 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
8027 
8028 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
8029 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
8030 /*! POST_DIV_SELECT
8031  *  0b00..Divide by 4.
8032  *  0b01..Divide by 2.
8033  *  0b10..Divide by 1.
8034  *  0b11..Reserved
8035  */
8036 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
8037 
8038 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK       (0x80000000U)
8039 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT      (31U)
8040 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
8041 /*! @} */
8042 
8043 /*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
8044 /*! @{ */
8045 
8046 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
8047 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
8048 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
8049 
8050 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK  (0x1000U)
8051 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
8052 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
8053 
8054 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK     (0x2000U)
8055 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT    (13U)
8056 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
8057 
8058 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8059 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8060 /*! BYPASS_CLK_SRC
8061  *  0b00..Select the 24MHz oscillator as source.
8062  *  0b01..Select the CLK1_N / CLK1_P as source.
8063  *  0b10..Reserved1
8064  *  0b11..Reserved2
8065  */
8066 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
8067 
8068 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK     (0x10000U)
8069 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT    (16U)
8070 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
8071 
8072 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
8073 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
8074 /*! POST_DIV_SELECT
8075  *  0b00..Divide by 4.
8076  *  0b01..Divide by 2.
8077  *  0b10..Divide by 1.
8078  *  0b11..Reserved
8079  */
8080 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
8081 
8082 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK       (0x80000000U)
8083 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT      (31U)
8084 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
8085 /*! @} */
8086 
8087 /*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
8088 /*! @{ */
8089 
8090 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK          (0x3FFFFFFFU)
8091 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT         (0U)
8092 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
8093 /*! @} */
8094 
8095 /*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
8096 /*! @{ */
8097 
8098 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK        (0x3FFFFFFFU)
8099 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT       (0U)
8100 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
8101 /*! @} */
8102 
8103 /*! @name PLL_VIDEO - Analog Video PLL control Register */
8104 /*! @{ */
8105 
8106 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK     (0x7FU)
8107 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT    (0U)
8108 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
8109 
8110 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK      (0x1000U)
8111 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT     (12U)
8112 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
8113 
8114 #define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK         (0x2000U)
8115 #define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT        (13U)
8116 #define CCM_ANALOG_PLL_VIDEO_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
8117 
8118 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
8119 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
8120 /*! BYPASS_CLK_SRC
8121  *  0b00..Select the 24MHz oscillator as source.
8122  *  0b01..Select the CLK1_N / CLK1_P as source.
8123  *  0b10..Reserved1
8124  *  0b11..Reserved2
8125  */
8126 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
8127 
8128 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK         (0x10000U)
8129 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT        (16U)
8130 #define CCM_ANALOG_PLL_VIDEO_BYPASS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
8131 
8132 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
8133 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
8134 /*! POST_DIV_SELECT
8135  *  0b00..Divide by 4.
8136  *  0b01..Divide by 2.
8137  *  0b10..Divide by 1.
8138  *  0b11..Reserved
8139  */
8140 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
8141 
8142 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK           (0x80000000U)
8143 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT          (31U)
8144 #define CCM_ANALOG_PLL_VIDEO_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
8145 /*! @} */
8146 
8147 /*! @name PLL_VIDEO_SET - Analog Video PLL control Register */
8148 /*! @{ */
8149 
8150 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
8151 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
8152 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
8153 
8154 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK  (0x1000U)
8155 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
8156 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
8157 
8158 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK     (0x2000U)
8159 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT    (13U)
8160 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
8161 
8162 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8163 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
8164 /*! BYPASS_CLK_SRC
8165  *  0b00..Select the 24MHz oscillator as source.
8166  *  0b01..Select the CLK1_N / CLK1_P as source.
8167  *  0b10..Reserved1
8168  *  0b11..Reserved2
8169  */
8170 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
8171 
8172 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK     (0x10000U)
8173 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT    (16U)
8174 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
8175 
8176 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
8177 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
8178 /*! POST_DIV_SELECT
8179  *  0b00..Divide by 4.
8180  *  0b01..Divide by 2.
8181  *  0b10..Divide by 1.
8182  *  0b11..Reserved
8183  */
8184 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
8185 
8186 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK       (0x80000000U)
8187 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT      (31U)
8188 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
8189 /*! @} */
8190 
8191 /*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */
8192 /*! @{ */
8193 
8194 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
8195 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
8196 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
8197 
8198 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK  (0x1000U)
8199 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
8200 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
8201 
8202 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK     (0x2000U)
8203 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT    (13U)
8204 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
8205 
8206 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8207 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8208 /*! BYPASS_CLK_SRC
8209  *  0b00..Select the 24MHz oscillator as source.
8210  *  0b01..Select the CLK1_N / CLK1_P as source.
8211  *  0b10..Reserved1
8212  *  0b11..Reserved2
8213  */
8214 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
8215 
8216 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK     (0x10000U)
8217 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT    (16U)
8218 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
8219 
8220 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
8221 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
8222 /*! POST_DIV_SELECT
8223  *  0b00..Divide by 4.
8224  *  0b01..Divide by 2.
8225  *  0b10..Divide by 1.
8226  *  0b11..Reserved
8227  */
8228 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
8229 
8230 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK       (0x80000000U)
8231 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT      (31U)
8232 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
8233 /*! @} */
8234 
8235 /*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */
8236 /*! @{ */
8237 
8238 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
8239 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
8240 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
8241 
8242 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK  (0x1000U)
8243 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
8244 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
8245 
8246 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK     (0x2000U)
8247 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT    (13U)
8248 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
8249 
8250 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8251 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8252 /*! BYPASS_CLK_SRC
8253  *  0b00..Select the 24MHz oscillator as source.
8254  *  0b01..Select the CLK1_N / CLK1_P as source.
8255  *  0b10..Reserved1
8256  *  0b11..Reserved2
8257  */
8258 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
8259 
8260 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK     (0x10000U)
8261 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT    (16U)
8262 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
8263 
8264 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
8265 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
8266 /*! POST_DIV_SELECT
8267  *  0b00..Divide by 4.
8268  *  0b01..Divide by 2.
8269  *  0b10..Divide by 1.
8270  *  0b11..Reserved
8271  */
8272 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
8273 
8274 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK       (0x80000000U)
8275 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT      (31U)
8276 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
8277 /*! @} */
8278 
8279 /*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */
8280 /*! @{ */
8281 
8282 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK          (0x3FFFFFFFU)
8283 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT         (0U)
8284 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
8285 /*! @} */
8286 
8287 /*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */
8288 /*! @{ */
8289 
8290 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK        (0x3FFFFFFFU)
8291 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT       (0U)
8292 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
8293 /*! @} */
8294 
8295 /*! @name PLL_ENET - Analog ENET PLL Control Register */
8296 /*! @{ */
8297 
8298 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK      (0x3U)
8299 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT     (0U)
8300 #define CCM_ANALOG_PLL_ENET_DIV_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
8301 
8302 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK       (0x1000U)
8303 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT      (12U)
8304 #define CCM_ANALOG_PLL_ENET_POWERDOWN(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
8305 
8306 #define CCM_ANALOG_PLL_ENET_ENABLE_MASK          (0x2000U)
8307 #define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT         (13U)
8308 #define CCM_ANALOG_PLL_ENET_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
8309 
8310 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK  (0xC000U)
8311 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
8312 /*! BYPASS_CLK_SRC
8313  *  0b00..Select the 24MHz oscillator as source.
8314  *  0b01..Select the CLK1_N / CLK1_P as source.
8315  *  0b10..Reserved1
8316  *  0b11..Reserved2
8317  */
8318 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
8319 
8320 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK          (0x10000U)
8321 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT         (16U)
8322 #define CCM_ANALOG_PLL_ENET_BYPASS(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
8323 
8324 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
8325 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
8326 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
8327 
8328 #define CCM_ANALOG_PLL_ENET_LOCK_MASK            (0x80000000U)
8329 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT           (31U)
8330 #define CCM_ANALOG_PLL_ENET_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
8331 /*! @} */
8332 
8333 /*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
8334 /*! @{ */
8335 
8336 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK  (0x3U)
8337 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
8338 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
8339 
8340 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK   (0x1000U)
8341 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT  (12U)
8342 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
8343 
8344 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK      (0x2000U)
8345 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT     (13U)
8346 #define CCM_ANALOG_PLL_ENET_SET_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
8347 
8348 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8349 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
8350 /*! BYPASS_CLK_SRC
8351  *  0b00..Select the 24MHz oscillator as source.
8352  *  0b01..Select the CLK1_N / CLK1_P as source.
8353  *  0b10..Reserved1
8354  *  0b11..Reserved2
8355  */
8356 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
8357 
8358 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK      (0x10000U)
8359 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT     (16U)
8360 #define CCM_ANALOG_PLL_ENET_SET_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
8361 
8362 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
8363 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
8364 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
8365 
8366 #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK        (0x80000000U)
8367 #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT       (31U)
8368 #define CCM_ANALOG_PLL_ENET_SET_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
8369 /*! @} */
8370 
8371 /*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
8372 /*! @{ */
8373 
8374 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK  (0x3U)
8375 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
8376 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
8377 
8378 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK   (0x1000U)
8379 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT  (12U)
8380 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
8381 
8382 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK      (0x2000U)
8383 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT     (13U)
8384 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
8385 
8386 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8387 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8388 /*! BYPASS_CLK_SRC
8389  *  0b00..Select the 24MHz oscillator as source.
8390  *  0b01..Select the CLK1_N / CLK1_P as source.
8391  *  0b10..Reserved1
8392  *  0b11..Reserved2
8393  */
8394 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
8395 
8396 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK      (0x10000U)
8397 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT     (16U)
8398 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
8399 
8400 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
8401 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
8402 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
8403 
8404 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK        (0x80000000U)
8405 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT       (31U)
8406 #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
8407 /*! @} */
8408 
8409 /*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
8410 /*! @{ */
8411 
8412 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK  (0x3U)
8413 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
8414 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
8415 
8416 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK   (0x1000U)
8417 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT  (12U)
8418 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
8419 
8420 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK      (0x2000U)
8421 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT     (13U)
8422 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
8423 
8424 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8425 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8426 /*! BYPASS_CLK_SRC
8427  *  0b00..Select the 24MHz oscillator as source.
8428  *  0b01..Select the CLK1_N / CLK1_P as source.
8429  *  0b10..Reserved1
8430  *  0b11..Reserved2
8431  */
8432 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
8433 
8434 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK      (0x10000U)
8435 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT     (16U)
8436 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
8437 
8438 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
8439 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
8440 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
8441 
8442 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK        (0x80000000U)
8443 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT       (31U)
8444 #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
8445 /*! @} */
8446 
8447 /*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8448 /*! @{ */
8449 
8450 #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK        (0x3FU)
8451 #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT       (0U)
8452 #define CCM_ANALOG_PFD_480_PFD0_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
8453 
8454 #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK      (0x40U)
8455 #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT     (6U)
8456 #define CCM_ANALOG_PFD_480_PFD0_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
8457 
8458 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK     (0x80U)
8459 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT    (7U)
8460 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
8461 
8462 #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK        (0x3F00U)
8463 #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT       (8U)
8464 #define CCM_ANALOG_PFD_480_PFD1_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
8465 
8466 #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK      (0x4000U)
8467 #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT     (14U)
8468 #define CCM_ANALOG_PFD_480_PFD1_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
8469 
8470 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK     (0x8000U)
8471 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT    (15U)
8472 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
8473 
8474 #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK        (0x3F0000U)
8475 #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT       (16U)
8476 #define CCM_ANALOG_PFD_480_PFD2_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
8477 
8478 #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK      (0x400000U)
8479 #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT     (22U)
8480 #define CCM_ANALOG_PFD_480_PFD2_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
8481 
8482 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK     (0x800000U)
8483 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT    (23U)
8484 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
8485 
8486 #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK        (0x3F000000U)
8487 #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT       (24U)
8488 #define CCM_ANALOG_PFD_480_PFD3_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
8489 
8490 #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK      (0x40000000U)
8491 #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT     (30U)
8492 #define CCM_ANALOG_PFD_480_PFD3_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
8493 
8494 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK     (0x80000000U)
8495 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT    (31U)
8496 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
8497 /*! @} */
8498 
8499 /*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8500 /*! @{ */
8501 
8502 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK    (0x3FU)
8503 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT   (0U)
8504 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
8505 
8506 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK  (0x40U)
8507 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
8508 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
8509 
8510 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
8511 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
8512 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
8513 
8514 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK    (0x3F00U)
8515 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT   (8U)
8516 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
8517 
8518 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK  (0x4000U)
8519 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
8520 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
8521 
8522 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
8523 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
8524 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
8525 
8526 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK    (0x3F0000U)
8527 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT   (16U)
8528 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
8529 
8530 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK  (0x400000U)
8531 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
8532 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
8533 
8534 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
8535 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
8536 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
8537 
8538 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK    (0x3F000000U)
8539 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT   (24U)
8540 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
8541 
8542 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK  (0x40000000U)
8543 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
8544 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
8545 
8546 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
8547 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
8548 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
8549 /*! @} */
8550 
8551 /*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8552 /*! @{ */
8553 
8554 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK    (0x3FU)
8555 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT   (0U)
8556 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
8557 
8558 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK  (0x40U)
8559 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
8560 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
8561 
8562 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
8563 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
8564 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
8565 
8566 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK    (0x3F00U)
8567 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT   (8U)
8568 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
8569 
8570 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK  (0x4000U)
8571 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
8572 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
8573 
8574 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
8575 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
8576 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
8577 
8578 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK    (0x3F0000U)
8579 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT   (16U)
8580 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
8581 
8582 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK  (0x400000U)
8583 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
8584 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
8585 
8586 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
8587 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
8588 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
8589 
8590 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK    (0x3F000000U)
8591 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT   (24U)
8592 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
8593 
8594 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK  (0x40000000U)
8595 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
8596 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
8597 
8598 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8599 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
8600 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
8601 /*! @} */
8602 
8603 /*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8604 /*! @{ */
8605 
8606 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK    (0x3FU)
8607 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT   (0U)
8608 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
8609 
8610 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK  (0x40U)
8611 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
8612 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
8613 
8614 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
8615 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
8616 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
8617 
8618 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK    (0x3F00U)
8619 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT   (8U)
8620 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
8621 
8622 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK  (0x4000U)
8623 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
8624 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
8625 
8626 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
8627 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
8628 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
8629 
8630 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK    (0x3F0000U)
8631 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT   (16U)
8632 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
8633 
8634 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK  (0x400000U)
8635 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
8636 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
8637 
8638 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
8639 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
8640 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
8641 
8642 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK    (0x3F000000U)
8643 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT   (24U)
8644 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
8645 
8646 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK  (0x40000000U)
8647 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
8648 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
8649 
8650 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8651 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
8652 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
8653 /*! @} */
8654 
8655 /*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8656 /*! @{ */
8657 
8658 #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK        (0x3FU)
8659 #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT       (0U)
8660 #define CCM_ANALOG_PFD_528_PFD0_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
8661 
8662 #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK      (0x40U)
8663 #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT     (6U)
8664 #define CCM_ANALOG_PFD_528_PFD0_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
8665 
8666 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK     (0x80U)
8667 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT    (7U)
8668 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
8669 
8670 #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK        (0x3F00U)
8671 #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT       (8U)
8672 #define CCM_ANALOG_PFD_528_PFD1_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
8673 
8674 #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK      (0x4000U)
8675 #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT     (14U)
8676 #define CCM_ANALOG_PFD_528_PFD1_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
8677 
8678 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK     (0x8000U)
8679 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT    (15U)
8680 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
8681 
8682 #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK        (0x3F0000U)
8683 #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT       (16U)
8684 #define CCM_ANALOG_PFD_528_PFD2_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
8685 
8686 #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK      (0x400000U)
8687 #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT     (22U)
8688 #define CCM_ANALOG_PFD_528_PFD2_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
8689 
8690 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK     (0x800000U)
8691 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT    (23U)
8692 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
8693 
8694 #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK        (0x3F000000U)
8695 #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT       (24U)
8696 #define CCM_ANALOG_PFD_528_PFD3_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
8697 
8698 #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK      (0x40000000U)
8699 #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT     (30U)
8700 #define CCM_ANALOG_PFD_528_PFD3_STABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
8701 
8702 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK     (0x80000000U)
8703 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT    (31U)
8704 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
8705 /*! @} */
8706 
8707 /*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8708 /*! @{ */
8709 
8710 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK    (0x3FU)
8711 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT   (0U)
8712 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
8713 
8714 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK  (0x40U)
8715 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
8716 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
8717 
8718 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
8719 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
8720 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
8721 
8722 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK    (0x3F00U)
8723 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT   (8U)
8724 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
8725 
8726 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK  (0x4000U)
8727 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
8728 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
8729 
8730 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
8731 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
8732 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
8733 
8734 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK    (0x3F0000U)
8735 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT   (16U)
8736 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
8737 
8738 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK  (0x400000U)
8739 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
8740 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
8741 
8742 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
8743 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
8744 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
8745 
8746 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK    (0x3F000000U)
8747 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT   (24U)
8748 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
8749 
8750 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK  (0x40000000U)
8751 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
8752 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
8753 
8754 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
8755 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
8756 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
8757 /*! @} */
8758 
8759 /*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8760 /*! @{ */
8761 
8762 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK    (0x3FU)
8763 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT   (0U)
8764 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
8765 
8766 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK  (0x40U)
8767 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
8768 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
8769 
8770 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
8771 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
8772 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
8773 
8774 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK    (0x3F00U)
8775 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT   (8U)
8776 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
8777 
8778 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK  (0x4000U)
8779 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
8780 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
8781 
8782 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
8783 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
8784 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
8785 
8786 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK    (0x3F0000U)
8787 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT   (16U)
8788 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
8789 
8790 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK  (0x400000U)
8791 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
8792 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
8793 
8794 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
8795 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
8796 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
8797 
8798 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK    (0x3F000000U)
8799 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT   (24U)
8800 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
8801 
8802 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK  (0x40000000U)
8803 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
8804 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
8805 
8806 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8807 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
8808 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
8809 /*! @} */
8810 
8811 /*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8812 /*! @{ */
8813 
8814 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK    (0x3FU)
8815 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT   (0U)
8816 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
8817 
8818 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK  (0x40U)
8819 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
8820 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
8821 
8822 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
8823 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
8824 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
8825 
8826 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK    (0x3F00U)
8827 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT   (8U)
8828 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
8829 
8830 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK  (0x4000U)
8831 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
8832 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
8833 
8834 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
8835 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
8836 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
8837 
8838 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK    (0x3F0000U)
8839 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT   (16U)
8840 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
8841 
8842 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK  (0x400000U)
8843 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
8844 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
8845 
8846 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
8847 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
8848 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
8849 
8850 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK    (0x3F000000U)
8851 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT   (24U)
8852 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
8853 
8854 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK  (0x40000000U)
8855 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
8856 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
8857 
8858 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8859 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
8860 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
8861 /*! @} */
8862 
8863 /*! @name MISC0 - Miscellaneous Register 0 */
8864 /*! @{ */
8865 
8866 #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK         (0x1U)
8867 #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT        (0U)
8868 #define CCM_ANALOG_MISC0_REFTOP_PWD(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
8869 
8870 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
8871 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
8872 /*! REFTOP_SELFBIASOFF
8873  *  0b0..Uses coarse bias currents for startup
8874  *  0b1..Uses bandgap-based bias currents for best performance.
8875  */
8876 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
8877 
8878 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK      (0x70U)
8879 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT     (4U)
8880 /*! REFTOP_VBGADJ
8881  *  0b000..Nominal VBG
8882  *  0b001..VBG+0.78%
8883  *  0b010..VBG+1.56%
8884  *  0b011..VBG+2.34%
8885  *  0b100..VBG-0.78%
8886  *  0b101..VBG-1.56%
8887  *  0b110..VBG-2.34%
8888  *  0b111..VBG-3.12%
8889  */
8890 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
8891 
8892 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK       (0x80U)
8893 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT      (7U)
8894 #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
8895 
8896 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK   (0xC00U)
8897 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT  (10U)
8898 /*! STOP_MODE_CONFIG
8899  *  0b00..All analog except RTC powered down on stop mode assertion.
8900  *  0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8901  *  0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8902  *        bandgap together with the rest analog is powered down.
8903  *  0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8904  */
8905 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
8906 
8907 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK   (0x1000U)
8908 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT  (12U)
8909 /*! DISCON_HIGH_SNVS
8910  *  0b0..Turn on the switch
8911  *  0b1..Turn off the switch
8912  */
8913 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
8914 
8915 #define CCM_ANALOG_MISC0_OSC_I_MASK              (0x6000U)
8916 #define CCM_ANALOG_MISC0_OSC_I_SHIFT             (13U)
8917 /*! OSC_I
8918  *  0b00..Nominal
8919  *  0b01..Decrease current by 12.5%
8920  *  0b10..Decrease current by 25.0%
8921  *  0b11..Decrease current by 37.5%
8922  */
8923 #define CCM_ANALOG_MISC0_OSC_I(x)                (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
8924 
8925 #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK         (0x8000U)
8926 #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT        (15U)
8927 #define CCM_ANALOG_MISC0_OSC_XTALOK(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
8928 
8929 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK      (0x10000U)
8930 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT     (16U)
8931 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
8932 
8933 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK       (0x2000000U)
8934 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT      (25U)
8935 /*! CLKGATE_CTRL
8936  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8937  *  0b1..Prevent the logic from ever gating off the clock.
8938  */
8939 #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
8940 
8941 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK      (0x1C000000U)
8942 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT     (26U)
8943 /*! CLKGATE_DELAY
8944  *  0b000..0.5ms
8945  *  0b001..1.0ms
8946  *  0b010..2.0ms
8947  *  0b011..3.0ms
8948  *  0b100..4.0ms
8949  *  0b101..5.0ms
8950  *  0b110..6.0ms
8951  *  0b111..7.0ms
8952  */
8953 #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
8954 
8955 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK    (0x20000000U)
8956 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT   (29U)
8957 /*! RTC_XTAL_SOURCE
8958  *  0b0..Internal ring oscillator
8959  *  0b1..RTC_XTAL
8960  */
8961 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
8962 
8963 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK       (0x40000000U)
8964 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT      (30U)
8965 #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
8966 /*! @} */
8967 
8968 /*! @name MISC0_SET - Miscellaneous Register 0 */
8969 /*! @{ */
8970 
8971 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK     (0x1U)
8972 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT    (0U)
8973 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
8974 
8975 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
8976 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
8977 /*! REFTOP_SELFBIASOFF
8978  *  0b0..Uses coarse bias currents for startup
8979  *  0b1..Uses bandgap-based bias currents for best performance.
8980  */
8981 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
8982 
8983 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK  (0x70U)
8984 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
8985 /*! REFTOP_VBGADJ
8986  *  0b000..Nominal VBG
8987  *  0b001..VBG+0.78%
8988  *  0b010..VBG+1.56%
8989  *  0b011..VBG+2.34%
8990  *  0b100..VBG-0.78%
8991  *  0b101..VBG-1.56%
8992  *  0b110..VBG-2.34%
8993  *  0b111..VBG-3.12%
8994  */
8995 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
8996 
8997 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK   (0x80U)
8998 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT  (7U)
8999 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
9000 
9001 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
9002 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
9003 /*! STOP_MODE_CONFIG
9004  *  0b00..All analog except RTC powered down on stop mode assertion.
9005  *  0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
9006  *  0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
9007  *        bandgap together with the rest analog is powered down.
9008  *  0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
9009  */
9010 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
9011 
9012 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
9013 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
9014 /*! DISCON_HIGH_SNVS
9015  *  0b0..Turn on the switch
9016  *  0b1..Turn off the switch
9017  */
9018 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
9019 
9020 #define CCM_ANALOG_MISC0_SET_OSC_I_MASK          (0x6000U)
9021 #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT         (13U)
9022 /*! OSC_I
9023  *  0b00..Nominal
9024  *  0b01..Decrease current by 12.5%
9025  *  0b10..Decrease current by 25.0%
9026  *  0b11..Decrease current by 37.5%
9027  */
9028 #define CCM_ANALOG_MISC0_SET_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
9029 
9030 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK     (0x8000U)
9031 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT    (15U)
9032 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
9033 
9034 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK  (0x10000U)
9035 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
9036 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
9037 
9038 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK   (0x2000000U)
9039 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT  (25U)
9040 /*! CLKGATE_CTRL
9041  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
9042  *  0b1..Prevent the logic from ever gating off the clock.
9043  */
9044 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
9045 
9046 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK  (0x1C000000U)
9047 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
9048 /*! CLKGATE_DELAY
9049  *  0b000..0.5ms
9050  *  0b001..1.0ms
9051  *  0b010..2.0ms
9052  *  0b011..3.0ms
9053  *  0b100..4.0ms
9054  *  0b101..5.0ms
9055  *  0b110..6.0ms
9056  *  0b111..7.0ms
9057  */
9058 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
9059 
9060 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
9061 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
9062 /*! RTC_XTAL_SOURCE
9063  *  0b0..Internal ring oscillator
9064  *  0b1..RTC_XTAL
9065  */
9066 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
9067 
9068 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK   (0x40000000U)
9069 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT  (30U)
9070 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
9071 /*! @} */
9072 
9073 /*! @name MISC0_CLR - Miscellaneous Register 0 */
9074 /*! @{ */
9075 
9076 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK     (0x1U)
9077 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT    (0U)
9078 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
9079 
9080 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
9081 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
9082 /*! REFTOP_SELFBIASOFF
9083  *  0b0..Uses coarse bias currents for startup
9084  *  0b1..Uses bandgap-based bias currents for best performance.
9085  */
9086 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
9087 
9088 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK  (0x70U)
9089 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
9090 /*! REFTOP_VBGADJ
9091  *  0b000..Nominal VBG
9092  *  0b001..VBG+0.78%
9093  *  0b010..VBG+1.56%
9094  *  0b011..VBG+2.34%
9095  *  0b100..VBG-0.78%
9096  *  0b101..VBG-1.56%
9097  *  0b110..VBG-2.34%
9098  *  0b111..VBG-3.12%
9099  */
9100 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
9101 
9102 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK   (0x80U)
9103 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT  (7U)
9104 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
9105 
9106 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
9107 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
9108 /*! STOP_MODE_CONFIG
9109  *  0b00..All analog except RTC powered down on stop mode assertion.
9110  *  0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
9111  *  0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
9112  *        bandgap together with the rest analog is powered down.
9113  *  0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
9114  */
9115 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
9116 
9117 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
9118 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
9119 /*! DISCON_HIGH_SNVS
9120  *  0b0..Turn on the switch
9121  *  0b1..Turn off the switch
9122  */
9123 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
9124 
9125 #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK          (0x6000U)
9126 #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT         (13U)
9127 /*! OSC_I
9128  *  0b00..Nominal
9129  *  0b01..Decrease current by 12.5%
9130  *  0b10..Decrease current by 25.0%
9131  *  0b11..Decrease current by 37.5%
9132  */
9133 #define CCM_ANALOG_MISC0_CLR_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
9134 
9135 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK     (0x8000U)
9136 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT    (15U)
9137 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
9138 
9139 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK  (0x10000U)
9140 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
9141 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
9142 
9143 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK   (0x2000000U)
9144 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT  (25U)
9145 /*! CLKGATE_CTRL
9146  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
9147  *  0b1..Prevent the logic from ever gating off the clock.
9148  */
9149 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
9150 
9151 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK  (0x1C000000U)
9152 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
9153 /*! CLKGATE_DELAY
9154  *  0b000..0.5ms
9155  *  0b001..1.0ms
9156  *  0b010..2.0ms
9157  *  0b011..3.0ms
9158  *  0b100..4.0ms
9159  *  0b101..5.0ms
9160  *  0b110..6.0ms
9161  *  0b111..7.0ms
9162  */
9163 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
9164 
9165 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
9166 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
9167 /*! RTC_XTAL_SOURCE
9168  *  0b0..Internal ring oscillator
9169  *  0b1..RTC_XTAL
9170  */
9171 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
9172 
9173 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK   (0x40000000U)
9174 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT  (30U)
9175 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
9176 /*! @} */
9177 
9178 /*! @name MISC0_TOG - Miscellaneous Register 0 */
9179 /*! @{ */
9180 
9181 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK     (0x1U)
9182 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT    (0U)
9183 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
9184 
9185 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
9186 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
9187 /*! REFTOP_SELFBIASOFF
9188  *  0b0..Uses coarse bias currents for startup
9189  *  0b1..Uses bandgap-based bias currents for best performance.
9190  */
9191 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
9192 
9193 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK  (0x70U)
9194 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
9195 /*! REFTOP_VBGADJ
9196  *  0b000..Nominal VBG
9197  *  0b001..VBG+0.78%
9198  *  0b010..VBG+1.56%
9199  *  0b011..VBG+2.34%
9200  *  0b100..VBG-0.78%
9201  *  0b101..VBG-1.56%
9202  *  0b110..VBG-2.34%
9203  *  0b111..VBG-3.12%
9204  */
9205 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
9206 
9207 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK   (0x80U)
9208 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT  (7U)
9209 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
9210 
9211 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
9212 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
9213 /*! STOP_MODE_CONFIG
9214  *  0b00..All analog except RTC powered down on stop mode assertion.
9215  *  0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
9216  *  0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
9217  *        bandgap together with the rest analog is powered down.
9218  *  0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
9219  */
9220 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
9221 
9222 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
9223 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
9224 /*! DISCON_HIGH_SNVS
9225  *  0b0..Turn on the switch
9226  *  0b1..Turn off the switch
9227  */
9228 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
9229 
9230 #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK          (0x6000U)
9231 #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT         (13U)
9232 /*! OSC_I
9233  *  0b00..Nominal
9234  *  0b01..Decrease current by 12.5%
9235  *  0b10..Decrease current by 25.0%
9236  *  0b11..Decrease current by 37.5%
9237  */
9238 #define CCM_ANALOG_MISC0_TOG_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
9239 
9240 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK     (0x8000U)
9241 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT    (15U)
9242 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
9243 
9244 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK  (0x10000U)
9245 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
9246 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
9247 
9248 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK   (0x2000000U)
9249 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT  (25U)
9250 /*! CLKGATE_CTRL
9251  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
9252  *  0b1..Prevent the logic from ever gating off the clock.
9253  */
9254 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
9255 
9256 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK  (0x1C000000U)
9257 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
9258 /*! CLKGATE_DELAY
9259  *  0b000..0.5ms
9260  *  0b001..1.0ms
9261  *  0b010..2.0ms
9262  *  0b011..3.0ms
9263  *  0b100..4.0ms
9264  *  0b101..5.0ms
9265  *  0b110..6.0ms
9266  *  0b111..7.0ms
9267  */
9268 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
9269 
9270 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
9271 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
9272 /*! RTC_XTAL_SOURCE
9273  *  0b0..Internal ring oscillator
9274  *  0b1..RTC_XTAL
9275  */
9276 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
9277 
9278 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK   (0x40000000U)
9279 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT  (30U)
9280 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
9281 /*! @} */
9282 
9283 /*! @name MISC1 - Miscellaneous Register 1 */
9284 /*! @{ */
9285 
9286 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK      (0x1FU)
9287 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT     (0U)
9288 /*! LVDS1_CLK_SEL
9289  *  0b00000..Arm PLL
9290  *  0b00001..System PLL
9291  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
9292  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
9293  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
9294  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
9295  *  0b00110..Audio PLL
9296  *  0b00111..Video PLL
9297  *  0b01001..ethernet ref clock (ENET_PLL)
9298  *  0b01100..USB1 PLL clock
9299  *  0b01101..USB2 PLL clock
9300  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
9301  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
9302  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
9303  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
9304  *  0b10010..xtal (24M)
9305  */
9306 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
9307 
9308 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK      (0x400U)
9309 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT     (10U)
9310 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
9311 
9312 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK      (0x1000U)
9313 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT     (12U)
9314 #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
9315 
9316 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9317 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
9318 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
9319 
9320 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9321 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
9322 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
9323 
9324 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK      (0x8000000U)
9325 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT     (27U)
9326 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
9327 
9328 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK        (0x10000000U)
9329 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT       (28U)
9330 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
9331 
9332 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK       (0x20000000U)
9333 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT      (29U)
9334 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
9335 
9336 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK         (0x40000000U)
9337 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT        (30U)
9338 #define CCM_ANALOG_MISC1_IRQ_ANA_BO(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
9339 
9340 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK         (0x80000000U)
9341 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT        (31U)
9342 #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
9343 /*! @} */
9344 
9345 /*! @name MISC1_SET - Miscellaneous Register 1 */
9346 /*! @{ */
9347 
9348 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK  (0x1FU)
9349 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
9350 /*! LVDS1_CLK_SEL
9351  *  0b00000..Arm PLL
9352  *  0b00001..System PLL
9353  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
9354  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
9355  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
9356  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
9357  *  0b00110..Audio PLL
9358  *  0b00111..Video PLL
9359  *  0b01001..ethernet ref clock (ENET_PLL)
9360  *  0b01100..USB1 PLL clock
9361  *  0b01101..USB2 PLL clock
9362  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
9363  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
9364  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
9365  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
9366  *  0b10010..xtal (24M)
9367  */
9368 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
9369 
9370 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK  (0x400U)
9371 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
9372 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
9373 
9374 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK  (0x1000U)
9375 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
9376 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
9377 
9378 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9379 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
9380 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
9381 
9382 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9383 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
9384 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
9385 
9386 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK  (0x8000000U)
9387 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
9388 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
9389 
9390 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK    (0x10000000U)
9391 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT   (28U)
9392 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
9393 
9394 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK   (0x20000000U)
9395 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT  (29U)
9396 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
9397 
9398 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK     (0x40000000U)
9399 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT    (30U)
9400 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
9401 
9402 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK     (0x80000000U)
9403 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT    (31U)
9404 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
9405 /*! @} */
9406 
9407 /*! @name MISC1_CLR - Miscellaneous Register 1 */
9408 /*! @{ */
9409 
9410 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK  (0x1FU)
9411 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
9412 /*! LVDS1_CLK_SEL
9413  *  0b00000..Arm PLL
9414  *  0b00001..System PLL
9415  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
9416  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
9417  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
9418  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
9419  *  0b00110..Audio PLL
9420  *  0b00111..Video PLL
9421  *  0b01001..ethernet ref clock (ENET_PLL)
9422  *  0b01100..USB1 PLL clock
9423  *  0b01101..USB2 PLL clock
9424  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
9425  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
9426  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
9427  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
9428  *  0b10010..xtal (24M)
9429  */
9430 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
9431 
9432 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK  (0x400U)
9433 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
9434 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
9435 
9436 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK  (0x1000U)
9437 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
9438 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
9439 
9440 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9441 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
9442 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
9443 
9444 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9445 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
9446 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
9447 
9448 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK  (0x8000000U)
9449 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
9450 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
9451 
9452 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK    (0x10000000U)
9453 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT   (28U)
9454 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
9455 
9456 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK   (0x20000000U)
9457 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT  (29U)
9458 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
9459 
9460 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK     (0x40000000U)
9461 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT    (30U)
9462 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
9463 
9464 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK     (0x80000000U)
9465 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT    (31U)
9466 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
9467 /*! @} */
9468 
9469 /*! @name MISC1_TOG - Miscellaneous Register 1 */
9470 /*! @{ */
9471 
9472 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK  (0x1FU)
9473 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
9474 /*! LVDS1_CLK_SEL
9475  *  0b00000..Arm PLL
9476  *  0b00001..System PLL
9477  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
9478  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
9479  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
9480  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
9481  *  0b00110..Audio PLL
9482  *  0b00111..Video PLL
9483  *  0b01001..ethernet ref clock (ENET_PLL)
9484  *  0b01100..USB1 PLL clock
9485  *  0b01101..USB2 PLL clock
9486  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
9487  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
9488  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
9489  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
9490  *  0b10010..xtal (24M)
9491  */
9492 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
9493 
9494 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK  (0x400U)
9495 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
9496 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
9497 
9498 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK  (0x1000U)
9499 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
9500 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
9501 
9502 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9503 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
9504 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
9505 
9506 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9507 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
9508 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
9509 
9510 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK  (0x8000000U)
9511 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
9512 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
9513 
9514 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK    (0x10000000U)
9515 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT   (28U)
9516 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
9517 
9518 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK   (0x20000000U)
9519 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT  (29U)
9520 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
9521 
9522 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK     (0x40000000U)
9523 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT    (30U)
9524 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
9525 
9526 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK     (0x80000000U)
9527 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT    (31U)
9528 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
9529 /*! @} */
9530 
9531 /*! @name MISC2 - Miscellaneous Register 2 */
9532 /*! @{ */
9533 
9534 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK     (0x7U)
9535 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT    (0U)
9536 /*! REG0_BO_OFFSET
9537  *  0b100..Brownout offset = 0.100V
9538  *  0b111..Brownout offset = 0.175V
9539  */
9540 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
9541 
9542 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK     (0x8U)
9543 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT    (3U)
9544 /*! REG0_BO_STATUS
9545  *  0b1..Brownout, supply is below target minus brownout offset.
9546  */
9547 #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
9548 
9549 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK     (0x20U)
9550 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT    (5U)
9551 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
9552 
9553 #define CCM_ANALOG_MISC2_REG0_OK_MASK            (0x40U)
9554 #define CCM_ANALOG_MISC2_REG0_OK_SHIFT           (6U)
9555 #define CCM_ANALOG_MISC2_REG0_OK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
9556 
9557 #define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK       (0x80U)
9558 #define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT      (7U)
9559 /*! PLL3_DISABLE
9560  *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9561  *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
9562  */
9563 #define CCM_ANALOG_MISC2_PLL3_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
9564 
9565 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK     (0x700U)
9566 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT    (8U)
9567 /*! REG1_BO_OFFSET
9568  *  0b100..Brownout offset = 0.100V
9569  *  0b111..Brownout offset = 0.175V
9570  */
9571 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
9572 
9573 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK     (0x800U)
9574 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT    (11U)
9575 /*! REG1_BO_STATUS
9576  *  0b1..Brownout, supply is below target minus brownout offset.
9577  */
9578 #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
9579 
9580 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK     (0x2000U)
9581 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT    (13U)
9582 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
9583 
9584 #define CCM_ANALOG_MISC2_REG1_OK_MASK            (0x4000U)
9585 #define CCM_ANALOG_MISC2_REG1_OK_SHIFT           (14U)
9586 #define CCM_ANALOG_MISC2_REG1_OK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
9587 
9588 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK      (0x8000U)
9589 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT     (15U)
9590 /*! AUDIO_DIV_LSB
9591  *  0b0..divide by 1 (Default)
9592  *  0b1..divide by 2
9593  */
9594 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
9595 
9596 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK     (0x70000U)
9597 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT    (16U)
9598 /*! REG2_BO_OFFSET
9599  *  0b100..Brownout offset = 0.100V
9600  *  0b111..Brownout offset = 0.175V
9601  */
9602 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
9603 
9604 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK     (0x80000U)
9605 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT    (19U)
9606 #define CCM_ANALOG_MISC2_REG2_BO_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
9607 
9608 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK     (0x200000U)
9609 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT    (21U)
9610 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
9611 
9612 #define CCM_ANALOG_MISC2_REG2_OK_MASK            (0x400000U)
9613 #define CCM_ANALOG_MISC2_REG2_OK_SHIFT           (22U)
9614 #define CCM_ANALOG_MISC2_REG2_OK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
9615 
9616 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK      (0x800000U)
9617 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT     (23U)
9618 /*! AUDIO_DIV_MSB
9619  *  0b0..divide by 1 (Default)
9620  *  0b1..divide by 2
9621  */
9622 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
9623 
9624 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK     (0x3000000U)
9625 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT    (24U)
9626 /*! REG0_STEP_TIME
9627  *  0b00..64
9628  *  0b01..128
9629  *  0b10..256
9630  *  0b11..512
9631  */
9632 #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
9633 
9634 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK     (0xC000000U)
9635 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT    (26U)
9636 /*! REG1_STEP_TIME
9637  *  0b00..64
9638  *  0b01..128
9639  *  0b10..256
9640  *  0b11..512
9641  */
9642 #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
9643 
9644 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK     (0x30000000U)
9645 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT    (28U)
9646 /*! REG2_STEP_TIME
9647  *  0b00..64
9648  *  0b01..128
9649  *  0b10..256
9650  *  0b11..512
9651  */
9652 #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
9653 
9654 #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK          (0xC0000000U)
9655 #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT         (30U)
9656 /*! VIDEO_DIV
9657  *  0b00..divide by 1 (Default)
9658  *  0b01..divide by 2
9659  *  0b10..divide by 1
9660  *  0b11..divide by 4
9661  */
9662 #define CCM_ANALOG_MISC2_VIDEO_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
9663 /*! @} */
9664 
9665 /*! @name MISC2_SET - Miscellaneous Register 2 */
9666 /*! @{ */
9667 
9668 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
9669 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
9670 /*! REG0_BO_OFFSET
9671  *  0b100..Brownout offset = 0.100V
9672  *  0b111..Brownout offset = 0.175V
9673  */
9674 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
9675 
9676 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
9677 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
9678 /*! REG0_BO_STATUS
9679  *  0b1..Brownout, supply is below target minus brownout offset.
9680  */
9681 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
9682 
9683 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
9684 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
9685 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
9686 
9687 #define CCM_ANALOG_MISC2_SET_REG0_OK_MASK        (0x40U)
9688 #define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT       (6U)
9689 #define CCM_ANALOG_MISC2_SET_REG0_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
9690 
9691 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK   (0x80U)
9692 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT  (7U)
9693 /*! PLL3_DISABLE
9694  *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9695  *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
9696  */
9697 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
9698 
9699 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
9700 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
9701 /*! REG1_BO_OFFSET
9702  *  0b100..Brownout offset = 0.100V
9703  *  0b111..Brownout offset = 0.175V
9704  */
9705 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
9706 
9707 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
9708 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
9709 /*! REG1_BO_STATUS
9710  *  0b1..Brownout, supply is below target minus brownout offset.
9711  */
9712 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
9713 
9714 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
9715 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
9716 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
9717 
9718 #define CCM_ANALOG_MISC2_SET_REG1_OK_MASK        (0x4000U)
9719 #define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT       (14U)
9720 #define CCM_ANALOG_MISC2_SET_REG1_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
9721 
9722 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK  (0x8000U)
9723 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
9724 /*! AUDIO_DIV_LSB
9725  *  0b0..divide by 1 (Default)
9726  *  0b1..divide by 2
9727  */
9728 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
9729 
9730 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
9731 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
9732 /*! REG2_BO_OFFSET
9733  *  0b100..Brownout offset = 0.100V
9734  *  0b111..Brownout offset = 0.175V
9735  */
9736 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
9737 
9738 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
9739 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
9740 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
9741 
9742 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
9743 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
9744 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
9745 
9746 #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK        (0x400000U)
9747 #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT       (22U)
9748 #define CCM_ANALOG_MISC2_SET_REG2_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
9749 
9750 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK  (0x800000U)
9751 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
9752 /*! AUDIO_DIV_MSB
9753  *  0b0..divide by 1 (Default)
9754  *  0b1..divide by 2
9755  */
9756 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
9757 
9758 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
9759 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
9760 /*! REG0_STEP_TIME
9761  *  0b00..64
9762  *  0b01..128
9763  *  0b10..256
9764  *  0b11..512
9765  */
9766 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
9767 
9768 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
9769 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
9770 /*! REG1_STEP_TIME
9771  *  0b00..64
9772  *  0b01..128
9773  *  0b10..256
9774  *  0b11..512
9775  */
9776 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
9777 
9778 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
9779 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
9780 /*! REG2_STEP_TIME
9781  *  0b00..64
9782  *  0b01..128
9783  *  0b10..256
9784  *  0b11..512
9785  */
9786 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
9787 
9788 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK      (0xC0000000U)
9789 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT     (30U)
9790 /*! VIDEO_DIV
9791  *  0b00..divide by 1 (Default)
9792  *  0b01..divide by 2
9793  *  0b10..divide by 1
9794  *  0b11..divide by 4
9795  */
9796 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
9797 /*! @} */
9798 
9799 /*! @name MISC2_CLR - Miscellaneous Register 2 */
9800 /*! @{ */
9801 
9802 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
9803 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
9804 /*! REG0_BO_OFFSET
9805  *  0b100..Brownout offset = 0.100V
9806  *  0b111..Brownout offset = 0.175V
9807  */
9808 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
9809 
9810 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
9811 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
9812 /*! REG0_BO_STATUS
9813  *  0b1..Brownout, supply is below target minus brownout offset.
9814  */
9815 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
9816 
9817 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
9818 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
9819 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
9820 
9821 #define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK        (0x40U)
9822 #define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT       (6U)
9823 #define CCM_ANALOG_MISC2_CLR_REG0_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
9824 
9825 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK   (0x80U)
9826 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT  (7U)
9827 /*! PLL3_DISABLE
9828  *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9829  *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
9830  */
9831 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
9832 
9833 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
9834 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
9835 /*! REG1_BO_OFFSET
9836  *  0b100..Brownout offset = 0.100V
9837  *  0b111..Brownout offset = 0.175V
9838  */
9839 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
9840 
9841 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
9842 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
9843 /*! REG1_BO_STATUS
9844  *  0b1..Brownout, supply is below target minus brownout offset.
9845  */
9846 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
9847 
9848 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
9849 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
9850 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
9851 
9852 #define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK        (0x4000U)
9853 #define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT       (14U)
9854 #define CCM_ANALOG_MISC2_CLR_REG1_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
9855 
9856 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK  (0x8000U)
9857 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
9858 /*! AUDIO_DIV_LSB
9859  *  0b0..divide by 1 (Default)
9860  *  0b1..divide by 2
9861  */
9862 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
9863 
9864 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
9865 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
9866 /*! REG2_BO_OFFSET
9867  *  0b100..Brownout offset = 0.100V
9868  *  0b111..Brownout offset = 0.175V
9869  */
9870 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
9871 
9872 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
9873 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
9874 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
9875 
9876 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
9877 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
9878 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
9879 
9880 #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK        (0x400000U)
9881 #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT       (22U)
9882 #define CCM_ANALOG_MISC2_CLR_REG2_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
9883 
9884 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK  (0x800000U)
9885 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
9886 /*! AUDIO_DIV_MSB
9887  *  0b0..divide by 1 (Default)
9888  *  0b1..divide by 2
9889  */
9890 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
9891 
9892 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
9893 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
9894 /*! REG0_STEP_TIME
9895  *  0b00..64
9896  *  0b01..128
9897  *  0b10..256
9898  *  0b11..512
9899  */
9900 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
9901 
9902 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
9903 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
9904 /*! REG1_STEP_TIME
9905  *  0b00..64
9906  *  0b01..128
9907  *  0b10..256
9908  *  0b11..512
9909  */
9910 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
9911 
9912 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
9913 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
9914 /*! REG2_STEP_TIME
9915  *  0b00..64
9916  *  0b01..128
9917  *  0b10..256
9918  *  0b11..512
9919  */
9920 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
9921 
9922 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK      (0xC0000000U)
9923 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT     (30U)
9924 /*! VIDEO_DIV
9925  *  0b00..divide by 1 (Default)
9926  *  0b01..divide by 2
9927  *  0b10..divide by 1
9928  *  0b11..divide by 4
9929  */
9930 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
9931 /*! @} */
9932 
9933 /*! @name MISC2_TOG - Miscellaneous Register 2 */
9934 /*! @{ */
9935 
9936 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
9937 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
9938 /*! REG0_BO_OFFSET
9939  *  0b100..Brownout offset = 0.100V
9940  *  0b111..Brownout offset = 0.175V
9941  */
9942 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
9943 
9944 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
9945 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
9946 /*! REG0_BO_STATUS
9947  *  0b1..Brownout, supply is below target minus brownout offset.
9948  */
9949 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
9950 
9951 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
9952 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
9953 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
9954 
9955 #define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK        (0x40U)
9956 #define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT       (6U)
9957 #define CCM_ANALOG_MISC2_TOG_REG0_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
9958 
9959 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK   (0x80U)
9960 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT  (7U)
9961 /*! PLL3_DISABLE
9962  *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9963  *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
9964  */
9965 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
9966 
9967 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
9968 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
9969 /*! REG1_BO_OFFSET
9970  *  0b100..Brownout offset = 0.100V
9971  *  0b111..Brownout offset = 0.175V
9972  */
9973 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
9974 
9975 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
9976 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
9977 /*! REG1_BO_STATUS
9978  *  0b1..Brownout, supply is below target minus brownout offset.
9979  */
9980 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
9981 
9982 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
9983 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
9984 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
9985 
9986 #define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK        (0x4000U)
9987 #define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT       (14U)
9988 #define CCM_ANALOG_MISC2_TOG_REG1_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
9989 
9990 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK  (0x8000U)
9991 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
9992 /*! AUDIO_DIV_LSB
9993  *  0b0..divide by 1 (Default)
9994  *  0b1..divide by 2
9995  */
9996 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
9997 
9998 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
9999 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
10000 /*! REG2_BO_OFFSET
10001  *  0b100..Brownout offset = 0.100V
10002  *  0b111..Brownout offset = 0.175V
10003  */
10004 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
10005 
10006 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
10007 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
10008 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
10009 
10010 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
10011 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
10012 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
10013 
10014 #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK        (0x400000U)
10015 #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT       (22U)
10016 #define CCM_ANALOG_MISC2_TOG_REG2_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
10017 
10018 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK  (0x800000U)
10019 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
10020 /*! AUDIO_DIV_MSB
10021  *  0b0..divide by 1 (Default)
10022  *  0b1..divide by 2
10023  */
10024 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
10025 
10026 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
10027 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
10028 /*! REG0_STEP_TIME
10029  *  0b00..64
10030  *  0b01..128
10031  *  0b10..256
10032  *  0b11..512
10033  */
10034 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
10035 
10036 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
10037 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
10038 /*! REG1_STEP_TIME
10039  *  0b00..64
10040  *  0b01..128
10041  *  0b10..256
10042  *  0b11..512
10043  */
10044 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
10045 
10046 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
10047 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
10048 /*! REG2_STEP_TIME
10049  *  0b00..64
10050  *  0b01..128
10051  *  0b10..256
10052  *  0b11..512
10053  */
10054 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
10055 
10056 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK      (0xC0000000U)
10057 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT     (30U)
10058 /*! VIDEO_DIV
10059  *  0b00..divide by 1 (Default)
10060  *  0b01..divide by 2
10061  *  0b10..divide by 1
10062  *  0b11..divide by 4
10063  */
10064 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
10065 /*! @} */
10066 
10067 
10068 /*!
10069  * @}
10070  */ /* end of group CCM_ANALOG_Register_Masks */
10071 
10072 
10073 /* CCM_ANALOG - Peripheral instance base addresses */
10074 /** Peripheral CCM_ANALOG base address */
10075 #define CCM_ANALOG_BASE                          (0x400D8000u)
10076 /** Peripheral CCM_ANALOG base pointer */
10077 #define CCM_ANALOG                               ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
10078 /** Array initializer of CCM_ANALOG peripheral base addresses */
10079 #define CCM_ANALOG_BASE_ADDRS                    { CCM_ANALOG_BASE }
10080 /** Array initializer of CCM_ANALOG peripheral base pointers */
10081 #define CCM_ANALOG_BASE_PTRS                     { CCM_ANALOG }
10082 
10083 /*!
10084  * @}
10085  */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
10086 
10087 
10088 /* ----------------------------------------------------------------------------
10089    -- CM7_MCM Peripheral Access Layer
10090    ---------------------------------------------------------------------------- */
10091 
10092 /*!
10093  * @addtogroup CM7_MCM_Peripheral_Access_Layer CM7_MCM Peripheral Access Layer
10094  * @{
10095  */
10096 
10097 /** CM7_MCM - Register Layout Typedef */
10098 typedef struct {
10099        uint8_t RESERVED_0[16];
10100   __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
10101 } CM7_MCM_Type;
10102 
10103 /* ----------------------------------------------------------------------------
10104    -- CM7_MCM Register Masks
10105    ---------------------------------------------------------------------------- */
10106 
10107 /*!
10108  * @addtogroup CM7_MCM_Register_Masks CM7_MCM Register Masks
10109  * @{
10110  */
10111 
10112 /*! @name ISCR - Interrupt Status and Control Register */
10113 /*! @{ */
10114 
10115 #define CM7_MCM_ISCR_WABS_MASK                   (0x20U)
10116 #define CM7_MCM_ISCR_WABS_SHIFT                  (5U)
10117 /*! WABS - Write Abort on Slave
10118  *  0b0..No abort
10119  *  0b1..Abort
10120  */
10121 #define CM7_MCM_ISCR_WABS(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK)
10122 
10123 #define CM7_MCM_ISCR_WABSO_MASK                  (0x40U)
10124 #define CM7_MCM_ISCR_WABSO_SHIFT                 (6U)
10125 /*! WABSO - Write Abort on Slave Overrun
10126  *  0b0..No write abort overrun
10127  *  0b1..Write abort overrun occurred
10128  */
10129 #define CM7_MCM_ISCR_WABSO(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK)
10130 
10131 #define CM7_MCM_ISCR_FIOC_MASK                   (0x100U)
10132 #define CM7_MCM_ISCR_FIOC_SHIFT                  (8U)
10133 /*! FIOC - FPU Invalid Operation interrupt Status
10134  *  0b0..No interrupt
10135  *  0b1..Interrupt occured
10136  */
10137 #define CM7_MCM_ISCR_FIOC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK)
10138 
10139 #define CM7_MCM_ISCR_FDZC_MASK                   (0x200U)
10140 #define CM7_MCM_ISCR_FDZC_SHIFT                  (9U)
10141 /*! FDZC - FPU Divide-by-Zero Interrupt Status
10142  *  0b0..No interrupt
10143  *  0b1..Interrupt occured
10144  */
10145 #define CM7_MCM_ISCR_FDZC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK)
10146 
10147 #define CM7_MCM_ISCR_FOFC_MASK                   (0x400U)
10148 #define CM7_MCM_ISCR_FOFC_SHIFT                  (10U)
10149 /*! FOFC - FPU Overflow interrupt status
10150  *  0b0..No interrupt
10151  *  0b1..Interrupt occured
10152  */
10153 #define CM7_MCM_ISCR_FOFC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK)
10154 
10155 #define CM7_MCM_ISCR_FUFC_MASK                   (0x800U)
10156 #define CM7_MCM_ISCR_FUFC_SHIFT                  (11U)
10157 /*! FUFC - FPU Underflow Interrupt Status
10158  *  0b0..No interrupt
10159  *  0b1..Interrupt occured
10160  */
10161 #define CM7_MCM_ISCR_FUFC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK)
10162 
10163 #define CM7_MCM_ISCR_FIXC_MASK                   (0x1000U)
10164 #define CM7_MCM_ISCR_FIXC_SHIFT                  (12U)
10165 /*! FIXC - FPU Inexact Interrupt Status
10166  *  0b0..No interrupt
10167  *  0b1..Interrupt occured
10168  */
10169 #define CM7_MCM_ISCR_FIXC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK)
10170 
10171 #define CM7_MCM_ISCR_FIDC_MASK                   (0x8000U)
10172 #define CM7_MCM_ISCR_FIDC_SHIFT                  (15U)
10173 /*! FIDC - FPU Input Denormal Interrupt Status
10174  *  0b0..No interrupt
10175  *  0b1..Interrupt occured
10176  */
10177 #define CM7_MCM_ISCR_FIDC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK)
10178 
10179 #define CM7_MCM_ISCR_WABE_MASK                   (0x200000U)
10180 #define CM7_MCM_ISCR_WABE_SHIFT                  (21U)
10181 /*! WABE - TCM Write Abort Interrupt enable
10182  *  0b0..Disable interrupt
10183  *  0b1..Enable interrupt
10184  */
10185 #define CM7_MCM_ISCR_WABE(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK)
10186 
10187 #define CM7_MCM_ISCR_FIOCE_MASK                  (0x1000000U)
10188 #define CM7_MCM_ISCR_FIOCE_SHIFT                 (24U)
10189 /*! FIOCE - FPU Invalid Operation Interrupt Enable
10190  *  0b0..Disable interrupt
10191  *  0b1..Enable interrupt
10192  */
10193 #define CM7_MCM_ISCR_FIOCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK)
10194 
10195 #define CM7_MCM_ISCR_FDZCE_MASK                  (0x2000000U)
10196 #define CM7_MCM_ISCR_FDZCE_SHIFT                 (25U)
10197 /*! FDZCE - FPU Divide-by-Zero Interrupt Enable
10198  *  0b0..Disable interrupt
10199  *  0b1..Enable interrupt
10200  */
10201 #define CM7_MCM_ISCR_FDZCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK)
10202 
10203 #define CM7_MCM_ISCR_FOFCE_MASK                  (0x4000000U)
10204 #define CM7_MCM_ISCR_FOFCE_SHIFT                 (26U)
10205 /*! FOFCE - FPU Overflow Interrupt Enable
10206  *  0b0..Disable interrupt
10207  *  0b1..Enable interrupt
10208  */
10209 #define CM7_MCM_ISCR_FOFCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK)
10210 
10211 #define CM7_MCM_ISCR_FUFCE_MASK                  (0x8000000U)
10212 #define CM7_MCM_ISCR_FUFCE_SHIFT                 (27U)
10213 /*! FUFCE - FPU Underflow Interrupt Enable
10214  *  0b0..Disable interrupt
10215  *  0b1..Enable interrupt
10216  */
10217 #define CM7_MCM_ISCR_FUFCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK)
10218 
10219 #define CM7_MCM_ISCR_FIXCE_MASK                  (0x10000000U)
10220 #define CM7_MCM_ISCR_FIXCE_SHIFT                 (28U)
10221 /*! FIXCE - FPU Inexact Interrupt Enable
10222  *  0b0..Disable interrupt
10223  *  0b1..Enable interrupt
10224  */
10225 #define CM7_MCM_ISCR_FIXCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK)
10226 
10227 #define CM7_MCM_ISCR_FIDCE_MASK                  (0x80000000U)
10228 #define CM7_MCM_ISCR_FIDCE_SHIFT                 (31U)
10229 /*! FIDCE - FPU Input Denormal Interrupt Enable
10230  *  0b0..Disable interrupt
10231  *  0b1..Enable interrupt
10232  */
10233 #define CM7_MCM_ISCR_FIDCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK)
10234 /*! @} */
10235 
10236 
10237 /*!
10238  * @}
10239  */ /* end of group CM7_MCM_Register_Masks */
10240 
10241 
10242 /* CM7_MCM - Peripheral instance base addresses */
10243 /** Peripheral CM7_MCM base address */
10244 #define CM7_MCM_BASE                             (0xE0080000u)
10245 /** Peripheral CM7_MCM base pointer */
10246 #define CM7_MCM                                  ((CM7_MCM_Type *)CM7_MCM_BASE)
10247 /** Array initializer of CM7_MCM peripheral base addresses */
10248 #define CM7_MCM_BASE_ADDRS                       { CM7_MCM_BASE }
10249 /** Array initializer of CM7_MCM peripheral base pointers */
10250 #define CM7_MCM_BASE_PTRS                        { CM7_MCM }
10251 
10252 /*!
10253  * @}
10254  */ /* end of group CM7_MCM_Peripheral_Access_Layer */
10255 
10256 
10257 /* ----------------------------------------------------------------------------
10258    -- CMP Peripheral Access Layer
10259    ---------------------------------------------------------------------------- */
10260 
10261 /*!
10262  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
10263  * @{
10264  */
10265 
10266 /** CMP - Register Layout Typedef */
10267 typedef struct {
10268   __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
10269   __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
10270   __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
10271   __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
10272   __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
10273   __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
10274 } CMP_Type;
10275 
10276 /* ----------------------------------------------------------------------------
10277    -- CMP Register Masks
10278    ---------------------------------------------------------------------------- */
10279 
10280 /*!
10281  * @addtogroup CMP_Register_Masks CMP Register Masks
10282  * @{
10283  */
10284 
10285 /*! @name CR0 - CMP Control Register 0 */
10286 /*! @{ */
10287 
10288 #define CMP_CR0_HYSTCTR_MASK                     (0x3U)
10289 #define CMP_CR0_HYSTCTR_SHIFT                    (0U)
10290 /*! HYSTCTR - Comparator hard block hysteresis control
10291  *  0b00..Level 0
10292  *  0b01..Level 1
10293  *  0b10..Level 2
10294  *  0b11..Level 3
10295  */
10296 #define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
10297 
10298 #define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
10299 #define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
10300 /*! FILTER_CNT - Filter Sample Count
10301  *  0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
10302  *  0b001..One sample must agree. The comparator output is simply sampled.
10303  *  0b010..2 consecutive samples must agree.
10304  *  0b011..3 consecutive samples must agree.
10305  *  0b100..4 consecutive samples must agree.
10306  *  0b101..5 consecutive samples must agree.
10307  *  0b110..6 consecutive samples must agree.
10308  *  0b111..7 consecutive samples must agree.
10309  */
10310 #define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
10311 /*! @} */
10312 
10313 /*! @name CR1 - CMP Control Register 1 */
10314 /*! @{ */
10315 
10316 #define CMP_CR1_EN_MASK                          (0x1U)
10317 #define CMP_CR1_EN_SHIFT                         (0U)
10318 /*! EN - Comparator Module Enable
10319  *  0b0..Analog Comparator is disabled.
10320  *  0b1..Analog Comparator is enabled.
10321  */
10322 #define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
10323 
10324 #define CMP_CR1_OPE_MASK                         (0x2U)
10325 #define CMP_CR1_OPE_SHIFT                        (1U)
10326 /*! OPE - Comparator Output Pin Enable
10327  *  0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
10328  *  0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
10329  *       associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
10330  *       bit has no effect.
10331  */
10332 #define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
10333 
10334 #define CMP_CR1_COS_MASK                         (0x4U)
10335 #define CMP_CR1_COS_SHIFT                        (2U)
10336 /*! COS - Comparator Output Select
10337  *  0b0..Set the filtered comparator output (CMPO) to equal COUT.
10338  *  0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
10339  */
10340 #define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
10341 
10342 #define CMP_CR1_INV_MASK                         (0x8U)
10343 #define CMP_CR1_INV_SHIFT                        (3U)
10344 /*! INV - Comparator INVERT
10345  *  0b0..Does not invert the comparator output.
10346  *  0b1..Inverts the comparator output.
10347  */
10348 #define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
10349 
10350 #define CMP_CR1_PMODE_MASK                       (0x10U)
10351 #define CMP_CR1_PMODE_SHIFT                      (4U)
10352 /*! PMODE - Power Mode Select
10353  *  0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
10354  *  0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
10355  */
10356 #define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
10357 
10358 #define CMP_CR1_WE_MASK                          (0x40U)
10359 #define CMP_CR1_WE_SHIFT                         (6U)
10360 /*! WE - Windowing Enable
10361  *  0b0..Windowing mode is not selected.
10362  *  0b1..Windowing mode is selected.
10363  */
10364 #define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
10365 
10366 #define CMP_CR1_SE_MASK                          (0x80U)
10367 #define CMP_CR1_SE_SHIFT                         (7U)
10368 /*! SE - Sample Enable
10369  *  0b0..Sampling mode is not selected.
10370  *  0b1..Sampling mode is selected.
10371  */
10372 #define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
10373 /*! @} */
10374 
10375 /*! @name FPR - CMP Filter Period Register */
10376 /*! @{ */
10377 
10378 #define CMP_FPR_FILT_PER_MASK                    (0xFFU)
10379 #define CMP_FPR_FILT_PER_SHIFT                   (0U)
10380 /*! FILT_PER - Filter Sample Period
10381  */
10382 #define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
10383 /*! @} */
10384 
10385 /*! @name SCR - CMP Status and Control Register */
10386 /*! @{ */
10387 
10388 #define CMP_SCR_COUT_MASK                        (0x1U)
10389 #define CMP_SCR_COUT_SHIFT                       (0U)
10390 /*! COUT - Analog Comparator Output
10391  */
10392 #define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
10393 
10394 #define CMP_SCR_CFF_MASK                         (0x2U)
10395 #define CMP_SCR_CFF_SHIFT                        (1U)
10396 /*! CFF - Analog Comparator Flag Falling
10397  *  0b0..Falling-edge on COUT has not been detected.
10398  *  0b1..Falling-edge on COUT has occurred.
10399  */
10400 #define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
10401 
10402 #define CMP_SCR_CFR_MASK                         (0x4U)
10403 #define CMP_SCR_CFR_SHIFT                        (2U)
10404 /*! CFR - Analog Comparator Flag Rising
10405  *  0b0..Rising-edge on COUT has not been detected.
10406  *  0b1..Rising-edge on COUT has occurred.
10407  */
10408 #define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
10409 
10410 #define CMP_SCR_IEF_MASK                         (0x8U)
10411 #define CMP_SCR_IEF_SHIFT                        (3U)
10412 /*! IEF - Comparator Interrupt Enable Falling
10413  *  0b0..Interrupt is disabled.
10414  *  0b1..Interrupt is enabled.
10415  */
10416 #define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
10417 
10418 #define CMP_SCR_IER_MASK                         (0x10U)
10419 #define CMP_SCR_IER_SHIFT                        (4U)
10420 /*! IER - Comparator Interrupt Enable Rising
10421  *  0b0..Interrupt is disabled.
10422  *  0b1..Interrupt is enabled.
10423  */
10424 #define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
10425 
10426 #define CMP_SCR_DMAEN_MASK                       (0x40U)
10427 #define CMP_SCR_DMAEN_SHIFT                      (6U)
10428 /*! DMAEN - DMA Enable Control
10429  *  0b0..DMA is disabled.
10430  *  0b1..DMA is enabled.
10431  */
10432 #define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
10433 /*! @} */
10434 
10435 /*! @name DACCR - DAC Control Register */
10436 /*! @{ */
10437 
10438 #define CMP_DACCR_VOSEL_MASK                     (0x3FU)
10439 #define CMP_DACCR_VOSEL_SHIFT                    (0U)
10440 /*! VOSEL - DAC Output Voltage Select
10441  */
10442 #define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
10443 
10444 #define CMP_DACCR_VRSEL_MASK                     (0x40U)
10445 #define CMP_DACCR_VRSEL_SHIFT                    (6U)
10446 /*! VRSEL - Supply Voltage Reference Source Select
10447  *  0b0..Vin1 is selected as resistor ladder network supply reference.
10448  *  0b1..Vin2 is selected as resistor ladder network supply reference.
10449  */
10450 #define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
10451 
10452 #define CMP_DACCR_DACEN_MASK                     (0x80U)
10453 #define CMP_DACCR_DACEN_SHIFT                    (7U)
10454 /*! DACEN - DAC Enable
10455  *  0b0..DAC is disabled.
10456  *  0b1..DAC is enabled.
10457  */
10458 #define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
10459 /*! @} */
10460 
10461 /*! @name MUXCR - MUX Control Register */
10462 /*! @{ */
10463 
10464 #define CMP_MUXCR_MSEL_MASK                      (0x7U)
10465 #define CMP_MUXCR_MSEL_SHIFT                     (0U)
10466 /*! MSEL - Minus Input Mux Control
10467  *  0b000..IN0
10468  *  0b001..IN1
10469  *  0b010..IN2
10470  *  0b011..IN3
10471  *  0b100..IN4
10472  *  0b101..IN5
10473  *  0b110..IN6
10474  *  0b111..IN7
10475  */
10476 #define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
10477 
10478 #define CMP_MUXCR_PSEL_MASK                      (0x38U)
10479 #define CMP_MUXCR_PSEL_SHIFT                     (3U)
10480 /*! PSEL - Plus Input Mux Control
10481  *  0b000..IN0
10482  *  0b001..IN1
10483  *  0b010..IN2
10484  *  0b011..IN3
10485  *  0b100..IN4
10486  *  0b101..IN5
10487  *  0b110..IN6
10488  *  0b111..IN7
10489  */
10490 #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
10491 /*! @} */
10492 
10493 
10494 /*!
10495  * @}
10496  */ /* end of group CMP_Register_Masks */
10497 
10498 
10499 /* CMP - Peripheral instance base addresses */
10500 /** Peripheral CMP1 base address */
10501 #define CMP1_BASE                                (0x40094000u)
10502 /** Peripheral CMP1 base pointer */
10503 #define CMP1                                     ((CMP_Type *)CMP1_BASE)
10504 /** Peripheral CMP2 base address */
10505 #define CMP2_BASE                                (0x40094008u)
10506 /** Peripheral CMP2 base pointer */
10507 #define CMP2                                     ((CMP_Type *)CMP2_BASE)
10508 /** Peripheral CMP3 base address */
10509 #define CMP3_BASE                                (0x40094010u)
10510 /** Peripheral CMP3 base pointer */
10511 #define CMP3                                     ((CMP_Type *)CMP3_BASE)
10512 /** Peripheral CMP4 base address */
10513 #define CMP4_BASE                                (0x40094018u)
10514 /** Peripheral CMP4 base pointer */
10515 #define CMP4                                     ((CMP_Type *)CMP4_BASE)
10516 /** Array initializer of CMP peripheral base addresses */
10517 #define CMP_BASE_ADDRS                           { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
10518 /** Array initializer of CMP peripheral base pointers */
10519 #define CMP_BASE_PTRS                            { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
10520 /** Interrupt vectors for the CMP peripheral type */
10521 #define CMP_IRQS                                 { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
10522 
10523 /*!
10524  * @}
10525  */ /* end of group CMP_Peripheral_Access_Layer */
10526 
10527 
10528 /* ----------------------------------------------------------------------------
10529    -- CSI Peripheral Access Layer
10530    ---------------------------------------------------------------------------- */
10531 
10532 /*!
10533  * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
10534  * @{
10535  */
10536 
10537 /** CSI - Register Layout Typedef */
10538 typedef struct {
10539   __IO uint32_t CR1;                               /**< CSI Control Register 1, offset: 0x0 */
10540   __IO uint32_t CR2;                               /**< CSI Control Register 2, offset: 0x4 */
10541   __IO uint32_t CR3;                               /**< CSI Control Register 3, offset: 0x8 */
10542   __I  uint32_t STATFIFO;                          /**< CSI Statistic FIFO Register, offset: 0xC */
10543   __I  uint32_t RFIFO;                             /**< CSI RX FIFO Register, offset: 0x10 */
10544   __IO uint32_t RXCNT;                             /**< CSI RX Count Register, offset: 0x14 */
10545   __IO uint32_t SR;                                /**< CSI Status Register, offset: 0x18 */
10546        uint8_t RESERVED_0[4];
10547   __IO uint32_t DMASA_STATFIFO;                    /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
10548   __IO uint32_t DMATS_STATFIFO;                    /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
10549   __IO uint32_t DMASA_FB1;                         /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
10550   __IO uint32_t DMASA_FB2;                         /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
10551   __IO uint32_t FBUF_PARA;                         /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
10552   __IO uint32_t IMAG_PARA;                         /**< CSI Image Parameter Register, offset: 0x34 */
10553        uint8_t RESERVED_1[16];
10554   __IO uint32_t CR18;                              /**< CSI Control Register 18, offset: 0x48 */
10555   __IO uint32_t CR19;                              /**< CSI Control Register 19, offset: 0x4C */
10556 } CSI_Type;
10557 
10558 /* ----------------------------------------------------------------------------
10559    -- CSI Register Masks
10560    ---------------------------------------------------------------------------- */
10561 
10562 /*!
10563  * @addtogroup CSI_Register_Masks CSI Register Masks
10564  * @{
10565  */
10566 
10567 /*! @name CR1 - CSI Control Register 1 */
10568 /*! @{ */
10569 
10570 #define CSI_CR1_PIXEL_BIT_MASK                   (0x1U)
10571 #define CSI_CR1_PIXEL_BIT_SHIFT                  (0U)
10572 /*! PIXEL_BIT
10573  *  0b0..8-bit data for each pixel
10574  *  0b1..10-bit data for each pixel
10575  */
10576 #define CSI_CR1_PIXEL_BIT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
10577 
10578 #define CSI_CR1_REDGE_MASK                       (0x2U)
10579 #define CSI_CR1_REDGE_SHIFT                      (1U)
10580 /*! REDGE
10581  *  0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
10582  *  0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
10583  */
10584 #define CSI_CR1_REDGE(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
10585 
10586 #define CSI_CR1_INV_PCLK_MASK                    (0x4U)
10587 #define CSI_CR1_INV_PCLK_SHIFT                   (2U)
10588 /*! INV_PCLK
10589  *  0b0..CSI_PIXCLK is directly applied to internal circuitry
10590  *  0b1..CSI_PIXCLK is inverted before applied to internal circuitry
10591  */
10592 #define CSI_CR1_INV_PCLK(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
10593 
10594 #define CSI_CR1_INV_DATA_MASK                    (0x8U)
10595 #define CSI_CR1_INV_DATA_SHIFT                   (3U)
10596 /*! INV_DATA
10597  *  0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
10598  *  0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
10599  */
10600 #define CSI_CR1_INV_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
10601 
10602 #define CSI_CR1_GCLK_MODE_MASK                   (0x10U)
10603 #define CSI_CR1_GCLK_MODE_SHIFT                  (4U)
10604 /*! GCLK_MODE
10605  *  0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
10606  *  0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
10607  */
10608 #define CSI_CR1_GCLK_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
10609 
10610 #define CSI_CR1_CLR_RXFIFO_MASK                  (0x20U)
10611 #define CSI_CR1_CLR_RXFIFO_SHIFT                 (5U)
10612 #define CSI_CR1_CLR_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
10613 
10614 #define CSI_CR1_CLR_STATFIFO_MASK                (0x40U)
10615 #define CSI_CR1_CLR_STATFIFO_SHIFT               (6U)
10616 #define CSI_CR1_CLR_STATFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
10617 
10618 #define CSI_CR1_PACK_DIR_MASK                    (0x80U)
10619 #define CSI_CR1_PACK_DIR_SHIFT                   (7U)
10620 /*! PACK_DIR
10621  *  0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
10622  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
10623  *  0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
10624  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
10625  */
10626 #define CSI_CR1_PACK_DIR(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
10627 
10628 #define CSI_CR1_FCC_MASK                         (0x100U)
10629 #define CSI_CR1_FCC_SHIFT                        (8U)
10630 /*! FCC
10631  *  0b0..Asynchronous FIFO clear is selected.
10632  *  0b1..Synchronous FIFO clear is selected.
10633  */
10634 #define CSI_CR1_FCC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
10635 
10636 #define CSI_CR1_CCIR_EN_MASK                     (0x400U)
10637 #define CSI_CR1_CCIR_EN_SHIFT                    (10U)
10638 /*! CCIR_EN
10639  *  0b0..Traditional interface is selected.
10640  *  0b1..BT.656 interface is selected.
10641  */
10642 #define CSI_CR1_CCIR_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
10643 
10644 #define CSI_CR1_HSYNC_POL_MASK                   (0x800U)
10645 #define CSI_CR1_HSYNC_POL_SHIFT                  (11U)
10646 /*! HSYNC_POL
10647  *  0b0..HSYNC is active low
10648  *  0b1..HSYNC is active high
10649  */
10650 #define CSI_CR1_HSYNC_POL(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
10651 
10652 #define CSI_CR1_SOF_INTEN_MASK                   (0x10000U)
10653 #define CSI_CR1_SOF_INTEN_SHIFT                  (16U)
10654 /*! SOF_INTEN
10655  *  0b0..SOF interrupt disable
10656  *  0b1..SOF interrupt enable
10657  */
10658 #define CSI_CR1_SOF_INTEN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
10659 
10660 #define CSI_CR1_SOF_POL_MASK                     (0x20000U)
10661 #define CSI_CR1_SOF_POL_SHIFT                    (17U)
10662 /*! SOF_POL
10663  *  0b0..SOF interrupt is generated on SOF falling edge
10664  *  0b1..SOF interrupt is generated on SOF rising edge
10665  */
10666 #define CSI_CR1_SOF_POL(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
10667 
10668 #define CSI_CR1_RXFF_INTEN_MASK                  (0x40000U)
10669 #define CSI_CR1_RXFF_INTEN_SHIFT                 (18U)
10670 /*! RXFF_INTEN
10671  *  0b0..RxFIFO full interrupt disable
10672  *  0b1..RxFIFO full interrupt enable
10673  */
10674 #define CSI_CR1_RXFF_INTEN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
10675 
10676 #define CSI_CR1_FB1_DMA_DONE_INTEN_MASK          (0x80000U)
10677 #define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT         (19U)
10678 /*! FB1_DMA_DONE_INTEN
10679  *  0b0..Frame Buffer1 DMA Transfer Done interrupt disable
10680  *  0b1..Frame Buffer1 DMA Transfer Done interrupt enable
10681  */
10682 #define CSI_CR1_FB1_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
10683 
10684 #define CSI_CR1_FB2_DMA_DONE_INTEN_MASK          (0x100000U)
10685 #define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT         (20U)
10686 /*! FB2_DMA_DONE_INTEN
10687  *  0b0..Frame Buffer2 DMA Transfer Done interrupt disable
10688  *  0b1..Frame Buffer2 DMA Transfer Done interrupt enable
10689  */
10690 #define CSI_CR1_FB2_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
10691 
10692 #define CSI_CR1_STATFF_INTEN_MASK                (0x200000U)
10693 #define CSI_CR1_STATFF_INTEN_SHIFT               (21U)
10694 /*! STATFF_INTEN
10695  *  0b0..STATFIFO full interrupt disable
10696  *  0b1..STATFIFO full interrupt enable
10697  */
10698 #define CSI_CR1_STATFF_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
10699 
10700 #define CSI_CR1_SFF_DMA_DONE_INTEN_MASK          (0x400000U)
10701 #define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT         (22U)
10702 /*! SFF_DMA_DONE_INTEN
10703  *  0b0..STATFIFO DMA Transfer Done interrupt disable
10704  *  0b1..STATFIFO DMA Transfer Done interrupt enable
10705  */
10706 #define CSI_CR1_SFF_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
10707 
10708 #define CSI_CR1_RF_OR_INTEN_MASK                 (0x1000000U)
10709 #define CSI_CR1_RF_OR_INTEN_SHIFT                (24U)
10710 /*! RF_OR_INTEN
10711  *  0b0..RxFIFO overrun interrupt is disabled
10712  *  0b1..RxFIFO overrun interrupt is enabled
10713  */
10714 #define CSI_CR1_RF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
10715 
10716 #define CSI_CR1_SF_OR_INTEN_MASK                 (0x2000000U)
10717 #define CSI_CR1_SF_OR_INTEN_SHIFT                (25U)
10718 /*! SF_OR_INTEN
10719  *  0b0..STATFIFO overrun interrupt is disabled
10720  *  0b1..STATFIFO overrun interrupt is enabled
10721  */
10722 #define CSI_CR1_SF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
10723 
10724 #define CSI_CR1_COF_INT_EN_MASK                  (0x4000000U)
10725 #define CSI_CR1_COF_INT_EN_SHIFT                 (26U)
10726 /*! COF_INT_EN
10727  *  0b0..COF interrupt is disabled
10728  *  0b1..COF interrupt is enabled
10729  */
10730 #define CSI_CR1_COF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
10731 
10732 #define CSI_CR1_CCIR_MODE_MASK                   (0x8000000U)
10733 #define CSI_CR1_CCIR_MODE_SHIFT                  (27U)
10734 /*! CCIR_MODE
10735  *  0b0..Progressive mode is selected
10736  *  0b1..Interlace mode is selected
10737  */
10738 #define CSI_CR1_CCIR_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_MODE_SHIFT)) & CSI_CR1_CCIR_MODE_MASK)
10739 
10740 #define CSI_CR1_PrP_IF_EN_MASK                   (0x10000000U)
10741 #define CSI_CR1_PrP_IF_EN_SHIFT                  (28U)
10742 /*! PrP_IF_EN
10743  *  0b0..CSI to PrP bus is disabled
10744  *  0b1..CSI to PrP bus is enabled
10745  */
10746 #define CSI_CR1_PrP_IF_EN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PrP_IF_EN_SHIFT)) & CSI_CR1_PrP_IF_EN_MASK)
10747 
10748 #define CSI_CR1_EOF_INT_EN_MASK                  (0x20000000U)
10749 #define CSI_CR1_EOF_INT_EN_SHIFT                 (29U)
10750 /*! EOF_INT_EN
10751  *  0b0..EOF interrupt is disabled.
10752  *  0b1..EOF interrupt is generated when RX count value is reached.
10753  */
10754 #define CSI_CR1_EOF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
10755 
10756 #define CSI_CR1_EXT_VSYNC_MASK                   (0x40000000U)
10757 #define CSI_CR1_EXT_VSYNC_SHIFT                  (30U)
10758 /*! EXT_VSYNC
10759  *  0b0..Internal VSYNC mode
10760  *  0b1..External VSYNC mode
10761  */
10762 #define CSI_CR1_EXT_VSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
10763 
10764 #define CSI_CR1_SWAP16_EN_MASK                   (0x80000000U)
10765 #define CSI_CR1_SWAP16_EN_SHIFT                  (31U)
10766 /*! SWAP16_EN
10767  *  0b0..Disable swapping
10768  *  0b1..Enable swapping
10769  */
10770 #define CSI_CR1_SWAP16_EN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
10771 /*! @} */
10772 
10773 /*! @name CR2 - CSI Control Register 2 */
10774 /*! @{ */
10775 
10776 #define CSI_CR2_HSC_MASK                         (0xFFU)
10777 #define CSI_CR2_HSC_SHIFT                        (0U)
10778 /*! HSC
10779  *  0b00000000-0b11111111..Number of pixels to skip minus 1
10780  */
10781 #define CSI_CR2_HSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
10782 
10783 #define CSI_CR2_VSC_MASK                         (0xFF00U)
10784 #define CSI_CR2_VSC_SHIFT                        (8U)
10785 /*! VSC
10786  *  0b00000000-0b11111111..Number of rows to skip minus 1
10787  */
10788 #define CSI_CR2_VSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
10789 
10790 #define CSI_CR2_LVRM_MASK                        (0x70000U)
10791 #define CSI_CR2_LVRM_SHIFT                       (16U)
10792 /*! LVRM
10793  *  0b000..512 x 384
10794  *  0b001..448 x 336
10795  *  0b010..384 x 288
10796  *  0b011..384 x 256
10797  *  0b100..320 x 240
10798  *  0b101..288 x 216
10799  *  0b110..400 x 300
10800  */
10801 #define CSI_CR2_LVRM(x)                          (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
10802 
10803 #define CSI_CR2_BTS_MASK                         (0x180000U)
10804 #define CSI_CR2_BTS_SHIFT                        (19U)
10805 /*! BTS
10806  *  0b00..GR
10807  *  0b01..RG
10808  *  0b10..BG
10809  *  0b11..GB
10810  */
10811 #define CSI_CR2_BTS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
10812 
10813 #define CSI_CR2_SCE_MASK                         (0x800000U)
10814 #define CSI_CR2_SCE_SHIFT                        (23U)
10815 /*! SCE
10816  *  0b0..Skip count disable
10817  *  0b1..Skip count enable
10818  */
10819 #define CSI_CR2_SCE(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
10820 
10821 #define CSI_CR2_AFS_MASK                         (0x3000000U)
10822 #define CSI_CR2_AFS_SHIFT                        (24U)
10823 /*! AFS
10824  *  0b00..Abs Diff on consecutive green pixels
10825  *  0b01..Abs Diff on every third green pixels
10826  *  0b1x..Abs Diff on every four green pixels
10827  */
10828 #define CSI_CR2_AFS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
10829 
10830 #define CSI_CR2_DRM_MASK                         (0x4000000U)
10831 #define CSI_CR2_DRM_SHIFT                        (26U)
10832 /*! DRM
10833  *  0b0..Stats grid of 8 x 6
10834  *  0b1..Stats grid of 8 x 12
10835  */
10836 #define CSI_CR2_DRM(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
10837 
10838 #define CSI_CR2_DMA_BURST_TYPE_SFF_MASK          (0x30000000U)
10839 #define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT         (28U)
10840 /*! DMA_BURST_TYPE_SFF
10841  *  0bx0..INCR8
10842  *  0b01..INCR4
10843  *  0b11..INCR16
10844  */
10845 #define CSI_CR2_DMA_BURST_TYPE_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
10846 
10847 #define CSI_CR2_DMA_BURST_TYPE_RFF_MASK          (0xC0000000U)
10848 #define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT         (30U)
10849 /*! DMA_BURST_TYPE_RFF
10850  *  0bx0..INCR8
10851  *  0b01..INCR4
10852  *  0b11..INCR16
10853  */
10854 #define CSI_CR2_DMA_BURST_TYPE_RFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
10855 /*! @} */
10856 
10857 /*! @name CR3 - CSI Control Register 3 */
10858 /*! @{ */
10859 
10860 #define CSI_CR3_ECC_AUTO_EN_MASK                 (0x1U)
10861 #define CSI_CR3_ECC_AUTO_EN_SHIFT                (0U)
10862 /*! ECC_AUTO_EN
10863  *  0b0..Auto Error correction is disabled.
10864  *  0b1..Auto Error correction is enabled.
10865  */
10866 #define CSI_CR3_ECC_AUTO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
10867 
10868 #define CSI_CR3_ECC_INT_EN_MASK                  (0x2U)
10869 #define CSI_CR3_ECC_INT_EN_SHIFT                 (1U)
10870 /*! ECC_INT_EN
10871  *  0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
10872  *  0b1..Interrupt is generated when error is detected.
10873  */
10874 #define CSI_CR3_ECC_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
10875 
10876 #define CSI_CR3_ZERO_PACK_EN_MASK                (0x4U)
10877 #define CSI_CR3_ZERO_PACK_EN_SHIFT               (2U)
10878 /*! ZERO_PACK_EN
10879  *  0b0..Zero packing disabled
10880  *  0b1..Zero packing enabled
10881  */
10882 #define CSI_CR3_ZERO_PACK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
10883 
10884 #define CSI_CR3_SENSOR_16BITS_MASK               (0x8U)
10885 #define CSI_CR3_SENSOR_16BITS_SHIFT              (3U)
10886 /*! SENSOR_16BITS
10887  *  0b0..Only one 8-bit sensor is connected.
10888  *  0b1..One 16-bit sensor is connected.
10889  */
10890 #define CSI_CR3_SENSOR_16BITS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
10891 
10892 #define CSI_CR3_RxFF_LEVEL_MASK                  (0x70U)
10893 #define CSI_CR3_RxFF_LEVEL_SHIFT                 (4U)
10894 /*! RxFF_LEVEL
10895  *  0b000..4 Double words
10896  *  0b001..8 Double words
10897  *  0b010..16 Double words
10898  *  0b011..24 Double words
10899  *  0b100..32 Double words
10900  *  0b101..48 Double words
10901  *  0b110..64 Double words
10902  *  0b111..96 Double words
10903  */
10904 #define CSI_CR3_RxFF_LEVEL(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
10905 
10906 #define CSI_CR3_HRESP_ERR_EN_MASK                (0x80U)
10907 #define CSI_CR3_HRESP_ERR_EN_SHIFT               (7U)
10908 /*! HRESP_ERR_EN
10909  *  0b0..Disable hresponse error interrupt
10910  *  0b1..Enable hresponse error interrupt
10911  */
10912 #define CSI_CR3_HRESP_ERR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
10913 
10914 #define CSI_CR3_STATFF_LEVEL_MASK                (0x700U)
10915 #define CSI_CR3_STATFF_LEVEL_SHIFT               (8U)
10916 /*! STATFF_LEVEL
10917  *  0b000..4 Double words
10918  *  0b001..8 Double words
10919  *  0b010..12 Double words
10920  *  0b011..16 Double words
10921  *  0b100..24 Double words
10922  *  0b101..32 Double words
10923  *  0b110..48 Double words
10924  *  0b111..64 Double words
10925  */
10926 #define CSI_CR3_STATFF_LEVEL(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
10927 
10928 #define CSI_CR3_DMA_REQ_EN_SFF_MASK              (0x800U)
10929 #define CSI_CR3_DMA_REQ_EN_SFF_SHIFT             (11U)
10930 /*! DMA_REQ_EN_SFF
10931  *  0b0..Disable the dma request
10932  *  0b1..Enable the dma request
10933  */
10934 #define CSI_CR3_DMA_REQ_EN_SFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
10935 
10936 #define CSI_CR3_DMA_REQ_EN_RFF_MASK              (0x1000U)
10937 #define CSI_CR3_DMA_REQ_EN_RFF_SHIFT             (12U)
10938 /*! DMA_REQ_EN_RFF
10939  *  0b0..Disable the dma request
10940  *  0b1..Enable the dma request
10941  */
10942 #define CSI_CR3_DMA_REQ_EN_RFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
10943 
10944 #define CSI_CR3_DMA_REFLASH_SFF_MASK             (0x2000U)
10945 #define CSI_CR3_DMA_REFLASH_SFF_SHIFT            (13U)
10946 /*! DMA_REFLASH_SFF
10947  *  0b0..No reflashing
10948  *  0b1..Reflash the embedded DMA controller
10949  */
10950 #define CSI_CR3_DMA_REFLASH_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
10951 
10952 #define CSI_CR3_DMA_REFLASH_RFF_MASK             (0x4000U)
10953 #define CSI_CR3_DMA_REFLASH_RFF_SHIFT            (14U)
10954 /*! DMA_REFLASH_RFF
10955  *  0b0..No reflashing
10956  *  0b1..Reflash the embedded DMA controller
10957  */
10958 #define CSI_CR3_DMA_REFLASH_RFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
10959 
10960 #define CSI_CR3_FRMCNT_RST_MASK                  (0x8000U)
10961 #define CSI_CR3_FRMCNT_RST_SHIFT                 (15U)
10962 /*! FRMCNT_RST
10963  *  0b0..Do not reset
10964  *  0b1..Reset frame counter immediately
10965  */
10966 #define CSI_CR3_FRMCNT_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
10967 
10968 #define CSI_CR3_FRMCNT_MASK                      (0xFFFF0000U)
10969 #define CSI_CR3_FRMCNT_SHIFT                     (16U)
10970 #define CSI_CR3_FRMCNT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
10971 /*! @} */
10972 
10973 /*! @name STATFIFO - CSI Statistic FIFO Register */
10974 /*! @{ */
10975 
10976 #define CSI_STATFIFO_STAT_MASK                   (0xFFFFFFFFU)
10977 #define CSI_STATFIFO_STAT_SHIFT                  (0U)
10978 #define CSI_STATFIFO_STAT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
10979 /*! @} */
10980 
10981 /*! @name RFIFO - CSI RX FIFO Register */
10982 /*! @{ */
10983 
10984 #define CSI_RFIFO_IMAGE_MASK                     (0xFFFFFFFFU)
10985 #define CSI_RFIFO_IMAGE_SHIFT                    (0U)
10986 #define CSI_RFIFO_IMAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
10987 /*! @} */
10988 
10989 /*! @name RXCNT - CSI RX Count Register */
10990 /*! @{ */
10991 
10992 #define CSI_RXCNT_RXCNT_MASK                     (0x3FFFFFU)
10993 #define CSI_RXCNT_RXCNT_SHIFT                    (0U)
10994 #define CSI_RXCNT_RXCNT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
10995 /*! @} */
10996 
10997 /*! @name SR - CSI Status Register */
10998 /*! @{ */
10999 
11000 #define CSI_SR_DRDY_MASK                         (0x1U)
11001 #define CSI_SR_DRDY_SHIFT                        (0U)
11002 /*! DRDY
11003  *  0b0..No data (word) is ready
11004  *  0b1..At least 1 datum (word) is ready in RXFIFO.
11005  */
11006 #define CSI_SR_DRDY(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
11007 
11008 #define CSI_SR_ECC_INT_MASK                      (0x2U)
11009 #define CSI_SR_ECC_INT_SHIFT                     (1U)
11010 /*! ECC_INT
11011  *  0b0..No error detected
11012  *  0b1..Error is detected in BT.656 coding
11013  */
11014 #define CSI_SR_ECC_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
11015 
11016 #define CSI_SR_HRESP_ERR_INT_MASK                (0x80U)
11017 #define CSI_SR_HRESP_ERR_INT_SHIFT               (7U)
11018 /*! HRESP_ERR_INT
11019  *  0b0..No hresponse error.
11020  *  0b1..Hresponse error is detected.
11021  */
11022 #define CSI_SR_HRESP_ERR_INT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
11023 
11024 #define CSI_SR_COF_INT_MASK                      (0x2000U)
11025 #define CSI_SR_COF_INT_SHIFT                     (13U)
11026 /*! COF_INT
11027  *  0b0..Video field has no change.
11028  *  0b1..Change of video field is detected.
11029  */
11030 #define CSI_SR_COF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
11031 
11032 #define CSI_SR_F1_INT_MASK                       (0x4000U)
11033 #define CSI_SR_F1_INT_SHIFT                      (14U)
11034 /*! F1_INT
11035  *  0b0..Field 1 of video is not detected.
11036  *  0b1..Field 1 of video is about to start.
11037  */
11038 #define CSI_SR_F1_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
11039 
11040 #define CSI_SR_F2_INT_MASK                       (0x8000U)
11041 #define CSI_SR_F2_INT_SHIFT                      (15U)
11042 /*! F2_INT
11043  *  0b0..Field 2 of video is not detected
11044  *  0b1..Field 2 of video is about to start
11045  */
11046 #define CSI_SR_F2_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
11047 
11048 #define CSI_SR_SOF_INT_MASK                      (0x10000U)
11049 #define CSI_SR_SOF_INT_SHIFT                     (16U)
11050 /*! SOF_INT
11051  *  0b0..SOF is not detected.
11052  *  0b1..SOF is detected.
11053  */
11054 #define CSI_SR_SOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
11055 
11056 #define CSI_SR_EOF_INT_MASK                      (0x20000U)
11057 #define CSI_SR_EOF_INT_SHIFT                     (17U)
11058 /*! EOF_INT
11059  *  0b0..EOF is not detected.
11060  *  0b1..EOF is detected.
11061  */
11062 #define CSI_SR_EOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
11063 
11064 #define CSI_SR_RxFF_INT_MASK                     (0x40000U)
11065 #define CSI_SR_RxFF_INT_SHIFT                    (18U)
11066 /*! RxFF_INT
11067  *  0b0..RxFIFO is not full.
11068  *  0b1..RxFIFO is full.
11069  */
11070 #define CSI_SR_RxFF_INT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
11071 
11072 #define CSI_SR_DMA_TSF_DONE_FB1_MASK             (0x80000U)
11073 #define CSI_SR_DMA_TSF_DONE_FB1_SHIFT            (19U)
11074 /*! DMA_TSF_DONE_FB1
11075  *  0b0..DMA transfer is not completed.
11076  *  0b1..DMA transfer is completed.
11077  */
11078 #define CSI_SR_DMA_TSF_DONE_FB1(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
11079 
11080 #define CSI_SR_DMA_TSF_DONE_FB2_MASK             (0x100000U)
11081 #define CSI_SR_DMA_TSF_DONE_FB2_SHIFT            (20U)
11082 /*! DMA_TSF_DONE_FB2
11083  *  0b0..DMA transfer is not completed.
11084  *  0b1..DMA transfer is completed.
11085  */
11086 #define CSI_SR_DMA_TSF_DONE_FB2(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
11087 
11088 #define CSI_SR_STATFF_INT_MASK                   (0x200000U)
11089 #define CSI_SR_STATFF_INT_SHIFT                  (21U)
11090 /*! STATFF_INT
11091  *  0b0..STATFIFO is not full.
11092  *  0b1..STATFIFO is full.
11093  */
11094 #define CSI_SR_STATFF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
11095 
11096 #define CSI_SR_DMA_TSF_DONE_SFF_MASK             (0x400000U)
11097 #define CSI_SR_DMA_TSF_DONE_SFF_SHIFT            (22U)
11098 /*! DMA_TSF_DONE_SFF
11099  *  0b0..DMA transfer is not completed.
11100  *  0b1..DMA transfer is completed.
11101  */
11102 #define CSI_SR_DMA_TSF_DONE_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
11103 
11104 #define CSI_SR_RF_OR_INT_MASK                    (0x1000000U)
11105 #define CSI_SR_RF_OR_INT_SHIFT                   (24U)
11106 /*! RF_OR_INT
11107  *  0b0..RXFIFO has not overflowed.
11108  *  0b1..RXFIFO has overflowed.
11109  */
11110 #define CSI_SR_RF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
11111 
11112 #define CSI_SR_SF_OR_INT_MASK                    (0x2000000U)
11113 #define CSI_SR_SF_OR_INT_SHIFT                   (25U)
11114 /*! SF_OR_INT
11115  *  0b0..STATFIFO has not overflowed.
11116  *  0b1..STATFIFO has overflowed.
11117  */
11118 #define CSI_SR_SF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
11119 
11120 #define CSI_SR_DMA_FIELD1_DONE_MASK              (0x4000000U)
11121 #define CSI_SR_DMA_FIELD1_DONE_SHIFT             (26U)
11122 #define CSI_SR_DMA_FIELD1_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
11123 
11124 #define CSI_SR_DMA_FIELD0_DONE_MASK              (0x8000000U)
11125 #define CSI_SR_DMA_FIELD0_DONE_SHIFT             (27U)
11126 #define CSI_SR_DMA_FIELD0_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
11127 
11128 #define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK       (0x10000000U)
11129 #define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT      (28U)
11130 #define CSI_SR_BASEADDR_CHHANGE_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
11131 /*! @} */
11132 
11133 /*! @name DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
11134 /*! @{ */
11135 
11136 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
11137 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
11138 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
11139 /*! @} */
11140 
11141 /*! @name DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
11142 /*! @{ */
11143 
11144 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
11145 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
11146 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)   (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
11147 /*! @} */
11148 
11149 /*! @name DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
11150 /*! @{ */
11151 
11152 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK    (0xFFFFFFFCU)
11153 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT   (2U)
11154 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
11155 /*! @} */
11156 
11157 /*! @name DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
11158 /*! @{ */
11159 
11160 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK    (0xFFFFFFFCU)
11161 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT   (2U)
11162 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
11163 /*! @} */
11164 
11165 /*! @name FBUF_PARA - CSI Frame Buffer Parameter Register */
11166 /*! @{ */
11167 
11168 #define CSI_FBUF_PARA_FBUF_STRIDE_MASK           (0xFFFFU)
11169 #define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT          (0U)
11170 #define CSI_FBUF_PARA_FBUF_STRIDE(x)             (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
11171 
11172 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK    (0xFFFF0000U)
11173 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT   (16U)
11174 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)      (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
11175 /*! @} */
11176 
11177 /*! @name IMAG_PARA - CSI Image Parameter Register */
11178 /*! @{ */
11179 
11180 #define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK          (0xFFFFU)
11181 #define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT         (0U)
11182 #define CSI_IMAG_PARA_IMAGE_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
11183 
11184 #define CSI_IMAG_PARA_IMAGE_WIDTH_MASK           (0xFFFF0000U)
11185 #define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT          (16U)
11186 #define CSI_IMAG_PARA_IMAGE_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
11187 /*! @} */
11188 
11189 /*! @name CR18 - CSI Control Register 18 */
11190 /*! @{ */
11191 
11192 #define CSI_CR18_DEINTERLACE_EN_MASK             (0x4U)
11193 #define CSI_CR18_DEINTERLACE_EN_SHIFT            (2U)
11194 /*! DEINTERLACE_EN
11195  *  0b0..Deinterlace disabled
11196  *  0b1..Deinterlace enabled
11197  */
11198 #define CSI_CR18_DEINTERLACE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
11199 
11200 #define CSI_CR18_PARALLEL24_EN_MASK              (0x8U)
11201 #define CSI_CR18_PARALLEL24_EN_SHIFT             (3U)
11202 /*! PARALLEL24_EN
11203  *  0b0..Input is disabled
11204  *  0b1..Input is enabled
11205  */
11206 #define CSI_CR18_PARALLEL24_EN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
11207 
11208 #define CSI_CR18_BASEADDR_SWITCH_EN_MASK         (0x10U)
11209 #define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT        (4U)
11210 #define CSI_CR18_BASEADDR_SWITCH_EN(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
11211 
11212 #define CSI_CR18_BASEADDR_SWITCH_SEL_MASK        (0x20U)
11213 #define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT       (5U)
11214 /*! BASEADDR_SWITCH_SEL
11215  *  0b0..Switching base address at the edge of the vsync
11216  *  0b1..Switching base address at the edge of the first data of each frame
11217  */
11218 #define CSI_CR18_BASEADDR_SWITCH_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
11219 
11220 #define CSI_CR18_FIELD0_DONE_IE_MASK             (0x40U)
11221 #define CSI_CR18_FIELD0_DONE_IE_SHIFT            (6U)
11222 /*! FIELD0_DONE_IE
11223  *  0b0..Interrupt disabled
11224  *  0b1..Interrupt enabled
11225  */
11226 #define CSI_CR18_FIELD0_DONE_IE(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
11227 
11228 #define CSI_CR18_DMA_FIELD1_DONE_IE_MASK         (0x80U)
11229 #define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT        (7U)
11230 /*! DMA_FIELD1_DONE_IE
11231  *  0b0..Interrupt disabled
11232  *  0b1..Interrupt enabled
11233  */
11234 #define CSI_CR18_DMA_FIELD1_DONE_IE(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
11235 
11236 #define CSI_CR18_LAST_DMA_REQ_SEL_MASK           (0x100U)
11237 #define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT          (8U)
11238 /*! LAST_DMA_REQ_SEL
11239  *  0b0..fifo_full_level
11240  *  0b1..hburst_length
11241  */
11242 #define CSI_CR18_LAST_DMA_REQ_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
11243 
11244 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK   (0x200U)
11245 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT  (9U)
11246 /*! BASEADDR_CHANGE_ERROR_IE
11247  *  0b0..Interrupt disabled
11248  *  0b1..Interrupt enabled
11249  */
11250 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)     (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
11251 
11252 #define CSI_CR18_RGB888A_FORMAT_SEL_MASK         (0x400U)
11253 #define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT        (10U)
11254 /*! RGB888A_FORMAT_SEL
11255  *  0b0..{8'h0, data[23:0]}
11256  *  0b1..{data[23:0], 8'h0}
11257  */
11258 #define CSI_CR18_RGB888A_FORMAT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
11259 
11260 #define CSI_CR18_AHB_HPROT_MASK                  (0xF000U)
11261 #define CSI_CR18_AHB_HPROT_SHIFT                 (12U)
11262 #define CSI_CR18_AHB_HPROT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
11263 
11264 #define CSI_CR18_MASK_OPTION_MASK                (0xC0000U)
11265 #define CSI_CR18_MASK_OPTION_SHIFT               (18U)
11266 /*! MASK_OPTION
11267  *  0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1.
11268  *  0b01..Writing to memory when CSI_ENABLE is 1.
11269  *  0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
11270  *  0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
11271  */
11272 #define CSI_CR18_MASK_OPTION(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
11273 
11274 #define CSI_CR18_CSI_ENABLE_MASK                 (0x80000000U)
11275 #define CSI_CR18_CSI_ENABLE_SHIFT                (31U)
11276 #define CSI_CR18_CSI_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
11277 /*! @} */
11278 
11279 /*! @name CR19 - CSI Control Register 19 */
11280 /*! @{ */
11281 
11282 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
11283 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
11284 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
11285 /*! @} */
11286 
11287 
11288 /*!
11289  * @}
11290  */ /* end of group CSI_Register_Masks */
11291 
11292 
11293 /* CSI - Peripheral instance base addresses */
11294 /** Peripheral CSI base address */
11295 #define CSI_BASE                                 (0x402BC000u)
11296 /** Peripheral CSI base pointer */
11297 #define CSI                                      ((CSI_Type *)CSI_BASE)
11298 /** Array initializer of CSI peripheral base addresses */
11299 #define CSI_BASE_ADDRS                           { CSI_BASE }
11300 /** Array initializer of CSI peripheral base pointers */
11301 #define CSI_BASE_PTRS                            { CSI }
11302 /** Interrupt vectors for the CSI peripheral type */
11303 #define CSI_IRQS                                 { CSI_IRQn }
11304 
11305 /*!
11306  * @}
11307  */ /* end of group CSI_Peripheral_Access_Layer */
11308 
11309 
11310 /* ----------------------------------------------------------------------------
11311    -- CSU Peripheral Access Layer
11312    ---------------------------------------------------------------------------- */
11313 
11314 /*!
11315  * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
11316  * @{
11317  */
11318 
11319 /** CSU - Register Layout Typedef */
11320 typedef struct {
11321   __IO uint32_t CSL[32];                           /**< Config security level register, array offset: 0x0, array step: 0x4 */
11322        uint8_t RESERVED_0[384];
11323   __IO uint32_t HP0;                               /**< HP0 register, offset: 0x200 */
11324        uint8_t RESERVED_1[20];
11325   __IO uint32_t SA;                                /**< Secure access register, offset: 0x218 */
11326        uint8_t RESERVED_2[316];
11327   __IO uint32_t HPCONTROL0;                        /**< HPCONTROL0 register, offset: 0x358 */
11328 } CSU_Type;
11329 
11330 /* ----------------------------------------------------------------------------
11331    -- CSU Register Masks
11332    ---------------------------------------------------------------------------- */
11333 
11334 /*!
11335  * @addtogroup CSU_Register_Masks CSU Register Masks
11336  * @{
11337  */
11338 
11339 /*! @name CSL - Config security level register */
11340 /*! @{ */
11341 
11342 #define CSU_CSL_SUR_S2_MASK                      (0x1U)
11343 #define CSU_CSL_SUR_S2_SHIFT                     (0U)
11344 /*! SUR_S2
11345  *  0b0..The secure user read access is disabled for the second slave.
11346  *  0b1..The secure user read access is enabled for the second slave.
11347  */
11348 #define CSU_CSL_SUR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
11349 
11350 #define CSU_CSL_SSR_S2_MASK                      (0x2U)
11351 #define CSU_CSL_SSR_S2_SHIFT                     (1U)
11352 /*! SSR_S2
11353  *  0b0..The secure supervisor read access is disabled for the second slave.
11354  *  0b1..The secure supervisor read access is enabled for the second slave.
11355  */
11356 #define CSU_CSL_SSR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
11357 
11358 #define CSU_CSL_NUR_S2_MASK                      (0x4U)
11359 #define CSU_CSL_NUR_S2_SHIFT                     (2U)
11360 /*! NUR_S2
11361  *  0b0..The non-secure user read access is disabled for the second slave.
11362  *  0b1..The non-secure user read access is enabled for the second slave.
11363  */
11364 #define CSU_CSL_NUR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
11365 
11366 #define CSU_CSL_NSR_S2_MASK                      (0x8U)
11367 #define CSU_CSL_NSR_S2_SHIFT                     (3U)
11368 /*! NSR_S2
11369  *  0b0..The non-secure supervisor read access is disabled for the second slave.
11370  *  0b1..The non-secure supervisor read access is enabled for the second slave.
11371  */
11372 #define CSU_CSL_NSR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
11373 
11374 #define CSU_CSL_SUW_S2_MASK                      (0x10U)
11375 #define CSU_CSL_SUW_S2_SHIFT                     (4U)
11376 /*! SUW_S2
11377  *  0b0..The secure user write access is disabled for the second slave.
11378  *  0b1..The secure user write access is enabled for the second slave.
11379  */
11380 #define CSU_CSL_SUW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
11381 
11382 #define CSU_CSL_SSW_S2_MASK                      (0x20U)
11383 #define CSU_CSL_SSW_S2_SHIFT                     (5U)
11384 /*! SSW_S2
11385  *  0b0..The secure supervisor write access is disabled for the second slave.
11386  *  0b1..The secure supervisor write access is enabled for the second slave.
11387  */
11388 #define CSU_CSL_SSW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
11389 
11390 #define CSU_CSL_NUW_S2_MASK                      (0x40U)
11391 #define CSU_CSL_NUW_S2_SHIFT                     (6U)
11392 /*! NUW_S2
11393  *  0b0..The non-secure user write access is disabled for the second slave.
11394  *  0b1..The non-secure user write access is enabled for the second slave.
11395  */
11396 #define CSU_CSL_NUW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
11397 
11398 #define CSU_CSL_NSW_S2_MASK                      (0x80U)
11399 #define CSU_CSL_NSW_S2_SHIFT                     (7U)
11400 /*! NSW_S2
11401  *  0b0..The non-secure supervisor write access is disabled for the second slave.
11402  *  0b1..The non-secure supervisor write access is enabled for the second slave.
11403  */
11404 #define CSU_CSL_NSW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
11405 
11406 #define CSU_CSL_LOCK_S2_MASK                     (0x100U)
11407 #define CSU_CSL_LOCK_S2_SHIFT                    (8U)
11408 /*! LOCK_S2
11409  *  0b0..Not locked. Bits 7-0 can be written by the software.
11410  *  0b1..Bits 7-0 are locked and cannot be written by the software
11411  */
11412 #define CSU_CSL_LOCK_S2(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
11413 
11414 #define CSU_CSL_SUR_S1_MASK                      (0x10000U)
11415 #define CSU_CSL_SUR_S1_SHIFT                     (16U)
11416 /*! SUR_S1
11417  *  0b0..The secure user read access is disabled for the first slave.
11418  *  0b1..The secure user read access is enabled for the first slave.
11419  */
11420 #define CSU_CSL_SUR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
11421 
11422 #define CSU_CSL_SSR_S1_MASK                      (0x20000U)
11423 #define CSU_CSL_SSR_S1_SHIFT                     (17U)
11424 /*! SSR_S1
11425  *  0b0..The secure supervisor read access is disabled for the first slave.
11426  *  0b1..The secure supervisor read access is enabled for the first slave.
11427  */
11428 #define CSU_CSL_SSR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
11429 
11430 #define CSU_CSL_NUR_S1_MASK                      (0x40000U)
11431 #define CSU_CSL_NUR_S1_SHIFT                     (18U)
11432 /*! NUR_S1
11433  *  0b0..The non-secure user read access is disabled for the first slave.
11434  *  0b1..The non-secure user read access is enabled for the first slave.
11435  */
11436 #define CSU_CSL_NUR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
11437 
11438 #define CSU_CSL_NSR_S1_MASK                      (0x80000U)
11439 #define CSU_CSL_NSR_S1_SHIFT                     (19U)
11440 /*! NSR_S1
11441  *  0b0..The non-secure supervisor read access is disabled for the first slave.
11442  *  0b1..The non-secure supervisor read access is enabled for the first slave.
11443  */
11444 #define CSU_CSL_NSR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
11445 
11446 #define CSU_CSL_SUW_S1_MASK                      (0x100000U)
11447 #define CSU_CSL_SUW_S1_SHIFT                     (20U)
11448 /*! SUW_S1
11449  *  0b0..The secure user write access is disabled for the first slave.
11450  *  0b1..The secure user write access is enabled for the first slave.
11451  */
11452 #define CSU_CSL_SUW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
11453 
11454 #define CSU_CSL_SSW_S1_MASK                      (0x200000U)
11455 #define CSU_CSL_SSW_S1_SHIFT                     (21U)
11456 /*! SSW_S1
11457  *  0b0..The secure supervisor write access is disabled for the first slave.
11458  *  0b1..The secure supervisor write access is enabled for the first slave.
11459  */
11460 #define CSU_CSL_SSW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
11461 
11462 #define CSU_CSL_NUW_S1_MASK                      (0x400000U)
11463 #define CSU_CSL_NUW_S1_SHIFT                     (22U)
11464 /*! NUW_S1
11465  *  0b0..The non-secure user write access is disabled for the first slave.
11466  *  0b1..The non-secure user write access is enabled for the first slave.
11467  */
11468 #define CSU_CSL_NUW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
11469 
11470 #define CSU_CSL_NSW_S1_MASK                      (0x800000U)
11471 #define CSU_CSL_NSW_S1_SHIFT                     (23U)
11472 /*! NSW_S1
11473  *  0b0..The non-secure supervisor write access is disabled for the first slave.
11474  *  0b1..The non-secure supervisor write access is enabled for the first slave
11475  */
11476 #define CSU_CSL_NSW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
11477 
11478 #define CSU_CSL_LOCK_S1_MASK                     (0x1000000U)
11479 #define CSU_CSL_LOCK_S1_SHIFT                    (24U)
11480 /*! LOCK_S1
11481  *  0b0..Not locked. The bits 16-23 can be written by the software.
11482  *  0b1..The bits 16-23 are locked and can't be written by the software.
11483  */
11484 #define CSU_CSL_LOCK_S1(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
11485 /*! @} */
11486 
11487 /* The count of CSU_CSL */
11488 #define CSU_CSL_COUNT                            (32U)
11489 
11490 /*! @name HP0 - HP0 register */
11491 /*! @{ */
11492 
11493 #define CSU_HP0_HP_DMA_MASK                      (0x4U)
11494 #define CSU_HP0_HP_DMA_SHIFT                     (2U)
11495 /*! HP_DMA
11496  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11497  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11498  */
11499 #define CSU_HP0_HP_DMA(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
11500 
11501 #define CSU_HP0_L_DMA_MASK                       (0x8U)
11502 #define CSU_HP0_L_DMA_SHIFT                      (3U)
11503 /*! L_DMA
11504  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11505  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11506  */
11507 #define CSU_HP0_L_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
11508 
11509 #define CSU_HP0_HP_LCDIF_MASK                    (0x10U)
11510 #define CSU_HP0_HP_LCDIF_SHIFT                   (4U)
11511 /*! HP_LCDIF
11512  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11513  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11514  */
11515 #define CSU_HP0_HP_LCDIF(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
11516 
11517 #define CSU_HP0_L_LCDIF_MASK                     (0x20U)
11518 #define CSU_HP0_L_LCDIF_SHIFT                    (5U)
11519 /*! L_LCDIF
11520  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11521  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11522  */
11523 #define CSU_HP0_L_LCDIF(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
11524 
11525 #define CSU_HP0_HP_CSI_MASK                      (0x40U)
11526 #define CSU_HP0_HP_CSI_SHIFT                     (6U)
11527 /*! HP_CSI
11528  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11529  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11530  */
11531 #define CSU_HP0_HP_CSI(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
11532 
11533 #define CSU_HP0_L_CSI_MASK                       (0x80U)
11534 #define CSU_HP0_L_CSI_SHIFT                      (7U)
11535 /*! L_CSI
11536  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11537  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11538  */
11539 #define CSU_HP0_L_CSI(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
11540 
11541 #define CSU_HP0_HP_PXP_MASK                      (0x100U)
11542 #define CSU_HP0_HP_PXP_SHIFT                     (8U)
11543 /*! HP_PXP
11544  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11545  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11546  */
11547 #define CSU_HP0_HP_PXP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
11548 
11549 #define CSU_HP0_L_PXP_MASK                       (0x200U)
11550 #define CSU_HP0_L_PXP_SHIFT                      (9U)
11551 /*! L_PXP
11552  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11553  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11554  */
11555 #define CSU_HP0_L_PXP(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
11556 
11557 #define CSU_HP0_HP_DCP_MASK                      (0x400U)
11558 #define CSU_HP0_HP_DCP_SHIFT                     (10U)
11559 /*! HP_DCP
11560  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11561  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11562  */
11563 #define CSU_HP0_HP_DCP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
11564 
11565 #define CSU_HP0_L_DCP_MASK                       (0x800U)
11566 #define CSU_HP0_L_DCP_SHIFT                      (11U)
11567 /*! L_DCP
11568  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11569  *  0b1..Lock-the adjacent (next lower) bit cannot be written by the software.
11570  */
11571 #define CSU_HP0_L_DCP(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
11572 
11573 #define CSU_HP0_HP_ENET_MASK                     (0x4000U)
11574 #define CSU_HP0_HP_ENET_SHIFT                    (14U)
11575 /*! HP_ENET
11576  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11577  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11578  */
11579 #define CSU_HP0_HP_ENET(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
11580 
11581 #define CSU_HP0_L_ENET_MASK                      (0x8000U)
11582 #define CSU_HP0_L_ENET_SHIFT                     (15U)
11583 /*! L_ENET
11584  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11585  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11586  */
11587 #define CSU_HP0_L_ENET(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
11588 
11589 #define CSU_HP0_HP_USDHC1_MASK                   (0x10000U)
11590 #define CSU_HP0_HP_USDHC1_SHIFT                  (16U)
11591 /*! HP_USDHC1
11592  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11593  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11594  */
11595 #define CSU_HP0_HP_USDHC1(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
11596 
11597 #define CSU_HP0_L_USDHC1_MASK                    (0x20000U)
11598 #define CSU_HP0_L_USDHC1_SHIFT                   (17U)
11599 /*! L_USDHC1
11600  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11601  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11602  */
11603 #define CSU_HP0_L_USDHC1(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
11604 
11605 #define CSU_HP0_HP_USDHC2_MASK                   (0x40000U)
11606 #define CSU_HP0_HP_USDHC2_SHIFT                  (18U)
11607 /*! HP_USDHC2
11608  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11609  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11610  */
11611 #define CSU_HP0_HP_USDHC2(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
11612 
11613 #define CSU_HP0_L_USDHC2_MASK                    (0x80000U)
11614 #define CSU_HP0_L_USDHC2_SHIFT                   (19U)
11615 /*! L_USDHC2
11616  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11617  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11618  */
11619 #define CSU_HP0_L_USDHC2(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
11620 
11621 #define CSU_HP0_HP_TPSMP_MASK                    (0x100000U)
11622 #define CSU_HP0_HP_TPSMP_SHIFT                   (20U)
11623 /*! HP_TPSMP
11624  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11625  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11626  */
11627 #define CSU_HP0_HP_TPSMP(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
11628 
11629 #define CSU_HP0_L_TPSMP_MASK                     (0x200000U)
11630 #define CSU_HP0_L_TPSMP_SHIFT                    (21U)
11631 /*! L_TPSMP
11632  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11633  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11634  */
11635 #define CSU_HP0_L_TPSMP(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
11636 
11637 #define CSU_HP0_HP_USB_MASK                      (0x400000U)
11638 #define CSU_HP0_HP_USB_SHIFT                     (22U)
11639 /*! HP_USB
11640  *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11641  *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11642  */
11643 #define CSU_HP0_HP_USB(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
11644 
11645 #define CSU_HP0_L_USB_MASK                       (0x800000U)
11646 #define CSU_HP0_L_USB_SHIFT                      (23U)
11647 /*! L_USB
11648  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11649  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11650  */
11651 #define CSU_HP0_L_USB(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
11652 /*! @} */
11653 
11654 /*! @name SA - Secure access register */
11655 /*! @{ */
11656 
11657 #define CSU_SA_NSA_DMA_MASK                      (0x4U)
11658 #define CSU_SA_NSA_DMA_SHIFT                     (2U)
11659 /*! NSA_DMA - Non-secure access policy indicator bit
11660  *  0b0..Secure access for the corresponding type-1 master
11661  *  0b1..Non-secure access for the corresponding type-1 master
11662  */
11663 #define CSU_SA_NSA_DMA(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
11664 
11665 #define CSU_SA_L_DMA_MASK                        (0x8U)
11666 #define CSU_SA_L_DMA_SHIFT                       (3U)
11667 /*! L_DMA
11668  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11669  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11670  */
11671 #define CSU_SA_L_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
11672 
11673 #define CSU_SA_NSA_LCDIF_MASK                    (0x10U)
11674 #define CSU_SA_NSA_LCDIF_SHIFT                   (4U)
11675 /*! NSA_LCDIF - Non-secure access policy indicator bit
11676  *  0b0..Secure access for the corresponding type-1 master
11677  *  0b1..Non-secure access for the corresponding type-1 master
11678  */
11679 #define CSU_SA_NSA_LCDIF(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
11680 
11681 #define CSU_SA_L_LCDIF_MASK                      (0x20U)
11682 #define CSU_SA_L_LCDIF_SHIFT                     (5U)
11683 /*! L_LCDIF
11684  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11685  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11686  */
11687 #define CSU_SA_L_LCDIF(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
11688 
11689 #define CSU_SA_NSA_CSI_MASK                      (0x40U)
11690 #define CSU_SA_NSA_CSI_SHIFT                     (6U)
11691 /*! NSA_CSI - Non-secure access policy indicator bit
11692  *  0b0..Secure access for the corresponding type-1 master
11693  *  0b1..Non-secure access for the corresponding type-1 master
11694  */
11695 #define CSU_SA_NSA_CSI(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
11696 
11697 #define CSU_SA_L_CSI_MASK                        (0x80U)
11698 #define CSU_SA_L_CSI_SHIFT                       (7U)
11699 /*! L_CSI
11700  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11701  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11702  */
11703 #define CSU_SA_L_CSI(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
11704 
11705 #define CSU_SA_NSA_PXP_MASK                      (0x100U)
11706 #define CSU_SA_NSA_PXP_SHIFT                     (8U)
11707 /*! NSA_PXP - Non-Secure Access Policy indicator bit
11708  *  0b0..Secure access for the corresponding type-1 master
11709  *  0b1..Non-secure access for the corresponding type-1 master
11710  */
11711 #define CSU_SA_NSA_PXP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
11712 
11713 #define CSU_SA_L_PXP_MASK                        (0x200U)
11714 #define CSU_SA_L_PXP_SHIFT                       (9U)
11715 /*! L_PXP
11716  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11717  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11718  */
11719 #define CSU_SA_L_PXP(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
11720 
11721 #define CSU_SA_NSA_DCP_MASK                      (0x400U)
11722 #define CSU_SA_NSA_DCP_SHIFT                     (10U)
11723 /*! NSA_DCP - Non-secure access policy indicator bit
11724  *  0b0..Secure access for the corresponding type-1 master
11725  *  0b1..Non-secure access for the corresponding type-1 master
11726  */
11727 #define CSU_SA_NSA_DCP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
11728 
11729 #define CSU_SA_L_DCP_MASK                        (0x800U)
11730 #define CSU_SA_L_DCP_SHIFT                       (11U)
11731 /*! L_DCP
11732  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11733  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11734  */
11735 #define CSU_SA_L_DCP(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
11736 
11737 #define CSU_SA_NSA_ENET_MASK                     (0x4000U)
11738 #define CSU_SA_NSA_ENET_SHIFT                    (14U)
11739 /*! NSA_ENET - Non-secure access policy indicator bit
11740  *  0b0..Secure access for the corresponding type-1 master
11741  *  0b1..Non-secure access for the corresponding type-1 master
11742  */
11743 #define CSU_SA_NSA_ENET(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
11744 
11745 #define CSU_SA_L_ENET_MASK                       (0x8000U)
11746 #define CSU_SA_L_ENET_SHIFT                      (15U)
11747 /*! L_ENET
11748  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11749  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11750  */
11751 #define CSU_SA_L_ENET(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
11752 
11753 #define CSU_SA_NSA_USDHC1_MASK                   (0x10000U)
11754 #define CSU_SA_NSA_USDHC1_SHIFT                  (16U)
11755 /*! NSA_USDHC1 - Non-secure access policy indicator bit
11756  *  0b0..Secure access for the corresponding type-1 master
11757  *  0b1..Non-secure access for the corresponding type-1 master
11758  */
11759 #define CSU_SA_NSA_USDHC1(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
11760 
11761 #define CSU_SA_L_USDHC1_MASK                     (0x20000U)
11762 #define CSU_SA_L_USDHC1_SHIFT                    (17U)
11763 /*! L_USDHC1
11764  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11765  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11766  */
11767 #define CSU_SA_L_USDHC1(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
11768 
11769 #define CSU_SA_NSA_USDHC2_MASK                   (0x40000U)
11770 #define CSU_SA_NSA_USDHC2_SHIFT                  (18U)
11771 /*! NSA_USDHC2 - Non-secure access policy indicator bit
11772  *  0b0..Secure access for the corresponding type-1 master
11773  *  0b1..Non-secure access for the corresponding type-1 master
11774  */
11775 #define CSU_SA_NSA_USDHC2(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
11776 
11777 #define CSU_SA_L_USDHC2_MASK                     (0x80000U)
11778 #define CSU_SA_L_USDHC2_SHIFT                    (19U)
11779 /*! L_USDHC2
11780  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11781  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11782  */
11783 #define CSU_SA_L_USDHC2(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
11784 
11785 #define CSU_SA_NSA_TPSMP_MASK                    (0x100000U)
11786 #define CSU_SA_NSA_TPSMP_SHIFT                   (20U)
11787 /*! NSA_TPSMP - Non-secure access policy indicator bit
11788  *  0b0..Secure access for the corresponding type-1 master
11789  *  0b1..Non-secure access for the corresponding type-1 master
11790  */
11791 #define CSU_SA_NSA_TPSMP(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
11792 
11793 #define CSU_SA_L_TPSMP_MASK                      (0x200000U)
11794 #define CSU_SA_L_TPSMP_SHIFT                     (21U)
11795 /*! L_TPSMP
11796  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11797  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11798  */
11799 #define CSU_SA_L_TPSMP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
11800 
11801 #define CSU_SA_NSA_USB_MASK                      (0x400000U)
11802 #define CSU_SA_NSA_USB_SHIFT                     (22U)
11803 /*! NSA_USB - Non-secure access policy indicator bit
11804  *  0b0..Secure access for the corresponding type-1 master
11805  *  0b1..Non-secure access for the corresponding type-1 master
11806  */
11807 #define CSU_SA_NSA_USB(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
11808 
11809 #define CSU_SA_L_USB_MASK                        (0x800000U)
11810 #define CSU_SA_L_USB_SHIFT                       (23U)
11811 /*! L_USB
11812  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11813  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11814  */
11815 #define CSU_SA_L_USB(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
11816 /*! @} */
11817 
11818 /*! @name HPCONTROL0 - HPCONTROL0 register */
11819 /*! @{ */
11820 
11821 #define CSU_HPCONTROL0_HPC_DMA_MASK              (0x4U)
11822 #define CSU_HPCONTROL0_HPC_DMA_SHIFT             (2U)
11823 /*! HPC_DMA
11824  *  0b0..User mode for the corresponding master
11825  *  0b1..Supervisor mode for the corresponding master
11826  */
11827 #define CSU_HPCONTROL0_HPC_DMA(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
11828 
11829 #define CSU_HPCONTROL0_L_DMA_MASK                (0x8U)
11830 #define CSU_HPCONTROL0_L_DMA_SHIFT               (3U)
11831 /*! L_DMA
11832  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11833  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11834  */
11835 #define CSU_HPCONTROL0_L_DMA(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
11836 
11837 #define CSU_HPCONTROL0_HPC_LCDIF_MASK            (0x10U)
11838 #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT           (4U)
11839 /*! HPC_LCDIF
11840  *  0b0..User mode for the corresponding master
11841  *  0b1..Supervisor mode for the corresponding master
11842  */
11843 #define CSU_HPCONTROL0_HPC_LCDIF(x)              (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
11844 
11845 #define CSU_HPCONTROL0_L_LCDIF_MASK              (0x20U)
11846 #define CSU_HPCONTROL0_L_LCDIF_SHIFT             (5U)
11847 /*! L_LCDIF
11848  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11849  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11850  */
11851 #define CSU_HPCONTROL0_L_LCDIF(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
11852 
11853 #define CSU_HPCONTROL0_HPC_CSI_MASK              (0x40U)
11854 #define CSU_HPCONTROL0_HPC_CSI_SHIFT             (6U)
11855 /*! HPC_CSI
11856  *  0b0..User mode for the corresponding master
11857  *  0b1..Supervisor mode for the corresponding master
11858  */
11859 #define CSU_HPCONTROL0_HPC_CSI(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
11860 
11861 #define CSU_HPCONTROL0_L_CSI_MASK                (0x80U)
11862 #define CSU_HPCONTROL0_L_CSI_SHIFT               (7U)
11863 /*! L_CSI
11864  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11865  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11866  */
11867 #define CSU_HPCONTROL0_L_CSI(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
11868 
11869 #define CSU_HPCONTROL0_HPC_PXP_MASK              (0x100U)
11870 #define CSU_HPCONTROL0_HPC_PXP_SHIFT             (8U)
11871 /*! HPC_PXP
11872  *  0b0..User mode for the corresponding master
11873  *  0b1..Supervisor mode for the corresponding master
11874  */
11875 #define CSU_HPCONTROL0_HPC_PXP(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
11876 
11877 #define CSU_HPCONTROL0_L_PXP_MASK                (0x200U)
11878 #define CSU_HPCONTROL0_L_PXP_SHIFT               (9U)
11879 /*! L_PXP
11880  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11881  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11882  */
11883 #define CSU_HPCONTROL0_L_PXP(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
11884 
11885 #define CSU_HPCONTROL0_HPC_DCP_MASK              (0x400U)
11886 #define CSU_HPCONTROL0_HPC_DCP_SHIFT             (10U)
11887 /*! HPC_DCP
11888  *  0b0..User mode for the corresponding master
11889  *  0b1..Supervisor mode for the corresponding master
11890  */
11891 #define CSU_HPCONTROL0_HPC_DCP(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
11892 
11893 #define CSU_HPCONTROL0_L_DCP_MASK                (0x800U)
11894 #define CSU_HPCONTROL0_L_DCP_SHIFT               (11U)
11895 /*! L_DCP
11896  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11897  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11898  */
11899 #define CSU_HPCONTROL0_L_DCP(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
11900 
11901 #define CSU_HPCONTROL0_HPC_ENET_MASK             (0x4000U)
11902 #define CSU_HPCONTROL0_HPC_ENET_SHIFT            (14U)
11903 /*! HPC_ENET
11904  *  0b0..User mode for the corresponding master
11905  *  0b1..Supervisor mode for the corresponding master
11906  */
11907 #define CSU_HPCONTROL0_HPC_ENET(x)               (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
11908 
11909 #define CSU_HPCONTROL0_L_ENET_MASK               (0x8000U)
11910 #define CSU_HPCONTROL0_L_ENET_SHIFT              (15U)
11911 /*! L_ENET
11912  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11913  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11914  */
11915 #define CSU_HPCONTROL0_L_ENET(x)                 (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
11916 
11917 #define CSU_HPCONTROL0_HPC_USDHC1_MASK           (0x10000U)
11918 #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT          (16U)
11919 /*! HPC_USDHC1
11920  *  0b0..User mode for the corresponding master
11921  *  0b1..Supervisor mode for the corresponding master
11922  */
11923 #define CSU_HPCONTROL0_HPC_USDHC1(x)             (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
11924 
11925 #define CSU_HPCONTROL0_L_USDHC1_MASK             (0x20000U)
11926 #define CSU_HPCONTROL0_L_USDHC1_SHIFT            (17U)
11927 /*! L_USDHC1
11928  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11929  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11930  */
11931 #define CSU_HPCONTROL0_L_USDHC1(x)               (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
11932 
11933 #define CSU_HPCONTROL0_HPC_USDHC2_MASK           (0x40000U)
11934 #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT          (18U)
11935 /*! HPC_USDHC2
11936  *  0b0..User mode for the corresponding master
11937  *  0b1..Supervisor mode for the corresponding master
11938  */
11939 #define CSU_HPCONTROL0_HPC_USDHC2(x)             (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
11940 
11941 #define CSU_HPCONTROL0_L_USDHC2_MASK             (0x80000U)
11942 #define CSU_HPCONTROL0_L_USDHC2_SHIFT            (19U)
11943 /*! L_USDHC2
11944  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11945  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11946  */
11947 #define CSU_HPCONTROL0_L_USDHC2(x)               (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
11948 
11949 #define CSU_HPCONTROL0_HPC_TPSMP_MASK            (0x100000U)
11950 #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT           (20U)
11951 /*! HPC_TPSMP
11952  *  0b0..User mode for the corresponding master
11953  *  0b1..Supervisor mode for the corresponding master
11954  */
11955 #define CSU_HPCONTROL0_HPC_TPSMP(x)              (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
11956 
11957 #define CSU_HPCONTROL0_L_TPSMP_MASK              (0x200000U)
11958 #define CSU_HPCONTROL0_L_TPSMP_SHIFT             (21U)
11959 /*! L_TPSMP
11960  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11961  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11962  */
11963 #define CSU_HPCONTROL0_L_TPSMP(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
11964 
11965 #define CSU_HPCONTROL0_HPC_USB_MASK              (0x400000U)
11966 #define CSU_HPCONTROL0_HPC_USB_SHIFT             (22U)
11967 /*! HPC_USB
11968  *  0b0..User mode for the corresponding master
11969  *  0b1..Supervisor mode for the corresponding master
11970  */
11971 #define CSU_HPCONTROL0_HPC_USB(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
11972 
11973 #define CSU_HPCONTROL0_L_USB_MASK                (0x800000U)
11974 #define CSU_HPCONTROL0_L_USB_SHIFT               (23U)
11975 /*! L_USB
11976  *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
11977  *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11978  */
11979 #define CSU_HPCONTROL0_L_USB(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
11980 /*! @} */
11981 
11982 
11983 /*!
11984  * @}
11985  */ /* end of group CSU_Register_Masks */
11986 
11987 
11988 /* CSU - Peripheral instance base addresses */
11989 /** Peripheral CSU base address */
11990 #define CSU_BASE                                 (0x400DC000u)
11991 /** Peripheral CSU base pointer */
11992 #define CSU                                      ((CSU_Type *)CSU_BASE)
11993 /** Array initializer of CSU peripheral base addresses */
11994 #define CSU_BASE_ADDRS                           { CSU_BASE }
11995 /** Array initializer of CSU peripheral base pointers */
11996 #define CSU_BASE_PTRS                            { CSU }
11997 
11998 /*!
11999  * @}
12000  */ /* end of group CSU_Peripheral_Access_Layer */
12001 
12002 
12003 /* ----------------------------------------------------------------------------
12004    -- DCDC Peripheral Access Layer
12005    ---------------------------------------------------------------------------- */
12006 
12007 /*!
12008  * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
12009  * @{
12010  */
12011 
12012 /** DCDC - Register Layout Typedef */
12013 typedef struct {
12014   __IO uint32_t REG0;                              /**< DCDC Register 0, offset: 0x0 */
12015   __IO uint32_t REG1;                              /**< DCDC Register 1, offset: 0x4 */
12016   __IO uint32_t REG2;                              /**< DCDC Register 2, offset: 0x8 */
12017   __IO uint32_t REG3;                              /**< DCDC Register 3, offset: 0xC */
12018 } DCDC_Type;
12019 
12020 /* ----------------------------------------------------------------------------
12021    -- DCDC Register Masks
12022    ---------------------------------------------------------------------------- */
12023 
12024 /*!
12025  * @addtogroup DCDC_Register_Masks DCDC Register Masks
12026  * @{
12027  */
12028 
12029 /*! @name REG0 - DCDC Register 0 */
12030 /*! @{ */
12031 
12032 #define DCDC_REG0_PWD_ZCD_MASK                   (0x1U)
12033 #define DCDC_REG0_PWD_ZCD_SHIFT                  (0U)
12034 /*! PWD_ZCD - Power Down Zero Cross Detection
12035  *  0b0..Zero cross detetion function powered up
12036  *  0b1..Zero cross detetion function powered down
12037  */
12038 #define DCDC_REG0_PWD_ZCD(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
12039 
12040 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
12041 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT  (1U)
12042 /*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch
12043  *  0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring OSC to 24M xtal automatically
12044  *  0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses
12045  */
12046 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
12047 
12048 #define DCDC_REG0_SEL_CLK_MASK                   (0x4U)
12049 #define DCDC_REG0_SEL_CLK_SHIFT                  (2U)
12050 /*! SEL_CLK - Select Clock
12051  *  0b0..DCDC uses internal ring oscillator
12052  *  0b1..DCDC uses 24M xtal
12053  */
12054 #define DCDC_REG0_SEL_CLK(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
12055 
12056 #define DCDC_REG0_PWD_OSC_INT_MASK               (0x8U)
12057 #define DCDC_REG0_PWD_OSC_INT_SHIFT              (3U)
12058 /*! PWD_OSC_INT - Power down internal osc
12059  *  0b0..Internal oscillator powered up
12060  *  0b1..Internal oscillator powered down
12061  */
12062 #define DCDC_REG0_PWD_OSC_INT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
12063 
12064 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK           (0x10U)
12065 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT          (4U)
12066 /*! PWD_CUR_SNS_CMP - Power down signal of the current detector.
12067  *  0b0..Current Detector powered up
12068  *  0b1..Current Detector powered down
12069  */
12070 #define DCDC_REG0_PWD_CUR_SNS_CMP(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
12071 
12072 #define DCDC_REG0_CUR_SNS_THRSH_MASK             (0xE0U)
12073 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT            (5U)
12074 /*! CUR_SNS_THRSH - Current Sense (detector) Threshold
12075  *  0b000..150 mA
12076  *  0b001..250 mA
12077  *  0b010..350 mA
12078  *  0b011..450 mA
12079  *  0b100..550 mA
12080  *  0b101..650 mA
12081  */
12082 #define DCDC_REG0_CUR_SNS_THRSH(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
12083 
12084 #define DCDC_REG0_PWD_OVERCUR_DET_MASK           (0x100U)
12085 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT          (8U)
12086 /*! PWD_OVERCUR_DET - Power down overcurrent detection comparator
12087  *  0b0..Overcurrent detection comparator is enabled
12088  *  0b1..Overcurrent detection comparator is disabled
12089  */
12090 #define DCDC_REG0_PWD_OVERCUR_DET(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
12091 
12092 #define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK          (0x600U)
12093 #define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT         (9U)
12094 /*! OVERCUR_TRIG_ADJ - Overcurrent Trigger Adjust
12095  *  0b00..In Run Mode, 1 A. In Power Save Mode, 0.25 A
12096  *  0b01..In Run Mode, 2 A. In Power Save Mode, 0.25 A
12097  *  0b10..In Run Mode, 1 A. In Power Save Mode, 0.2 A
12098  *  0b11..In Run Mode, 2 A. In Power Save Mode, 0.2 A
12099  */
12100 #define DCDC_REG0_OVERCUR_TRIG_ADJ(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
12101 
12102 #define DCDC_REG0_PWD_CMP_BATT_DET_MASK          (0x800U)
12103 #define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT         (11U)
12104 /*! PWD_CMP_BATT_DET - Power Down Battery Detection Comparator
12105  *  0b0..Low voltage detection comparator is enabled
12106  *  0b1..Low voltage detection comparator is disabled
12107  */
12108 #define DCDC_REG0_PWD_CMP_BATT_DET(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
12109 
12110 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK        (0x10000U)
12111 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT       (16U)
12112 /*! EN_LP_OVERLOAD_SNS - Low Power Overload Sense Enable
12113  *  0b0..Overload Detection in power save mode disabled
12114  *  0b1..Overload Detection in power save mode enabled
12115  */
12116 #define DCDC_REG0_EN_LP_OVERLOAD_SNS(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
12117 
12118 #define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK         (0x20000U)
12119 #define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT        (17U)
12120 /*! PWD_HIGH_VOLT_DET - Power Down High Voltage Detection
12121  *  0b0..Overvoltage detection comparator is enabled
12122  *  0b1..Overvoltage detection comparator is disabled
12123  */
12124 #define DCDC_REG0_PWD_HIGH_VOLT_DET(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
12125 
12126 #define DCDC_REG0_LP_OVERLOAD_THRSH_MASK         (0xC0000U)
12127 #define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT        (18U)
12128 /*! LP_OVERLOAD_THRSH - Low Power Overload Threshold
12129  *  0b00..32
12130  *  0b01..64
12131  *  0b10..16
12132  *  0b11..8
12133  */
12134 #define DCDC_REG0_LP_OVERLOAD_THRSH(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
12135 
12136 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK      (0x100000U)
12137 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT     (20U)
12138 /*! LP_OVERLOAD_FREQ_SEL - Low Power Overload Frequency Select
12139  *  0b0..eight 32k cycle
12140  *  0b1..sixteen 32k cycle
12141  */
12142 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
12143 
12144 #define DCDC_REG0_LP_HIGH_HYS_MASK               (0x200000U)
12145 #define DCDC_REG0_LP_HIGH_HYS_SHIFT              (21U)
12146 /*! LP_HIGH_HYS - Low Power High Hysteric Value
12147  *  0b0..Adjust hysteretic value in low power to 12.5mV
12148  *  0b1..Adjust hysteretic value in low power to 25mV
12149  */
12150 #define DCDC_REG0_LP_HIGH_HYS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
12151 
12152 #define DCDC_REG0_PWD_CMP_OFFSET_MASK            (0x4000000U)
12153 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT           (26U)
12154 /*! PWD_CMP_OFFSET - Power down output range comparator
12155  *  0b0..Output range comparator powered up
12156  *  0b1..Output range comparator powered down
12157  */
12158 #define DCDC_REG0_PWD_CMP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
12159 
12160 #define DCDC_REG0_XTALOK_DISABLE_MASK            (0x8000000U)
12161 #define DCDC_REG0_XTALOK_DISABLE_SHIFT           (27U)
12162 /*! XTALOK_DISABLE - Disable xtalok detection circuit
12163  *  0b0..Enable xtalok detection circuit
12164  *  0b1..Disable xtalok detection circuit and always outputs OK signal "1"
12165  */
12166 #define DCDC_REG0_XTALOK_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
12167 
12168 #define DCDC_REG0_CURRENT_ALERT_RESET_MASK       (0x10000000U)
12169 #define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT      (28U)
12170 /*! CURRENT_ALERT_RESET - Reset Current Alert Signal
12171  *  0b0..Current Alert Signal not reset
12172  *  0b1..Current Alert Signal reset
12173  */
12174 #define DCDC_REG0_CURRENT_ALERT_RESET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
12175 
12176 #define DCDC_REG0_XTAL_24M_OK_MASK               (0x20000000U)
12177 #define DCDC_REG0_XTAL_24M_OK_SHIFT              (29U)
12178 /*! XTAL_24M_OK - 24M XTAL OK
12179  *  0b0..DCDC uses internal ring OSC
12180  *  0b1..DCDC uses xtal 24M
12181  */
12182 #define DCDC_REG0_XTAL_24M_OK(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
12183 
12184 #define DCDC_REG0_STS_DC_OK_MASK                 (0x80000000U)
12185 #define DCDC_REG0_STS_DC_OK_SHIFT                (31U)
12186 /*! STS_DC_OK - DCDC Output OK
12187  *  0b0..DCDC is settling
12188  *  0b1..DCDC already settled
12189  */
12190 #define DCDC_REG0_STS_DC_OK(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
12191 /*! @} */
12192 
12193 /*! @name REG1 - DCDC Register 1 */
12194 /*! @{ */
12195 
12196 #define DCDC_REG1_REG_FBK_SEL_MASK               (0x180U)
12197 #define DCDC_REG1_REG_FBK_SEL_SHIFT              (7U)
12198 /*! REG_FBK_SEL
12199  *  0b00..The regulator outputs 1.0V with 1.2V reference voltage
12200  *  0b01..The regulator outputs 1.1V with 1.2V reference voltage
12201  *  0b10..The regulator outputs 1.0V with 1.3V reference voltage
12202  *  0b11..The regulator outputs 1.1V with 1.3V reference voltage
12203  */
12204 #define DCDC_REG1_REG_FBK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
12205 
12206 #define DCDC_REG1_REG_RLOAD_SW_MASK              (0x200U)
12207 #define DCDC_REG1_REG_RLOAD_SW_SHIFT             (9U)
12208 /*! REG_RLOAD_SW
12209  *  0b0..Load resistor disconnected
12210  *  0b1..Load resistor connected
12211  */
12212 #define DCDC_REG1_REG_RLOAD_SW(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
12213 
12214 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK           (0x3000U)
12215 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT          (12U)
12216 /*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias
12217  *  0b00..50 nA
12218  *  0b01..100 nA
12219  *  0b10..200 nA
12220  *  0b11..400 nA
12221  */
12222 #define DCDC_REG1_LP_CMP_ISRC_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
12223 
12224 #define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK       (0x200000U)
12225 #define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT      (21U)
12226 /*! LOOPCTRL_HST_THRESH - Increase Threshold Detection
12227  *  0b0..Lower hysteresis threshold (about 2.5mV in typical, but this value can vary with PVT corners
12228  *  0b1..Higher hysteresis threshold (about 5mV in typical)
12229  */
12230 #define DCDC_REG1_LOOPCTRL_HST_THRESH(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
12231 
12232 #define DCDC_REG1_LOOPCTRL_EN_HYST_MASK          (0x800000U)
12233 #define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT         (23U)
12234 /*! LOOPCTRL_EN_HYST - Enable Hysteresis
12235  *  0b0..Disable hysteresis in switching converter common mode analog comparators
12236  *  0b1..Enable hysteresis in switching converter common mode analog comparators
12237  */
12238 #define DCDC_REG1_LOOPCTRL_EN_HYST(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
12239 
12240 #define DCDC_REG1_VBG_TRIM_MASK                  (0x1F000000U)
12241 #define DCDC_REG1_VBG_TRIM_SHIFT                 (24U)
12242 /*! VBG_TRIM - Trim Bandgap Voltage
12243  */
12244 #define DCDC_REG1_VBG_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
12245 /*! @} */
12246 
12247 /*! @name REG2 - DCDC Register 2 */
12248 /*! @{ */
12249 
12250 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK            (0x1C0U)
12251 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT           (6U)
12252 #define DCDC_REG2_LOOPCTRL_DC_FF(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
12253 
12254 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK       (0xE00U)
12255 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT      (9U)
12256 /*! LOOPCTRL_EN_RCSCALE - Enable RC Scale
12257  */
12258 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
12259 
12260 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK    (0x1000U)
12261 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
12262 /*! LOOPCTRL_RCSCALE_THRSH
12263  *  0b0..Do not increase the threshold detection for RC scale circuit.
12264  *  0b1..Increase the threshold detection for RC scale circuit.
12265  */
12266 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
12267 
12268 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK        (0x2000U)
12269 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT       (13U)
12270 /*! LOOPCTRL_HYST_SIGN
12271  *  0b0..Do not invert sign of the hysteresis
12272  *  0b1..Invert sign of the hysteresis
12273  */
12274 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
12275 
12276 #define DCDC_REG2_DISABLE_PULSE_SKIP_MASK        (0x8000000U)
12277 #define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT       (27U)
12278 /*! DISABLE_PULSE_SKIP - Disable Pulse Skip
12279  *  0b0..DCDC will be idle to save current dissipation when the duty cycle get to the low limit which is set by NEGLIMIT_IN.
12280  *  0b1..DCDC will keep working with the low limited duty cycle NEGLIMIT_IN.
12281  */
12282 #define DCDC_REG2_DISABLE_PULSE_SKIP(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
12283 
12284 #define DCDC_REG2_DCM_SET_CTRL_MASK              (0x10000000U)
12285 #define DCDC_REG2_DCM_SET_CTRL_SHIFT             (28U)
12286 /*! DCM_SET_CTRL - DCM Set Control
12287  */
12288 #define DCDC_REG2_DCM_SET_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
12289 /*! @} */
12290 
12291 /*! @name REG3 - DCDC Register 3 */
12292 /*! @{ */
12293 
12294 #define DCDC_REG3_TRG_MASK                       (0x1FU)
12295 #define DCDC_REG3_TRG_SHIFT                      (0U)
12296 /*! TRG - Target value of VDD_SOC
12297  */
12298 #define DCDC_REG3_TRG(x)                         (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
12299 
12300 #define DCDC_REG3_TARGET_LP_MASK                 (0x700U)
12301 #define DCDC_REG3_TARGET_LP_SHIFT                (8U)
12302 /*! TARGET_LP - Low Power Target Value
12303  *  0b000..0.9 V
12304  *  0b001..0.925 V
12305  *  0b010..0.95 V
12306  *  0b011..0.975 V
12307  *  0b100..1.0 V
12308  */
12309 #define DCDC_REG3_TARGET_LP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
12310 
12311 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK         (0x1000000U)
12312 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT        (24U)
12313 /*! MINPWR_DC_HALFCLK
12314  *  0b0..DCDC clock remains at full frequency for continuous mode
12315  *  0b1..DCDC clock set to half frequency for continuous mode
12316  */
12317 #define DCDC_REG3_MINPWR_DC_HALFCLK(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
12318 
12319 #define DCDC_REG3_DISABLE_STEP_MASK              (0x40000000U)
12320 #define DCDC_REG3_DISABLE_STEP_SHIFT             (30U)
12321 /*! DISABLE_STEP - Disable Step
12322  *  0b0..Enable stepping for the output of VDD_SOC of DCDC
12323  *  0b1..Disable stepping for the output of VDD_SOC of DCDC
12324  */
12325 #define DCDC_REG3_DISABLE_STEP(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
12326 /*! @} */
12327 
12328 
12329 /*!
12330  * @}
12331  */ /* end of group DCDC_Register_Masks */
12332 
12333 
12334 /* DCDC - Peripheral instance base addresses */
12335 /** Peripheral DCDC base address */
12336 #define DCDC_BASE                                (0x40080000u)
12337 /** Peripheral DCDC base pointer */
12338 #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
12339 /** Array initializer of DCDC peripheral base addresses */
12340 #define DCDC_BASE_ADDRS                          { DCDC_BASE }
12341 /** Array initializer of DCDC peripheral base pointers */
12342 #define DCDC_BASE_PTRS                           { DCDC }
12343 /** Interrupt vectors for the DCDC peripheral type */
12344 #define DCDC_IRQS                                { DCDC_IRQn }
12345 
12346 /*!
12347  * @}
12348  */ /* end of group DCDC_Peripheral_Access_Layer */
12349 
12350 
12351 /* ----------------------------------------------------------------------------
12352    -- DCP Peripheral Access Layer
12353    ---------------------------------------------------------------------------- */
12354 
12355 /*!
12356  * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer
12357  * @{
12358  */
12359 
12360 /** DCP - Register Layout Typedef */
12361 typedef struct {
12362   __IO uint32_t CTRL;                              /**< DCP control register 0, offset: 0x0 */
12363   __IO uint32_t CTRL_SET;                          /**< DCP control register 0, offset: 0x4 */
12364   __IO uint32_t CTRL_CLR;                          /**< DCP control register 0, offset: 0x8 */
12365   __IO uint32_t CTRL_TOG;                          /**< DCP control register 0, offset: 0xC */
12366   __IO uint32_t STAT;                              /**< DCP status register, offset: 0x10 */
12367   __IO uint32_t STAT_SET;                          /**< DCP status register, offset: 0x14 */
12368   __IO uint32_t STAT_CLR;                          /**< DCP status register, offset: 0x18 */
12369   __IO uint32_t STAT_TOG;                          /**< DCP status register, offset: 0x1C */
12370   __IO uint32_t CHANNELCTRL;                       /**< DCP channel control register, offset: 0x20 */
12371   __IO uint32_t CHANNELCTRL_SET;                   /**< DCP channel control register, offset: 0x24 */
12372   __IO uint32_t CHANNELCTRL_CLR;                   /**< DCP channel control register, offset: 0x28 */
12373   __IO uint32_t CHANNELCTRL_TOG;                   /**< DCP channel control register, offset: 0x2C */
12374   __IO uint32_t CAPABILITY0;                       /**< DCP capability 0 register, offset: 0x30 */
12375        uint8_t RESERVED_0[12];
12376   __I  uint32_t CAPABILITY1;                       /**< DCP capability 1 register, offset: 0x40 */
12377        uint8_t RESERVED_1[12];
12378   __IO uint32_t CONTEXT;                           /**< DCP context buffer pointer, offset: 0x50 */
12379        uint8_t RESERVED_2[12];
12380   __IO uint32_t KEY;                               /**< DCP key index, offset: 0x60 */
12381        uint8_t RESERVED_3[12];
12382   __IO uint32_t KEYDATA;                           /**< DCP key data, offset: 0x70 */
12383        uint8_t RESERVED_4[12];
12384   __I  uint32_t PACKET0;                           /**< DCP work packet 0 status register, offset: 0x80 */
12385        uint8_t RESERVED_5[12];
12386   __I  uint32_t PACKET1;                           /**< DCP work packet 1 status register, offset: 0x90 */
12387        uint8_t RESERVED_6[12];
12388   __I  uint32_t PACKET2;                           /**< DCP work packet 2 status register, offset: 0xA0 */
12389        uint8_t RESERVED_7[12];
12390   __I  uint32_t PACKET3;                           /**< DCP work packet 3 status register, offset: 0xB0 */
12391        uint8_t RESERVED_8[12];
12392   __I  uint32_t PACKET4;                           /**< DCP work packet 4 status register, offset: 0xC0 */
12393        uint8_t RESERVED_9[12];
12394   __I  uint32_t PACKET5;                           /**< DCP work packet 5 status register, offset: 0xD0 */
12395        uint8_t RESERVED_10[12];
12396   __I  uint32_t PACKET6;                           /**< DCP work packet 6 status register, offset: 0xE0 */
12397        uint8_t RESERVED_11[28];
12398   __IO uint32_t CH0CMDPTR;                         /**< DCP channel 0 command pointer address register, offset: 0x100 */
12399        uint8_t RESERVED_12[12];
12400   __IO uint32_t CH0SEMA;                           /**< DCP channel 0 semaphore register, offset: 0x110 */
12401        uint8_t RESERVED_13[12];
12402   __IO uint32_t CH0STAT;                           /**< DCP channel 0 status register, offset: 0x120 */
12403   __IO uint32_t CH0STAT_SET;                       /**< DCP channel 0 status register, offset: 0x124 */
12404   __IO uint32_t CH0STAT_CLR;                       /**< DCP channel 0 status register, offset: 0x128 */
12405   __IO uint32_t CH0STAT_TOG;                       /**< DCP channel 0 status register, offset: 0x12C */
12406   __IO uint32_t CH0OPTS;                           /**< DCP channel 0 options register, offset: 0x130 */
12407   __IO uint32_t CH0OPTS_SET;                       /**< DCP channel 0 options register, offset: 0x134 */
12408   __IO uint32_t CH0OPTS_CLR;                       /**< DCP channel 0 options register, offset: 0x138 */
12409   __IO uint32_t CH0OPTS_TOG;                       /**< DCP channel 0 options register, offset: 0x13C */
12410   __IO uint32_t CH1CMDPTR;                         /**< DCP channel 1 command pointer address register, offset: 0x140 */
12411        uint8_t RESERVED_14[12];
12412   __IO uint32_t CH1SEMA;                           /**< DCP channel 1 semaphore register, offset: 0x150 */
12413        uint8_t RESERVED_15[12];
12414   __IO uint32_t CH1STAT;                           /**< DCP channel 1 status register, offset: 0x160 */
12415   __IO uint32_t CH1STAT_SET;                       /**< DCP channel 1 status register, offset: 0x164 */
12416   __IO uint32_t CH1STAT_CLR;                       /**< DCP channel 1 status register, offset: 0x168 */
12417   __IO uint32_t CH1STAT_TOG;                       /**< DCP channel 1 status register, offset: 0x16C */
12418   __IO uint32_t CH1OPTS;                           /**< DCP channel 1 options register, offset: 0x170 */
12419   __IO uint32_t CH1OPTS_SET;                       /**< DCP channel 1 options register, offset: 0x174 */
12420   __IO uint32_t CH1OPTS_CLR;                       /**< DCP channel 1 options register, offset: 0x178 */
12421   __IO uint32_t CH1OPTS_TOG;                       /**< DCP channel 1 options register, offset: 0x17C */
12422   __IO uint32_t CH2CMDPTR;                         /**< DCP channel 2 command pointer address register, offset: 0x180 */
12423        uint8_t RESERVED_16[12];
12424   __IO uint32_t CH2SEMA;                           /**< DCP channel 2 semaphore register, offset: 0x190 */
12425        uint8_t RESERVED_17[12];
12426   __IO uint32_t CH2STAT;                           /**< DCP channel 2 status register, offset: 0x1A0 */
12427   __IO uint32_t CH2STAT_SET;                       /**< DCP channel 2 status register, offset: 0x1A4 */
12428   __IO uint32_t CH2STAT_CLR;                       /**< DCP channel 2 status register, offset: 0x1A8 */
12429   __IO uint32_t CH2STAT_TOG;                       /**< DCP channel 2 status register, offset: 0x1AC */
12430   __IO uint32_t CH2OPTS;                           /**< DCP channel 2 options register, offset: 0x1B0 */
12431   __IO uint32_t CH2OPTS_SET;                       /**< DCP channel 2 options register, offset: 0x1B4 */
12432   __IO uint32_t CH2OPTS_CLR;                       /**< DCP channel 2 options register, offset: 0x1B8 */
12433   __IO uint32_t CH2OPTS_TOG;                       /**< DCP channel 2 options register, offset: 0x1BC */
12434   __IO uint32_t CH3CMDPTR;                         /**< DCP channel 3 command pointer address register, offset: 0x1C0 */
12435        uint8_t RESERVED_18[12];
12436   __IO uint32_t CH3SEMA;                           /**< DCP channel 3 semaphore register, offset: 0x1D0 */
12437        uint8_t RESERVED_19[12];
12438   __IO uint32_t CH3STAT;                           /**< DCP channel 3 status register, offset: 0x1E0 */
12439   __IO uint32_t CH3STAT_SET;                       /**< DCP channel 3 status register, offset: 0x1E4 */
12440   __IO uint32_t CH3STAT_CLR;                       /**< DCP channel 3 status register, offset: 0x1E8 */
12441   __IO uint32_t CH3STAT_TOG;                       /**< DCP channel 3 status register, offset: 0x1EC */
12442   __IO uint32_t CH3OPTS;                           /**< DCP channel 3 options register, offset: 0x1F0 */
12443   __IO uint32_t CH3OPTS_SET;                       /**< DCP channel 3 options register, offset: 0x1F4 */
12444   __IO uint32_t CH3OPTS_CLR;                       /**< DCP channel 3 options register, offset: 0x1F8 */
12445   __IO uint32_t CH3OPTS_TOG;                       /**< DCP channel 3 options register, offset: 0x1FC */
12446        uint8_t RESERVED_20[512];
12447   __IO uint32_t DBGSELECT;                         /**< DCP debug select register, offset: 0x400 */
12448        uint8_t RESERVED_21[12];
12449   __I  uint32_t DBGDATA;                           /**< DCP debug data register, offset: 0x410 */
12450        uint8_t RESERVED_22[12];
12451   __IO uint32_t PAGETABLE;                         /**< DCP page table register, offset: 0x420 */
12452        uint8_t RESERVED_23[12];
12453   __I  uint32_t VERSION;                           /**< DCP version register, offset: 0x430 */
12454 } DCP_Type;
12455 
12456 /* ----------------------------------------------------------------------------
12457    -- DCP Register Masks
12458    ---------------------------------------------------------------------------- */
12459 
12460 /*!
12461  * @addtogroup DCP_Register_Masks DCP Register Masks
12462  * @{
12463  */
12464 
12465 /*! @name CTRL - DCP control register 0 */
12466 /*! @{ */
12467 
12468 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK   (0xFFU)
12469 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT  (0U)
12470 /*! CHANNEL_INTERRUPT_ENABLE
12471  *  0b00000001..CH0
12472  *  0b00000010..CH1
12473  *  0b00000100..CH2
12474  *  0b00001000..CH3
12475  */
12476 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
12477 
12478 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK  (0x100U)
12479 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12480 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12481 
12482 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK   (0x200000U)
12483 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT  (21U)
12484 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x)     (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
12485 
12486 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK     (0x400000U)
12487 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT    (22U)
12488 #define DCP_CTRL_ENABLE_CONTEXT_CACHING(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
12489 
12490 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK     (0x800000U)
12491 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT    (23U)
12492 #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
12493 
12494 #define DCP_CTRL_PRESENT_SHA_MASK                (0x10000000U)
12495 #define DCP_CTRL_PRESENT_SHA_SHIFT               (28U)
12496 /*! PRESENT_SHA
12497  *  0b1..Present
12498  *  0b0..Absent
12499  */
12500 #define DCP_CTRL_PRESENT_SHA(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
12501 
12502 #define DCP_CTRL_PRESENT_CRYPTO_MASK             (0x20000000U)
12503 #define DCP_CTRL_PRESENT_CRYPTO_SHIFT            (29U)
12504 /*! PRESENT_CRYPTO
12505  *  0b1..Present
12506  *  0b0..Absent
12507  */
12508 #define DCP_CTRL_PRESENT_CRYPTO(x)               (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
12509 
12510 #define DCP_CTRL_CLKGATE_MASK                    (0x40000000U)
12511 #define DCP_CTRL_CLKGATE_SHIFT                   (30U)
12512 #define DCP_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
12513 
12514 #define DCP_CTRL_SFTRST_MASK                     (0x80000000U)
12515 #define DCP_CTRL_SFTRST_SHIFT                    (31U)
12516 #define DCP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
12517 /*! @} */
12518 
12519 /*! @name CTRL_SET - DCP control register 0 */
12520 /*! @{ */
12521 
12522 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12523 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12524 /*! CHANNEL_INTERRUPT_ENABLE
12525  *  0b00000001..CH0
12526  *  0b00000010..CH1
12527  *  0b00000100..CH2
12528  *  0b00001000..CH3
12529  */
12530 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
12531 
12532 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12533 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12534 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12535 
12536 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12537 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12538 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
12539 
12540 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12541 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12542 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
12543 
12544 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12545 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12546 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
12547 
12548 #define DCP_CTRL_SET_PRESENT_SHA_MASK            (0x10000000U)
12549 #define DCP_CTRL_SET_PRESENT_SHA_SHIFT           (28U)
12550 /*! PRESENT_SHA
12551  *  0b1..Present
12552  *  0b0..Absent
12553  */
12554 #define DCP_CTRL_SET_PRESENT_SHA(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
12555 
12556 #define DCP_CTRL_SET_PRESENT_CRYPTO_MASK         (0x20000000U)
12557 #define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT        (29U)
12558 /*! PRESENT_CRYPTO
12559  *  0b1..Present
12560  *  0b0..Absent
12561  */
12562 #define DCP_CTRL_SET_PRESENT_CRYPTO(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
12563 
12564 #define DCP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
12565 #define DCP_CTRL_SET_CLKGATE_SHIFT               (30U)
12566 #define DCP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
12567 
12568 #define DCP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
12569 #define DCP_CTRL_SET_SFTRST_SHIFT                (31U)
12570 #define DCP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
12571 /*! @} */
12572 
12573 /*! @name CTRL_CLR - DCP control register 0 */
12574 /*! @{ */
12575 
12576 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12577 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12578 /*! CHANNEL_INTERRUPT_ENABLE
12579  *  0b00000001..CH0
12580  *  0b00000010..CH1
12581  *  0b00000100..CH2
12582  *  0b00001000..CH3
12583  */
12584 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
12585 
12586 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12587 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12588 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12589 
12590 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12591 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12592 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
12593 
12594 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12595 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12596 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
12597 
12598 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12599 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12600 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
12601 
12602 #define DCP_CTRL_CLR_PRESENT_SHA_MASK            (0x10000000U)
12603 #define DCP_CTRL_CLR_PRESENT_SHA_SHIFT           (28U)
12604 /*! PRESENT_SHA
12605  *  0b1..Present
12606  *  0b0..Absent
12607  */
12608 #define DCP_CTRL_CLR_PRESENT_SHA(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
12609 
12610 #define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK         (0x20000000U)
12611 #define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT        (29U)
12612 /*! PRESENT_CRYPTO
12613  *  0b1..Present
12614  *  0b0..Absent
12615  */
12616 #define DCP_CTRL_CLR_PRESENT_CRYPTO(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
12617 
12618 #define DCP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
12619 #define DCP_CTRL_CLR_CLKGATE_SHIFT               (30U)
12620 #define DCP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
12621 
12622 #define DCP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
12623 #define DCP_CTRL_CLR_SFTRST_SHIFT                (31U)
12624 #define DCP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
12625 /*! @} */
12626 
12627 /*! @name CTRL_TOG - DCP control register 0 */
12628 /*! @{ */
12629 
12630 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12631 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12632 /*! CHANNEL_INTERRUPT_ENABLE
12633  *  0b00000001..CH0
12634  *  0b00000010..CH1
12635  *  0b00000100..CH2
12636  *  0b00001000..CH3
12637  */
12638 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
12639 
12640 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12641 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12642 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12643 
12644 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12645 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12646 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
12647 
12648 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12649 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12650 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
12651 
12652 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12653 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12654 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
12655 
12656 #define DCP_CTRL_TOG_PRESENT_SHA_MASK            (0x10000000U)
12657 #define DCP_CTRL_TOG_PRESENT_SHA_SHIFT           (28U)
12658 /*! PRESENT_SHA
12659  *  0b1..Present
12660  *  0b0..Absent
12661  */
12662 #define DCP_CTRL_TOG_PRESENT_SHA(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
12663 
12664 #define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK         (0x20000000U)
12665 #define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT        (29U)
12666 /*! PRESENT_CRYPTO
12667  *  0b1..Present
12668  *  0b0..Absent
12669  */
12670 #define DCP_CTRL_TOG_PRESENT_CRYPTO(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
12671 
12672 #define DCP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
12673 #define DCP_CTRL_TOG_CLKGATE_SHIFT               (30U)
12674 #define DCP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
12675 
12676 #define DCP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
12677 #define DCP_CTRL_TOG_SFTRST_SHIFT                (31U)
12678 #define DCP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
12679 /*! @} */
12680 
12681 /*! @name STAT - DCP status register */
12682 /*! @{ */
12683 
12684 #define DCP_STAT_IRQ_MASK                        (0xFU)
12685 #define DCP_STAT_IRQ_SHIFT                       (0U)
12686 #define DCP_STAT_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
12687 
12688 #define DCP_STAT_RSVD_IRQ_MASK                   (0x100U)
12689 #define DCP_STAT_RSVD_IRQ_SHIFT                  (8U)
12690 #define DCP_STAT_RSVD_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
12691 
12692 #define DCP_STAT_READY_CHANNELS_MASK             (0xFF0000U)
12693 #define DCP_STAT_READY_CHANNELS_SHIFT            (16U)
12694 /*! READY_CHANNELS
12695  *  0b00000001..CH0
12696  *  0b00000010..CH1
12697  *  0b00000100..CH2
12698  *  0b00001000..CH3
12699  */
12700 #define DCP_STAT_READY_CHANNELS(x)               (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
12701 
12702 #define DCP_STAT_CUR_CHANNEL_MASK                (0xF000000U)
12703 #define DCP_STAT_CUR_CHANNEL_SHIFT               (24U)
12704 /*! CUR_CHANNEL
12705  *  0b0000..None
12706  *  0b0001..CH0
12707  *  0b0010..CH1
12708  *  0b0011..CH2
12709  *  0b0100..CH3
12710  */
12711 #define DCP_STAT_CUR_CHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
12712 
12713 #define DCP_STAT_OTP_KEY_READY_MASK              (0x10000000U)
12714 #define DCP_STAT_OTP_KEY_READY_SHIFT             (28U)
12715 #define DCP_STAT_OTP_KEY_READY(x)                (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
12716 /*! @} */
12717 
12718 /*! @name STAT_SET - DCP status register */
12719 /*! @{ */
12720 
12721 #define DCP_STAT_SET_IRQ_MASK                    (0xFU)
12722 #define DCP_STAT_SET_IRQ_SHIFT                   (0U)
12723 #define DCP_STAT_SET_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
12724 
12725 #define DCP_STAT_SET_RSVD_IRQ_MASK               (0x100U)
12726 #define DCP_STAT_SET_RSVD_IRQ_SHIFT              (8U)
12727 #define DCP_STAT_SET_RSVD_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
12728 
12729 #define DCP_STAT_SET_READY_CHANNELS_MASK         (0xFF0000U)
12730 #define DCP_STAT_SET_READY_CHANNELS_SHIFT        (16U)
12731 /*! READY_CHANNELS
12732  *  0b00000001..CH0
12733  *  0b00000010..CH1
12734  *  0b00000100..CH2
12735  *  0b00001000..CH3
12736  */
12737 #define DCP_STAT_SET_READY_CHANNELS(x)           (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
12738 
12739 #define DCP_STAT_SET_CUR_CHANNEL_MASK            (0xF000000U)
12740 #define DCP_STAT_SET_CUR_CHANNEL_SHIFT           (24U)
12741 /*! CUR_CHANNEL
12742  *  0b0000..None
12743  *  0b0001..CH0
12744  *  0b0010..CH1
12745  *  0b0011..CH2
12746  *  0b0100..CH3
12747  */
12748 #define DCP_STAT_SET_CUR_CHANNEL(x)              (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
12749 
12750 #define DCP_STAT_SET_OTP_KEY_READY_MASK          (0x10000000U)
12751 #define DCP_STAT_SET_OTP_KEY_READY_SHIFT         (28U)
12752 #define DCP_STAT_SET_OTP_KEY_READY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
12753 /*! @} */
12754 
12755 /*! @name STAT_CLR - DCP status register */
12756 /*! @{ */
12757 
12758 #define DCP_STAT_CLR_IRQ_MASK                    (0xFU)
12759 #define DCP_STAT_CLR_IRQ_SHIFT                   (0U)
12760 #define DCP_STAT_CLR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
12761 
12762 #define DCP_STAT_CLR_RSVD_IRQ_MASK               (0x100U)
12763 #define DCP_STAT_CLR_RSVD_IRQ_SHIFT              (8U)
12764 #define DCP_STAT_CLR_RSVD_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
12765 
12766 #define DCP_STAT_CLR_READY_CHANNELS_MASK         (0xFF0000U)
12767 #define DCP_STAT_CLR_READY_CHANNELS_SHIFT        (16U)
12768 /*! READY_CHANNELS
12769  *  0b00000001..CH0
12770  *  0b00000010..CH1
12771  *  0b00000100..CH2
12772  *  0b00001000..CH3
12773  */
12774 #define DCP_STAT_CLR_READY_CHANNELS(x)           (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
12775 
12776 #define DCP_STAT_CLR_CUR_CHANNEL_MASK            (0xF000000U)
12777 #define DCP_STAT_CLR_CUR_CHANNEL_SHIFT           (24U)
12778 /*! CUR_CHANNEL
12779  *  0b0000..None
12780  *  0b0001..CH0
12781  *  0b0010..CH1
12782  *  0b0011..CH2
12783  *  0b0100..CH3
12784  */
12785 #define DCP_STAT_CLR_CUR_CHANNEL(x)              (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
12786 
12787 #define DCP_STAT_CLR_OTP_KEY_READY_MASK          (0x10000000U)
12788 #define DCP_STAT_CLR_OTP_KEY_READY_SHIFT         (28U)
12789 #define DCP_STAT_CLR_OTP_KEY_READY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
12790 /*! @} */
12791 
12792 /*! @name STAT_TOG - DCP status register */
12793 /*! @{ */
12794 
12795 #define DCP_STAT_TOG_IRQ_MASK                    (0xFU)
12796 #define DCP_STAT_TOG_IRQ_SHIFT                   (0U)
12797 #define DCP_STAT_TOG_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
12798 
12799 #define DCP_STAT_TOG_RSVD_IRQ_MASK               (0x100U)
12800 #define DCP_STAT_TOG_RSVD_IRQ_SHIFT              (8U)
12801 #define DCP_STAT_TOG_RSVD_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
12802 
12803 #define DCP_STAT_TOG_READY_CHANNELS_MASK         (0xFF0000U)
12804 #define DCP_STAT_TOG_READY_CHANNELS_SHIFT        (16U)
12805 /*! READY_CHANNELS
12806  *  0b00000001..CH0
12807  *  0b00000010..CH1
12808  *  0b00000100..CH2
12809  *  0b00001000..CH3
12810  */
12811 #define DCP_STAT_TOG_READY_CHANNELS(x)           (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
12812 
12813 #define DCP_STAT_TOG_CUR_CHANNEL_MASK            (0xF000000U)
12814 #define DCP_STAT_TOG_CUR_CHANNEL_SHIFT           (24U)
12815 /*! CUR_CHANNEL
12816  *  0b0000..None
12817  *  0b0001..CH0
12818  *  0b0010..CH1
12819  *  0b0011..CH2
12820  *  0b0100..CH3
12821  */
12822 #define DCP_STAT_TOG_CUR_CHANNEL(x)              (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
12823 
12824 #define DCP_STAT_TOG_OTP_KEY_READY_MASK          (0x10000000U)
12825 #define DCP_STAT_TOG_OTP_KEY_READY_SHIFT         (28U)
12826 #define DCP_STAT_TOG_OTP_KEY_READY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
12827 /*! @} */
12828 
12829 /*! @name CHANNELCTRL - DCP channel control register */
12830 /*! @{ */
12831 
12832 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK      (0xFFU)
12833 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT     (0U)
12834 /*! ENABLE_CHANNEL
12835  *  0b00000001..CH0
12836  *  0b00000010..CH1
12837  *  0b00000100..CH2
12838  *  0b00001000..CH3
12839  */
12840 #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
12841 
12842 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12843 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12844 /*! HIGH_PRIORITY_CHANNEL
12845  *  0b00000001..CH0
12846  *  0b00000010..CH1
12847  *  0b00000100..CH2
12848  *  0b00001000..CH3
12849  */
12850 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
12851 
12852 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK      (0x10000U)
12853 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT     (16U)
12854 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
12855 
12856 #define DCP_CHANNELCTRL_RSVD_MASK                (0xFFFE0000U)
12857 #define DCP_CHANNELCTRL_RSVD_SHIFT               (17U)
12858 #define DCP_CHANNELCTRL_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
12859 /*! @} */
12860 
12861 /*! @name CHANNELCTRL_SET - DCP channel control register */
12862 /*! @{ */
12863 
12864 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK  (0xFFU)
12865 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
12866 /*! ENABLE_CHANNEL
12867  *  0b00000001..CH0
12868  *  0b00000010..CH1
12869  *  0b00000100..CH2
12870  *  0b00001000..CH3
12871  */
12872 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
12873 
12874 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12875 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12876 /*! HIGH_PRIORITY_CHANNEL
12877  *  0b00000001..CH0
12878  *  0b00000010..CH1
12879  *  0b00000100..CH2
12880  *  0b00001000..CH3
12881  */
12882 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
12883 
12884 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK  (0x10000U)
12885 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
12886 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
12887 
12888 #define DCP_CHANNELCTRL_SET_RSVD_MASK            (0xFFFE0000U)
12889 #define DCP_CHANNELCTRL_SET_RSVD_SHIFT           (17U)
12890 #define DCP_CHANNELCTRL_SET_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
12891 /*! @} */
12892 
12893 /*! @name CHANNELCTRL_CLR - DCP channel control register */
12894 /*! @{ */
12895 
12896 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK  (0xFFU)
12897 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
12898 /*! ENABLE_CHANNEL
12899  *  0b00000001..CH0
12900  *  0b00000010..CH1
12901  *  0b00000100..CH2
12902  *  0b00001000..CH3
12903  */
12904 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
12905 
12906 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12907 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12908 /*! HIGH_PRIORITY_CHANNEL
12909  *  0b00000001..CH0
12910  *  0b00000010..CH1
12911  *  0b00000100..CH2
12912  *  0b00001000..CH3
12913  */
12914 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
12915 
12916 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK  (0x10000U)
12917 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
12918 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
12919 
12920 #define DCP_CHANNELCTRL_CLR_RSVD_MASK            (0xFFFE0000U)
12921 #define DCP_CHANNELCTRL_CLR_RSVD_SHIFT           (17U)
12922 #define DCP_CHANNELCTRL_CLR_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
12923 /*! @} */
12924 
12925 /*! @name CHANNELCTRL_TOG - DCP channel control register */
12926 /*! @{ */
12927 
12928 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK  (0xFFU)
12929 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
12930 /*! ENABLE_CHANNEL
12931  *  0b00000001..CH0
12932  *  0b00000010..CH1
12933  *  0b00000100..CH2
12934  *  0b00001000..CH3
12935  */
12936 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
12937 
12938 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12939 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12940 /*! HIGH_PRIORITY_CHANNEL
12941  *  0b00000001..CH0
12942  *  0b00000010..CH1
12943  *  0b00000100..CH2
12944  *  0b00001000..CH3
12945  */
12946 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
12947 
12948 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK  (0x10000U)
12949 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
12950 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
12951 
12952 #define DCP_CHANNELCTRL_TOG_RSVD_MASK            (0xFFFE0000U)
12953 #define DCP_CHANNELCTRL_TOG_RSVD_SHIFT           (17U)
12954 #define DCP_CHANNELCTRL_TOG_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
12955 /*! @} */
12956 
12957 /*! @name CAPABILITY0 - DCP capability 0 register */
12958 /*! @{ */
12959 
12960 #define DCP_CAPABILITY0_NUM_KEYS_MASK            (0xFFU)
12961 #define DCP_CAPABILITY0_NUM_KEYS_SHIFT           (0U)
12962 #define DCP_CAPABILITY0_NUM_KEYS(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
12963 
12964 #define DCP_CAPABILITY0_NUM_CHANNELS_MASK        (0xF00U)
12965 #define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT       (8U)
12966 #define DCP_CAPABILITY0_NUM_CHANNELS(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
12967 
12968 #define DCP_CAPABILITY0_RSVD_MASK                (0x1FFFF000U)
12969 #define DCP_CAPABILITY0_RSVD_SHIFT               (12U)
12970 #define DCP_CAPABILITY0_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
12971 
12972 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK  (0x20000000U)
12973 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
12974 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
12975 
12976 #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK     (0x80000000U)
12977 #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT    (31U)
12978 #define DCP_CAPABILITY0_DISABLE_DECRYPT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
12979 /*! @} */
12980 
12981 /*! @name CAPABILITY1 - DCP capability 1 register */
12982 /*! @{ */
12983 
12984 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK   (0xFFFFU)
12985 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT  (0U)
12986 /*! CIPHER_ALGORITHMS
12987  *  0b0000000000000001..AES128
12988  */
12989 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x)     (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
12990 
12991 #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK     (0xFFFF0000U)
12992 #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT    (16U)
12993 /*! HASH_ALGORITHMS
12994  *  0b0000000000000001..SHA1
12995  *  0b0000000000000010..CRC32
12996  *  0b0000000000000100..SHA256
12997  */
12998 #define DCP_CAPABILITY1_HASH_ALGORITHMS(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
12999 /*! @} */
13000 
13001 /*! @name CONTEXT - DCP context buffer pointer */
13002 /*! @{ */
13003 
13004 #define DCP_CONTEXT_ADDR_MASK                    (0xFFFFFFFFU)
13005 #define DCP_CONTEXT_ADDR_SHIFT                   (0U)
13006 #define DCP_CONTEXT_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
13007 /*! @} */
13008 
13009 /*! @name KEY - DCP key index */
13010 /*! @{ */
13011 
13012 #define DCP_KEY_SUBWORD_MASK                     (0x3U)
13013 #define DCP_KEY_SUBWORD_SHIFT                    (0U)
13014 #define DCP_KEY_SUBWORD(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
13015 
13016 #define DCP_KEY_RSVD_SUBWORD_MASK                (0xCU)
13017 #define DCP_KEY_RSVD_SUBWORD_SHIFT               (2U)
13018 #define DCP_KEY_RSVD_SUBWORD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
13019 
13020 #define DCP_KEY_INDEX_MASK                       (0x30U)
13021 #define DCP_KEY_INDEX_SHIFT                      (4U)
13022 #define DCP_KEY_INDEX(x)                         (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
13023 
13024 #define DCP_KEY_RSVD_INDEX_MASK                  (0xC0U)
13025 #define DCP_KEY_RSVD_INDEX_SHIFT                 (6U)
13026 #define DCP_KEY_RSVD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
13027 
13028 #define DCP_KEY_RSVD_MASK                        (0xFFFFFF00U)
13029 #define DCP_KEY_RSVD_SHIFT                       (8U)
13030 #define DCP_KEY_RSVD(x)                          (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
13031 /*! @} */
13032 
13033 /*! @name KEYDATA - DCP key data */
13034 /*! @{ */
13035 
13036 #define DCP_KEYDATA_DATA_MASK                    (0xFFFFFFFFU)
13037 #define DCP_KEYDATA_DATA_SHIFT                   (0U)
13038 #define DCP_KEYDATA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
13039 /*! @} */
13040 
13041 /*! @name PACKET0 - DCP work packet 0 status register */
13042 /*! @{ */
13043 
13044 #define DCP_PACKET0_ADDR_MASK                    (0xFFFFFFFFU)
13045 #define DCP_PACKET0_ADDR_SHIFT                   (0U)
13046 #define DCP_PACKET0_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
13047 /*! @} */
13048 
13049 /*! @name PACKET1 - DCP work packet 1 status register */
13050 /*! @{ */
13051 
13052 #define DCP_PACKET1_INTERRUPT_MASK               (0x1U)
13053 #define DCP_PACKET1_INTERRUPT_SHIFT              (0U)
13054 #define DCP_PACKET1_INTERRUPT(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
13055 
13056 #define DCP_PACKET1_DECR_SEMAPHORE_MASK          (0x2U)
13057 #define DCP_PACKET1_DECR_SEMAPHORE_SHIFT         (1U)
13058 #define DCP_PACKET1_DECR_SEMAPHORE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
13059 
13060 #define DCP_PACKET1_CHAIN_MASK                   (0x4U)
13061 #define DCP_PACKET1_CHAIN_SHIFT                  (2U)
13062 #define DCP_PACKET1_CHAIN(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
13063 
13064 #define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK        (0x8U)
13065 #define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT       (3U)
13066 #define DCP_PACKET1_CHAIN_CONTIGUOUS(x)          (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
13067 
13068 #define DCP_PACKET1_ENABLE_MEMCOPY_MASK          (0x10U)
13069 #define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT         (4U)
13070 #define DCP_PACKET1_ENABLE_MEMCOPY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
13071 
13072 #define DCP_PACKET1_ENABLE_CIPHER_MASK           (0x20U)
13073 #define DCP_PACKET1_ENABLE_CIPHER_SHIFT          (5U)
13074 #define DCP_PACKET1_ENABLE_CIPHER(x)             (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
13075 
13076 #define DCP_PACKET1_ENABLE_HASH_MASK             (0x40U)
13077 #define DCP_PACKET1_ENABLE_HASH_SHIFT            (6U)
13078 #define DCP_PACKET1_ENABLE_HASH(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
13079 
13080 #define DCP_PACKET1_ENABLE_BLIT_MASK             (0x80U)
13081 #define DCP_PACKET1_ENABLE_BLIT_SHIFT            (7U)
13082 #define DCP_PACKET1_ENABLE_BLIT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
13083 
13084 #define DCP_PACKET1_CIPHER_ENCRYPT_MASK          (0x100U)
13085 #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT         (8U)
13086 /*! CIPHER_ENCRYPT
13087  *  0b1..ENCRYPT
13088  *  0b0..DECRYPT
13089  */
13090 #define DCP_PACKET1_CIPHER_ENCRYPT(x)            (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
13091 
13092 #define DCP_PACKET1_CIPHER_INIT_MASK             (0x200U)
13093 #define DCP_PACKET1_CIPHER_INIT_SHIFT            (9U)
13094 #define DCP_PACKET1_CIPHER_INIT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
13095 
13096 #define DCP_PACKET1_OTP_KEY_MASK                 (0x400U)
13097 #define DCP_PACKET1_OTP_KEY_SHIFT                (10U)
13098 #define DCP_PACKET1_OTP_KEY(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
13099 
13100 #define DCP_PACKET1_PAYLOAD_KEY_MASK             (0x800U)
13101 #define DCP_PACKET1_PAYLOAD_KEY_SHIFT            (11U)
13102 #define DCP_PACKET1_PAYLOAD_KEY(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
13103 
13104 #define DCP_PACKET1_HASH_INIT_MASK               (0x1000U)
13105 #define DCP_PACKET1_HASH_INIT_SHIFT              (12U)
13106 #define DCP_PACKET1_HASH_INIT(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
13107 
13108 #define DCP_PACKET1_HASH_TERM_MASK               (0x2000U)
13109 #define DCP_PACKET1_HASH_TERM_SHIFT              (13U)
13110 #define DCP_PACKET1_HASH_TERM(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
13111 
13112 #define DCP_PACKET1_CHECK_HASH_MASK              (0x4000U)
13113 #define DCP_PACKET1_CHECK_HASH_SHIFT             (14U)
13114 #define DCP_PACKET1_CHECK_HASH(x)                (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
13115 
13116 #define DCP_PACKET1_HASH_OUTPUT_MASK             (0x8000U)
13117 #define DCP_PACKET1_HASH_OUTPUT_SHIFT            (15U)
13118 /*! HASH_OUTPUT
13119  *  0b0..INPUT
13120  *  0b1..OUTPUT
13121  */
13122 #define DCP_PACKET1_HASH_OUTPUT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
13123 
13124 #define DCP_PACKET1_CONSTANT_FILL_MASK           (0x10000U)
13125 #define DCP_PACKET1_CONSTANT_FILL_SHIFT          (16U)
13126 #define DCP_PACKET1_CONSTANT_FILL(x)             (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
13127 
13128 #define DCP_PACKET1_TEST_SEMA_IRQ_MASK           (0x20000U)
13129 #define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT          (17U)
13130 #define DCP_PACKET1_TEST_SEMA_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
13131 
13132 #define DCP_PACKET1_KEY_BYTESWAP_MASK            (0x40000U)
13133 #define DCP_PACKET1_KEY_BYTESWAP_SHIFT           (18U)
13134 #define DCP_PACKET1_KEY_BYTESWAP(x)              (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
13135 
13136 #define DCP_PACKET1_KEY_WORDSWAP_MASK            (0x80000U)
13137 #define DCP_PACKET1_KEY_WORDSWAP_SHIFT           (19U)
13138 #define DCP_PACKET1_KEY_WORDSWAP(x)              (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
13139 
13140 #define DCP_PACKET1_INPUT_BYTESWAP_MASK          (0x100000U)
13141 #define DCP_PACKET1_INPUT_BYTESWAP_SHIFT         (20U)
13142 #define DCP_PACKET1_INPUT_BYTESWAP(x)            (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
13143 
13144 #define DCP_PACKET1_INPUT_WORDSWAP_MASK          (0x200000U)
13145 #define DCP_PACKET1_INPUT_WORDSWAP_SHIFT         (21U)
13146 #define DCP_PACKET1_INPUT_WORDSWAP(x)            (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
13147 
13148 #define DCP_PACKET1_OUTPUT_BYTESWAP_MASK         (0x400000U)
13149 #define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT        (22U)
13150 #define DCP_PACKET1_OUTPUT_BYTESWAP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
13151 
13152 #define DCP_PACKET1_OUTPUT_WORDSWAP_MASK         (0x800000U)
13153 #define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT        (23U)
13154 #define DCP_PACKET1_OUTPUT_WORDSWAP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
13155 
13156 #define DCP_PACKET1_TAG_MASK                     (0xFF000000U)
13157 #define DCP_PACKET1_TAG_SHIFT                    (24U)
13158 #define DCP_PACKET1_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
13159 /*! @} */
13160 
13161 /*! @name PACKET2 - DCP work packet 2 status register */
13162 /*! @{ */
13163 
13164 #define DCP_PACKET2_CIPHER_SELECT_MASK           (0xFU)
13165 #define DCP_PACKET2_CIPHER_SELECT_SHIFT          (0U)
13166 /*! CIPHER_SELECT
13167  *  0b0000..AES128
13168  */
13169 #define DCP_PACKET2_CIPHER_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
13170 
13171 #define DCP_PACKET2_CIPHER_MODE_MASK             (0xF0U)
13172 #define DCP_PACKET2_CIPHER_MODE_SHIFT            (4U)
13173 /*! CIPHER_MODE
13174  *  0b0000..ECB
13175  *  0b0001..CBC
13176  */
13177 #define DCP_PACKET2_CIPHER_MODE(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
13178 
13179 #define DCP_PACKET2_KEY_SELECT_MASK              (0xFF00U)
13180 #define DCP_PACKET2_KEY_SELECT_SHIFT             (8U)
13181 /*! KEY_SELECT
13182  *  0b00000000..KEY0
13183  *  0b00000001..KEY1
13184  *  0b00000010..KEY2
13185  *  0b00000011..KEY3
13186  *  0b11111110..UNIQUE_KEY
13187  *  0b11111111..OTP_KEY
13188  */
13189 #define DCP_PACKET2_KEY_SELECT(x)                (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
13190 
13191 #define DCP_PACKET2_HASH_SELECT_MASK             (0xF0000U)
13192 #define DCP_PACKET2_HASH_SELECT_SHIFT            (16U)
13193 /*! HASH_SELECT
13194  *  0b0000..SHA1
13195  *  0b0001..CRC32
13196  *  0b0010..SHA256
13197  */
13198 #define DCP_PACKET2_HASH_SELECT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
13199 
13200 #define DCP_PACKET2_RSVD_MASK                    (0xF00000U)
13201 #define DCP_PACKET2_RSVD_SHIFT                   (20U)
13202 #define DCP_PACKET2_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
13203 
13204 #define DCP_PACKET2_CIPHER_CFG_MASK              (0xFF000000U)
13205 #define DCP_PACKET2_CIPHER_CFG_SHIFT             (24U)
13206 #define DCP_PACKET2_CIPHER_CFG(x)                (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
13207 /*! @} */
13208 
13209 /*! @name PACKET3 - DCP work packet 3 status register */
13210 /*! @{ */
13211 
13212 #define DCP_PACKET3_ADDR_MASK                    (0xFFFFFFFFU)
13213 #define DCP_PACKET3_ADDR_SHIFT                   (0U)
13214 #define DCP_PACKET3_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
13215 /*! @} */
13216 
13217 /*! @name PACKET4 - DCP work packet 4 status register */
13218 /*! @{ */
13219 
13220 #define DCP_PACKET4_ADDR_MASK                    (0xFFFFFFFFU)
13221 #define DCP_PACKET4_ADDR_SHIFT                   (0U)
13222 #define DCP_PACKET4_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
13223 /*! @} */
13224 
13225 /*! @name PACKET5 - DCP work packet 5 status register */
13226 /*! @{ */
13227 
13228 #define DCP_PACKET5_COUNT_MASK                   (0xFFFFFFFFU)
13229 #define DCP_PACKET5_COUNT_SHIFT                  (0U)
13230 #define DCP_PACKET5_COUNT(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
13231 /*! @} */
13232 
13233 /*! @name PACKET6 - DCP work packet 6 status register */
13234 /*! @{ */
13235 
13236 #define DCP_PACKET6_ADDR_MASK                    (0xFFFFFFFFU)
13237 #define DCP_PACKET6_ADDR_SHIFT                   (0U)
13238 #define DCP_PACKET6_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
13239 /*! @} */
13240 
13241 /*! @name CH0CMDPTR - DCP channel 0 command pointer address register */
13242 /*! @{ */
13243 
13244 #define DCP_CH0CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
13245 #define DCP_CH0CMDPTR_ADDR_SHIFT                 (0U)
13246 #define DCP_CH0CMDPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
13247 /*! @} */
13248 
13249 /*! @name CH0SEMA - DCP channel 0 semaphore register */
13250 /*! @{ */
13251 
13252 #define DCP_CH0SEMA_INCREMENT_MASK               (0xFFU)
13253 #define DCP_CH0SEMA_INCREMENT_SHIFT              (0U)
13254 #define DCP_CH0SEMA_INCREMENT(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
13255 
13256 #define DCP_CH0SEMA_VALUE_MASK                   (0xFF0000U)
13257 #define DCP_CH0SEMA_VALUE_SHIFT                  (16U)
13258 #define DCP_CH0SEMA_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
13259 /*! @} */
13260 
13261 /*! @name CH0STAT - DCP channel 0 status register */
13262 /*! @{ */
13263 
13264 #define DCP_CH0STAT_RSVD_COMPLETE_MASK           (0x1U)
13265 #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT          (0U)
13266 #define DCP_CH0STAT_RSVD_COMPLETE(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
13267 
13268 #define DCP_CH0STAT_HASH_MISMATCH_MASK           (0x2U)
13269 #define DCP_CH0STAT_HASH_MISMATCH_SHIFT          (1U)
13270 #define DCP_CH0STAT_HASH_MISMATCH(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
13271 
13272 #define DCP_CH0STAT_ERROR_SETUP_MASK             (0x4U)
13273 #define DCP_CH0STAT_ERROR_SETUP_SHIFT            (2U)
13274 #define DCP_CH0STAT_ERROR_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
13275 
13276 #define DCP_CH0STAT_ERROR_PACKET_MASK            (0x8U)
13277 #define DCP_CH0STAT_ERROR_PACKET_SHIFT           (3U)
13278 #define DCP_CH0STAT_ERROR_PACKET(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
13279 
13280 #define DCP_CH0STAT_ERROR_SRC_MASK               (0x10U)
13281 #define DCP_CH0STAT_ERROR_SRC_SHIFT              (4U)
13282 #define DCP_CH0STAT_ERROR_SRC(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
13283 
13284 #define DCP_CH0STAT_ERROR_DST_MASK               (0x20U)
13285 #define DCP_CH0STAT_ERROR_DST_SHIFT              (5U)
13286 #define DCP_CH0STAT_ERROR_DST(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
13287 
13288 #define DCP_CH0STAT_ERROR_PAGEFAULT_MASK         (0x40U)
13289 #define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT        (6U)
13290 #define DCP_CH0STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
13291 
13292 #define DCP_CH0STAT_ERROR_CODE_MASK              (0xFF0000U)
13293 #define DCP_CH0STAT_ERROR_CODE_SHIFT             (16U)
13294 /*! ERROR_CODE
13295  *  0b00000001..Error signalled because the next pointer is 0x00000000
13296  *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
13297  *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
13298  *  0b00000100..Error signalled because an error is reported reading/writing the payload
13299  *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
13300  */
13301 #define DCP_CH0STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
13302 
13303 #define DCP_CH0STAT_TAG_MASK                     (0xFF000000U)
13304 #define DCP_CH0STAT_TAG_SHIFT                    (24U)
13305 #define DCP_CH0STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
13306 /*! @} */
13307 
13308 /*! @name CH0STAT_SET - DCP channel 0 status register */
13309 /*! @{ */
13310 
13311 #define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
13312 #define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
13313 #define DCP_CH0STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
13314 
13315 #define DCP_CH0STAT_SET_HASH_MISMATCH_MASK       (0x2U)
13316 #define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT      (1U)
13317 #define DCP_CH0STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
13318 
13319 #define DCP_CH0STAT_SET_ERROR_SETUP_MASK         (0x4U)
13320 #define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT        (2U)
13321 #define DCP_CH0STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
13322 
13323 #define DCP_CH0STAT_SET_ERROR_PACKET_MASK        (0x8U)
13324 #define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT       (3U)
13325 #define DCP_CH0STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
13326 
13327 #define DCP_CH0STAT_SET_ERROR_SRC_MASK           (0x10U)
13328 #define DCP_CH0STAT_SET_ERROR_SRC_SHIFT          (4U)
13329 #define DCP_CH0STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
13330 
13331 #define DCP_CH0STAT_SET_ERROR_DST_MASK           (0x20U)
13332 #define DCP_CH0STAT_SET_ERROR_DST_SHIFT          (5U)
13333 #define DCP_CH0STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
13334 
13335 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
13336 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
13337 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
13338 
13339 #define DCP_CH0STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
13340 #define DCP_CH0STAT_SET_ERROR_CODE_SHIFT         (16U)
13341 /*! ERROR_CODE
13342  *  0b00000001..Error signalled because the next pointer is 0x00000000
13343  *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
13344  *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
13345  *  0b00000100..Error signalled because an error is reported reading/writing the payload
13346  *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
13347  */
13348 #define DCP_CH0STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
13349 
13350 #define DCP_CH0STAT_SET_TAG_MASK                 (0xFF000000U)
13351 #define DCP_CH0STAT_SET_TAG_SHIFT                (24U)
13352 #define DCP_CH0STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
13353 /*! @} */
13354 
13355 /*! @name CH0STAT_CLR - DCP channel 0 status register */
13356 /*! @{ */
13357 
13358 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
13359 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
13360 #define DCP_CH0STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
13361 
13362 #define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
13363 #define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
13364 #define DCP_CH0STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
13365 
13366 #define DCP_CH0STAT_CLR_ERROR_SETUP_MASK         (0x4U)
13367 #define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT        (2U)
13368 #define DCP_CH0STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
13369 
13370 #define DCP_CH0STAT_CLR_ERROR_PACKET_MASK        (0x8U)
13371 #define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT       (3U)
13372 #define DCP_CH0STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
13373 
13374 #define DCP_CH0STAT_CLR_ERROR_SRC_MASK           (0x10U)
13375 #define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT          (4U)
13376 #define DCP_CH0STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
13377 
13378 #define DCP_CH0STAT_CLR_ERROR_DST_MASK           (0x20U)
13379 #define DCP_CH0STAT_CLR_ERROR_DST_SHIFT          (5U)
13380 #define DCP_CH0STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
13381 
13382 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
13383 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
13384 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
13385 
13386 #define DCP_CH0STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
13387 #define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT         (16U)
13388 /*! ERROR_CODE
13389  *  0b00000001..Error signalled because the next pointer is 0x00000000
13390  *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
13391  *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
13392  *  0b00000100..Error signalled because an error is reported reading/writing the payload
13393  *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
13394  */
13395 #define DCP_CH0STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
13396 
13397 #define DCP_CH0STAT_CLR_TAG_MASK                 (0xFF000000U)
13398 #define DCP_CH0STAT_CLR_TAG_SHIFT                (24U)
13399 #define DCP_CH0STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
13400 /*! @} */
13401 
13402 /*! @name CH0STAT_TOG - DCP channel 0 status register */
13403 /*! @{ */
13404 
13405 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
13406 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
13407 #define DCP_CH0STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
13408 
13409 #define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
13410 #define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
13411 #define DCP_CH0STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
13412 
13413 #define DCP_CH0STAT_TOG_ERROR_SETUP_MASK         (0x4U)
13414 #define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT        (2U)
13415 #define DCP_CH0STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
13416 
13417 #define DCP_CH0STAT_TOG_ERROR_PACKET_MASK        (0x8U)
13418 #define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT       (3U)
13419 #define DCP_CH0STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
13420 
13421 #define DCP_CH0STAT_TOG_ERROR_SRC_MASK           (0x10U)
13422 #define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT          (4U)
13423 #define DCP_CH0STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
13424 
13425 #define DCP_CH0STAT_TOG_ERROR_DST_MASK           (0x20U)
13426 #define DCP_CH0STAT_TOG_ERROR_DST_SHIFT          (5U)
13427 #define DCP_CH0STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
13428 
13429 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
13430 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
13431 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
13432 
13433 #define DCP_CH0STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
13434 #define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT         (16U)
13435 /*! ERROR_CODE
13436  *  0b00000001..Error signalled because the next pointer is 0x00000000
13437  *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
13438  *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
13439  *  0b00000100..Error signalled because an error is reported reading/writing the payload
13440  *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
13441  */
13442 #define DCP_CH0STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
13443 
13444 #define DCP_CH0STAT_TOG_TAG_MASK                 (0xFF000000U)
13445 #define DCP_CH0STAT_TOG_TAG_SHIFT                (24U)
13446 #define DCP_CH0STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
13447 /*! @} */
13448 
13449 /*! @name CH0OPTS - DCP channel 0 options register */
13450 /*! @{ */
13451 
13452 #define DCP_CH0OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
13453 #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT         (0U)
13454 #define DCP_CH0OPTS_RECOVERY_TIMER(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
13455 
13456 #define DCP_CH0OPTS_RSVD_MASK                    (0xFFFF0000U)
13457 #define DCP_CH0OPTS_RSVD_SHIFT                   (16U)
13458 #define DCP_CH0OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
13459 /*! @} */
13460 
13461 /*! @name CH0OPTS_SET - DCP channel 0 options register */
13462 /*! @{ */
13463 
13464 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
13465 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
13466 #define DCP_CH0OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
13467 
13468 #define DCP_CH0OPTS_SET_RSVD_MASK                (0xFFFF0000U)
13469 #define DCP_CH0OPTS_SET_RSVD_SHIFT               (16U)
13470 #define DCP_CH0OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
13471 /*! @} */
13472 
13473 /*! @name CH0OPTS_CLR - DCP channel 0 options register */
13474 /*! @{ */
13475 
13476 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
13477 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
13478 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
13479 
13480 #define DCP_CH0OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
13481 #define DCP_CH0OPTS_CLR_RSVD_SHIFT               (16U)
13482 #define DCP_CH0OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
13483 /*! @} */
13484 
13485 /*! @name CH0OPTS_TOG - DCP channel 0 options register */
13486 /*! @{ */
13487 
13488 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
13489 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
13490 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
13491 
13492 #define DCP_CH0OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
13493 #define DCP_CH0OPTS_TOG_RSVD_SHIFT               (16U)
13494 #define DCP_CH0OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
13495 /*! @} */
13496 
13497 /*! @name CH1CMDPTR - DCP channel 1 command pointer address register */
13498 /*! @{ */
13499 
13500 #define DCP_CH1CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
13501 #define DCP_CH1CMDPTR_ADDR_SHIFT                 (0U)
13502 #define DCP_CH1CMDPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
13503 /*! @} */
13504 
13505 /*! @name CH1SEMA - DCP channel 1 semaphore register */
13506 /*! @{ */
13507 
13508 #define DCP_CH1SEMA_INCREMENT_MASK               (0xFFU)
13509 #define DCP_CH1SEMA_INCREMENT_SHIFT              (0U)
13510 #define DCP_CH1SEMA_INCREMENT(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
13511 
13512 #define DCP_CH1SEMA_VALUE_MASK                   (0xFF0000U)
13513 #define DCP_CH1SEMA_VALUE_SHIFT                  (16U)
13514 #define DCP_CH1SEMA_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
13515 /*! @} */
13516 
13517 /*! @name CH1STAT - DCP channel 1 status register */
13518 /*! @{ */
13519 
13520 #define DCP_CH1STAT_RSVD_COMPLETE_MASK           (0x1U)
13521 #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT          (0U)
13522 #define DCP_CH1STAT_RSVD_COMPLETE(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
13523 
13524 #define DCP_CH1STAT_HASH_MISMATCH_MASK           (0x2U)
13525 #define DCP_CH1STAT_HASH_MISMATCH_SHIFT          (1U)
13526 #define DCP_CH1STAT_HASH_MISMATCH(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
13527 
13528 #define DCP_CH1STAT_ERROR_SETUP_MASK             (0x4U)
13529 #define DCP_CH1STAT_ERROR_SETUP_SHIFT            (2U)
13530 #define DCP_CH1STAT_ERROR_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
13531 
13532 #define DCP_CH1STAT_ERROR_PACKET_MASK            (0x8U)
13533 #define DCP_CH1STAT_ERROR_PACKET_SHIFT           (3U)
13534 #define DCP_CH1STAT_ERROR_PACKET(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
13535 
13536 #define DCP_CH1STAT_ERROR_SRC_MASK               (0x10U)
13537 #define DCP_CH1STAT_ERROR_SRC_SHIFT              (4U)
13538 #define DCP_CH1STAT_ERROR_SRC(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
13539 
13540 #define DCP_CH1STAT_ERROR_DST_MASK               (0x20U)
13541 #define DCP_CH1STAT_ERROR_DST_SHIFT              (5U)
13542 #define DCP_CH1STAT_ERROR_DST(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
13543 
13544 #define DCP_CH1STAT_ERROR_PAGEFAULT_MASK         (0x40U)
13545 #define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT        (6U)
13546 #define DCP_CH1STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
13547 
13548 #define DCP_CH1STAT_ERROR_CODE_MASK              (0xFF0000U)
13549 #define DCP_CH1STAT_ERROR_CODE_SHIFT             (16U)
13550 /*! ERROR_CODE
13551  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13552  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13553  *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
13554  *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
13555  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
13556  */
13557 #define DCP_CH1STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
13558 
13559 #define DCP_CH1STAT_TAG_MASK                     (0xFF000000U)
13560 #define DCP_CH1STAT_TAG_SHIFT                    (24U)
13561 #define DCP_CH1STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
13562 /*! @} */
13563 
13564 /*! @name CH1STAT_SET - DCP channel 1 status register */
13565 /*! @{ */
13566 
13567 #define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
13568 #define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
13569 #define DCP_CH1STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
13570 
13571 #define DCP_CH1STAT_SET_HASH_MISMATCH_MASK       (0x2U)
13572 #define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT      (1U)
13573 #define DCP_CH1STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
13574 
13575 #define DCP_CH1STAT_SET_ERROR_SETUP_MASK         (0x4U)
13576 #define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT        (2U)
13577 #define DCP_CH1STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
13578 
13579 #define DCP_CH1STAT_SET_ERROR_PACKET_MASK        (0x8U)
13580 #define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT       (3U)
13581 #define DCP_CH1STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
13582 
13583 #define DCP_CH1STAT_SET_ERROR_SRC_MASK           (0x10U)
13584 #define DCP_CH1STAT_SET_ERROR_SRC_SHIFT          (4U)
13585 #define DCP_CH1STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
13586 
13587 #define DCP_CH1STAT_SET_ERROR_DST_MASK           (0x20U)
13588 #define DCP_CH1STAT_SET_ERROR_DST_SHIFT          (5U)
13589 #define DCP_CH1STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
13590 
13591 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
13592 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
13593 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
13594 
13595 #define DCP_CH1STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
13596 #define DCP_CH1STAT_SET_ERROR_CODE_SHIFT         (16U)
13597 /*! ERROR_CODE
13598  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13599  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13600  *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
13601  *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
13602  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
13603  */
13604 #define DCP_CH1STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
13605 
13606 #define DCP_CH1STAT_SET_TAG_MASK                 (0xFF000000U)
13607 #define DCP_CH1STAT_SET_TAG_SHIFT                (24U)
13608 #define DCP_CH1STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
13609 /*! @} */
13610 
13611 /*! @name CH1STAT_CLR - DCP channel 1 status register */
13612 /*! @{ */
13613 
13614 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
13615 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
13616 #define DCP_CH1STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
13617 
13618 #define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
13619 #define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
13620 #define DCP_CH1STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
13621 
13622 #define DCP_CH1STAT_CLR_ERROR_SETUP_MASK         (0x4U)
13623 #define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT        (2U)
13624 #define DCP_CH1STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
13625 
13626 #define DCP_CH1STAT_CLR_ERROR_PACKET_MASK        (0x8U)
13627 #define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT       (3U)
13628 #define DCP_CH1STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
13629 
13630 #define DCP_CH1STAT_CLR_ERROR_SRC_MASK           (0x10U)
13631 #define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT          (4U)
13632 #define DCP_CH1STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
13633 
13634 #define DCP_CH1STAT_CLR_ERROR_DST_MASK           (0x20U)
13635 #define DCP_CH1STAT_CLR_ERROR_DST_SHIFT          (5U)
13636 #define DCP_CH1STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
13637 
13638 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
13639 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
13640 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
13641 
13642 #define DCP_CH1STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
13643 #define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT         (16U)
13644 /*! ERROR_CODE
13645  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13646  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13647  *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
13648  *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
13649  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
13650  */
13651 #define DCP_CH1STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
13652 
13653 #define DCP_CH1STAT_CLR_TAG_MASK                 (0xFF000000U)
13654 #define DCP_CH1STAT_CLR_TAG_SHIFT                (24U)
13655 #define DCP_CH1STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
13656 /*! @} */
13657 
13658 /*! @name CH1STAT_TOG - DCP channel 1 status register */
13659 /*! @{ */
13660 
13661 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
13662 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
13663 #define DCP_CH1STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
13664 
13665 #define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
13666 #define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
13667 #define DCP_CH1STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
13668 
13669 #define DCP_CH1STAT_TOG_ERROR_SETUP_MASK         (0x4U)
13670 #define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT        (2U)
13671 #define DCP_CH1STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
13672 
13673 #define DCP_CH1STAT_TOG_ERROR_PACKET_MASK        (0x8U)
13674 #define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT       (3U)
13675 #define DCP_CH1STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
13676 
13677 #define DCP_CH1STAT_TOG_ERROR_SRC_MASK           (0x10U)
13678 #define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT          (4U)
13679 #define DCP_CH1STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
13680 
13681 #define DCP_CH1STAT_TOG_ERROR_DST_MASK           (0x20U)
13682 #define DCP_CH1STAT_TOG_ERROR_DST_SHIFT          (5U)
13683 #define DCP_CH1STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
13684 
13685 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
13686 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
13687 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
13688 
13689 #define DCP_CH1STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
13690 #define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT         (16U)
13691 /*! ERROR_CODE
13692  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13693  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13694  *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
13695  *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
13696  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
13697  */
13698 #define DCP_CH1STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
13699 
13700 #define DCP_CH1STAT_TOG_TAG_MASK                 (0xFF000000U)
13701 #define DCP_CH1STAT_TOG_TAG_SHIFT                (24U)
13702 #define DCP_CH1STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
13703 /*! @} */
13704 
13705 /*! @name CH1OPTS - DCP channel 1 options register */
13706 /*! @{ */
13707 
13708 #define DCP_CH1OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
13709 #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT         (0U)
13710 #define DCP_CH1OPTS_RECOVERY_TIMER(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
13711 
13712 #define DCP_CH1OPTS_RSVD_MASK                    (0xFFFF0000U)
13713 #define DCP_CH1OPTS_RSVD_SHIFT                   (16U)
13714 #define DCP_CH1OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
13715 /*! @} */
13716 
13717 /*! @name CH1OPTS_SET - DCP channel 1 options register */
13718 /*! @{ */
13719 
13720 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
13721 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
13722 #define DCP_CH1OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
13723 
13724 #define DCP_CH1OPTS_SET_RSVD_MASK                (0xFFFF0000U)
13725 #define DCP_CH1OPTS_SET_RSVD_SHIFT               (16U)
13726 #define DCP_CH1OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
13727 /*! @} */
13728 
13729 /*! @name CH1OPTS_CLR - DCP channel 1 options register */
13730 /*! @{ */
13731 
13732 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
13733 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
13734 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
13735 
13736 #define DCP_CH1OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
13737 #define DCP_CH1OPTS_CLR_RSVD_SHIFT               (16U)
13738 #define DCP_CH1OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
13739 /*! @} */
13740 
13741 /*! @name CH1OPTS_TOG - DCP channel 1 options register */
13742 /*! @{ */
13743 
13744 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
13745 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
13746 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
13747 
13748 #define DCP_CH1OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
13749 #define DCP_CH1OPTS_TOG_RSVD_SHIFT               (16U)
13750 #define DCP_CH1OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
13751 /*! @} */
13752 
13753 /*! @name CH2CMDPTR - DCP channel 2 command pointer address register */
13754 /*! @{ */
13755 
13756 #define DCP_CH2CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
13757 #define DCP_CH2CMDPTR_ADDR_SHIFT                 (0U)
13758 #define DCP_CH2CMDPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
13759 /*! @} */
13760 
13761 /*! @name CH2SEMA - DCP channel 2 semaphore register */
13762 /*! @{ */
13763 
13764 #define DCP_CH2SEMA_INCREMENT_MASK               (0xFFU)
13765 #define DCP_CH2SEMA_INCREMENT_SHIFT              (0U)
13766 #define DCP_CH2SEMA_INCREMENT(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
13767 
13768 #define DCP_CH2SEMA_VALUE_MASK                   (0xFF0000U)
13769 #define DCP_CH2SEMA_VALUE_SHIFT                  (16U)
13770 #define DCP_CH2SEMA_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
13771 /*! @} */
13772 
13773 /*! @name CH2STAT - DCP channel 2 status register */
13774 /*! @{ */
13775 
13776 #define DCP_CH2STAT_RSVD_COMPLETE_MASK           (0x1U)
13777 #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT          (0U)
13778 #define DCP_CH2STAT_RSVD_COMPLETE(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
13779 
13780 #define DCP_CH2STAT_HASH_MISMATCH_MASK           (0x2U)
13781 #define DCP_CH2STAT_HASH_MISMATCH_SHIFT          (1U)
13782 #define DCP_CH2STAT_HASH_MISMATCH(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
13783 
13784 #define DCP_CH2STAT_ERROR_SETUP_MASK             (0x4U)
13785 #define DCP_CH2STAT_ERROR_SETUP_SHIFT            (2U)
13786 #define DCP_CH2STAT_ERROR_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
13787 
13788 #define DCP_CH2STAT_ERROR_PACKET_MASK            (0x8U)
13789 #define DCP_CH2STAT_ERROR_PACKET_SHIFT           (3U)
13790 #define DCP_CH2STAT_ERROR_PACKET(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
13791 
13792 #define DCP_CH2STAT_ERROR_SRC_MASK               (0x10U)
13793 #define DCP_CH2STAT_ERROR_SRC_SHIFT              (4U)
13794 #define DCP_CH2STAT_ERROR_SRC(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
13795 
13796 #define DCP_CH2STAT_ERROR_DST_MASK               (0x20U)
13797 #define DCP_CH2STAT_ERROR_DST_SHIFT              (5U)
13798 #define DCP_CH2STAT_ERROR_DST(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
13799 
13800 #define DCP_CH2STAT_ERROR_PAGEFAULT_MASK         (0x40U)
13801 #define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT        (6U)
13802 #define DCP_CH2STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
13803 
13804 #define DCP_CH2STAT_ERROR_CODE_MASK              (0xFF0000U)
13805 #define DCP_CH2STAT_ERROR_CODE_SHIFT             (16U)
13806 /*! ERROR_CODE
13807  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13808  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13809  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
13810  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
13811  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
13812  */
13813 #define DCP_CH2STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
13814 
13815 #define DCP_CH2STAT_TAG_MASK                     (0xFF000000U)
13816 #define DCP_CH2STAT_TAG_SHIFT                    (24U)
13817 #define DCP_CH2STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
13818 /*! @} */
13819 
13820 /*! @name CH2STAT_SET - DCP channel 2 status register */
13821 /*! @{ */
13822 
13823 #define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
13824 #define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
13825 #define DCP_CH2STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
13826 
13827 #define DCP_CH2STAT_SET_HASH_MISMATCH_MASK       (0x2U)
13828 #define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT      (1U)
13829 #define DCP_CH2STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
13830 
13831 #define DCP_CH2STAT_SET_ERROR_SETUP_MASK         (0x4U)
13832 #define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT        (2U)
13833 #define DCP_CH2STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
13834 
13835 #define DCP_CH2STAT_SET_ERROR_PACKET_MASK        (0x8U)
13836 #define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT       (3U)
13837 #define DCP_CH2STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
13838 
13839 #define DCP_CH2STAT_SET_ERROR_SRC_MASK           (0x10U)
13840 #define DCP_CH2STAT_SET_ERROR_SRC_SHIFT          (4U)
13841 #define DCP_CH2STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
13842 
13843 #define DCP_CH2STAT_SET_ERROR_DST_MASK           (0x20U)
13844 #define DCP_CH2STAT_SET_ERROR_DST_SHIFT          (5U)
13845 #define DCP_CH2STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
13846 
13847 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
13848 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
13849 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
13850 
13851 #define DCP_CH2STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
13852 #define DCP_CH2STAT_SET_ERROR_CODE_SHIFT         (16U)
13853 /*! ERROR_CODE
13854  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13855  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13856  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
13857  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
13858  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
13859  */
13860 #define DCP_CH2STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
13861 
13862 #define DCP_CH2STAT_SET_TAG_MASK                 (0xFF000000U)
13863 #define DCP_CH2STAT_SET_TAG_SHIFT                (24U)
13864 #define DCP_CH2STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
13865 /*! @} */
13866 
13867 /*! @name CH2STAT_CLR - DCP channel 2 status register */
13868 /*! @{ */
13869 
13870 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
13871 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
13872 #define DCP_CH2STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
13873 
13874 #define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
13875 #define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
13876 #define DCP_CH2STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
13877 
13878 #define DCP_CH2STAT_CLR_ERROR_SETUP_MASK         (0x4U)
13879 #define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT        (2U)
13880 #define DCP_CH2STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
13881 
13882 #define DCP_CH2STAT_CLR_ERROR_PACKET_MASK        (0x8U)
13883 #define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT       (3U)
13884 #define DCP_CH2STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
13885 
13886 #define DCP_CH2STAT_CLR_ERROR_SRC_MASK           (0x10U)
13887 #define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT          (4U)
13888 #define DCP_CH2STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
13889 
13890 #define DCP_CH2STAT_CLR_ERROR_DST_MASK           (0x20U)
13891 #define DCP_CH2STAT_CLR_ERROR_DST_SHIFT          (5U)
13892 #define DCP_CH2STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
13893 
13894 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
13895 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
13896 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
13897 
13898 #define DCP_CH2STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
13899 #define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT         (16U)
13900 /*! ERROR_CODE
13901  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13902  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13903  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
13904  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
13905  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
13906  */
13907 #define DCP_CH2STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
13908 
13909 #define DCP_CH2STAT_CLR_TAG_MASK                 (0xFF000000U)
13910 #define DCP_CH2STAT_CLR_TAG_SHIFT                (24U)
13911 #define DCP_CH2STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
13912 /*! @} */
13913 
13914 /*! @name CH2STAT_TOG - DCP channel 2 status register */
13915 /*! @{ */
13916 
13917 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
13918 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
13919 #define DCP_CH2STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
13920 
13921 #define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
13922 #define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
13923 #define DCP_CH2STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
13924 
13925 #define DCP_CH2STAT_TOG_ERROR_SETUP_MASK         (0x4U)
13926 #define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT        (2U)
13927 #define DCP_CH2STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
13928 
13929 #define DCP_CH2STAT_TOG_ERROR_PACKET_MASK        (0x8U)
13930 #define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT       (3U)
13931 #define DCP_CH2STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
13932 
13933 #define DCP_CH2STAT_TOG_ERROR_SRC_MASK           (0x10U)
13934 #define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT          (4U)
13935 #define DCP_CH2STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
13936 
13937 #define DCP_CH2STAT_TOG_ERROR_DST_MASK           (0x20U)
13938 #define DCP_CH2STAT_TOG_ERROR_DST_SHIFT          (5U)
13939 #define DCP_CH2STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
13940 
13941 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
13942 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
13943 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
13944 
13945 #define DCP_CH2STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
13946 #define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT         (16U)
13947 /*! ERROR_CODE
13948  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
13949  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
13950  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
13951  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
13952  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
13953  */
13954 #define DCP_CH2STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
13955 
13956 #define DCP_CH2STAT_TOG_TAG_MASK                 (0xFF000000U)
13957 #define DCP_CH2STAT_TOG_TAG_SHIFT                (24U)
13958 #define DCP_CH2STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
13959 /*! @} */
13960 
13961 /*! @name CH2OPTS - DCP channel 2 options register */
13962 /*! @{ */
13963 
13964 #define DCP_CH2OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
13965 #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT         (0U)
13966 #define DCP_CH2OPTS_RECOVERY_TIMER(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
13967 
13968 #define DCP_CH2OPTS_RSVD_MASK                    (0xFFFF0000U)
13969 #define DCP_CH2OPTS_RSVD_SHIFT                   (16U)
13970 #define DCP_CH2OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
13971 /*! @} */
13972 
13973 /*! @name CH2OPTS_SET - DCP channel 2 options register */
13974 /*! @{ */
13975 
13976 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
13977 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
13978 #define DCP_CH2OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
13979 
13980 #define DCP_CH2OPTS_SET_RSVD_MASK                (0xFFFF0000U)
13981 #define DCP_CH2OPTS_SET_RSVD_SHIFT               (16U)
13982 #define DCP_CH2OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
13983 /*! @} */
13984 
13985 /*! @name CH2OPTS_CLR - DCP channel 2 options register */
13986 /*! @{ */
13987 
13988 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
13989 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
13990 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
13991 
13992 #define DCP_CH2OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
13993 #define DCP_CH2OPTS_CLR_RSVD_SHIFT               (16U)
13994 #define DCP_CH2OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
13995 /*! @} */
13996 
13997 /*! @name CH2OPTS_TOG - DCP channel 2 options register */
13998 /*! @{ */
13999 
14000 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
14001 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
14002 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
14003 
14004 #define DCP_CH2OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
14005 #define DCP_CH2OPTS_TOG_RSVD_SHIFT               (16U)
14006 #define DCP_CH2OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
14007 /*! @} */
14008 
14009 /*! @name CH3CMDPTR - DCP channel 3 command pointer address register */
14010 /*! @{ */
14011 
14012 #define DCP_CH3CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
14013 #define DCP_CH3CMDPTR_ADDR_SHIFT                 (0U)
14014 #define DCP_CH3CMDPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
14015 /*! @} */
14016 
14017 /*! @name CH3SEMA - DCP channel 3 semaphore register */
14018 /*! @{ */
14019 
14020 #define DCP_CH3SEMA_INCREMENT_MASK               (0xFFU)
14021 #define DCP_CH3SEMA_INCREMENT_SHIFT              (0U)
14022 #define DCP_CH3SEMA_INCREMENT(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
14023 
14024 #define DCP_CH3SEMA_VALUE_MASK                   (0xFF0000U)
14025 #define DCP_CH3SEMA_VALUE_SHIFT                  (16U)
14026 #define DCP_CH3SEMA_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
14027 /*! @} */
14028 
14029 /*! @name CH3STAT - DCP channel 3 status register */
14030 /*! @{ */
14031 
14032 #define DCP_CH3STAT_RSVD_COMPLETE_MASK           (0x1U)
14033 #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT          (0U)
14034 #define DCP_CH3STAT_RSVD_COMPLETE(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
14035 
14036 #define DCP_CH3STAT_HASH_MISMATCH_MASK           (0x2U)
14037 #define DCP_CH3STAT_HASH_MISMATCH_SHIFT          (1U)
14038 #define DCP_CH3STAT_HASH_MISMATCH(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
14039 
14040 #define DCP_CH3STAT_ERROR_SETUP_MASK             (0x4U)
14041 #define DCP_CH3STAT_ERROR_SETUP_SHIFT            (2U)
14042 #define DCP_CH3STAT_ERROR_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
14043 
14044 #define DCP_CH3STAT_ERROR_PACKET_MASK            (0x8U)
14045 #define DCP_CH3STAT_ERROR_PACKET_SHIFT           (3U)
14046 #define DCP_CH3STAT_ERROR_PACKET(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
14047 
14048 #define DCP_CH3STAT_ERROR_SRC_MASK               (0x10U)
14049 #define DCP_CH3STAT_ERROR_SRC_SHIFT              (4U)
14050 #define DCP_CH3STAT_ERROR_SRC(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
14051 
14052 #define DCP_CH3STAT_ERROR_DST_MASK               (0x20U)
14053 #define DCP_CH3STAT_ERROR_DST_SHIFT              (5U)
14054 #define DCP_CH3STAT_ERROR_DST(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
14055 
14056 #define DCP_CH3STAT_ERROR_PAGEFAULT_MASK         (0x40U)
14057 #define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT        (6U)
14058 #define DCP_CH3STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
14059 
14060 #define DCP_CH3STAT_ERROR_CODE_MASK              (0xFF0000U)
14061 #define DCP_CH3STAT_ERROR_CODE_SHIFT             (16U)
14062 /*! ERROR_CODE
14063  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
14064  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
14065  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
14066  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
14067  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
14068  */
14069 #define DCP_CH3STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
14070 
14071 #define DCP_CH3STAT_TAG_MASK                     (0xFF000000U)
14072 #define DCP_CH3STAT_TAG_SHIFT                    (24U)
14073 #define DCP_CH3STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
14074 /*! @} */
14075 
14076 /*! @name CH3STAT_SET - DCP channel 3 status register */
14077 /*! @{ */
14078 
14079 #define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
14080 #define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
14081 #define DCP_CH3STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
14082 
14083 #define DCP_CH3STAT_SET_HASH_MISMATCH_MASK       (0x2U)
14084 #define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT      (1U)
14085 #define DCP_CH3STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
14086 
14087 #define DCP_CH3STAT_SET_ERROR_SETUP_MASK         (0x4U)
14088 #define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT        (2U)
14089 #define DCP_CH3STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
14090 
14091 #define DCP_CH3STAT_SET_ERROR_PACKET_MASK        (0x8U)
14092 #define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT       (3U)
14093 #define DCP_CH3STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
14094 
14095 #define DCP_CH3STAT_SET_ERROR_SRC_MASK           (0x10U)
14096 #define DCP_CH3STAT_SET_ERROR_SRC_SHIFT          (4U)
14097 #define DCP_CH3STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
14098 
14099 #define DCP_CH3STAT_SET_ERROR_DST_MASK           (0x20U)
14100 #define DCP_CH3STAT_SET_ERROR_DST_SHIFT          (5U)
14101 #define DCP_CH3STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
14102 
14103 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
14104 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
14105 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
14106 
14107 #define DCP_CH3STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
14108 #define DCP_CH3STAT_SET_ERROR_CODE_SHIFT         (16U)
14109 /*! ERROR_CODE
14110  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
14111  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
14112  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
14113  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
14114  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
14115  */
14116 #define DCP_CH3STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
14117 
14118 #define DCP_CH3STAT_SET_TAG_MASK                 (0xFF000000U)
14119 #define DCP_CH3STAT_SET_TAG_SHIFT                (24U)
14120 #define DCP_CH3STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
14121 /*! @} */
14122 
14123 /*! @name CH3STAT_CLR - DCP channel 3 status register */
14124 /*! @{ */
14125 
14126 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
14127 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
14128 #define DCP_CH3STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
14129 
14130 #define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
14131 #define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
14132 #define DCP_CH3STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
14133 
14134 #define DCP_CH3STAT_CLR_ERROR_SETUP_MASK         (0x4U)
14135 #define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT        (2U)
14136 #define DCP_CH3STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
14137 
14138 #define DCP_CH3STAT_CLR_ERROR_PACKET_MASK        (0x8U)
14139 #define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT       (3U)
14140 #define DCP_CH3STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
14141 
14142 #define DCP_CH3STAT_CLR_ERROR_SRC_MASK           (0x10U)
14143 #define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT          (4U)
14144 #define DCP_CH3STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
14145 
14146 #define DCP_CH3STAT_CLR_ERROR_DST_MASK           (0x20U)
14147 #define DCP_CH3STAT_CLR_ERROR_DST_SHIFT          (5U)
14148 #define DCP_CH3STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
14149 
14150 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
14151 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
14152 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
14153 
14154 #define DCP_CH3STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
14155 #define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT         (16U)
14156 /*! ERROR_CODE
14157  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
14158  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
14159  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
14160  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
14161  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
14162  */
14163 #define DCP_CH3STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
14164 
14165 #define DCP_CH3STAT_CLR_TAG_MASK                 (0xFF000000U)
14166 #define DCP_CH3STAT_CLR_TAG_SHIFT                (24U)
14167 #define DCP_CH3STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
14168 /*! @} */
14169 
14170 /*! @name CH3STAT_TOG - DCP channel 3 status register */
14171 /*! @{ */
14172 
14173 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
14174 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
14175 #define DCP_CH3STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
14176 
14177 #define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
14178 #define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
14179 #define DCP_CH3STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
14180 
14181 #define DCP_CH3STAT_TOG_ERROR_SETUP_MASK         (0x4U)
14182 #define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT        (2U)
14183 #define DCP_CH3STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
14184 
14185 #define DCP_CH3STAT_TOG_ERROR_PACKET_MASK        (0x8U)
14186 #define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT       (3U)
14187 #define DCP_CH3STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
14188 
14189 #define DCP_CH3STAT_TOG_ERROR_SRC_MASK           (0x10U)
14190 #define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT          (4U)
14191 #define DCP_CH3STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
14192 
14193 #define DCP_CH3STAT_TOG_ERROR_DST_MASK           (0x20U)
14194 #define DCP_CH3STAT_TOG_ERROR_DST_SHIFT          (5U)
14195 #define DCP_CH3STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
14196 
14197 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
14198 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
14199 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
14200 
14201 #define DCP_CH3STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
14202 #define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT         (16U)
14203 /*! ERROR_CODE
14204  *  0b00000001..Error is signalled because the next pointer is 0x00000000.
14205  *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
14206  *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
14207  *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
14208  *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
14209  */
14210 #define DCP_CH3STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
14211 
14212 #define DCP_CH3STAT_TOG_TAG_MASK                 (0xFF000000U)
14213 #define DCP_CH3STAT_TOG_TAG_SHIFT                (24U)
14214 #define DCP_CH3STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
14215 /*! @} */
14216 
14217 /*! @name CH3OPTS - DCP channel 3 options register */
14218 /*! @{ */
14219 
14220 #define DCP_CH3OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
14221 #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT         (0U)
14222 #define DCP_CH3OPTS_RECOVERY_TIMER(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
14223 
14224 #define DCP_CH3OPTS_RSVD_MASK                    (0xFFFF0000U)
14225 #define DCP_CH3OPTS_RSVD_SHIFT                   (16U)
14226 #define DCP_CH3OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
14227 /*! @} */
14228 
14229 /*! @name CH3OPTS_SET - DCP channel 3 options register */
14230 /*! @{ */
14231 
14232 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
14233 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
14234 #define DCP_CH3OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
14235 
14236 #define DCP_CH3OPTS_SET_RSVD_MASK                (0xFFFF0000U)
14237 #define DCP_CH3OPTS_SET_RSVD_SHIFT               (16U)
14238 #define DCP_CH3OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
14239 /*! @} */
14240 
14241 /*! @name CH3OPTS_CLR - DCP channel 3 options register */
14242 /*! @{ */
14243 
14244 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
14245 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
14246 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
14247 
14248 #define DCP_CH3OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
14249 #define DCP_CH3OPTS_CLR_RSVD_SHIFT               (16U)
14250 #define DCP_CH3OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
14251 /*! @} */
14252 
14253 /*! @name CH3OPTS_TOG - DCP channel 3 options register */
14254 /*! @{ */
14255 
14256 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
14257 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
14258 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
14259 
14260 #define DCP_CH3OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
14261 #define DCP_CH3OPTS_TOG_RSVD_SHIFT               (16U)
14262 #define DCP_CH3OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
14263 /*! @} */
14264 
14265 /*! @name DBGSELECT - DCP debug select register */
14266 /*! @{ */
14267 
14268 #define DCP_DBGSELECT_INDEX_MASK                 (0xFFU)
14269 #define DCP_DBGSELECT_INDEX_SHIFT                (0U)
14270 /*! INDEX
14271  *  0b00000001..CONTROL
14272  *  0b00010000..OTPKEY0
14273  *  0b00010001..OTPKEY1
14274  *  0b00010010..OTPKEY2
14275  *  0b00010011..OTPKEY3
14276  */
14277 #define DCP_DBGSELECT_INDEX(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
14278 
14279 #define DCP_DBGSELECT_RSVD_MASK                  (0xFFFFFF00U)
14280 #define DCP_DBGSELECT_RSVD_SHIFT                 (8U)
14281 #define DCP_DBGSELECT_RSVD(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
14282 /*! @} */
14283 
14284 /*! @name DBGDATA - DCP debug data register */
14285 /*! @{ */
14286 
14287 #define DCP_DBGDATA_DATA_MASK                    (0xFFFFFFFFU)
14288 #define DCP_DBGDATA_DATA_SHIFT                   (0U)
14289 #define DCP_DBGDATA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
14290 /*! @} */
14291 
14292 /*! @name PAGETABLE - DCP page table register */
14293 /*! @{ */
14294 
14295 #define DCP_PAGETABLE_ENABLE_MASK                (0x1U)
14296 #define DCP_PAGETABLE_ENABLE_SHIFT               (0U)
14297 #define DCP_PAGETABLE_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
14298 
14299 #define DCP_PAGETABLE_FLUSH_MASK                 (0x2U)
14300 #define DCP_PAGETABLE_FLUSH_SHIFT                (1U)
14301 #define DCP_PAGETABLE_FLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
14302 
14303 #define DCP_PAGETABLE_BASE_MASK                  (0xFFFFFFFCU)
14304 #define DCP_PAGETABLE_BASE_SHIFT                 (2U)
14305 #define DCP_PAGETABLE_BASE(x)                    (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
14306 /*! @} */
14307 
14308 /*! @name VERSION - DCP version register */
14309 /*! @{ */
14310 
14311 #define DCP_VERSION_STEP_MASK                    (0xFFFFU)
14312 #define DCP_VERSION_STEP_SHIFT                   (0U)
14313 #define DCP_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
14314 
14315 #define DCP_VERSION_MINOR_MASK                   (0xFF0000U)
14316 #define DCP_VERSION_MINOR_SHIFT                  (16U)
14317 #define DCP_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
14318 
14319 #define DCP_VERSION_MAJOR_MASK                   (0xFF000000U)
14320 #define DCP_VERSION_MAJOR_SHIFT                  (24U)
14321 #define DCP_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
14322 /*! @} */
14323 
14324 
14325 /*!
14326  * @}
14327  */ /* end of group DCP_Register_Masks */
14328 
14329 
14330 /* DCP - Peripheral instance base addresses */
14331 /** Peripheral DCP base address */
14332 #define DCP_BASE                                 (0x402FC000u)
14333 /** Peripheral DCP base pointer */
14334 #define DCP                                      ((DCP_Type *)DCP_BASE)
14335 /** Array initializer of DCP peripheral base addresses */
14336 #define DCP_BASE_ADDRS                           { DCP_BASE }
14337 /** Array initializer of DCP peripheral base pointers */
14338 #define DCP_BASE_PTRS                            { DCP }
14339 /** Interrupt vectors for the DCP peripheral type */
14340 #define DCP_IRQS                                 { DCP_IRQn }
14341 #define DCP_VMI_IRQS                             { DCP_VMI_IRQn }
14342 
14343 /*!
14344  * @}
14345  */ /* end of group DCP_Peripheral_Access_Layer */
14346 
14347 
14348 /* ----------------------------------------------------------------------------
14349    -- DMA Peripheral Access Layer
14350    ---------------------------------------------------------------------------- */
14351 
14352 /*!
14353  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
14354  * @{
14355  */
14356 
14357 /** DMA - Register Layout Typedef */
14358 typedef struct {
14359   __IO uint32_t CR;                                /**< Control, offset: 0x0 */
14360   __I  uint32_t ES;                                /**< Error Status, offset: 0x4 */
14361        uint8_t RESERVED_0[4];
14362   __IO uint32_t ERQ;                               /**< Enable Request, offset: 0xC */
14363        uint8_t RESERVED_1[4];
14364   __IO uint32_t EEI;                               /**< Enable Error Interrupt, offset: 0x14 */
14365   __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt, offset: 0x18 */
14366   __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt, offset: 0x19 */
14367   __O  uint8_t CERQ;                               /**< Clear Enable Request, offset: 0x1A */
14368   __O  uint8_t SERQ;                               /**< Set Enable Request, offset: 0x1B */
14369   __O  uint8_t CDNE;                               /**< Clear DONE Status Bit, offset: 0x1C */
14370   __O  uint8_t SSRT;                               /**< Set START Bit, offset: 0x1D */
14371   __O  uint8_t CERR;                               /**< Clear Error, offset: 0x1E */
14372   __O  uint8_t CINT;                               /**< Clear Interrupt Request, offset: 0x1F */
14373        uint8_t RESERVED_2[4];
14374   __IO uint32_t INT;                               /**< Interrupt Request, offset: 0x24 */
14375        uint8_t RESERVED_3[4];
14376   __IO uint32_t ERR;                               /**< Error, offset: 0x2C */
14377        uint8_t RESERVED_4[4];
14378   __I  uint32_t HRS;                               /**< Hardware Request Status, offset: 0x34 */
14379        uint8_t RESERVED_5[12];
14380   __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop, offset: 0x44 */
14381        uint8_t RESERVED_6[184];
14382   __IO uint8_t DCHPRI3;                            /**< Channel Priority, offset: 0x100 */
14383   __IO uint8_t DCHPRI2;                            /**< Channel Priority, offset: 0x101 */
14384   __IO uint8_t DCHPRI1;                            /**< Channel Priority, offset: 0x102 */
14385   __IO uint8_t DCHPRI0;                            /**< Channel Priority, offset: 0x103 */
14386   __IO uint8_t DCHPRI7;                            /**< Channel Priority, offset: 0x104 */
14387   __IO uint8_t DCHPRI6;                            /**< Channel Priority, offset: 0x105 */
14388   __IO uint8_t DCHPRI5;                            /**< Channel Priority, offset: 0x106 */
14389   __IO uint8_t DCHPRI4;                            /**< Channel Priority, offset: 0x107 */
14390   __IO uint8_t DCHPRI11;                           /**< Channel Priority, offset: 0x108 */
14391   __IO uint8_t DCHPRI10;                           /**< Channel Priority, offset: 0x109 */
14392   __IO uint8_t DCHPRI9;                            /**< Channel Priority, offset: 0x10A */
14393   __IO uint8_t DCHPRI8;                            /**< Channel Priority, offset: 0x10B */
14394   __IO uint8_t DCHPRI15;                           /**< Channel Priority, offset: 0x10C */
14395   __IO uint8_t DCHPRI14;                           /**< Channel Priority, offset: 0x10D */
14396   __IO uint8_t DCHPRI13;                           /**< Channel Priority, offset: 0x10E */
14397   __IO uint8_t DCHPRI12;                           /**< Channel Priority, offset: 0x10F */
14398   __IO uint8_t DCHPRI19;                           /**< Channel Priority, offset: 0x110 */
14399   __IO uint8_t DCHPRI18;                           /**< Channel Priority, offset: 0x111 */
14400   __IO uint8_t DCHPRI17;                           /**< Channel Priority, offset: 0x112 */
14401   __IO uint8_t DCHPRI16;                           /**< Channel Priority, offset: 0x113 */
14402   __IO uint8_t DCHPRI23;                           /**< Channel Priority, offset: 0x114 */
14403   __IO uint8_t DCHPRI22;                           /**< Channel Priority, offset: 0x115 */
14404   __IO uint8_t DCHPRI21;                           /**< Channel Priority, offset: 0x116 */
14405   __IO uint8_t DCHPRI20;                           /**< Channel Priority, offset: 0x117 */
14406   __IO uint8_t DCHPRI27;                           /**< Channel Priority, offset: 0x118 */
14407   __IO uint8_t DCHPRI26;                           /**< Channel Priority, offset: 0x119 */
14408   __IO uint8_t DCHPRI25;                           /**< Channel Priority, offset: 0x11A */
14409   __IO uint8_t DCHPRI24;                           /**< Channel Priority, offset: 0x11B */
14410   __IO uint8_t DCHPRI31;                           /**< Channel Priority, offset: 0x11C */
14411   __IO uint8_t DCHPRI30;                           /**< Channel Priority, offset: 0x11D */
14412   __IO uint8_t DCHPRI29;                           /**< Channel Priority, offset: 0x11E */
14413   __IO uint8_t DCHPRI28;                           /**< Channel Priority, offset: 0x11F */
14414        uint8_t RESERVED_7[3808];
14415   struct {                                         /* offset: 0x1000, array step: 0x20 */
14416     __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
14417     __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
14418     __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
14419     union {                                          /* offset: 0x1008, array step: 0x20 */
14420       __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
14421       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
14422       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
14423     };
14424     __IO int32_t SLAST;                              /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
14425     __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
14426     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
14427     union {                                          /* offset: 0x1016, array step: 0x20 */
14428       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
14429       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
14430     };
14431     __IO int32_t DLAST_SGA;                          /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
14432     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
14433     union {                                          /* offset: 0x101E, array step: 0x20 */
14434       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
14435       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
14436     };
14437   } TCD[32];
14438 } DMA_Type;
14439 
14440 /* ----------------------------------------------------------------------------
14441    -- DMA Register Masks
14442    ---------------------------------------------------------------------------- */
14443 
14444 /*!
14445  * @addtogroup DMA_Register_Masks DMA Register Masks
14446  * @{
14447  */
14448 
14449 /*! @name CR - Control */
14450 /*! @{ */
14451 
14452 #define DMA_CR_EDBG_MASK                         (0x2U)
14453 #define DMA_CR_EDBG_SHIFT                        (1U)
14454 /*! EDBG - Enable Debug
14455  *  0b0..When the chip is in Debug mode, the eDMA continues to operate.
14456  *  0b1..Entry of the chip into Debug mode is effective
14457  */
14458 #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
14459 
14460 #define DMA_CR_ERCA_MASK                         (0x4U)
14461 #define DMA_CR_ERCA_SHIFT                        (2U)
14462 /*! ERCA - Enable Round Robin Channel Arbitration
14463  *  0b0..Fixed priority arbitration within each group
14464  *  0b1..Round robin arbitration within each group
14465  */
14466 #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
14467 
14468 #define DMA_CR_ERGA_MASK                         (0x8U)
14469 #define DMA_CR_ERGA_SHIFT                        (3U)
14470 /*! ERGA - Enable Round Robin Group Arbitration
14471  *  0b0..Fixed priority arbitration
14472  *  0b1..Round robin arbitration
14473  */
14474 #define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
14475 
14476 #define DMA_CR_HOE_MASK                          (0x10U)
14477 #define DMA_CR_HOE_SHIFT                         (4U)
14478 /*! HOE - Halt On Error
14479  *  0b0..Normal operation
14480  *  0b1..Error causes HALT field to be automatically set to 1
14481  */
14482 #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
14483 
14484 #define DMA_CR_HALT_MASK                         (0x20U)
14485 #define DMA_CR_HALT_SHIFT                        (5U)
14486 /*! HALT - Halt eDMA Operations
14487  *  0b0..Normal operation
14488  *  0b1..eDMA operations halted
14489  */
14490 #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
14491 
14492 #define DMA_CR_CLM_MASK                          (0x40U)
14493 #define DMA_CR_CLM_SHIFT                         (6U)
14494 /*! CLM - Continuous Link Mode
14495  *  0b0..Continuous link mode is off
14496  *  0b1..Continuous link mode is on
14497  */
14498 #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
14499 
14500 #define DMA_CR_EMLM_MASK                         (0x80U)
14501 #define DMA_CR_EMLM_SHIFT                        (7U)
14502 /*! EMLM - Enable Minor Loop Mapping
14503  *  0b0..Disabled
14504  *  0b1..Enabled
14505  */
14506 #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
14507 
14508 #define DMA_CR_GRP0PRI_MASK                      (0x100U)
14509 #define DMA_CR_GRP0PRI_SHIFT                     (8U)
14510 /*! GRP0PRI - Channel Group 0 Priority
14511  */
14512 #define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
14513 
14514 #define DMA_CR_GRP1PRI_MASK                      (0x400U)
14515 #define DMA_CR_GRP1PRI_SHIFT                     (10U)
14516 /*! GRP1PRI - Channel Group 1 Priority
14517  */
14518 #define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
14519 
14520 #define DMA_CR_ECX_MASK                          (0x10000U)
14521 #define DMA_CR_ECX_SHIFT                         (16U)
14522 /*! ECX - Error Cancel Transfer
14523  *  0b0..Normal operation
14524  *  0b1..Cancel the remaining data transfer
14525  */
14526 #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
14527 
14528 #define DMA_CR_CX_MASK                           (0x20000U)
14529 #define DMA_CR_CX_SHIFT                          (17U)
14530 /*! CX - Cancel Transfer
14531  *  0b0..Normal operation
14532  *  0b1..Cancel the remaining data transfer
14533  */
14534 #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
14535 
14536 #define DMA_CR_VERSION_MASK                      (0x7F000000U)
14537 #define DMA_CR_VERSION_SHIFT                     (24U)
14538 /*! VERSION - eDMA version number
14539  */
14540 #define DMA_CR_VERSION(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
14541 
14542 #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
14543 #define DMA_CR_ACTIVE_SHIFT                      (31U)
14544 /*! ACTIVE - eDMA Active Status
14545  *  0b0..eDMA is idle
14546  *  0b1..eDMA is executing a channel
14547  */
14548 #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
14549 /*! @} */
14550 
14551 /*! @name ES - Error Status */
14552 /*! @{ */
14553 
14554 #define DMA_ES_DBE_MASK                          (0x1U)
14555 #define DMA_ES_DBE_SHIFT                         (0U)
14556 /*! DBE - Destination Bus Error
14557  *  0b0..No destination bus error.
14558  *  0b1..The most-recently recorded error was a bus error on a destination write.
14559  */
14560 #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
14561 
14562 #define DMA_ES_SBE_MASK                          (0x2U)
14563 #define DMA_ES_SBE_SHIFT                         (1U)
14564 /*! SBE - Source Bus Error
14565  *  0b0..No source bus error.
14566  *  0b1..The most-recently recorded error was a bus error on a source read.
14567  */
14568 #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
14569 
14570 #define DMA_ES_SGE_MASK                          (0x4U)
14571 #define DMA_ES_SGE_SHIFT                         (2U)
14572 /*! SGE - Scatter/Gather Configuration Error
14573  *  0b0..No scatter/gather configuration error.
14574  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.
14575  */
14576 #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
14577 
14578 #define DMA_ES_NCE_MASK                          (0x8U)
14579 #define DMA_ES_NCE_SHIFT                         (3U)
14580 /*! NCE - NBYTES/CITER Configuration Error
14581  *  0b0..No NBYTES/CITER configuration error.
14582  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
14583  *       fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or
14584  *       TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].
14585  */
14586 #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
14587 
14588 #define DMA_ES_DOE_MASK                          (0x10U)
14589 #define DMA_ES_DOE_SHIFT                         (4U)
14590 /*! DOE - Destination Offset Error
14591  *  0b0..No destination offset configuration error.
14592  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
14593  */
14594 #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
14595 
14596 #define DMA_ES_DAE_MASK                          (0x20U)
14597 #define DMA_ES_DAE_SHIFT                         (5U)
14598 /*! DAE - Destination Address Error
14599  *  0b0..No destination address configuration error.
14600  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR
14601  *       is inconsistent with TCDn_ATTR[DSIZE].
14602  */
14603 #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
14604 
14605 #define DMA_ES_SOE_MASK                          (0x40U)
14606 #define DMA_ES_SOE_SHIFT                         (6U)
14607 /*! SOE - Source Offset Error
14608  *  0b0..No source offset configuration error.
14609  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
14610  */
14611 #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
14612 
14613 #define DMA_ES_SAE_MASK                          (0x80U)
14614 #define DMA_ES_SAE_SHIFT                         (7U)
14615 /*! SAE - Source Address Error
14616  *  0b0..No source address configuration error.
14617  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
14618  *       is inconsistent with TCDn_ATTR[SSIZE].
14619  */
14620 #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
14621 
14622 #define DMA_ES_ERRCHN_MASK                       (0x1F00U)
14623 #define DMA_ES_ERRCHN_SHIFT                      (8U)
14624 /*! ERRCHN - Error Channel Number or Canceled Channel Number
14625  */
14626 #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
14627 
14628 #define DMA_ES_CPE_MASK                          (0x4000U)
14629 #define DMA_ES_CPE_SHIFT                         (14U)
14630 /*! CPE - Channel Priority Error
14631  *  0b0..No channel priority error.
14632  *  0b1..The most-recently recorded error was a configuration error in the channel priorities within a group.
14633  *       Channel priorities within a group are not unique.
14634  */
14635 #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
14636 
14637 #define DMA_ES_GPE_MASK                          (0x8000U)
14638 #define DMA_ES_GPE_SHIFT                         (15U)
14639 /*! GPE - Group Priority Error
14640  *  0b0..No group priority error.
14641  *  0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.
14642  */
14643 #define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
14644 
14645 #define DMA_ES_ECX_MASK                          (0x10000U)
14646 #define DMA_ES_ECX_SHIFT                         (16U)
14647 /*! ECX - Transfer Canceled
14648  *  0b0..No canceled transfers
14649  *  0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field
14650  */
14651 #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
14652 
14653 #define DMA_ES_VLD_MASK                          (0x80000000U)
14654 #define DMA_ES_VLD_SHIFT                         (31U)
14655 /*! VLD - Logical OR of all ERR status fields
14656  *  0b0..No ERR fields are 1
14657  *  0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared
14658  */
14659 #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
14660 /*! @} */
14661 
14662 /*! @name ERQ - Enable Request */
14663 /*! @{ */
14664 
14665 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
14666 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
14667 /*! ERQ0 - Enable DMA Request 0
14668  *  0b0..The DMA request signal for channel 0 is disabled
14669  *  0b1..The DMA request signal for channel 0 is enabled
14670  */
14671 #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
14672 
14673 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
14674 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
14675 /*! ERQ1 - Enable DMA Request 1
14676  *  0b0..The DMA request signal for channel 1 is disabled
14677  *  0b1..The DMA request signal for channel 1 is enabled
14678  */
14679 #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
14680 
14681 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
14682 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
14683 /*! ERQ2 - Enable DMA Request 2
14684  *  0b0..The DMA request signal for channel 2 is disabled
14685  *  0b1..The DMA request signal for channel 2 is enabled
14686  */
14687 #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
14688 
14689 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
14690 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
14691 /*! ERQ3 - Enable DMA Request 3
14692  *  0b0..The DMA request signal for channel 3 is disabled
14693  *  0b1..The DMA request signal for channel 3 is enabled
14694  */
14695 #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
14696 
14697 #define DMA_ERQ_ERQ4_MASK                        (0x10U)
14698 #define DMA_ERQ_ERQ4_SHIFT                       (4U)
14699 /*! ERQ4 - Enable DMA Request 4
14700  *  0b0..The DMA request signal for channel 4 is disabled
14701  *  0b1..The DMA request signal for channel 4 is enabled
14702  */
14703 #define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
14704 
14705 #define DMA_ERQ_ERQ5_MASK                        (0x20U)
14706 #define DMA_ERQ_ERQ5_SHIFT                       (5U)
14707 /*! ERQ5 - Enable DMA Request 5
14708  *  0b0..The DMA request signal for channel 5 is disabled
14709  *  0b1..The DMA request signal for channel 5 is enabled
14710  */
14711 #define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
14712 
14713 #define DMA_ERQ_ERQ6_MASK                        (0x40U)
14714 #define DMA_ERQ_ERQ6_SHIFT                       (6U)
14715 /*! ERQ6 - Enable DMA Request 6
14716  *  0b0..The DMA request signal for channel 6 is disabled
14717  *  0b1..The DMA request signal for channel 6 is enabled
14718  */
14719 #define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
14720 
14721 #define DMA_ERQ_ERQ7_MASK                        (0x80U)
14722 #define DMA_ERQ_ERQ7_SHIFT                       (7U)
14723 /*! ERQ7 - Enable DMA Request 7
14724  *  0b0..The DMA request signal for channel 7 is disabled
14725  *  0b1..The DMA request signal for channel 7 is enabled
14726  */
14727 #define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
14728 
14729 #define DMA_ERQ_ERQ8_MASK                        (0x100U)
14730 #define DMA_ERQ_ERQ8_SHIFT                       (8U)
14731 /*! ERQ8 - Enable DMA Request 8
14732  *  0b0..The DMA request signal for channel 8 is disabled
14733  *  0b1..The DMA request signal for channel 8 is enabled
14734  */
14735 #define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
14736 
14737 #define DMA_ERQ_ERQ9_MASK                        (0x200U)
14738 #define DMA_ERQ_ERQ9_SHIFT                       (9U)
14739 /*! ERQ9 - Enable DMA Request 9
14740  *  0b0..The DMA request signal for channel 9 is disabled
14741  *  0b1..The DMA request signal for channel 9 is enabled
14742  */
14743 #define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
14744 
14745 #define DMA_ERQ_ERQ10_MASK                       (0x400U)
14746 #define DMA_ERQ_ERQ10_SHIFT                      (10U)
14747 /*! ERQ10 - Enable DMA Request 10
14748  *  0b0..The DMA request signal for channel 10 is disabled
14749  *  0b1..The DMA request signal for channel 10 is enabled
14750  */
14751 #define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
14752 
14753 #define DMA_ERQ_ERQ11_MASK                       (0x800U)
14754 #define DMA_ERQ_ERQ11_SHIFT                      (11U)
14755 /*! ERQ11 - Enable DMA Request 11
14756  *  0b0..The DMA request signal for channel 11 is disabled
14757  *  0b1..The DMA request signal for channel 11 is enabled
14758  */
14759 #define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
14760 
14761 #define DMA_ERQ_ERQ12_MASK                       (0x1000U)
14762 #define DMA_ERQ_ERQ12_SHIFT                      (12U)
14763 /*! ERQ12 - Enable DMA Request 12
14764  *  0b0..The DMA request signal for channel 12 is disabled
14765  *  0b1..The DMA request signal for channel 12 is enabled
14766  */
14767 #define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
14768 
14769 #define DMA_ERQ_ERQ13_MASK                       (0x2000U)
14770 #define DMA_ERQ_ERQ13_SHIFT                      (13U)
14771 /*! ERQ13 - Enable DMA Request 13
14772  *  0b0..The DMA request signal for channel 13 is disabled
14773  *  0b1..The DMA request signal for channel 13 is enabled
14774  */
14775 #define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
14776 
14777 #define DMA_ERQ_ERQ14_MASK                       (0x4000U)
14778 #define DMA_ERQ_ERQ14_SHIFT                      (14U)
14779 /*! ERQ14 - Enable DMA Request 14
14780  *  0b0..The DMA request signal for channel 14 is disabled
14781  *  0b1..The DMA request signal for channel 14 is enabled
14782  */
14783 #define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
14784 
14785 #define DMA_ERQ_ERQ15_MASK                       (0x8000U)
14786 #define DMA_ERQ_ERQ15_SHIFT                      (15U)
14787 /*! ERQ15 - Enable DMA Request 15
14788  *  0b0..The DMA request signal for channel 15 is disabled
14789  *  0b1..The DMA request signal for channel 15 is enabled
14790  */
14791 #define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
14792 
14793 #define DMA_ERQ_ERQ16_MASK                       (0x10000U)
14794 #define DMA_ERQ_ERQ16_SHIFT                      (16U)
14795 /*! ERQ16 - Enable DMA Request 16
14796  *  0b0..The DMA request signal for channel 16 is disabled
14797  *  0b1..The DMA request signal for channel 16 is enabled
14798  */
14799 #define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
14800 
14801 #define DMA_ERQ_ERQ17_MASK                       (0x20000U)
14802 #define DMA_ERQ_ERQ17_SHIFT                      (17U)
14803 /*! ERQ17 - Enable DMA Request 17
14804  *  0b0..The DMA request signal for channel 17 is disabled
14805  *  0b1..The DMA request signal for channel 17 is enabled
14806  */
14807 #define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
14808 
14809 #define DMA_ERQ_ERQ18_MASK                       (0x40000U)
14810 #define DMA_ERQ_ERQ18_SHIFT                      (18U)
14811 /*! ERQ18 - Enable DMA Request 18
14812  *  0b0..The DMA request signal for channel 18 is disabled
14813  *  0b1..The DMA request signal for channel 18 is enabled
14814  */
14815 #define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
14816 
14817 #define DMA_ERQ_ERQ19_MASK                       (0x80000U)
14818 #define DMA_ERQ_ERQ19_SHIFT                      (19U)
14819 /*! ERQ19 - Enable DMA Request 19
14820  *  0b0..The DMA request signal for channel 19 is disabled
14821  *  0b1..The DMA request signal for channel 19 is enabled
14822  */
14823 #define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
14824 
14825 #define DMA_ERQ_ERQ20_MASK                       (0x100000U)
14826 #define DMA_ERQ_ERQ20_SHIFT                      (20U)
14827 /*! ERQ20 - Enable DMA Request 20
14828  *  0b0..The DMA request signal for channel 20 is disabled
14829  *  0b1..The DMA request signal for channel 20 is enabled
14830  */
14831 #define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
14832 
14833 #define DMA_ERQ_ERQ21_MASK                       (0x200000U)
14834 #define DMA_ERQ_ERQ21_SHIFT                      (21U)
14835 /*! ERQ21 - Enable DMA Request 21
14836  *  0b0..The DMA request signal for channel 21 is disabled
14837  *  0b1..The DMA request signal for channel 21 is enabled
14838  */
14839 #define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
14840 
14841 #define DMA_ERQ_ERQ22_MASK                       (0x400000U)
14842 #define DMA_ERQ_ERQ22_SHIFT                      (22U)
14843 /*! ERQ22 - Enable DMA Request 22
14844  *  0b0..The DMA request signal for channel 22 is disabled
14845  *  0b1..The DMA request signal for channel 22 is enabled
14846  */
14847 #define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
14848 
14849 #define DMA_ERQ_ERQ23_MASK                       (0x800000U)
14850 #define DMA_ERQ_ERQ23_SHIFT                      (23U)
14851 /*! ERQ23 - Enable DMA Request 23
14852  *  0b0..The DMA request signal for channel 23 is disabled
14853  *  0b1..The DMA request signal for channel 23 is enabled
14854  */
14855 #define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
14856 
14857 #define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
14858 #define DMA_ERQ_ERQ24_SHIFT                      (24U)
14859 /*! ERQ24 - Enable DMA Request 24
14860  *  0b0..The DMA request signal for channel 24 is disabled
14861  *  0b1..The DMA request signal for channel 24 is enabled
14862  */
14863 #define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
14864 
14865 #define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
14866 #define DMA_ERQ_ERQ25_SHIFT                      (25U)
14867 /*! ERQ25 - Enable DMA Request 25
14868  *  0b0..The DMA request signal for channel 25 is disabled
14869  *  0b1..The DMA request signal for channel 25 is enabled
14870  */
14871 #define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
14872 
14873 #define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
14874 #define DMA_ERQ_ERQ26_SHIFT                      (26U)
14875 /*! ERQ26 - Enable DMA Request 26
14876  *  0b0..The DMA request signal for channel 26 is disabled
14877  *  0b1..The DMA request signal for channel 26 is enabled
14878  */
14879 #define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
14880 
14881 #define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
14882 #define DMA_ERQ_ERQ27_SHIFT                      (27U)
14883 /*! ERQ27 - Enable DMA Request 27
14884  *  0b0..The DMA request signal for channel 27 is disabled
14885  *  0b1..The DMA request signal for channel 27 is enabled
14886  */
14887 #define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
14888 
14889 #define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
14890 #define DMA_ERQ_ERQ28_SHIFT                      (28U)
14891 /*! ERQ28 - Enable DMA Request 28
14892  *  0b0..The DMA request signal for channel 28 is disabled
14893  *  0b1..The DMA request signal for channel 28 is enabled
14894  */
14895 #define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
14896 
14897 #define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
14898 #define DMA_ERQ_ERQ29_SHIFT                      (29U)
14899 /*! ERQ29 - Enable DMA Request 29
14900  *  0b0..The DMA request signal for channel 29 is disabled
14901  *  0b1..The DMA request signal for channel 29 is enabled
14902  */
14903 #define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
14904 
14905 #define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
14906 #define DMA_ERQ_ERQ30_SHIFT                      (30U)
14907 /*! ERQ30 - Enable DMA Request 30
14908  *  0b0..The DMA request signal for channel 30 is disabled
14909  *  0b1..The DMA request signal for channel 30 is enabled
14910  */
14911 #define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
14912 
14913 #define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
14914 #define DMA_ERQ_ERQ31_SHIFT                      (31U)
14915 /*! ERQ31 - Enable DMA Request 31
14916  *  0b0..The DMA request signal for channel 31 is disabled
14917  *  0b1..The DMA request signal for channel 31 is enabled
14918  */
14919 #define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
14920 /*! @} */
14921 
14922 /*! @name EEI - Enable Error Interrupt */
14923 /*! @{ */
14924 
14925 #define DMA_EEI_EEI0_MASK                        (0x1U)
14926 #define DMA_EEI_EEI0_SHIFT                       (0U)
14927 /*! EEI0 - Enable Error Interrupt 0
14928  *  0b0..An error on channel 0 does not generate an error interrupt
14929  *  0b1..An error on channel 0 generates an error interrupt request
14930  */
14931 #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
14932 
14933 #define DMA_EEI_EEI1_MASK                        (0x2U)
14934 #define DMA_EEI_EEI1_SHIFT                       (1U)
14935 /*! EEI1 - Enable Error Interrupt 1
14936  *  0b0..An error on channel 1 does not generate an error interrupt
14937  *  0b1..An error on channel 1 generates an error interrupt request
14938  */
14939 #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
14940 
14941 #define DMA_EEI_EEI2_MASK                        (0x4U)
14942 #define DMA_EEI_EEI2_SHIFT                       (2U)
14943 /*! EEI2 - Enable Error Interrupt 2
14944  *  0b0..An error on channel 2 does not generate an error interrupt
14945  *  0b1..An error on channel 2 generates an error interrupt request
14946  */
14947 #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
14948 
14949 #define DMA_EEI_EEI3_MASK                        (0x8U)
14950 #define DMA_EEI_EEI3_SHIFT                       (3U)
14951 /*! EEI3 - Enable Error Interrupt 3
14952  *  0b0..An error on channel 3 does not generate an error interrupt
14953  *  0b1..An error on channel 3 generates an error interrupt request
14954  */
14955 #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
14956 
14957 #define DMA_EEI_EEI4_MASK                        (0x10U)
14958 #define DMA_EEI_EEI4_SHIFT                       (4U)
14959 /*! EEI4 - Enable Error Interrupt 4
14960  *  0b0..An error on channel 4 does not generate an error interrupt
14961  *  0b1..An error on channel 4 generates an error interrupt request
14962  */
14963 #define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
14964 
14965 #define DMA_EEI_EEI5_MASK                        (0x20U)
14966 #define DMA_EEI_EEI5_SHIFT                       (5U)
14967 /*! EEI5 - Enable Error Interrupt 5
14968  *  0b0..An error on channel 5 does not generate an error interrupt
14969  *  0b1..An error on channel 5 generates an error interrupt request
14970  */
14971 #define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
14972 
14973 #define DMA_EEI_EEI6_MASK                        (0x40U)
14974 #define DMA_EEI_EEI6_SHIFT                       (6U)
14975 /*! EEI6 - Enable Error Interrupt 6
14976  *  0b0..An error on channel 6 does not generate an error interrupt
14977  *  0b1..An error on channel 6 generates an error interrupt request
14978  */
14979 #define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
14980 
14981 #define DMA_EEI_EEI7_MASK                        (0x80U)
14982 #define DMA_EEI_EEI7_SHIFT                       (7U)
14983 /*! EEI7 - Enable Error Interrupt 7
14984  *  0b0..An error on channel 7 does not generate an error interrupt
14985  *  0b1..An error on channel 7 generates an error interrupt request
14986  */
14987 #define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
14988 
14989 #define DMA_EEI_EEI8_MASK                        (0x100U)
14990 #define DMA_EEI_EEI8_SHIFT                       (8U)
14991 /*! EEI8 - Enable Error Interrupt 8
14992  *  0b0..An error on channel 8 does not generate an error interrupt
14993  *  0b1..An error on channel 8 generates an error interrupt request
14994  */
14995 #define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
14996 
14997 #define DMA_EEI_EEI9_MASK                        (0x200U)
14998 #define DMA_EEI_EEI9_SHIFT                       (9U)
14999 /*! EEI9 - Enable Error Interrupt 9
15000  *  0b0..An error on channel 9 does not generate an error interrupt
15001  *  0b1..An error on channel 9 generates an error interrupt request
15002  */
15003 #define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
15004 
15005 #define DMA_EEI_EEI10_MASK                       (0x400U)
15006 #define DMA_EEI_EEI10_SHIFT                      (10U)
15007 /*! EEI10 - Enable Error Interrupt 10
15008  *  0b0..An error on channel 10 does not generate an error interrupt
15009  *  0b1..An error on channel 10 generates an error interrupt request
15010  */
15011 #define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
15012 
15013 #define DMA_EEI_EEI11_MASK                       (0x800U)
15014 #define DMA_EEI_EEI11_SHIFT                      (11U)
15015 /*! EEI11 - Enable Error Interrupt 11
15016  *  0b0..An error on channel 11 does not generate an error interrupt
15017  *  0b1..An error on channel 11 generates an error interrupt request
15018  */
15019 #define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
15020 
15021 #define DMA_EEI_EEI12_MASK                       (0x1000U)
15022 #define DMA_EEI_EEI12_SHIFT                      (12U)
15023 /*! EEI12 - Enable Error Interrupt 12
15024  *  0b0..An error on channel 12 does not generate an error interrupt
15025  *  0b1..An error on channel 12 generates an error interrupt request
15026  */
15027 #define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
15028 
15029 #define DMA_EEI_EEI13_MASK                       (0x2000U)
15030 #define DMA_EEI_EEI13_SHIFT                      (13U)
15031 /*! EEI13 - Enable Error Interrupt 13
15032  *  0b0..An error on channel 13 does not generate an error interrupt
15033  *  0b1..An error on channel 13 generates an error interrupt request
15034  */
15035 #define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
15036 
15037 #define DMA_EEI_EEI14_MASK                       (0x4000U)
15038 #define DMA_EEI_EEI14_SHIFT                      (14U)
15039 /*! EEI14 - Enable Error Interrupt 14
15040  *  0b0..An error on channel 14 does not generate an error interrupt
15041  *  0b1..An error on channel 14 generates an error interrupt request
15042  */
15043 #define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
15044 
15045 #define DMA_EEI_EEI15_MASK                       (0x8000U)
15046 #define DMA_EEI_EEI15_SHIFT                      (15U)
15047 /*! EEI15 - Enable Error Interrupt 15
15048  *  0b0..An error on channel 15 does not generate an error interrupt
15049  *  0b1..An error on channel 15 generates an error interrupt request
15050  */
15051 #define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
15052 
15053 #define DMA_EEI_EEI16_MASK                       (0x10000U)
15054 #define DMA_EEI_EEI16_SHIFT                      (16U)
15055 /*! EEI16 - Enable Error Interrupt 16
15056  *  0b0..An error on channel 16 does not generate an error interrupt
15057  *  0b1..An error on channel 16 generates an error interrupt request
15058  */
15059 #define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
15060 
15061 #define DMA_EEI_EEI17_MASK                       (0x20000U)
15062 #define DMA_EEI_EEI17_SHIFT                      (17U)
15063 /*! EEI17 - Enable Error Interrupt 17
15064  *  0b0..An error on channel 17 does not generate an error interrupt
15065  *  0b1..An error on channel 17 generates an error interrupt request
15066  */
15067 #define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
15068 
15069 #define DMA_EEI_EEI18_MASK                       (0x40000U)
15070 #define DMA_EEI_EEI18_SHIFT                      (18U)
15071 /*! EEI18 - Enable Error Interrupt 18
15072  *  0b0..An error on channel 18 does not generate an error interrupt
15073  *  0b1..An error on channel 18 generates an error interrupt request
15074  */
15075 #define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
15076 
15077 #define DMA_EEI_EEI19_MASK                       (0x80000U)
15078 #define DMA_EEI_EEI19_SHIFT                      (19U)
15079 /*! EEI19 - Enable Error Interrupt 19
15080  *  0b0..An error on channel 19 does not generate an error interrupt
15081  *  0b1..An error on channel 19 generates an error interrupt request
15082  */
15083 #define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
15084 
15085 #define DMA_EEI_EEI20_MASK                       (0x100000U)
15086 #define DMA_EEI_EEI20_SHIFT                      (20U)
15087 /*! EEI20 - Enable Error Interrupt 20
15088  *  0b0..An error on channel 20 does not generate an error interrupt
15089  *  0b1..An error on channel 20 generates an error interrupt request
15090  */
15091 #define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
15092 
15093 #define DMA_EEI_EEI21_MASK                       (0x200000U)
15094 #define DMA_EEI_EEI21_SHIFT                      (21U)
15095 /*! EEI21 - Enable Error Interrupt 21
15096  *  0b0..An error on channel 21 does not generate an error interrupt
15097  *  0b1..An error on channel 21 generates an error interrupt request
15098  */
15099 #define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
15100 
15101 #define DMA_EEI_EEI22_MASK                       (0x400000U)
15102 #define DMA_EEI_EEI22_SHIFT                      (22U)
15103 /*! EEI22 - Enable Error Interrupt 22
15104  *  0b0..An error on channel 22 does not generate an error interrupt
15105  *  0b1..An error on channel 22 generates an error interrupt request
15106  */
15107 #define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
15108 
15109 #define DMA_EEI_EEI23_MASK                       (0x800000U)
15110 #define DMA_EEI_EEI23_SHIFT                      (23U)
15111 /*! EEI23 - Enable Error Interrupt 23
15112  *  0b0..An error on channel 23 does not generate an error interrupt
15113  *  0b1..An error on channel 23 generates an error interrupt request
15114  */
15115 #define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
15116 
15117 #define DMA_EEI_EEI24_MASK                       (0x1000000U)
15118 #define DMA_EEI_EEI24_SHIFT                      (24U)
15119 /*! EEI24 - Enable Error Interrupt 24
15120  *  0b0..An error on channel 24 does not generate an error interrupt
15121  *  0b1..An error on channel 24 generates an error interrupt request
15122  */
15123 #define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
15124 
15125 #define DMA_EEI_EEI25_MASK                       (0x2000000U)
15126 #define DMA_EEI_EEI25_SHIFT                      (25U)
15127 /*! EEI25 - Enable Error Interrupt 25
15128  *  0b0..An error on channel 25 does not generate an error interrupt
15129  *  0b1..An error on channel 25 generates an error interrupt request
15130  */
15131 #define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
15132 
15133 #define DMA_EEI_EEI26_MASK                       (0x4000000U)
15134 #define DMA_EEI_EEI26_SHIFT                      (26U)
15135 /*! EEI26 - Enable Error Interrupt 26
15136  *  0b0..An error on channel 26 does not generate an error interrupt
15137  *  0b1..An error on channel 26 generates an error interrupt request
15138  */
15139 #define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
15140 
15141 #define DMA_EEI_EEI27_MASK                       (0x8000000U)
15142 #define DMA_EEI_EEI27_SHIFT                      (27U)
15143 /*! EEI27 - Enable Error Interrupt 27
15144  *  0b0..An error on channel 27 does not generate an error interrupt
15145  *  0b1..An error on channel 27 generates an error interrupt request
15146  */
15147 #define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
15148 
15149 #define DMA_EEI_EEI28_MASK                       (0x10000000U)
15150 #define DMA_EEI_EEI28_SHIFT                      (28U)
15151 /*! EEI28 - Enable Error Interrupt 28
15152  *  0b0..An error on channel 28 does not generate an error interrupt
15153  *  0b1..An error on channel 28 generates an error interrupt request
15154  */
15155 #define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
15156 
15157 #define DMA_EEI_EEI29_MASK                       (0x20000000U)
15158 #define DMA_EEI_EEI29_SHIFT                      (29U)
15159 /*! EEI29 - Enable Error Interrupt 29
15160  *  0b0..An error on channel 29 does not generate an error interrupt
15161  *  0b1..An error on channel 29 generates an error interrupt request
15162  */
15163 #define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
15164 
15165 #define DMA_EEI_EEI30_MASK                       (0x40000000U)
15166 #define DMA_EEI_EEI30_SHIFT                      (30U)
15167 /*! EEI30 - Enable Error Interrupt 30
15168  *  0b0..An error on channel 30 does not generate an error interrupt
15169  *  0b1..An error on channel 30 generates an error interrupt request
15170  */
15171 #define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
15172 
15173 #define DMA_EEI_EEI31_MASK                       (0x80000000U)
15174 #define DMA_EEI_EEI31_SHIFT                      (31U)
15175 /*! EEI31 - Enable Error Interrupt 31
15176  *  0b0..An error on channel 31 does not generate an error interrupt
15177  *  0b1..An error on channel 31 generates an error interrupt request
15178  */
15179 #define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
15180 /*! @} */
15181 
15182 /*! @name CEEI - Clear Enable Error Interrupt */
15183 /*! @{ */
15184 
15185 #define DMA_CEEI_CEEI_MASK                       (0x1FU)
15186 #define DMA_CEEI_CEEI_SHIFT                      (0U)
15187 /*! CEEI - Clear Enable Error Interrupt
15188  */
15189 #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
15190 
15191 #define DMA_CEEI_CAEE_MASK                       (0x40U)
15192 #define DMA_CEEI_CAEE_SHIFT                      (6U)
15193 /*! CAEE - Clear All Enable Error Interrupts
15194  *  0b0..Write 0 only to the EEI field specified in the CEEI field
15195  *  0b1..Write 0 to all fields in EEI
15196  */
15197 #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
15198 
15199 #define DMA_CEEI_NOP_MASK                        (0x80U)
15200 #define DMA_CEEI_NOP_SHIFT                       (7U)
15201 /*! NOP - No Op Enable
15202  *  0b0..Normal operation
15203  *  0b1..No operation, ignore the other fields in this register
15204  */
15205 #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
15206 /*! @} */
15207 
15208 /*! @name SEEI - Set Enable Error Interrupt */
15209 /*! @{ */
15210 
15211 #define DMA_SEEI_SEEI_MASK                       (0x1FU)
15212 #define DMA_SEEI_SEEI_SHIFT                      (0U)
15213 /*! SEEI - Set Enable Error Interrupt
15214  */
15215 #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
15216 
15217 #define DMA_SEEI_SAEE_MASK                       (0x40U)
15218 #define DMA_SEEI_SAEE_SHIFT                      (6U)
15219 /*! SAEE - Set All Enable Error Interrupts
15220  *  0b0..Write 1 only to the EEI field specified in the SEEI field
15221  *  0b1..Writes 1 to all fields in EEI
15222  */
15223 #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
15224 
15225 #define DMA_SEEI_NOP_MASK                        (0x80U)
15226 #define DMA_SEEI_NOP_SHIFT                       (7U)
15227 /*! NOP - No Op Enable
15228  *  0b0..Normal operation
15229  *  0b1..No operation, ignore the other fields in this register
15230  */
15231 #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
15232 /*! @} */
15233 
15234 /*! @name CERQ - Clear Enable Request */
15235 /*! @{ */
15236 
15237 #define DMA_CERQ_CERQ_MASK                       (0x1FU)
15238 #define DMA_CERQ_CERQ_SHIFT                      (0U)
15239 /*! CERQ - Clear Enable Request
15240  */
15241 #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
15242 
15243 #define DMA_CERQ_CAER_MASK                       (0x40U)
15244 #define DMA_CERQ_CAER_SHIFT                      (6U)
15245 /*! CAER - Clear All Enable Requests
15246  *  0b0..Write 0 to only the ERQ field specified in the CERQ field
15247  *  0b1..Write 0 to all fields in ERQ
15248  */
15249 #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
15250 
15251 #define DMA_CERQ_NOP_MASK                        (0x80U)
15252 #define DMA_CERQ_NOP_SHIFT                       (7U)
15253 /*! NOP - No Op Enable
15254  *  0b0..Normal operation
15255  *  0b1..No operation, ignore the other fields in this register
15256  */
15257 #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
15258 /*! @} */
15259 
15260 /*! @name SERQ - Set Enable Request */
15261 /*! @{ */
15262 
15263 #define DMA_SERQ_SERQ_MASK                       (0x1FU)
15264 #define DMA_SERQ_SERQ_SHIFT                      (0U)
15265 /*! SERQ - Set Enable Request
15266  */
15267 #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
15268 
15269 #define DMA_SERQ_SAER_MASK                       (0x40U)
15270 #define DMA_SERQ_SAER_SHIFT                      (6U)
15271 /*! SAER - Set All Enable Requests
15272  *  0b0..Write 1 to only the ERQ field specified in the SERQ field
15273  *  0b1..Write 1 to all fields in ERQ
15274  */
15275 #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
15276 
15277 #define DMA_SERQ_NOP_MASK                        (0x80U)
15278 #define DMA_SERQ_NOP_SHIFT                       (7U)
15279 /*! NOP - No Op Enable
15280  *  0b0..Normal operation
15281  *  0b1..No operation, ignore the other fields in this register
15282  */
15283 #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
15284 /*! @} */
15285 
15286 /*! @name CDNE - Clear DONE Status Bit */
15287 /*! @{ */
15288 
15289 #define DMA_CDNE_CDNE_MASK                       (0x1FU)
15290 #define DMA_CDNE_CDNE_SHIFT                      (0U)
15291 /*! CDNE - Clear DONE field
15292  */
15293 #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
15294 
15295 #define DMA_CDNE_CADN_MASK                       (0x40U)
15296 #define DMA_CDNE_CADN_SHIFT                      (6U)
15297 /*! CADN - Clears All DONE fields
15298  *  0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field
15299  *  0b1..Writes 0 to all bits in TCDn_CSR[DONE]
15300  */
15301 #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
15302 
15303 #define DMA_CDNE_NOP_MASK                        (0x80U)
15304 #define DMA_CDNE_NOP_SHIFT                       (7U)
15305 /*! NOP - No Op Enable
15306  *  0b0..Normal operation
15307  *  0b1..No operation; all other fields in this register are ignored.
15308  */
15309 #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
15310 /*! @} */
15311 
15312 /*! @name SSRT - Set START Bit */
15313 /*! @{ */
15314 
15315 #define DMA_SSRT_SSRT_MASK                       (0x1FU)
15316 #define DMA_SSRT_SSRT_SHIFT                      (0U)
15317 /*! SSRT - Set START field
15318  */
15319 #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
15320 
15321 #define DMA_SSRT_SAST_MASK                       (0x40U)
15322 #define DMA_SSRT_SAST_SHIFT                      (6U)
15323 /*! SAST - Set All START fields (activates all channels)
15324  *  0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field
15325  *  0b1..Write 1 to all bits in TCDn_CSR[START]
15326  */
15327 #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
15328 
15329 #define DMA_SSRT_NOP_MASK                        (0x80U)
15330 #define DMA_SSRT_NOP_SHIFT                       (7U)
15331 /*! NOP - No Op Enable
15332  *  0b0..Normal operation
15333  *  0b1..No operation; all other fields in this register are ignored.
15334  */
15335 #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
15336 /*! @} */
15337 
15338 /*! @name CERR - Clear Error */
15339 /*! @{ */
15340 
15341 #define DMA_CERR_CERR_MASK                       (0x1FU)
15342 #define DMA_CERR_CERR_SHIFT                      (0U)
15343 /*! CERR - Clear Error Indicator
15344  */
15345 #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
15346 
15347 #define DMA_CERR_CAEI_MASK                       (0x40U)
15348 #define DMA_CERR_CAEI_SHIFT                      (6U)
15349 /*! CAEI - Clear All Error Indicators
15350  *  0b0..Write 0 to only the ERR field specified in the CERR field
15351  *  0b1..Write 0 to all fields in ERR
15352  */
15353 #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
15354 
15355 #define DMA_CERR_NOP_MASK                        (0x80U)
15356 #define DMA_CERR_NOP_SHIFT                       (7U)
15357 /*! NOP - No Op Enable
15358  *  0b0..Normal operation
15359  *  0b1..No operation; all other fields in this register are ignored.
15360  */
15361 #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
15362 /*! @} */
15363 
15364 /*! @name CINT - Clear Interrupt Request */
15365 /*! @{ */
15366 
15367 #define DMA_CINT_CINT_MASK                       (0x1FU)
15368 #define DMA_CINT_CINT_SHIFT                      (0U)
15369 /*! CINT - Clear Interrupt Request
15370  */
15371 #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
15372 
15373 #define DMA_CINT_CAIR_MASK                       (0x40U)
15374 #define DMA_CINT_CAIR_SHIFT                      (6U)
15375 /*! CAIR - Clear All Interrupt Requests
15376  *  0b0..Clear only the INT field specified in the CINT field
15377  *  0b1..Clear all bits in INT
15378  */
15379 #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
15380 
15381 #define DMA_CINT_NOP_MASK                        (0x80U)
15382 #define DMA_CINT_NOP_SHIFT                       (7U)
15383 /*! NOP - No Op Enable
15384  *  0b0..Normal operation
15385  *  0b1..No operation; all other fields in this register are ignored.
15386  */
15387 #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
15388 /*! @} */
15389 
15390 /*! @name INT - Interrupt Request */
15391 /*! @{ */
15392 
15393 #define DMA_INT_INT0_MASK                        (0x1U)
15394 #define DMA_INT_INT0_SHIFT                       (0U)
15395 /*! INT0 - Interrupt Request 0
15396  *  0b0..The interrupt request for channel 0 is cleared
15397  *  0b1..The interrupt request for channel 0 is active
15398  */
15399 #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
15400 
15401 #define DMA_INT_INT1_MASK                        (0x2U)
15402 #define DMA_INT_INT1_SHIFT                       (1U)
15403 /*! INT1 - Interrupt Request 1
15404  *  0b0..The interrupt request for channel 1 is cleared
15405  *  0b1..The interrupt request for channel 1 is active
15406  */
15407 #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
15408 
15409 #define DMA_INT_INT2_MASK                        (0x4U)
15410 #define DMA_INT_INT2_SHIFT                       (2U)
15411 /*! INT2 - Interrupt Request 2
15412  *  0b0..The interrupt request for channel 2 is cleared
15413  *  0b1..The interrupt request for channel 2 is active
15414  */
15415 #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
15416 
15417 #define DMA_INT_INT3_MASK                        (0x8U)
15418 #define DMA_INT_INT3_SHIFT                       (3U)
15419 /*! INT3 - Interrupt Request 3
15420  *  0b0..The interrupt request for channel 3 is cleared
15421  *  0b1..The interrupt request for channel 3 is active
15422  */
15423 #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
15424 
15425 #define DMA_INT_INT4_MASK                        (0x10U)
15426 #define DMA_INT_INT4_SHIFT                       (4U)
15427 /*! INT4 - Interrupt Request 4
15428  *  0b0..The interrupt request for channel 4 is cleared
15429  *  0b1..The interrupt request for channel 4 is active
15430  */
15431 #define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
15432 
15433 #define DMA_INT_INT5_MASK                        (0x20U)
15434 #define DMA_INT_INT5_SHIFT                       (5U)
15435 /*! INT5 - Interrupt Request 5
15436  *  0b0..The interrupt request for channel 5 is cleared
15437  *  0b1..The interrupt request for channel 5 is active
15438  */
15439 #define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
15440 
15441 #define DMA_INT_INT6_MASK                        (0x40U)
15442 #define DMA_INT_INT6_SHIFT                       (6U)
15443 /*! INT6 - Interrupt Request 6
15444  *  0b0..The interrupt request for channel 6 is cleared
15445  *  0b1..The interrupt request for channel 6 is active
15446  */
15447 #define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
15448 
15449 #define DMA_INT_INT7_MASK                        (0x80U)
15450 #define DMA_INT_INT7_SHIFT                       (7U)
15451 /*! INT7 - Interrupt Request 7
15452  *  0b0..The interrupt request for channel 7 is cleared
15453  *  0b1..The interrupt request for channel 7 is active
15454  */
15455 #define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
15456 
15457 #define DMA_INT_INT8_MASK                        (0x100U)
15458 #define DMA_INT_INT8_SHIFT                       (8U)
15459 /*! INT8 - Interrupt Request 8
15460  *  0b0..The interrupt request for channel 8 is cleared
15461  *  0b1..The interrupt request for channel 8 is active
15462  */
15463 #define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
15464 
15465 #define DMA_INT_INT9_MASK                        (0x200U)
15466 #define DMA_INT_INT9_SHIFT                       (9U)
15467 /*! INT9 - Interrupt Request 9
15468  *  0b0..The interrupt request for channel 9 is cleared
15469  *  0b1..The interrupt request for channel 9 is active
15470  */
15471 #define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
15472 
15473 #define DMA_INT_INT10_MASK                       (0x400U)
15474 #define DMA_INT_INT10_SHIFT                      (10U)
15475 /*! INT10 - Interrupt Request 10
15476  *  0b0..The interrupt request for channel 10 is cleared
15477  *  0b1..The interrupt request for channel 10 is active
15478  */
15479 #define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
15480 
15481 #define DMA_INT_INT11_MASK                       (0x800U)
15482 #define DMA_INT_INT11_SHIFT                      (11U)
15483 /*! INT11 - Interrupt Request 11
15484  *  0b0..The interrupt request for channel 11 is cleared
15485  *  0b1..The interrupt request for channel 11 is active
15486  */
15487 #define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
15488 
15489 #define DMA_INT_INT12_MASK                       (0x1000U)
15490 #define DMA_INT_INT12_SHIFT                      (12U)
15491 /*! INT12 - Interrupt Request 12
15492  *  0b0..The interrupt request for channel 12 is cleared
15493  *  0b1..The interrupt request for channel 12 is active
15494  */
15495 #define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
15496 
15497 #define DMA_INT_INT13_MASK                       (0x2000U)
15498 #define DMA_INT_INT13_SHIFT                      (13U)
15499 /*! INT13 - Interrupt Request 13
15500  *  0b0..The interrupt request for channel 13 is cleared
15501  *  0b1..The interrupt request for channel 13 is active
15502  */
15503 #define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
15504 
15505 #define DMA_INT_INT14_MASK                       (0x4000U)
15506 #define DMA_INT_INT14_SHIFT                      (14U)
15507 /*! INT14 - Interrupt Request 14
15508  *  0b0..The interrupt request for channel 14 is cleared
15509  *  0b1..The interrupt request for channel 14 is active
15510  */
15511 #define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
15512 
15513 #define DMA_INT_INT15_MASK                       (0x8000U)
15514 #define DMA_INT_INT15_SHIFT                      (15U)
15515 /*! INT15 - Interrupt Request 15
15516  *  0b0..The interrupt request for channel 15 is cleared
15517  *  0b1..The interrupt request for channel 15 is active
15518  */
15519 #define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
15520 
15521 #define DMA_INT_INT16_MASK                       (0x10000U)
15522 #define DMA_INT_INT16_SHIFT                      (16U)
15523 /*! INT16 - Interrupt Request 16
15524  *  0b0..The interrupt request for channel 16 is cleared
15525  *  0b1..The interrupt request for channel 16 is active
15526  */
15527 #define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
15528 
15529 #define DMA_INT_INT17_MASK                       (0x20000U)
15530 #define DMA_INT_INT17_SHIFT                      (17U)
15531 /*! INT17 - Interrupt Request 17
15532  *  0b0..The interrupt request for channel 17 is cleared
15533  *  0b1..The interrupt request for channel 17 is active
15534  */
15535 #define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
15536 
15537 #define DMA_INT_INT18_MASK                       (0x40000U)
15538 #define DMA_INT_INT18_SHIFT                      (18U)
15539 /*! INT18 - Interrupt Request 18
15540  *  0b0..The interrupt request for channel 18 is cleared
15541  *  0b1..The interrupt request for channel 18 is active
15542  */
15543 #define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
15544 
15545 #define DMA_INT_INT19_MASK                       (0x80000U)
15546 #define DMA_INT_INT19_SHIFT                      (19U)
15547 /*! INT19 - Interrupt Request 19
15548  *  0b0..The interrupt request for channel 19 is cleared
15549  *  0b1..The interrupt request for channel 19 is active
15550  */
15551 #define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
15552 
15553 #define DMA_INT_INT20_MASK                       (0x100000U)
15554 #define DMA_INT_INT20_SHIFT                      (20U)
15555 /*! INT20 - Interrupt Request 20
15556  *  0b0..The interrupt request for channel 20 is cleared
15557  *  0b1..The interrupt request for channel 20 is active
15558  */
15559 #define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
15560 
15561 #define DMA_INT_INT21_MASK                       (0x200000U)
15562 #define DMA_INT_INT21_SHIFT                      (21U)
15563 /*! INT21 - Interrupt Request 21
15564  *  0b0..The interrupt request for channel 21 is cleared
15565  *  0b1..The interrupt request for channel 21 is active
15566  */
15567 #define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
15568 
15569 #define DMA_INT_INT22_MASK                       (0x400000U)
15570 #define DMA_INT_INT22_SHIFT                      (22U)
15571 /*! INT22 - Interrupt Request 22
15572  *  0b0..The interrupt request for channel 22 is cleared
15573  *  0b1..The interrupt request for channel 22 is active
15574  */
15575 #define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
15576 
15577 #define DMA_INT_INT23_MASK                       (0x800000U)
15578 #define DMA_INT_INT23_SHIFT                      (23U)
15579 /*! INT23 - Interrupt Request 23
15580  *  0b0..The interrupt request for channel 23 is cleared
15581  *  0b1..The interrupt request for channel 23 is active
15582  */
15583 #define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
15584 
15585 #define DMA_INT_INT24_MASK                       (0x1000000U)
15586 #define DMA_INT_INT24_SHIFT                      (24U)
15587 /*! INT24 - Interrupt Request 24
15588  *  0b0..The interrupt request for channel 24 is cleared
15589  *  0b1..The interrupt request for channel 24 is active
15590  */
15591 #define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
15592 
15593 #define DMA_INT_INT25_MASK                       (0x2000000U)
15594 #define DMA_INT_INT25_SHIFT                      (25U)
15595 /*! INT25 - Interrupt Request 25
15596  *  0b0..The interrupt request for channel 25 is cleared
15597  *  0b1..The interrupt request for channel 25 is active
15598  */
15599 #define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
15600 
15601 #define DMA_INT_INT26_MASK                       (0x4000000U)
15602 #define DMA_INT_INT26_SHIFT                      (26U)
15603 /*! INT26 - Interrupt Request 26
15604  *  0b0..The interrupt request for channel 26 is cleared
15605  *  0b1..The interrupt request for channel 26 is active
15606  */
15607 #define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
15608 
15609 #define DMA_INT_INT27_MASK                       (0x8000000U)
15610 #define DMA_INT_INT27_SHIFT                      (27U)
15611 /*! INT27 - Interrupt Request 27
15612  *  0b0..The interrupt request for channel 27 is cleared
15613  *  0b1..The interrupt request for channel 27 is active
15614  */
15615 #define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
15616 
15617 #define DMA_INT_INT28_MASK                       (0x10000000U)
15618 #define DMA_INT_INT28_SHIFT                      (28U)
15619 /*! INT28 - Interrupt Request 28
15620  *  0b0..The interrupt request for channel 28 is cleared
15621  *  0b1..The interrupt request for channel 28 is active
15622  */
15623 #define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
15624 
15625 #define DMA_INT_INT29_MASK                       (0x20000000U)
15626 #define DMA_INT_INT29_SHIFT                      (29U)
15627 /*! INT29 - Interrupt Request 29
15628  *  0b0..The interrupt request for channel 29 is cleared
15629  *  0b1..The interrupt request for channel 29 is active
15630  */
15631 #define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
15632 
15633 #define DMA_INT_INT30_MASK                       (0x40000000U)
15634 #define DMA_INT_INT30_SHIFT                      (30U)
15635 /*! INT30 - Interrupt Request 30
15636  *  0b0..The interrupt request for channel 30 is cleared
15637  *  0b1..The interrupt request for channel 30 is active
15638  */
15639 #define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
15640 
15641 #define DMA_INT_INT31_MASK                       (0x80000000U)
15642 #define DMA_INT_INT31_SHIFT                      (31U)
15643 /*! INT31 - Interrupt Request 31
15644  *  0b0..The interrupt request for channel 31 is cleared
15645  *  0b1..The interrupt request for channel 31 is active
15646  */
15647 #define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
15648 /*! @} */
15649 
15650 /*! @name ERR - Error */
15651 /*! @{ */
15652 
15653 #define DMA_ERR_ERR0_MASK                        (0x1U)
15654 #define DMA_ERR_ERR0_SHIFT                       (0U)
15655 /*! ERR0 - Error In Channel 0
15656  *  0b0..No error in this channel has occurred
15657  *  0b1..An error in this channel has occurred
15658  */
15659 #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
15660 
15661 #define DMA_ERR_ERR1_MASK                        (0x2U)
15662 #define DMA_ERR_ERR1_SHIFT                       (1U)
15663 /*! ERR1 - Error In Channel 1
15664  *  0b0..No error in this channel has occurred
15665  *  0b1..An error in this channel has occurred
15666  */
15667 #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
15668 
15669 #define DMA_ERR_ERR2_MASK                        (0x4U)
15670 #define DMA_ERR_ERR2_SHIFT                       (2U)
15671 /*! ERR2 - Error In Channel 2
15672  *  0b0..No error in this channel has occurred
15673  *  0b1..An error in this channel has occurred
15674  */
15675 #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
15676 
15677 #define DMA_ERR_ERR3_MASK                        (0x8U)
15678 #define DMA_ERR_ERR3_SHIFT                       (3U)
15679 /*! ERR3 - Error In Channel 3
15680  *  0b0..No error in this channel has occurred
15681  *  0b1..An error in this channel has occurred
15682  */
15683 #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
15684 
15685 #define DMA_ERR_ERR4_MASK                        (0x10U)
15686 #define DMA_ERR_ERR4_SHIFT                       (4U)
15687 /*! ERR4 - Error In Channel 4
15688  *  0b0..No error in this channel has occurred
15689  *  0b1..An error in this channel has occurred
15690  */
15691 #define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
15692 
15693 #define DMA_ERR_ERR5_MASK                        (0x20U)
15694 #define DMA_ERR_ERR5_SHIFT                       (5U)
15695 /*! ERR5 - Error In Channel 5
15696  *  0b0..No error in this channel has occurred
15697  *  0b1..An error in this channel has occurred
15698  */
15699 #define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
15700 
15701 #define DMA_ERR_ERR6_MASK                        (0x40U)
15702 #define DMA_ERR_ERR6_SHIFT                       (6U)
15703 /*! ERR6 - Error In Channel 6
15704  *  0b0..No error in this channel has occurred
15705  *  0b1..An error in this channel has occurred
15706  */
15707 #define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
15708 
15709 #define DMA_ERR_ERR7_MASK                        (0x80U)
15710 #define DMA_ERR_ERR7_SHIFT                       (7U)
15711 /*! ERR7 - Error In Channel 7
15712  *  0b0..No error in this channel has occurred
15713  *  0b1..An error in this channel has occurred
15714  */
15715 #define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
15716 
15717 #define DMA_ERR_ERR8_MASK                        (0x100U)
15718 #define DMA_ERR_ERR8_SHIFT                       (8U)
15719 /*! ERR8 - Error In Channel 8
15720  *  0b0..No error in this channel has occurred
15721  *  0b1..An error in this channel has occurred
15722  */
15723 #define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
15724 
15725 #define DMA_ERR_ERR9_MASK                        (0x200U)
15726 #define DMA_ERR_ERR9_SHIFT                       (9U)
15727 /*! ERR9 - Error In Channel 9
15728  *  0b0..No error in this channel has occurred
15729  *  0b1..An error in this channel has occurred
15730  */
15731 #define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
15732 
15733 #define DMA_ERR_ERR10_MASK                       (0x400U)
15734 #define DMA_ERR_ERR10_SHIFT                      (10U)
15735 /*! ERR10 - Error In Channel 10
15736  *  0b0..No error in this channel has occurred
15737  *  0b1..An error in this channel has occurred
15738  */
15739 #define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
15740 
15741 #define DMA_ERR_ERR11_MASK                       (0x800U)
15742 #define DMA_ERR_ERR11_SHIFT                      (11U)
15743 /*! ERR11 - Error In Channel 11
15744  *  0b0..No error in this channel has occurred
15745  *  0b1..An error in this channel has occurred
15746  */
15747 #define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
15748 
15749 #define DMA_ERR_ERR12_MASK                       (0x1000U)
15750 #define DMA_ERR_ERR12_SHIFT                      (12U)
15751 /*! ERR12 - Error In Channel 12
15752  *  0b0..No error in this channel has occurred
15753  *  0b1..An error in this channel has occurred
15754  */
15755 #define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
15756 
15757 #define DMA_ERR_ERR13_MASK                       (0x2000U)
15758 #define DMA_ERR_ERR13_SHIFT                      (13U)
15759 /*! ERR13 - Error In Channel 13
15760  *  0b0..No error in this channel has occurred
15761  *  0b1..An error in this channel has occurred
15762  */
15763 #define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
15764 
15765 #define DMA_ERR_ERR14_MASK                       (0x4000U)
15766 #define DMA_ERR_ERR14_SHIFT                      (14U)
15767 /*! ERR14 - Error In Channel 14
15768  *  0b0..No error in this channel has occurred
15769  *  0b1..An error in this channel has occurred
15770  */
15771 #define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
15772 
15773 #define DMA_ERR_ERR15_MASK                       (0x8000U)
15774 #define DMA_ERR_ERR15_SHIFT                      (15U)
15775 /*! ERR15 - Error In Channel 15
15776  *  0b0..No error in this channel has occurred
15777  *  0b1..An error in this channel has occurred
15778  */
15779 #define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
15780 
15781 #define DMA_ERR_ERR16_MASK                       (0x10000U)
15782 #define DMA_ERR_ERR16_SHIFT                      (16U)
15783 /*! ERR16 - Error In Channel 16
15784  *  0b0..No error in this channel has occurred
15785  *  0b1..An error in this channel has occurred
15786  */
15787 #define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
15788 
15789 #define DMA_ERR_ERR17_MASK                       (0x20000U)
15790 #define DMA_ERR_ERR17_SHIFT                      (17U)
15791 /*! ERR17 - Error In Channel 17
15792  *  0b0..No error in this channel has occurred
15793  *  0b1..An error in this channel has occurred
15794  */
15795 #define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
15796 
15797 #define DMA_ERR_ERR18_MASK                       (0x40000U)
15798 #define DMA_ERR_ERR18_SHIFT                      (18U)
15799 /*! ERR18 - Error In Channel 18
15800  *  0b0..No error in this channel has occurred
15801  *  0b1..An error in this channel has occurred
15802  */
15803 #define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
15804 
15805 #define DMA_ERR_ERR19_MASK                       (0x80000U)
15806 #define DMA_ERR_ERR19_SHIFT                      (19U)
15807 /*! ERR19 - Error In Channel 19
15808  *  0b0..No error in this channel has occurred
15809  *  0b1..An error in this channel has occurred
15810  */
15811 #define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
15812 
15813 #define DMA_ERR_ERR20_MASK                       (0x100000U)
15814 #define DMA_ERR_ERR20_SHIFT                      (20U)
15815 /*! ERR20 - Error In Channel 20
15816  *  0b0..No error in this channel has occurred
15817  *  0b1..An error in this channel has occurred
15818  */
15819 #define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
15820 
15821 #define DMA_ERR_ERR21_MASK                       (0x200000U)
15822 #define DMA_ERR_ERR21_SHIFT                      (21U)
15823 /*! ERR21 - Error In Channel 21
15824  *  0b0..No error in this channel has occurred
15825  *  0b1..An error in this channel has occurred
15826  */
15827 #define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
15828 
15829 #define DMA_ERR_ERR22_MASK                       (0x400000U)
15830 #define DMA_ERR_ERR22_SHIFT                      (22U)
15831 /*! ERR22 - Error In Channel 22
15832  *  0b0..No error in this channel has occurred
15833  *  0b1..An error in this channel has occurred
15834  */
15835 #define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
15836 
15837 #define DMA_ERR_ERR23_MASK                       (0x800000U)
15838 #define DMA_ERR_ERR23_SHIFT                      (23U)
15839 /*! ERR23 - Error In Channel 23
15840  *  0b0..No error in this channel has occurred
15841  *  0b1..An error in this channel has occurred
15842  */
15843 #define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
15844 
15845 #define DMA_ERR_ERR24_MASK                       (0x1000000U)
15846 #define DMA_ERR_ERR24_SHIFT                      (24U)
15847 /*! ERR24 - Error In Channel 24
15848  *  0b0..No error in this channel has occurred
15849  *  0b1..An error in this channel has occurred
15850  */
15851 #define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
15852 
15853 #define DMA_ERR_ERR25_MASK                       (0x2000000U)
15854 #define DMA_ERR_ERR25_SHIFT                      (25U)
15855 /*! ERR25 - Error In Channel 25
15856  *  0b0..No error in this channel has occurred
15857  *  0b1..An error in this channel has occurred
15858  */
15859 #define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
15860 
15861 #define DMA_ERR_ERR26_MASK                       (0x4000000U)
15862 #define DMA_ERR_ERR26_SHIFT                      (26U)
15863 /*! ERR26 - Error In Channel 26
15864  *  0b0..No error in this channel has occurred
15865  *  0b1..An error in this channel has occurred
15866  */
15867 #define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
15868 
15869 #define DMA_ERR_ERR27_MASK                       (0x8000000U)
15870 #define DMA_ERR_ERR27_SHIFT                      (27U)
15871 /*! ERR27 - Error In Channel 27
15872  *  0b0..No error in this channel has occurred
15873  *  0b1..An error in this channel has occurred
15874  */
15875 #define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
15876 
15877 #define DMA_ERR_ERR28_MASK                       (0x10000000U)
15878 #define DMA_ERR_ERR28_SHIFT                      (28U)
15879 /*! ERR28 - Error In Channel 28
15880  *  0b0..No error in this channel has occurred
15881  *  0b1..An error in this channel has occurred
15882  */
15883 #define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
15884 
15885 #define DMA_ERR_ERR29_MASK                       (0x20000000U)
15886 #define DMA_ERR_ERR29_SHIFT                      (29U)
15887 /*! ERR29 - Error In Channel 29
15888  *  0b0..No error in this channel has occurred
15889  *  0b1..An error in this channel has occurred
15890  */
15891 #define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
15892 
15893 #define DMA_ERR_ERR30_MASK                       (0x40000000U)
15894 #define DMA_ERR_ERR30_SHIFT                      (30U)
15895 /*! ERR30 - Error In Channel 30
15896  *  0b0..No error in this channel has occurred
15897  *  0b1..An error in this channel has occurred
15898  */
15899 #define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
15900 
15901 #define DMA_ERR_ERR31_MASK                       (0x80000000U)
15902 #define DMA_ERR_ERR31_SHIFT                      (31U)
15903 /*! ERR31 - Error In Channel 31
15904  *  0b0..No error in this channel has occurred
15905  *  0b1..An error in this channel has occurred
15906  */
15907 #define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
15908 /*! @} */
15909 
15910 /*! @name HRS - Hardware Request Status */
15911 /*! @{ */
15912 
15913 #define DMA_HRS_HRS0_MASK                        (0x1U)
15914 #define DMA_HRS_HRS0_SHIFT                       (0U)
15915 /*! HRS0 - Hardware Request Status Channel 0
15916  *  0b0..A hardware service request for channel 0 is not present
15917  *  0b1..A hardware service request for channel 0 is present
15918  */
15919 #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
15920 
15921 #define DMA_HRS_HRS1_MASK                        (0x2U)
15922 #define DMA_HRS_HRS1_SHIFT                       (1U)
15923 /*! HRS1 - Hardware Request Status Channel 1
15924  *  0b0..A hardware service request for channel 1 is not present
15925  *  0b1..A hardware service request for channel 1 is present
15926  */
15927 #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
15928 
15929 #define DMA_HRS_HRS2_MASK                        (0x4U)
15930 #define DMA_HRS_HRS2_SHIFT                       (2U)
15931 /*! HRS2 - Hardware Request Status Channel 2
15932  *  0b0..A hardware service request for channel 2 is not present
15933  *  0b1..A hardware service request for channel 2 is present
15934  */
15935 #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
15936 
15937 #define DMA_HRS_HRS3_MASK                        (0x8U)
15938 #define DMA_HRS_HRS3_SHIFT                       (3U)
15939 /*! HRS3 - Hardware Request Status Channel 3
15940  *  0b0..A hardware service request for channel 3 is not present
15941  *  0b1..A hardware service request for channel 3 is present
15942  */
15943 #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
15944 
15945 #define DMA_HRS_HRS4_MASK                        (0x10U)
15946 #define DMA_HRS_HRS4_SHIFT                       (4U)
15947 /*! HRS4 - Hardware Request Status Channel 4
15948  *  0b0..A hardware service request for channel 4 is not present
15949  *  0b1..A hardware service request for channel 4 is present
15950  */
15951 #define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
15952 
15953 #define DMA_HRS_HRS5_MASK                        (0x20U)
15954 #define DMA_HRS_HRS5_SHIFT                       (5U)
15955 /*! HRS5 - Hardware Request Status Channel 5
15956  *  0b0..A hardware service request for channel 5 is not present
15957  *  0b1..A hardware service request for channel 5 is present
15958  */
15959 #define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
15960 
15961 #define DMA_HRS_HRS6_MASK                        (0x40U)
15962 #define DMA_HRS_HRS6_SHIFT                       (6U)
15963 /*! HRS6 - Hardware Request Status Channel 6
15964  *  0b0..A hardware service request for channel 6 is not present
15965  *  0b1..A hardware service request for channel 6 is present
15966  */
15967 #define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
15968 
15969 #define DMA_HRS_HRS7_MASK                        (0x80U)
15970 #define DMA_HRS_HRS7_SHIFT                       (7U)
15971 /*! HRS7 - Hardware Request Status Channel 7
15972  *  0b0..A hardware service request for channel 7 is not present
15973  *  0b1..A hardware service request for channel 7 is present
15974  */
15975 #define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
15976 
15977 #define DMA_HRS_HRS8_MASK                        (0x100U)
15978 #define DMA_HRS_HRS8_SHIFT                       (8U)
15979 /*! HRS8 - Hardware Request Status Channel 8
15980  *  0b0..A hardware service request for channel 8 is not present
15981  *  0b1..A hardware service request for channel 8 is present
15982  */
15983 #define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
15984 
15985 #define DMA_HRS_HRS9_MASK                        (0x200U)
15986 #define DMA_HRS_HRS9_SHIFT                       (9U)
15987 /*! HRS9 - Hardware Request Status Channel 9
15988  *  0b0..A hardware service request for channel 9 is not present
15989  *  0b1..A hardware service request for channel 9 is present
15990  */
15991 #define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
15992 
15993 #define DMA_HRS_HRS10_MASK                       (0x400U)
15994 #define DMA_HRS_HRS10_SHIFT                      (10U)
15995 /*! HRS10 - Hardware Request Status Channel 10
15996  *  0b0..A hardware service request for channel 10 is not present
15997  *  0b1..A hardware service request for channel 10 is present
15998  */
15999 #define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
16000 
16001 #define DMA_HRS_HRS11_MASK                       (0x800U)
16002 #define DMA_HRS_HRS11_SHIFT                      (11U)
16003 /*! HRS11 - Hardware Request Status Channel 11
16004  *  0b0..A hardware service request for channel 11 is not present
16005  *  0b1..A hardware service request for channel 11 is present
16006  */
16007 #define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
16008 
16009 #define DMA_HRS_HRS12_MASK                       (0x1000U)
16010 #define DMA_HRS_HRS12_SHIFT                      (12U)
16011 /*! HRS12 - Hardware Request Status Channel 12
16012  *  0b0..A hardware service request for channel 12 is not present
16013  *  0b1..A hardware service request for channel 12 is present
16014  */
16015 #define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
16016 
16017 #define DMA_HRS_HRS13_MASK                       (0x2000U)
16018 #define DMA_HRS_HRS13_SHIFT                      (13U)
16019 /*! HRS13 - Hardware Request Status Channel 13
16020  *  0b0..A hardware service request for channel 13 is not present
16021  *  0b1..A hardware service request for channel 13 is present
16022  */
16023 #define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
16024 
16025 #define DMA_HRS_HRS14_MASK                       (0x4000U)
16026 #define DMA_HRS_HRS14_SHIFT                      (14U)
16027 /*! HRS14 - Hardware Request Status Channel 14
16028  *  0b0..A hardware service request for channel 14 is not present
16029  *  0b1..A hardware service request for channel 14 is present
16030  */
16031 #define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
16032 
16033 #define DMA_HRS_HRS15_MASK                       (0x8000U)
16034 #define DMA_HRS_HRS15_SHIFT                      (15U)
16035 /*! HRS15 - Hardware Request Status Channel 15
16036  *  0b0..A hardware service request for channel 15 is not present
16037  *  0b1..A hardware service request for channel 15 is present
16038  */
16039 #define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
16040 
16041 #define DMA_HRS_HRS16_MASK                       (0x10000U)
16042 #define DMA_HRS_HRS16_SHIFT                      (16U)
16043 /*! HRS16 - Hardware Request Status Channel 16
16044  *  0b0..A hardware service request for channel 16 is not present
16045  *  0b1..A hardware service request for channel 16 is present
16046  */
16047 #define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
16048 
16049 #define DMA_HRS_HRS17_MASK                       (0x20000U)
16050 #define DMA_HRS_HRS17_SHIFT                      (17U)
16051 /*! HRS17 - Hardware Request Status Channel 17
16052  *  0b0..A hardware service request for channel 17 is not present
16053  *  0b1..A hardware service request for channel 17 is present
16054  */
16055 #define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
16056 
16057 #define DMA_HRS_HRS18_MASK                       (0x40000U)
16058 #define DMA_HRS_HRS18_SHIFT                      (18U)
16059 /*! HRS18 - Hardware Request Status Channel 18
16060  *  0b0..A hardware service request for channel 18 is not present
16061  *  0b1..A hardware service request for channel 18 is present
16062  */
16063 #define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
16064 
16065 #define DMA_HRS_HRS19_MASK                       (0x80000U)
16066 #define DMA_HRS_HRS19_SHIFT                      (19U)
16067 /*! HRS19 - Hardware Request Status Channel 19
16068  *  0b0..A hardware service request for channel 19 is not present
16069  *  0b1..A hardware service request for channel 19 is present
16070  */
16071 #define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
16072 
16073 #define DMA_HRS_HRS20_MASK                       (0x100000U)
16074 #define DMA_HRS_HRS20_SHIFT                      (20U)
16075 /*! HRS20 - Hardware Request Status Channel 20
16076  *  0b0..A hardware service request for channel 20 is not present
16077  *  0b1..A hardware service request for channel 20 is present
16078  */
16079 #define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
16080 
16081 #define DMA_HRS_HRS21_MASK                       (0x200000U)
16082 #define DMA_HRS_HRS21_SHIFT                      (21U)
16083 /*! HRS21 - Hardware Request Status Channel 21
16084  *  0b0..A hardware service request for channel 21 is not present
16085  *  0b1..A hardware service request for channel 21 is present
16086  */
16087 #define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
16088 
16089 #define DMA_HRS_HRS22_MASK                       (0x400000U)
16090 #define DMA_HRS_HRS22_SHIFT                      (22U)
16091 /*! HRS22 - Hardware Request Status Channel 22
16092  *  0b0..A hardware service request for channel 22 is not present
16093  *  0b1..A hardware service request for channel 22 is present
16094  */
16095 #define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
16096 
16097 #define DMA_HRS_HRS23_MASK                       (0x800000U)
16098 #define DMA_HRS_HRS23_SHIFT                      (23U)
16099 /*! HRS23 - Hardware Request Status Channel 23
16100  *  0b0..A hardware service request for channel 23 is not present
16101  *  0b1..A hardware service request for channel 23 is present
16102  */
16103 #define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
16104 
16105 #define DMA_HRS_HRS24_MASK                       (0x1000000U)
16106 #define DMA_HRS_HRS24_SHIFT                      (24U)
16107 /*! HRS24 - Hardware Request Status Channel 24
16108  *  0b0..A hardware service request for channel 24 is not present
16109  *  0b1..A hardware service request for channel 24 is present
16110  */
16111 #define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
16112 
16113 #define DMA_HRS_HRS25_MASK                       (0x2000000U)
16114 #define DMA_HRS_HRS25_SHIFT                      (25U)
16115 /*! HRS25 - Hardware Request Status Channel 25
16116  *  0b0..A hardware service request for channel 25 is not present
16117  *  0b1..A hardware service request for channel 25 is present
16118  */
16119 #define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
16120 
16121 #define DMA_HRS_HRS26_MASK                       (0x4000000U)
16122 #define DMA_HRS_HRS26_SHIFT                      (26U)
16123 /*! HRS26 - Hardware Request Status Channel 26
16124  *  0b0..A hardware service request for channel 26 is not present
16125  *  0b1..A hardware service request for channel 26 is present
16126  */
16127 #define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
16128 
16129 #define DMA_HRS_HRS27_MASK                       (0x8000000U)
16130 #define DMA_HRS_HRS27_SHIFT                      (27U)
16131 /*! HRS27 - Hardware Request Status Channel 27
16132  *  0b0..A hardware service request for channel 27 is not present
16133  *  0b1..A hardware service request for channel 27 is present
16134  */
16135 #define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
16136 
16137 #define DMA_HRS_HRS28_MASK                       (0x10000000U)
16138 #define DMA_HRS_HRS28_SHIFT                      (28U)
16139 /*! HRS28 - Hardware Request Status Channel 28
16140  *  0b0..A hardware service request for channel 28 is not present
16141  *  0b1..A hardware service request for channel 28 is present
16142  */
16143 #define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
16144 
16145 #define DMA_HRS_HRS29_MASK                       (0x20000000U)
16146 #define DMA_HRS_HRS29_SHIFT                      (29U)
16147 /*! HRS29 - Hardware Request Status Channel 29
16148  *  0b0..A hardware service request for channel 29 is not preset
16149  *  0b1..A hardware service request for channel 29 is present
16150  */
16151 #define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
16152 
16153 #define DMA_HRS_HRS30_MASK                       (0x40000000U)
16154 #define DMA_HRS_HRS30_SHIFT                      (30U)
16155 /*! HRS30 - Hardware Request Status Channel 30
16156  *  0b0..A hardware service request for channel 30 is not present
16157  *  0b1..A hardware service request for channel 30 is present
16158  */
16159 #define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
16160 
16161 #define DMA_HRS_HRS31_MASK                       (0x80000000U)
16162 #define DMA_HRS_HRS31_SHIFT                      (31U)
16163 /*! HRS31 - Hardware Request Status Channel 31
16164  *  0b0..A hardware service request for channel 31 is not present
16165  *  0b1..A hardware service request for channel 31 is present
16166  */
16167 #define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
16168 /*! @} */
16169 
16170 /*! @name EARS - Enable Asynchronous Request in Stop */
16171 /*! @{ */
16172 
16173 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
16174 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
16175 /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
16176  *  0b0..Disable asynchronous DMA request for channel 0
16177  *  0b1..Enable asynchronous DMA request for channel 0
16178  */
16179 #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
16180 
16181 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
16182 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
16183 /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
16184  *  0b0..Disable asynchronous DMA request for channel 1
16185  *  0b1..Enable asynchronous DMA request for channel 1
16186  */
16187 #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
16188 
16189 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
16190 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
16191 /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
16192  *  0b0..Disable asynchronous DMA request for channel 2
16193  *  0b1..Enable asynchronous DMA request for channel 2
16194  */
16195 #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
16196 
16197 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
16198 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
16199 /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
16200  *  0b0..Disable asynchronous DMA request for channel 3
16201  *  0b1..Enable asynchronous DMA request for channel 3
16202  */
16203 #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
16204 
16205 #define DMA_EARS_EDREQ_4_MASK                    (0x10U)
16206 #define DMA_EARS_EDREQ_4_SHIFT                   (4U)
16207 /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4.
16208  *  0b0..Disable asynchronous DMA request for channel 4
16209  *  0b1..Enable asynchronous DMA request for channel 4
16210  */
16211 #define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
16212 
16213 #define DMA_EARS_EDREQ_5_MASK                    (0x20U)
16214 #define DMA_EARS_EDREQ_5_SHIFT                   (5U)
16215 /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5.
16216  *  0b0..Disable asynchronous DMA request for channel 5
16217  *  0b1..Enable asynchronous DMA request for channel 5
16218  */
16219 #define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
16220 
16221 #define DMA_EARS_EDREQ_6_MASK                    (0x40U)
16222 #define DMA_EARS_EDREQ_6_SHIFT                   (6U)
16223 /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6.
16224  *  0b0..Disable asynchronous DMA request for channel 6
16225  *  0b1..Enable asynchronous DMA request for channel 6
16226  */
16227 #define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
16228 
16229 #define DMA_EARS_EDREQ_7_MASK                    (0x80U)
16230 #define DMA_EARS_EDREQ_7_SHIFT                   (7U)
16231 /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7.
16232  *  0b0..Disable asynchronous DMA request for channel 7
16233  *  0b1..Enable asynchronous DMA request for channel 7
16234  */
16235 #define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
16236 
16237 #define DMA_EARS_EDREQ_8_MASK                    (0x100U)
16238 #define DMA_EARS_EDREQ_8_SHIFT                   (8U)
16239 /*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8.
16240  *  0b0..Disable asynchronous DMA request for channel 8
16241  *  0b1..Enable asynchronous DMA request for channel 8
16242  */
16243 #define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
16244 
16245 #define DMA_EARS_EDREQ_9_MASK                    (0x200U)
16246 #define DMA_EARS_EDREQ_9_SHIFT                   (9U)
16247 /*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9.
16248  *  0b0..Disable asynchronous DMA request for channel 9
16249  *  0b1..Enable asynchronous DMA request for channel 9
16250  */
16251 #define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
16252 
16253 #define DMA_EARS_EDREQ_10_MASK                   (0x400U)
16254 #define DMA_EARS_EDREQ_10_SHIFT                  (10U)
16255 /*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10.
16256  *  0b0..Disable asynchronous DMA request for channel 10
16257  *  0b1..Enable asynchronous DMA request for channel 10
16258  */
16259 #define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
16260 
16261 #define DMA_EARS_EDREQ_11_MASK                   (0x800U)
16262 #define DMA_EARS_EDREQ_11_SHIFT                  (11U)
16263 /*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11.
16264  *  0b0..Disable asynchronous DMA request for channel 11
16265  *  0b1..Enable asynchronous DMA request for channel 11
16266  */
16267 #define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
16268 
16269 #define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
16270 #define DMA_EARS_EDREQ_12_SHIFT                  (12U)
16271 /*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12.
16272  *  0b0..Disable asynchronous DMA request for channel 12
16273  *  0b1..Enable asynchronous DMA request for channel 12
16274  */
16275 #define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
16276 
16277 #define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
16278 #define DMA_EARS_EDREQ_13_SHIFT                  (13U)
16279 /*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13.
16280  *  0b0..Disable asynchronous DMA request for channel 13
16281  *  0b1..Enable asynchronous DMA request for channel 13
16282  */
16283 #define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
16284 
16285 #define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
16286 #define DMA_EARS_EDREQ_14_SHIFT                  (14U)
16287 /*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14.
16288  *  0b0..Disable asynchronous DMA request for channel 14
16289  *  0b1..Enable asynchronous DMA request for channel 14
16290  */
16291 #define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
16292 
16293 #define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
16294 #define DMA_EARS_EDREQ_15_SHIFT                  (15U)
16295 /*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15.
16296  *  0b0..Disable asynchronous DMA request for channel 15
16297  *  0b1..Enable asynchronous DMA request for channel 15
16298  */
16299 #define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
16300 
16301 #define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
16302 #define DMA_EARS_EDREQ_16_SHIFT                  (16U)
16303 /*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16.
16304  *  0b0..Disable asynchronous DMA request for channel 16
16305  *  0b1..Enable asynchronous DMA request for channel 16
16306  */
16307 #define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
16308 
16309 #define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
16310 #define DMA_EARS_EDREQ_17_SHIFT                  (17U)
16311 /*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17.
16312  *  0b0..Disable asynchronous DMA request for channel 17
16313  *  0b1..Enable asynchronous DMA request for channel 17
16314  */
16315 #define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
16316 
16317 #define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
16318 #define DMA_EARS_EDREQ_18_SHIFT                  (18U)
16319 /*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18.
16320  *  0b0..Disable asynchronous DMA request for channel 18
16321  *  0b1..Enable asynchronous DMA request for channel 18
16322  */
16323 #define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
16324 
16325 #define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
16326 #define DMA_EARS_EDREQ_19_SHIFT                  (19U)
16327 /*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19.
16328  *  0b0..Disable asynchronous DMA request for channel 19
16329  *  0b1..Enable asynchronous DMA request for channel 19
16330  */
16331 #define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
16332 
16333 #define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
16334 #define DMA_EARS_EDREQ_20_SHIFT                  (20U)
16335 /*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20.
16336  *  0b0..Disable asynchronous DMA request for channel 20
16337  *  0b1..Enable asynchronous DMA request for channel 20
16338  */
16339 #define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
16340 
16341 #define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
16342 #define DMA_EARS_EDREQ_21_SHIFT                  (21U)
16343 /*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21.
16344  *  0b0..Disable asynchronous DMA request for channel 21
16345  *  0b1..Enable asynchronous DMA request for channel 21
16346  */
16347 #define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
16348 
16349 #define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
16350 #define DMA_EARS_EDREQ_22_SHIFT                  (22U)
16351 /*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22.
16352  *  0b0..Disable asynchronous DMA request for channel 22
16353  *  0b1..Enable asynchronous DMA request for channel 22
16354  */
16355 #define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
16356 
16357 #define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
16358 #define DMA_EARS_EDREQ_23_SHIFT                  (23U)
16359 /*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23.
16360  *  0b0..Disable asynchronous DMA request for channel 23
16361  *  0b1..Enable asynchronous DMA request for channel 23
16362  */
16363 #define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
16364 
16365 #define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
16366 #define DMA_EARS_EDREQ_24_SHIFT                  (24U)
16367 /*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24.
16368  *  0b0..Disable asynchronous DMA request for channel 24
16369  *  0b1..Enable asynchronous DMA request for channel 24
16370  */
16371 #define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
16372 
16373 #define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
16374 #define DMA_EARS_EDREQ_25_SHIFT                  (25U)
16375 /*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25.
16376  *  0b0..Disable asynchronous DMA request for channel 25
16377  *  0b1..Enable asynchronous DMA request for channel 25
16378  */
16379 #define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
16380 
16381 #define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
16382 #define DMA_EARS_EDREQ_26_SHIFT                  (26U)
16383 /*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26.
16384  *  0b0..Disable asynchronous DMA request for channel 26
16385  *  0b1..Enable asynchronous DMA request for channel 26
16386  */
16387 #define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
16388 
16389 #define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
16390 #define DMA_EARS_EDREQ_27_SHIFT                  (27U)
16391 /*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27.
16392  *  0b0..Disable asynchronous DMA request for channel 27
16393  *  0b1..Enable asynchronous DMA request for channel 27
16394  */
16395 #define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
16396 
16397 #define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
16398 #define DMA_EARS_EDREQ_28_SHIFT                  (28U)
16399 /*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28.
16400  *  0b0..Disable asynchronous DMA request for channel 28
16401  *  0b1..Enable asynchronous DMA request for channel 28
16402  */
16403 #define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
16404 
16405 #define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
16406 #define DMA_EARS_EDREQ_29_SHIFT                  (29U)
16407 /*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29.
16408  *  0b0..Disable asynchronous DMA request for channel 29
16409  *  0b1..Enable asynchronous DMA request for channel 29
16410  */
16411 #define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
16412 
16413 #define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
16414 #define DMA_EARS_EDREQ_30_SHIFT                  (30U)
16415 /*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30.
16416  *  0b0..Disable asynchronous DMA request for channel 30
16417  *  0b1..Enable asynchronous DMA request for channel 30
16418  */
16419 #define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
16420 
16421 #define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
16422 #define DMA_EARS_EDREQ_31_SHIFT                  (31U)
16423 /*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31.
16424  *  0b0..Disable asynchronous DMA request for channel 31
16425  *  0b1..Enable asynchronous DMA request for channel 31
16426  */
16427 #define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
16428 /*! @} */
16429 
16430 /*! @name DCHPRI3 - Channel Priority */
16431 /*! @{ */
16432 
16433 #define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
16434 #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
16435 /*! CHPRI - Channel n Arbitration Priority
16436  */
16437 #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
16438 
16439 #define DMA_DCHPRI3_GRPPRI_MASK                  (0x30U)
16440 #define DMA_DCHPRI3_GRPPRI_SHIFT                 (4U)
16441 /*! GRPPRI - Channel n Current Group Priority
16442  */
16443 #define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
16444 
16445 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
16446 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
16447 /*! DPA - Disable Preempt Ability. This field resets to 0.
16448  *  0b0..Channel n can suspend a lower priority channel
16449  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16450  */
16451 #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
16452 
16453 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
16454 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
16455 /*! ECP - Enable Channel Preemption. This field resets to 0.
16456  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16457  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16458  */
16459 #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
16460 /*! @} */
16461 
16462 /*! @name DCHPRI2 - Channel Priority */
16463 /*! @{ */
16464 
16465 #define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
16466 #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
16467 /*! CHPRI - Channel n Arbitration Priority
16468  */
16469 #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
16470 
16471 #define DMA_DCHPRI2_GRPPRI_MASK                  (0x30U)
16472 #define DMA_DCHPRI2_GRPPRI_SHIFT                 (4U)
16473 /*! GRPPRI - Channel n Current Group Priority
16474  */
16475 #define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
16476 
16477 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
16478 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
16479 /*! DPA - Disable Preempt Ability. This field resets to 0.
16480  *  0b0..Channel n can suspend a lower priority channel
16481  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16482  */
16483 #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
16484 
16485 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
16486 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
16487 /*! ECP - Enable Channel Preemption. This field resets to 0.
16488  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16489  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16490  */
16491 #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
16492 /*! @} */
16493 
16494 /*! @name DCHPRI1 - Channel Priority */
16495 /*! @{ */
16496 
16497 #define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
16498 #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
16499 /*! CHPRI - Channel n Arbitration Priority
16500  */
16501 #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
16502 
16503 #define DMA_DCHPRI1_GRPPRI_MASK                  (0x30U)
16504 #define DMA_DCHPRI1_GRPPRI_SHIFT                 (4U)
16505 /*! GRPPRI - Channel n Current Group Priority
16506  */
16507 #define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
16508 
16509 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
16510 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
16511 /*! DPA - Disable Preempt Ability. This field resets to 0.
16512  *  0b0..Channel n can suspend a lower priority channel
16513  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16514  */
16515 #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
16516 
16517 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
16518 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
16519 /*! ECP - Enable Channel Preemption. This field resets to 0.
16520  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16521  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16522  */
16523 #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
16524 /*! @} */
16525 
16526 /*! @name DCHPRI0 - Channel Priority */
16527 /*! @{ */
16528 
16529 #define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
16530 #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
16531 /*! CHPRI - Channel n Arbitration Priority
16532  */
16533 #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
16534 
16535 #define DMA_DCHPRI0_GRPPRI_MASK                  (0x30U)
16536 #define DMA_DCHPRI0_GRPPRI_SHIFT                 (4U)
16537 /*! GRPPRI - Channel n Current Group Priority
16538  */
16539 #define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
16540 
16541 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
16542 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
16543 /*! DPA - Disable Preempt Ability. This field resets to 0.
16544  *  0b0..Channel n can suspend a lower priority channel
16545  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16546  */
16547 #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
16548 
16549 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
16550 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
16551 /*! ECP - Enable Channel Preemption. This field resets to 0.
16552  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16553  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16554  */
16555 #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
16556 /*! @} */
16557 
16558 /*! @name DCHPRI7 - Channel Priority */
16559 /*! @{ */
16560 
16561 #define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
16562 #define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
16563 /*! CHPRI - Channel n Arbitration Priority
16564  */
16565 #define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
16566 
16567 #define DMA_DCHPRI7_GRPPRI_MASK                  (0x30U)
16568 #define DMA_DCHPRI7_GRPPRI_SHIFT                 (4U)
16569 /*! GRPPRI - Channel n Current Group Priority
16570  */
16571 #define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
16572 
16573 #define DMA_DCHPRI7_DPA_MASK                     (0x40U)
16574 #define DMA_DCHPRI7_DPA_SHIFT                    (6U)
16575 /*! DPA - Disable Preempt Ability. This field resets to 0.
16576  *  0b0..Channel n can suspend a lower priority channel
16577  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16578  */
16579 #define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
16580 
16581 #define DMA_DCHPRI7_ECP_MASK                     (0x80U)
16582 #define DMA_DCHPRI7_ECP_SHIFT                    (7U)
16583 /*! ECP - Enable Channel Preemption. This field resets to 0.
16584  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16585  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16586  */
16587 #define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
16588 /*! @} */
16589 
16590 /*! @name DCHPRI6 - Channel Priority */
16591 /*! @{ */
16592 
16593 #define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
16594 #define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
16595 /*! CHPRI - Channel n Arbitration Priority
16596  */
16597 #define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
16598 
16599 #define DMA_DCHPRI6_GRPPRI_MASK                  (0x30U)
16600 #define DMA_DCHPRI6_GRPPRI_SHIFT                 (4U)
16601 /*! GRPPRI - Channel n Current Group Priority
16602  */
16603 #define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
16604 
16605 #define DMA_DCHPRI6_DPA_MASK                     (0x40U)
16606 #define DMA_DCHPRI6_DPA_SHIFT                    (6U)
16607 /*! DPA - Disable Preempt Ability. This field resets to 0.
16608  *  0b0..Channel n can suspend a lower priority channel
16609  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16610  */
16611 #define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
16612 
16613 #define DMA_DCHPRI6_ECP_MASK                     (0x80U)
16614 #define DMA_DCHPRI6_ECP_SHIFT                    (7U)
16615 /*! ECP - Enable Channel Preemption. This field resets to 0.
16616  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16617  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16618  */
16619 #define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
16620 /*! @} */
16621 
16622 /*! @name DCHPRI5 - Channel Priority */
16623 /*! @{ */
16624 
16625 #define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
16626 #define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
16627 /*! CHPRI - Channel n Arbitration Priority
16628  */
16629 #define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
16630 
16631 #define DMA_DCHPRI5_GRPPRI_MASK                  (0x30U)
16632 #define DMA_DCHPRI5_GRPPRI_SHIFT                 (4U)
16633 /*! GRPPRI - Channel n Current Group Priority
16634  */
16635 #define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
16636 
16637 #define DMA_DCHPRI5_DPA_MASK                     (0x40U)
16638 #define DMA_DCHPRI5_DPA_SHIFT                    (6U)
16639 /*! DPA - Disable Preempt Ability. This field resets to 0.
16640  *  0b0..Channel n can suspend a lower priority channel
16641  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16642  */
16643 #define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
16644 
16645 #define DMA_DCHPRI5_ECP_MASK                     (0x80U)
16646 #define DMA_DCHPRI5_ECP_SHIFT                    (7U)
16647 /*! ECP - Enable Channel Preemption. This field resets to 0.
16648  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16649  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16650  */
16651 #define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
16652 /*! @} */
16653 
16654 /*! @name DCHPRI4 - Channel Priority */
16655 /*! @{ */
16656 
16657 #define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
16658 #define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
16659 /*! CHPRI - Channel n Arbitration Priority
16660  */
16661 #define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
16662 
16663 #define DMA_DCHPRI4_GRPPRI_MASK                  (0x30U)
16664 #define DMA_DCHPRI4_GRPPRI_SHIFT                 (4U)
16665 /*! GRPPRI - Channel n Current Group Priority
16666  */
16667 #define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
16668 
16669 #define DMA_DCHPRI4_DPA_MASK                     (0x40U)
16670 #define DMA_DCHPRI4_DPA_SHIFT                    (6U)
16671 /*! DPA - Disable Preempt Ability. This field resets to 0.
16672  *  0b0..Channel n can suspend a lower priority channel
16673  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16674  */
16675 #define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
16676 
16677 #define DMA_DCHPRI4_ECP_MASK                     (0x80U)
16678 #define DMA_DCHPRI4_ECP_SHIFT                    (7U)
16679 /*! ECP - Enable Channel Preemption. This field resets to 0.
16680  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16681  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16682  */
16683 #define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
16684 /*! @} */
16685 
16686 /*! @name DCHPRI11 - Channel Priority */
16687 /*! @{ */
16688 
16689 #define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
16690 #define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
16691 /*! CHPRI - Channel n Arbitration Priority
16692  */
16693 #define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
16694 
16695 #define DMA_DCHPRI11_GRPPRI_MASK                 (0x30U)
16696 #define DMA_DCHPRI11_GRPPRI_SHIFT                (4U)
16697 /*! GRPPRI - Channel n Current Group Priority
16698  */
16699 #define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
16700 
16701 #define DMA_DCHPRI11_DPA_MASK                    (0x40U)
16702 #define DMA_DCHPRI11_DPA_SHIFT                   (6U)
16703 /*! DPA - Disable Preempt Ability. This field resets to 0.
16704  *  0b0..Channel n can suspend a lower priority channel
16705  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16706  */
16707 #define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
16708 
16709 #define DMA_DCHPRI11_ECP_MASK                    (0x80U)
16710 #define DMA_DCHPRI11_ECP_SHIFT                   (7U)
16711 /*! ECP - Enable Channel Preemption. This field resets to 0.
16712  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16713  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16714  */
16715 #define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
16716 /*! @} */
16717 
16718 /*! @name DCHPRI10 - Channel Priority */
16719 /*! @{ */
16720 
16721 #define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
16722 #define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
16723 /*! CHPRI - Channel n Arbitration Priority
16724  */
16725 #define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
16726 
16727 #define DMA_DCHPRI10_GRPPRI_MASK                 (0x30U)
16728 #define DMA_DCHPRI10_GRPPRI_SHIFT                (4U)
16729 /*! GRPPRI - Channel n Current Group Priority
16730  */
16731 #define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
16732 
16733 #define DMA_DCHPRI10_DPA_MASK                    (0x40U)
16734 #define DMA_DCHPRI10_DPA_SHIFT                   (6U)
16735 /*! DPA - Disable Preempt Ability. This field resets to 0.
16736  *  0b0..Channel n can suspend a lower priority channel
16737  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16738  */
16739 #define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
16740 
16741 #define DMA_DCHPRI10_ECP_MASK                    (0x80U)
16742 #define DMA_DCHPRI10_ECP_SHIFT                   (7U)
16743 /*! ECP - Enable Channel Preemption. This field resets to 0.
16744  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16745  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16746  */
16747 #define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
16748 /*! @} */
16749 
16750 /*! @name DCHPRI9 - Channel Priority */
16751 /*! @{ */
16752 
16753 #define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
16754 #define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
16755 /*! CHPRI - Channel n Arbitration Priority
16756  */
16757 #define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
16758 
16759 #define DMA_DCHPRI9_GRPPRI_MASK                  (0x30U)
16760 #define DMA_DCHPRI9_GRPPRI_SHIFT                 (4U)
16761 /*! GRPPRI - Channel n Current Group Priority
16762  */
16763 #define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
16764 
16765 #define DMA_DCHPRI9_DPA_MASK                     (0x40U)
16766 #define DMA_DCHPRI9_DPA_SHIFT                    (6U)
16767 /*! DPA - Disable Preempt Ability. This field resets to 0.
16768  *  0b0..Channel n can suspend a lower priority channel
16769  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16770  */
16771 #define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
16772 
16773 #define DMA_DCHPRI9_ECP_MASK                     (0x80U)
16774 #define DMA_DCHPRI9_ECP_SHIFT                    (7U)
16775 /*! ECP - Enable Channel Preemption. This field resets to 0.
16776  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16777  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16778  */
16779 #define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
16780 /*! @} */
16781 
16782 /*! @name DCHPRI8 - Channel Priority */
16783 /*! @{ */
16784 
16785 #define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
16786 #define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
16787 /*! CHPRI - Channel n Arbitration Priority
16788  */
16789 #define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
16790 
16791 #define DMA_DCHPRI8_GRPPRI_MASK                  (0x30U)
16792 #define DMA_DCHPRI8_GRPPRI_SHIFT                 (4U)
16793 /*! GRPPRI - Channel n Current Group Priority
16794  */
16795 #define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
16796 
16797 #define DMA_DCHPRI8_DPA_MASK                     (0x40U)
16798 #define DMA_DCHPRI8_DPA_SHIFT                    (6U)
16799 /*! DPA - Disable Preempt Ability. This field resets to 0.
16800  *  0b0..Channel n can suspend a lower priority channel
16801  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16802  */
16803 #define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
16804 
16805 #define DMA_DCHPRI8_ECP_MASK                     (0x80U)
16806 #define DMA_DCHPRI8_ECP_SHIFT                    (7U)
16807 /*! ECP - Enable Channel Preemption. This field resets to 0.
16808  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16809  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16810  */
16811 #define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
16812 /*! @} */
16813 
16814 /*! @name DCHPRI15 - Channel Priority */
16815 /*! @{ */
16816 
16817 #define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
16818 #define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
16819 /*! CHPRI - Channel n Arbitration Priority
16820  */
16821 #define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
16822 
16823 #define DMA_DCHPRI15_GRPPRI_MASK                 (0x30U)
16824 #define DMA_DCHPRI15_GRPPRI_SHIFT                (4U)
16825 /*! GRPPRI - Channel n Current Group Priority
16826  */
16827 #define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
16828 
16829 #define DMA_DCHPRI15_DPA_MASK                    (0x40U)
16830 #define DMA_DCHPRI15_DPA_SHIFT                   (6U)
16831 /*! DPA - Disable Preempt Ability. This field resets to 0.
16832  *  0b0..Channel n can suspend a lower priority channel
16833  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16834  */
16835 #define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
16836 
16837 #define DMA_DCHPRI15_ECP_MASK                    (0x80U)
16838 #define DMA_DCHPRI15_ECP_SHIFT                   (7U)
16839 /*! ECP - Enable Channel Preemption. This field resets to 0.
16840  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16841  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16842  */
16843 #define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
16844 /*! @} */
16845 
16846 /*! @name DCHPRI14 - Channel Priority */
16847 /*! @{ */
16848 
16849 #define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
16850 #define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
16851 /*! CHPRI - Channel n Arbitration Priority
16852  */
16853 #define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
16854 
16855 #define DMA_DCHPRI14_GRPPRI_MASK                 (0x30U)
16856 #define DMA_DCHPRI14_GRPPRI_SHIFT                (4U)
16857 /*! GRPPRI - Channel n Current Group Priority
16858  */
16859 #define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
16860 
16861 #define DMA_DCHPRI14_DPA_MASK                    (0x40U)
16862 #define DMA_DCHPRI14_DPA_SHIFT                   (6U)
16863 /*! DPA - Disable Preempt Ability. This field resets to 0.
16864  *  0b0..Channel n can suspend a lower priority channel
16865  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16866  */
16867 #define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
16868 
16869 #define DMA_DCHPRI14_ECP_MASK                    (0x80U)
16870 #define DMA_DCHPRI14_ECP_SHIFT                   (7U)
16871 /*! ECP - Enable Channel Preemption. This field resets to 0.
16872  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16873  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16874  */
16875 #define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
16876 /*! @} */
16877 
16878 /*! @name DCHPRI13 - Channel Priority */
16879 /*! @{ */
16880 
16881 #define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
16882 #define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
16883 /*! CHPRI - Channel n Arbitration Priority
16884  */
16885 #define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
16886 
16887 #define DMA_DCHPRI13_GRPPRI_MASK                 (0x30U)
16888 #define DMA_DCHPRI13_GRPPRI_SHIFT                (4U)
16889 /*! GRPPRI - Channel n Current Group Priority
16890  */
16891 #define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
16892 
16893 #define DMA_DCHPRI13_DPA_MASK                    (0x40U)
16894 #define DMA_DCHPRI13_DPA_SHIFT                   (6U)
16895 /*! DPA - Disable Preempt Ability. This field resets to 0.
16896  *  0b0..Channel n can suspend a lower priority channel
16897  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16898  */
16899 #define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
16900 
16901 #define DMA_DCHPRI13_ECP_MASK                    (0x80U)
16902 #define DMA_DCHPRI13_ECP_SHIFT                   (7U)
16903 /*! ECP - Enable Channel Preemption. This field resets to 0.
16904  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16905  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16906  */
16907 #define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
16908 /*! @} */
16909 
16910 /*! @name DCHPRI12 - Channel Priority */
16911 /*! @{ */
16912 
16913 #define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
16914 #define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
16915 /*! CHPRI - Channel n Arbitration Priority
16916  */
16917 #define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
16918 
16919 #define DMA_DCHPRI12_GRPPRI_MASK                 (0x30U)
16920 #define DMA_DCHPRI12_GRPPRI_SHIFT                (4U)
16921 /*! GRPPRI - Channel n Current Group Priority
16922  */
16923 #define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
16924 
16925 #define DMA_DCHPRI12_DPA_MASK                    (0x40U)
16926 #define DMA_DCHPRI12_DPA_SHIFT                   (6U)
16927 /*! DPA - Disable Preempt Ability. This field resets to 0.
16928  *  0b0..Channel n can suspend a lower priority channel
16929  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16930  */
16931 #define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
16932 
16933 #define DMA_DCHPRI12_ECP_MASK                    (0x80U)
16934 #define DMA_DCHPRI12_ECP_SHIFT                   (7U)
16935 /*! ECP - Enable Channel Preemption. This field resets to 0.
16936  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16937  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16938  */
16939 #define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
16940 /*! @} */
16941 
16942 /*! @name DCHPRI19 - Channel Priority */
16943 /*! @{ */
16944 
16945 #define DMA_DCHPRI19_CHPRI_MASK                  (0xFU)
16946 #define DMA_DCHPRI19_CHPRI_SHIFT                 (0U)
16947 /*! CHPRI - Channel n Arbitration Priority
16948  */
16949 #define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
16950 
16951 #define DMA_DCHPRI19_GRPPRI_MASK                 (0x30U)
16952 #define DMA_DCHPRI19_GRPPRI_SHIFT                (4U)
16953 /*! GRPPRI - Channel n Current Group Priority
16954  */
16955 #define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
16956 
16957 #define DMA_DCHPRI19_DPA_MASK                    (0x40U)
16958 #define DMA_DCHPRI19_DPA_SHIFT                   (6U)
16959 /*! DPA - Disable Preempt Ability. This field resets to 0.
16960  *  0b0..Channel n can suspend a lower priority channel
16961  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16962  */
16963 #define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
16964 
16965 #define DMA_DCHPRI19_ECP_MASK                    (0x80U)
16966 #define DMA_DCHPRI19_ECP_SHIFT                   (7U)
16967 /*! ECP - Enable Channel Preemption. This field resets to 0.
16968  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
16969  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
16970  */
16971 #define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
16972 /*! @} */
16973 
16974 /*! @name DCHPRI18 - Channel Priority */
16975 /*! @{ */
16976 
16977 #define DMA_DCHPRI18_CHPRI_MASK                  (0xFU)
16978 #define DMA_DCHPRI18_CHPRI_SHIFT                 (0U)
16979 /*! CHPRI - Channel n Arbitration Priority
16980  */
16981 #define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
16982 
16983 #define DMA_DCHPRI18_GRPPRI_MASK                 (0x30U)
16984 #define DMA_DCHPRI18_GRPPRI_SHIFT                (4U)
16985 /*! GRPPRI - Channel n Current Group Priority
16986  */
16987 #define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
16988 
16989 #define DMA_DCHPRI18_DPA_MASK                    (0x40U)
16990 #define DMA_DCHPRI18_DPA_SHIFT                   (6U)
16991 /*! DPA - Disable Preempt Ability. This field resets to 0.
16992  *  0b0..Channel n can suspend a lower priority channel
16993  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
16994  */
16995 #define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
16996 
16997 #define DMA_DCHPRI18_ECP_MASK                    (0x80U)
16998 #define DMA_DCHPRI18_ECP_SHIFT                   (7U)
16999 /*! ECP - Enable Channel Preemption. This field resets to 0.
17000  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17001  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17002  */
17003 #define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
17004 /*! @} */
17005 
17006 /*! @name DCHPRI17 - Channel Priority */
17007 /*! @{ */
17008 
17009 #define DMA_DCHPRI17_CHPRI_MASK                  (0xFU)
17010 #define DMA_DCHPRI17_CHPRI_SHIFT                 (0U)
17011 /*! CHPRI - Channel n Arbitration Priority
17012  */
17013 #define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
17014 
17015 #define DMA_DCHPRI17_GRPPRI_MASK                 (0x30U)
17016 #define DMA_DCHPRI17_GRPPRI_SHIFT                (4U)
17017 /*! GRPPRI - Channel n Current Group Priority
17018  */
17019 #define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
17020 
17021 #define DMA_DCHPRI17_DPA_MASK                    (0x40U)
17022 #define DMA_DCHPRI17_DPA_SHIFT                   (6U)
17023 /*! DPA - Disable Preempt Ability. This field resets to 0.
17024  *  0b0..Channel n can suspend a lower priority channel
17025  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17026  */
17027 #define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
17028 
17029 #define DMA_DCHPRI17_ECP_MASK                    (0x80U)
17030 #define DMA_DCHPRI17_ECP_SHIFT                   (7U)
17031 /*! ECP - Enable Channel Preemption. This field resets to 0.
17032  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17033  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17034  */
17035 #define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
17036 /*! @} */
17037 
17038 /*! @name DCHPRI16 - Channel Priority */
17039 /*! @{ */
17040 
17041 #define DMA_DCHPRI16_CHPRI_MASK                  (0xFU)
17042 #define DMA_DCHPRI16_CHPRI_SHIFT                 (0U)
17043 /*! CHPRI - Channel n Arbitration Priority
17044  */
17045 #define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
17046 
17047 #define DMA_DCHPRI16_GRPPRI_MASK                 (0x30U)
17048 #define DMA_DCHPRI16_GRPPRI_SHIFT                (4U)
17049 /*! GRPPRI - Channel n Current Group Priority
17050  */
17051 #define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
17052 
17053 #define DMA_DCHPRI16_DPA_MASK                    (0x40U)
17054 #define DMA_DCHPRI16_DPA_SHIFT                   (6U)
17055 /*! DPA - Disable Preempt Ability. This field resets to 0.
17056  *  0b0..Channel n can suspend a lower priority channel
17057  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17058  */
17059 #define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
17060 
17061 #define DMA_DCHPRI16_ECP_MASK                    (0x80U)
17062 #define DMA_DCHPRI16_ECP_SHIFT                   (7U)
17063 /*! ECP - Enable Channel Preemption. This field resets to 0.
17064  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17065  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17066  */
17067 #define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
17068 /*! @} */
17069 
17070 /*! @name DCHPRI23 - Channel Priority */
17071 /*! @{ */
17072 
17073 #define DMA_DCHPRI23_CHPRI_MASK                  (0xFU)
17074 #define DMA_DCHPRI23_CHPRI_SHIFT                 (0U)
17075 /*! CHPRI - Channel n Arbitration Priority
17076  */
17077 #define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
17078 
17079 #define DMA_DCHPRI23_GRPPRI_MASK                 (0x30U)
17080 #define DMA_DCHPRI23_GRPPRI_SHIFT                (4U)
17081 /*! GRPPRI - Channel n Current Group Priority
17082  */
17083 #define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
17084 
17085 #define DMA_DCHPRI23_DPA_MASK                    (0x40U)
17086 #define DMA_DCHPRI23_DPA_SHIFT                   (6U)
17087 /*! DPA - Disable Preempt Ability. This field resets to 0.
17088  *  0b0..Channel n can suspend a lower priority channel
17089  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17090  */
17091 #define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
17092 
17093 #define DMA_DCHPRI23_ECP_MASK                    (0x80U)
17094 #define DMA_DCHPRI23_ECP_SHIFT                   (7U)
17095 /*! ECP - Enable Channel Preemption. This field resets to 0.
17096  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17097  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17098  */
17099 #define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
17100 /*! @} */
17101 
17102 /*! @name DCHPRI22 - Channel Priority */
17103 /*! @{ */
17104 
17105 #define DMA_DCHPRI22_CHPRI_MASK                  (0xFU)
17106 #define DMA_DCHPRI22_CHPRI_SHIFT                 (0U)
17107 /*! CHPRI - Channel n Arbitration Priority
17108  */
17109 #define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
17110 
17111 #define DMA_DCHPRI22_GRPPRI_MASK                 (0x30U)
17112 #define DMA_DCHPRI22_GRPPRI_SHIFT                (4U)
17113 /*! GRPPRI - Channel n Current Group Priority
17114  */
17115 #define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
17116 
17117 #define DMA_DCHPRI22_DPA_MASK                    (0x40U)
17118 #define DMA_DCHPRI22_DPA_SHIFT                   (6U)
17119 /*! DPA - Disable Preempt Ability. This field resets to 0.
17120  *  0b0..Channel n can suspend a lower priority channel
17121  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17122  */
17123 #define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
17124 
17125 #define DMA_DCHPRI22_ECP_MASK                    (0x80U)
17126 #define DMA_DCHPRI22_ECP_SHIFT                   (7U)
17127 /*! ECP - Enable Channel Preemption. This field resets to 0.
17128  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17129  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17130  */
17131 #define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
17132 /*! @} */
17133 
17134 /*! @name DCHPRI21 - Channel Priority */
17135 /*! @{ */
17136 
17137 #define DMA_DCHPRI21_CHPRI_MASK                  (0xFU)
17138 #define DMA_DCHPRI21_CHPRI_SHIFT                 (0U)
17139 /*! CHPRI - Channel n Arbitration Priority
17140  */
17141 #define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
17142 
17143 #define DMA_DCHPRI21_GRPPRI_MASK                 (0x30U)
17144 #define DMA_DCHPRI21_GRPPRI_SHIFT                (4U)
17145 /*! GRPPRI - Channel n Current Group Priority
17146  */
17147 #define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
17148 
17149 #define DMA_DCHPRI21_DPA_MASK                    (0x40U)
17150 #define DMA_DCHPRI21_DPA_SHIFT                   (6U)
17151 /*! DPA - Disable Preempt Ability. This field resets to 0.
17152  *  0b0..Channel n can suspend a lower priority channel
17153  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17154  */
17155 #define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
17156 
17157 #define DMA_DCHPRI21_ECP_MASK                    (0x80U)
17158 #define DMA_DCHPRI21_ECP_SHIFT                   (7U)
17159 /*! ECP - Enable Channel Preemption. This field resets to 0.
17160  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17161  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17162  */
17163 #define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
17164 /*! @} */
17165 
17166 /*! @name DCHPRI20 - Channel Priority */
17167 /*! @{ */
17168 
17169 #define DMA_DCHPRI20_CHPRI_MASK                  (0xFU)
17170 #define DMA_DCHPRI20_CHPRI_SHIFT                 (0U)
17171 /*! CHPRI - Channel n Arbitration Priority
17172  */
17173 #define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
17174 
17175 #define DMA_DCHPRI20_GRPPRI_MASK                 (0x30U)
17176 #define DMA_DCHPRI20_GRPPRI_SHIFT                (4U)
17177 /*! GRPPRI - Channel n Current Group Priority
17178  */
17179 #define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
17180 
17181 #define DMA_DCHPRI20_DPA_MASK                    (0x40U)
17182 #define DMA_DCHPRI20_DPA_SHIFT                   (6U)
17183 /*! DPA - Disable Preempt Ability. This field resets to 0.
17184  *  0b0..Channel n can suspend a lower priority channel
17185  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17186  */
17187 #define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
17188 
17189 #define DMA_DCHPRI20_ECP_MASK                    (0x80U)
17190 #define DMA_DCHPRI20_ECP_SHIFT                   (7U)
17191 /*! ECP - Enable Channel Preemption. This field resets to 0.
17192  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17193  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17194  */
17195 #define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
17196 /*! @} */
17197 
17198 /*! @name DCHPRI27 - Channel Priority */
17199 /*! @{ */
17200 
17201 #define DMA_DCHPRI27_CHPRI_MASK                  (0xFU)
17202 #define DMA_DCHPRI27_CHPRI_SHIFT                 (0U)
17203 /*! CHPRI - Channel n Arbitration Priority
17204  */
17205 #define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
17206 
17207 #define DMA_DCHPRI27_GRPPRI_MASK                 (0x30U)
17208 #define DMA_DCHPRI27_GRPPRI_SHIFT                (4U)
17209 /*! GRPPRI - Channel n Current Group Priority
17210  */
17211 #define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
17212 
17213 #define DMA_DCHPRI27_DPA_MASK                    (0x40U)
17214 #define DMA_DCHPRI27_DPA_SHIFT                   (6U)
17215 /*! DPA - Disable Preempt Ability. This field resets to 0.
17216  *  0b0..Channel n can suspend a lower priority channel
17217  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17218  */
17219 #define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
17220 
17221 #define DMA_DCHPRI27_ECP_MASK                    (0x80U)
17222 #define DMA_DCHPRI27_ECP_SHIFT                   (7U)
17223 /*! ECP - Enable Channel Preemption. This field resets to 0.
17224  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17225  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17226  */
17227 #define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
17228 /*! @} */
17229 
17230 /*! @name DCHPRI26 - Channel Priority */
17231 /*! @{ */
17232 
17233 #define DMA_DCHPRI26_CHPRI_MASK                  (0xFU)
17234 #define DMA_DCHPRI26_CHPRI_SHIFT                 (0U)
17235 /*! CHPRI - Channel n Arbitration Priority
17236  */
17237 #define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
17238 
17239 #define DMA_DCHPRI26_GRPPRI_MASK                 (0x30U)
17240 #define DMA_DCHPRI26_GRPPRI_SHIFT                (4U)
17241 /*! GRPPRI - Channel n Current Group Priority
17242  */
17243 #define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
17244 
17245 #define DMA_DCHPRI26_DPA_MASK                    (0x40U)
17246 #define DMA_DCHPRI26_DPA_SHIFT                   (6U)
17247 /*! DPA - Disable Preempt Ability. This field resets to 0.
17248  *  0b0..Channel n can suspend a lower priority channel
17249  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17250  */
17251 #define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
17252 
17253 #define DMA_DCHPRI26_ECP_MASK                    (0x80U)
17254 #define DMA_DCHPRI26_ECP_SHIFT                   (7U)
17255 /*! ECP - Enable Channel Preemption. This field resets to 0.
17256  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17257  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17258  */
17259 #define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
17260 /*! @} */
17261 
17262 /*! @name DCHPRI25 - Channel Priority */
17263 /*! @{ */
17264 
17265 #define DMA_DCHPRI25_CHPRI_MASK                  (0xFU)
17266 #define DMA_DCHPRI25_CHPRI_SHIFT                 (0U)
17267 /*! CHPRI - Channel n Arbitration Priority
17268  */
17269 #define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
17270 
17271 #define DMA_DCHPRI25_GRPPRI_MASK                 (0x30U)
17272 #define DMA_DCHPRI25_GRPPRI_SHIFT                (4U)
17273 /*! GRPPRI - Channel n Current Group Priority
17274  */
17275 #define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
17276 
17277 #define DMA_DCHPRI25_DPA_MASK                    (0x40U)
17278 #define DMA_DCHPRI25_DPA_SHIFT                   (6U)
17279 /*! DPA - Disable Preempt Ability. This field resets to 0.
17280  *  0b0..Channel n can suspend a lower priority channel
17281  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17282  */
17283 #define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
17284 
17285 #define DMA_DCHPRI25_ECP_MASK                    (0x80U)
17286 #define DMA_DCHPRI25_ECP_SHIFT                   (7U)
17287 /*! ECP - Enable Channel Preemption. This field resets to 0.
17288  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17289  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17290  */
17291 #define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
17292 /*! @} */
17293 
17294 /*! @name DCHPRI24 - Channel Priority */
17295 /*! @{ */
17296 
17297 #define DMA_DCHPRI24_CHPRI_MASK                  (0xFU)
17298 #define DMA_DCHPRI24_CHPRI_SHIFT                 (0U)
17299 /*! CHPRI - Channel n Arbitration Priority
17300  */
17301 #define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
17302 
17303 #define DMA_DCHPRI24_GRPPRI_MASK                 (0x30U)
17304 #define DMA_DCHPRI24_GRPPRI_SHIFT                (4U)
17305 /*! GRPPRI - Channel n Current Group Priority
17306  */
17307 #define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
17308 
17309 #define DMA_DCHPRI24_DPA_MASK                    (0x40U)
17310 #define DMA_DCHPRI24_DPA_SHIFT                   (6U)
17311 /*! DPA - Disable Preempt Ability. This field resets to 0.
17312  *  0b0..Channel n can suspend a lower priority channel
17313  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17314  */
17315 #define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
17316 
17317 #define DMA_DCHPRI24_ECP_MASK                    (0x80U)
17318 #define DMA_DCHPRI24_ECP_SHIFT                   (7U)
17319 /*! ECP - Enable Channel Preemption. This field resets to 0.
17320  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17321  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17322  */
17323 #define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
17324 /*! @} */
17325 
17326 /*! @name DCHPRI31 - Channel Priority */
17327 /*! @{ */
17328 
17329 #define DMA_DCHPRI31_CHPRI_MASK                  (0xFU)
17330 #define DMA_DCHPRI31_CHPRI_SHIFT                 (0U)
17331 /*! CHPRI - Channel n Arbitration Priority
17332  */
17333 #define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
17334 
17335 #define DMA_DCHPRI31_GRPPRI_MASK                 (0x30U)
17336 #define DMA_DCHPRI31_GRPPRI_SHIFT                (4U)
17337 /*! GRPPRI - Channel n Current Group Priority
17338  */
17339 #define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
17340 
17341 #define DMA_DCHPRI31_DPA_MASK                    (0x40U)
17342 #define DMA_DCHPRI31_DPA_SHIFT                   (6U)
17343 /*! DPA - Disable Preempt Ability. This field resets to 0.
17344  *  0b0..Channel n can suspend a lower priority channel
17345  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17346  */
17347 #define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
17348 
17349 #define DMA_DCHPRI31_ECP_MASK                    (0x80U)
17350 #define DMA_DCHPRI31_ECP_SHIFT                   (7U)
17351 /*! ECP - Enable Channel Preemption. This field resets to 0.
17352  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17353  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17354  */
17355 #define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
17356 /*! @} */
17357 
17358 /*! @name DCHPRI30 - Channel Priority */
17359 /*! @{ */
17360 
17361 #define DMA_DCHPRI30_CHPRI_MASK                  (0xFU)
17362 #define DMA_DCHPRI30_CHPRI_SHIFT                 (0U)
17363 /*! CHPRI - Channel n Arbitration Priority
17364  */
17365 #define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
17366 
17367 #define DMA_DCHPRI30_GRPPRI_MASK                 (0x30U)
17368 #define DMA_DCHPRI30_GRPPRI_SHIFT                (4U)
17369 /*! GRPPRI - Channel n Current Group Priority
17370  */
17371 #define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
17372 
17373 #define DMA_DCHPRI30_DPA_MASK                    (0x40U)
17374 #define DMA_DCHPRI30_DPA_SHIFT                   (6U)
17375 /*! DPA - Disable Preempt Ability. This field resets to 0.
17376  *  0b0..Channel n can suspend a lower priority channel
17377  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17378  */
17379 #define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
17380 
17381 #define DMA_DCHPRI30_ECP_MASK                    (0x80U)
17382 #define DMA_DCHPRI30_ECP_SHIFT                   (7U)
17383 /*! ECP - Enable Channel Preemption. This field resets to 0.
17384  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17385  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17386  */
17387 #define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
17388 /*! @} */
17389 
17390 /*! @name DCHPRI29 - Channel Priority */
17391 /*! @{ */
17392 
17393 #define DMA_DCHPRI29_CHPRI_MASK                  (0xFU)
17394 #define DMA_DCHPRI29_CHPRI_SHIFT                 (0U)
17395 /*! CHPRI - Channel n Arbitration Priority
17396  */
17397 #define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
17398 
17399 #define DMA_DCHPRI29_GRPPRI_MASK                 (0x30U)
17400 #define DMA_DCHPRI29_GRPPRI_SHIFT                (4U)
17401 /*! GRPPRI - Channel n Current Group Priority
17402  */
17403 #define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
17404 
17405 #define DMA_DCHPRI29_DPA_MASK                    (0x40U)
17406 #define DMA_DCHPRI29_DPA_SHIFT                   (6U)
17407 /*! DPA - Disable Preempt Ability. This field resets to 0.
17408  *  0b0..Channel n can suspend a lower priority channel
17409  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17410  */
17411 #define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
17412 
17413 #define DMA_DCHPRI29_ECP_MASK                    (0x80U)
17414 #define DMA_DCHPRI29_ECP_SHIFT                   (7U)
17415 /*! ECP - Enable Channel Preemption. This field resets to 0.
17416  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17417  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17418  */
17419 #define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
17420 /*! @} */
17421 
17422 /*! @name DCHPRI28 - Channel Priority */
17423 /*! @{ */
17424 
17425 #define DMA_DCHPRI28_CHPRI_MASK                  (0xFU)
17426 #define DMA_DCHPRI28_CHPRI_SHIFT                 (0U)
17427 /*! CHPRI - Channel n Arbitration Priority
17428  */
17429 #define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
17430 
17431 #define DMA_DCHPRI28_GRPPRI_MASK                 (0x30U)
17432 #define DMA_DCHPRI28_GRPPRI_SHIFT                (4U)
17433 /*! GRPPRI - Channel n Current Group Priority
17434  */
17435 #define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
17436 
17437 #define DMA_DCHPRI28_DPA_MASK                    (0x40U)
17438 #define DMA_DCHPRI28_DPA_SHIFT                   (6U)
17439 /*! DPA - Disable Preempt Ability. This field resets to 0.
17440  *  0b0..Channel n can suspend a lower priority channel
17441  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
17442  */
17443 #define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
17444 
17445 #define DMA_DCHPRI28_ECP_MASK                    (0x80U)
17446 #define DMA_DCHPRI28_ECP_SHIFT                   (7U)
17447 /*! ECP - Enable Channel Preemption. This field resets to 0.
17448  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
17449  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
17450  */
17451 #define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
17452 /*! @} */
17453 
17454 /*! @name SADDR - TCD Source Address */
17455 /*! @{ */
17456 
17457 #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
17458 #define DMA_SADDR_SADDR_SHIFT                    (0U)
17459 /*! SADDR - Source Address
17460  */
17461 #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
17462 /*! @} */
17463 
17464 /* The count of DMA_SADDR */
17465 #define DMA_SADDR_COUNT                          (32U)
17466 
17467 /*! @name SOFF - TCD Signed Source Address Offset */
17468 /*! @{ */
17469 
17470 #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
17471 #define DMA_SOFF_SOFF_SHIFT                      (0U)
17472 /*! SOFF - Source address signed offset
17473  */
17474 #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
17475 /*! @} */
17476 
17477 /* The count of DMA_SOFF */
17478 #define DMA_SOFF_COUNT                           (32U)
17479 
17480 /*! @name ATTR - TCD Transfer Attributes */
17481 /*! @{ */
17482 
17483 #define DMA_ATTR_DSIZE_MASK                      (0x7U)
17484 #define DMA_ATTR_DSIZE_SHIFT                     (0U)
17485 /*! DSIZE - Destination data transfer size
17486  */
17487 #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
17488 
17489 #define DMA_ATTR_DMOD_MASK                       (0xF8U)
17490 #define DMA_ATTR_DMOD_SHIFT                      (3U)
17491 /*! DMOD - Destination Address Modulo
17492  */
17493 #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
17494 
17495 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
17496 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
17497 /*! SSIZE - Source data transfer size
17498  *  0b000..8-bit
17499  *  0b001..16-bit
17500  *  0b010..32-bit
17501  *  0b011..64-bit
17502  *  0b100..Reserved
17503  *  0b101..32-byte burst (4 beats of 64 bits)
17504  *  0b110..Reserved
17505  *  0b111..Reserved
17506  */
17507 #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
17508 
17509 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
17510 #define DMA_ATTR_SMOD_SHIFT                      (11U)
17511 /*! SMOD - Source Address Modulo
17512  *  0b00000..Source address modulo feature is disabled
17513  *  0b00001-0b11111..Value defines address range used to set up circular data queue
17514  */
17515 #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
17516 /*! @} */
17517 
17518 /* The count of DMA_ATTR */
17519 #define DMA_ATTR_COUNT                           (32U)
17520 
17521 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
17522 /*! @{ */
17523 
17524 #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
17525 #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
17526 /*! NBYTES - Minor Byte Transfer Count
17527  */
17528 #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
17529 /*! @} */
17530 
17531 /* The count of DMA_NBYTES_MLNO */
17532 #define DMA_NBYTES_MLNO_COUNT                    (32U)
17533 
17534 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
17535 /*! @{ */
17536 
17537 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
17538 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
17539 /*! NBYTES - Minor Byte Transfer Count
17540  */
17541 #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
17542 
17543 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
17544 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
17545 /*! DMLOE - Destination Minor Loop Offset Enable
17546  *  0b0..The minor loop offset is not applied to the DADDR
17547  *  0b1..The minor loop offset is applied to the DADDR
17548  */
17549 #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
17550 
17551 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
17552 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
17553 /*! SMLOE - Source Minor Loop Offset Enable
17554  *  0b0..The minor loop offset is not applied to the SADDR
17555  *  0b1..The minor loop offset is applied to the SADDR
17556  */
17557 #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
17558 /*! @} */
17559 
17560 /* The count of DMA_NBYTES_MLOFFNO */
17561 #define DMA_NBYTES_MLOFFNO_COUNT                 (32U)
17562 
17563 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
17564 /*! @{ */
17565 
17566 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
17567 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
17568 /*! NBYTES - Minor Byte Transfer Count
17569  */
17570 #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
17571 
17572 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
17573 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
17574 /*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the
17575  *    source or destination address to form the next-state value after the minor loop completes.
17576  */
17577 #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
17578 
17579 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
17580 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
17581 /*! DMLOE - Destination Minor Loop Offset Enable
17582  *  0b0..The minor loop offset is not applied to the DADDR
17583  *  0b1..The minor loop offset is applied to the DADDR
17584  */
17585 #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
17586 
17587 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
17588 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
17589 /*! SMLOE - Source Minor Loop Offset Enable
17590  *  0b0..The minor loop offset is not applied to the SADDR
17591  *  0b1..The minor loop offset is applied to the SADDR
17592  */
17593 #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
17594 /*! @} */
17595 
17596 /* The count of DMA_NBYTES_MLOFFYES */
17597 #define DMA_NBYTES_MLOFFYES_COUNT                (32U)
17598 
17599 /*! @name SLAST - TCD Last Source Address Adjustment */
17600 /*! @{ */
17601 
17602 #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
17603 #define DMA_SLAST_SLAST_SHIFT                    (0U)
17604 /*! SLAST - Last Source Address Adjustment
17605  */
17606 #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
17607 /*! @} */
17608 
17609 /* The count of DMA_SLAST */
17610 #define DMA_SLAST_COUNT                          (32U)
17611 
17612 /*! @name DADDR - TCD Destination Address */
17613 /*! @{ */
17614 
17615 #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
17616 #define DMA_DADDR_DADDR_SHIFT                    (0U)
17617 /*! DADDR - Destination Address
17618  */
17619 #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
17620 /*! @} */
17621 
17622 /* The count of DMA_DADDR */
17623 #define DMA_DADDR_COUNT                          (32U)
17624 
17625 /*! @name DOFF - TCD Signed Destination Address Offset */
17626 /*! @{ */
17627 
17628 #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
17629 #define DMA_DOFF_DOFF_SHIFT                      (0U)
17630 /*! DOFF - Destination Address Signed Offset
17631  */
17632 #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
17633 /*! @} */
17634 
17635 /* The count of DMA_DOFF */
17636 #define DMA_DOFF_COUNT                           (32U)
17637 
17638 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
17639 /*! @{ */
17640 
17641 #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
17642 #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
17643 /*! CITER - Current Major Iteration Count
17644  */
17645 #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
17646 
17647 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
17648 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
17649 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
17650  *  0b0..Channel-to-channel linking is disabled
17651  *  0b1..Channel-to-channel linking is enabled
17652  */
17653 #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
17654 /*! @} */
17655 
17656 /* The count of DMA_CITER_ELINKNO */
17657 #define DMA_CITER_ELINKNO_COUNT                  (32U)
17658 
17659 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
17660 /*! @{ */
17661 
17662 #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
17663 #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
17664 /*! CITER - Current Major Iteration Count
17665  */
17666 #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
17667 
17668 #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x3E00U)
17669 #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
17670 /*! LINKCH - Minor Loop Link Channel Number
17671  */
17672 #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
17673 
17674 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
17675 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
17676 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
17677  *  0b0..Channel-to-channel linking is disabled
17678  *  0b1..Channel-to-channel linking is enabled
17679  */
17680 #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
17681 /*! @} */
17682 
17683 /* The count of DMA_CITER_ELINKYES */
17684 #define DMA_CITER_ELINKYES_COUNT                 (32U)
17685 
17686 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
17687 /*! @{ */
17688 
17689 #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
17690 #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
17691 /*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)
17692  */
17693 #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
17694 /*! @} */
17695 
17696 /* The count of DMA_DLAST_SGA */
17697 #define DMA_DLAST_SGA_COUNT                      (32U)
17698 
17699 /*! @name CSR - TCD Control and Status */
17700 /*! @{ */
17701 
17702 #define DMA_CSR_START_MASK                       (0x1U)
17703 #define DMA_CSR_START_SHIFT                      (0U)
17704 /*! START - Channel Start
17705  *  0b0..Channel is not explicitly started
17706  *  0b1..Channel is explicitly started via a software initiated service request
17707  */
17708 #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
17709 
17710 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
17711 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
17712 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
17713  *  0b0..End of major loop interrupt is disabled
17714  *  0b1..End of major loop interrupt is enabled
17715  */
17716 #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
17717 
17718 #define DMA_CSR_INTHALF_MASK                     (0x4U)
17719 #define DMA_CSR_INTHALF_SHIFT                    (2U)
17720 /*! INTHALF - Enable an interrupt when major counter is half complete.
17721  *  0b0..Half-point interrupt is disabled
17722  *  0b1..Half-point interrupt is enabled
17723  */
17724 #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
17725 
17726 #define DMA_CSR_DREQ_MASK                        (0x8U)
17727 #define DMA_CSR_DREQ_SHIFT                       (3U)
17728 /*! DREQ - Disable Request
17729  *  0b0..The channel's ERQ field is not affected
17730  *  0b1..The channel's ERQ field value changes to 0 when the major loop is complete
17731  */
17732 #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
17733 
17734 #define DMA_CSR_ESG_MASK                         (0x10U)
17735 #define DMA_CSR_ESG_SHIFT                        (4U)
17736 /*! ESG - Enable Scatter/Gather Processing
17737  *  0b0..The current channel's TCD is normal format
17738  *  0b1..The current channel's TCD specifies a scatter gather format
17739  */
17740 #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
17741 
17742 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
17743 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
17744 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
17745  *  0b0..Channel-to-channel linking is disabled
17746  *  0b1..Channel-to-channel linking is enabled
17747  */
17748 #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
17749 
17750 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
17751 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
17752 /*! ACTIVE - Channel Active
17753  */
17754 #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
17755 
17756 #define DMA_CSR_DONE_MASK                        (0x80U)
17757 #define DMA_CSR_DONE_SHIFT                       (7U)
17758 /*! DONE - Channel Done
17759  */
17760 #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
17761 
17762 #define DMA_CSR_MAJORLINKCH_MASK                 (0x1F00U)
17763 #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
17764 /*! MAJORLINKCH - Major Loop Link Channel Number
17765  */
17766 #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
17767 
17768 #define DMA_CSR_BWC_MASK                         (0xC000U)
17769 #define DMA_CSR_BWC_SHIFT                        (14U)
17770 /*! BWC - Bandwidth Control
17771  *  0b00..No eDMA engine stalls
17772  *  0b01..Reserved
17773  *  0b10..eDMA engine stalls for 4 cycles after each R/W
17774  *  0b11..eDMA engine stalls for 8 cycles after each R/W
17775  */
17776 #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
17777 /*! @} */
17778 
17779 /* The count of DMA_CSR */
17780 #define DMA_CSR_COUNT                            (32U)
17781 
17782 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
17783 /*! @{ */
17784 
17785 #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
17786 #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
17787 /*! BITER - Starting Major Iteration Count
17788  */
17789 #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
17790 
17791 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
17792 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
17793 /*! ELINK - Enables channel-to-channel linking on minor loop complete
17794  *  0b0..Channel-to-channel linking is disabled
17795  *  0b1..Channel-to-channel linking is enabled
17796  */
17797 #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
17798 /*! @} */
17799 
17800 /* The count of DMA_BITER_ELINKNO */
17801 #define DMA_BITER_ELINKNO_COUNT                  (32U)
17802 
17803 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
17804 /*! @{ */
17805 
17806 #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
17807 #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
17808 /*! BITER - Starting major iteration count
17809  */
17810 #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
17811 
17812 #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x3E00U)
17813 #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
17814 /*! LINKCH - Link Channel Number
17815  */
17816 #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
17817 
17818 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
17819 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
17820 /*! ELINK - Enables channel-to-channel linking on minor loop complete
17821  *  0b0..Channel-to-channel linking is disabled
17822  *  0b1..Channel-to-channel linking is enabled
17823  */
17824 #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
17825 /*! @} */
17826 
17827 /* The count of DMA_BITER_ELINKYES */
17828 #define DMA_BITER_ELINKYES_COUNT                 (32U)
17829 
17830 
17831 /*!
17832  * @}
17833  */ /* end of group DMA_Register_Masks */
17834 
17835 
17836 /* DMA - Peripheral instance base addresses */
17837 /** Peripheral DMA0 base address */
17838 #define DMA0_BASE                                (0x400E8000u)
17839 /** Peripheral DMA0 base pointer */
17840 #define DMA0                                     ((DMA_Type *)DMA0_BASE)
17841 /** Array initializer of DMA peripheral base addresses */
17842 #define DMA_BASE_ADDRS                           { DMA0_BASE }
17843 /** Array initializer of DMA peripheral base pointers */
17844 #define DMA_BASE_PTRS                            { DMA0 }
17845 /** Interrupt vectors for the DMA peripheral type */
17846 #define DMA_CHN_IRQS                             { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
17847 #define DMA_ERROR_IRQS                           { DMA_ERROR_IRQn }
17848 
17849 /*!
17850  * @}
17851  */ /* end of group DMA_Peripheral_Access_Layer */
17852 
17853 
17854 /* ----------------------------------------------------------------------------
17855    -- DMAMUX Peripheral Access Layer
17856    ---------------------------------------------------------------------------- */
17857 
17858 /*!
17859  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
17860  * @{
17861  */
17862 
17863 /** DMAMUX - Register Layout Typedef */
17864 typedef struct {
17865   __IO uint32_t CHCFG[32];                         /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
17866 } DMAMUX_Type;
17867 
17868 /* ----------------------------------------------------------------------------
17869    -- DMAMUX Register Masks
17870    ---------------------------------------------------------------------------- */
17871 
17872 /*!
17873  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
17874  * @{
17875  */
17876 
17877 /*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
17878 /*! @{ */
17879 
17880 #define DMAMUX_CHCFG_SOURCE_MASK                 (0x7FU)
17881 #define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
17882 /*! SOURCE - DMA Channel Source (Slot Number)
17883  */
17884 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
17885 
17886 #define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
17887 #define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
17888 /*! A_ON - DMA Channel Always Enable
17889  *  0b0..DMA Channel Always ON function is disabled
17890  *  0b1..DMA Channel Always ON function is enabled
17891  */
17892 #define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
17893 
17894 #define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
17895 #define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
17896 /*! TRIG - DMA Channel Trigger Enable
17897  *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
17898  *       specified source to the DMA channel. (Normal mode)
17899  *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
17900  */
17901 #define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
17902 
17903 #define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
17904 #define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
17905 /*! ENBL - DMA Mux Channel Enable
17906  *  0b0..DMA Mux channel is disabled
17907  *  0b1..DMA Mux channel is enabled
17908  */
17909 #define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
17910 /*! @} */
17911 
17912 /* The count of DMAMUX_CHCFG */
17913 #define DMAMUX_CHCFG_COUNT                       (32U)
17914 
17915 
17916 /*!
17917  * @}
17918  */ /* end of group DMAMUX_Register_Masks */
17919 
17920 
17921 /* DMAMUX - Peripheral instance base addresses */
17922 /** Peripheral DMAMUX base address */
17923 #define DMAMUX_BASE                              (0x400EC000u)
17924 /** Peripheral DMAMUX base pointer */
17925 #define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
17926 /** Array initializer of DMAMUX peripheral base addresses */
17927 #define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
17928 /** Array initializer of DMAMUX peripheral base pointers */
17929 #define DMAMUX_BASE_PTRS                         { DMAMUX }
17930 
17931 /*!
17932  * @}
17933  */ /* end of group DMAMUX_Peripheral_Access_Layer */
17934 
17935 
17936 /* ----------------------------------------------------------------------------
17937    -- ENC Peripheral Access Layer
17938    ---------------------------------------------------------------------------- */
17939 
17940 /*!
17941  * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
17942  * @{
17943  */
17944 
17945 /** ENC - Register Layout Typedef */
17946 typedef struct {
17947   __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
17948   __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x2 */
17949   __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x4 */
17950   __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x6 */
17951   __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x8 */
17952   __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0xA */
17953   __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0xC */
17954   __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xE */
17955   __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0x10 */
17956   __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x12 */
17957   __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x14 */
17958   __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x16 */
17959   __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x18 */
17960   __I  uint16_t IMR;                               /**< Input Monitor Register, offset: 0x1A */
17961   __IO uint16_t TST;                               /**< Test Register, offset: 0x1C */
17962   __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x1E */
17963   __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x20 */
17964   __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x22 */
17965   __IO uint16_t UCOMP;                             /**< Upper Position Compare Register, offset: 0x24 */
17966   __IO uint16_t LCOMP;                             /**< Lower Position Compare Register, offset: 0x26 */
17967 } ENC_Type;
17968 
17969 /* ----------------------------------------------------------------------------
17970    -- ENC Register Masks
17971    ---------------------------------------------------------------------------- */
17972 
17973 /*!
17974  * @addtogroup ENC_Register_Masks ENC Register Masks
17975  * @{
17976  */
17977 
17978 /*! @name CTRL - Control Register */
17979 /*! @{ */
17980 
17981 #define ENC_CTRL_CMPIE_MASK                      (0x1U)
17982 #define ENC_CTRL_CMPIE_SHIFT                     (0U)
17983 /*! CMPIE - Compare Interrupt Enable
17984  *  0b0..Disabled
17985  *  0b1..Enabled
17986  */
17987 #define ENC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
17988 
17989 #define ENC_CTRL_CMPIRQ_MASK                     (0x2U)
17990 #define ENC_CTRL_CMPIRQ_SHIFT                    (1U)
17991 /*! CMPIRQ - Compare Interrupt Request
17992  *  0b0..No match has occurred (the counter does not match the COMP value)
17993  *  0b1..COMP match has occurred (the counter matches the COMP value)
17994  */
17995 #define ENC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
17996 
17997 #define ENC_CTRL_WDE_MASK                        (0x4U)
17998 #define ENC_CTRL_WDE_SHIFT                       (2U)
17999 /*! WDE - Watchdog Enable
18000  *  0b0..Disabled
18001  *  0b1..Enabled
18002  */
18003 #define ENC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
18004 
18005 #define ENC_CTRL_DIE_MASK                        (0x8U)
18006 #define ENC_CTRL_DIE_SHIFT                       (3U)
18007 /*! DIE - Watchdog Timeout Interrupt Enable
18008  *  0b0..Disabled
18009  *  0b1..Enabled
18010  */
18011 #define ENC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
18012 
18013 #define ENC_CTRL_DIRQ_MASK                       (0x10U)
18014 #define ENC_CTRL_DIRQ_SHIFT                      (4U)
18015 /*! DIRQ - Watchdog Timeout Interrupt Request
18016  *  0b0..No Watchdog timeout interrupt has occurred
18017  *  0b1..Watchdog timeout interrupt has occurred
18018  */
18019 #define ENC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
18020 
18021 #define ENC_CTRL_XNE_MASK                        (0x20U)
18022 #define ENC_CTRL_XNE_SHIFT                       (5U)
18023 /*! XNE - Use Negative Edge of INDEX Pulse
18024  *  0b0..Use positive edge of INDEX pulse
18025  *  0b1..Use negative edge of INDEX pulse
18026  */
18027 #define ENC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
18028 
18029 #define ENC_CTRL_XIP_MASK                        (0x40U)
18030 #define ENC_CTRL_XIP_SHIFT                       (6U)
18031 /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
18032  *  0b0..INDEX pulse does not initialize the position counter
18033  *  0b1..INDEX pulse initializes the position counter
18034  */
18035 #define ENC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
18036 
18037 #define ENC_CTRL_XIE_MASK                        (0x80U)
18038 #define ENC_CTRL_XIE_SHIFT                       (7U)
18039 /*! XIE - INDEX Pulse Interrupt Enable
18040  *  0b0..Disabled
18041  *  0b1..Enabled
18042  */
18043 #define ENC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
18044 
18045 #define ENC_CTRL_XIRQ_MASK                       (0x100U)
18046 #define ENC_CTRL_XIRQ_SHIFT                      (8U)
18047 /*! XIRQ - INDEX Pulse Interrupt Request
18048  *  0b0..INDEX pulse has not occurred
18049  *  0b1..INDEX pulse has occurred
18050  */
18051 #define ENC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
18052 
18053 #define ENC_CTRL_PH1_MASK                        (0x200U)
18054 #define ENC_CTRL_PH1_SHIFT                       (9U)
18055 /*! PH1 - Enable Signal Phase Count Mode
18056  *  0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
18057  *  0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
18058  *       PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If
18059  *       CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1,
18060  *       PHASEB = 0, then count down
18061  */
18062 #define ENC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
18063 
18064 #define ENC_CTRL_REV_MASK                        (0x400U)
18065 #define ENC_CTRL_REV_SHIFT                       (10U)
18066 /*! REV - Enable Reverse Direction Counting
18067  *  0b0..Count normally
18068  *  0b1..Count in the reverse direction
18069  */
18070 #define ENC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
18071 
18072 #define ENC_CTRL_SWIP_MASK                       (0x800U)
18073 #define ENC_CTRL_SWIP_SHIFT                      (11U)
18074 /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
18075  *  0b0..No action
18076  *  0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)
18077  */
18078 #define ENC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
18079 
18080 #define ENC_CTRL_HNE_MASK                        (0x1000U)
18081 #define ENC_CTRL_HNE_SHIFT                       (12U)
18082 /*! HNE - Use Negative Edge of HOME Input
18083  *  0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
18084  *  0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
18085  */
18086 #define ENC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
18087 
18088 #define ENC_CTRL_HIP_MASK                        (0x2000U)
18089 #define ENC_CTRL_HIP_SHIFT                       (13U)
18090 /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
18091  *  0b0..No action
18092  *  0b1..HOME signal initializes the position counter
18093  */
18094 #define ENC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
18095 
18096 #define ENC_CTRL_HIE_MASK                        (0x4000U)
18097 #define ENC_CTRL_HIE_SHIFT                       (14U)
18098 /*! HIE - HOME Interrupt Enable
18099  *  0b0..Disabled
18100  *  0b1..Enabled
18101  */
18102 #define ENC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
18103 
18104 #define ENC_CTRL_HIRQ_MASK                       (0x8000U)
18105 #define ENC_CTRL_HIRQ_SHIFT                      (15U)
18106 /*! HIRQ - HOME Signal Transition Interrupt Request
18107  *  0b0..No transition on the HOME signal has occurred
18108  *  0b1..A transition on the HOME signal has occurred
18109  */
18110 #define ENC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
18111 /*! @} */
18112 
18113 /*! @name FILT - Input Filter Register */
18114 /*! @{ */
18115 
18116 #define ENC_FILT_FILT_PER_MASK                   (0xFFU)
18117 #define ENC_FILT_FILT_PER_SHIFT                  (0U)
18118 /*! FILT_PER - Input Filter Sample Period
18119  */
18120 #define ENC_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
18121 
18122 #define ENC_FILT_FILT_CNT_MASK                   (0x700U)
18123 #define ENC_FILT_FILT_CNT_SHIFT                  (8U)
18124 /*! FILT_CNT - Input Filter Sample Count
18125  */
18126 #define ENC_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
18127 /*! @} */
18128 
18129 /*! @name WTR - Watchdog Timeout Register */
18130 /*! @{ */
18131 
18132 #define ENC_WTR_WDOG_MASK                        (0xFFFFU)
18133 #define ENC_WTR_WDOG_SHIFT                       (0U)
18134 /*! WDOG - WDOG
18135  */
18136 #define ENC_WTR_WDOG(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
18137 /*! @} */
18138 
18139 /*! @name POSD - Position Difference Counter Register */
18140 /*! @{ */
18141 
18142 #define ENC_POSD_POSD_MASK                       (0xFFFFU)
18143 #define ENC_POSD_POSD_SHIFT                      (0U)
18144 /*! POSD - POSD
18145  */
18146 #define ENC_POSD_POSD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
18147 /*! @} */
18148 
18149 /*! @name POSDH - Position Difference Hold Register */
18150 /*! @{ */
18151 
18152 #define ENC_POSDH_POSDH_MASK                     (0xFFFFU)
18153 #define ENC_POSDH_POSDH_SHIFT                    (0U)
18154 /*! POSDH - POSDH
18155  */
18156 #define ENC_POSDH_POSDH(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
18157 /*! @} */
18158 
18159 /*! @name REV - Revolution Counter Register */
18160 /*! @{ */
18161 
18162 #define ENC_REV_REV_MASK                         (0xFFFFU)
18163 #define ENC_REV_REV_SHIFT                        (0U)
18164 /*! REV - REV
18165  */
18166 #define ENC_REV_REV(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
18167 /*! @} */
18168 
18169 /*! @name REVH - Revolution Hold Register */
18170 /*! @{ */
18171 
18172 #define ENC_REVH_REVH_MASK                       (0xFFFFU)
18173 #define ENC_REVH_REVH_SHIFT                      (0U)
18174 /*! REVH - REVH
18175  */
18176 #define ENC_REVH_REVH(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
18177 /*! @} */
18178 
18179 /*! @name UPOS - Upper Position Counter Register */
18180 /*! @{ */
18181 
18182 #define ENC_UPOS_POS_MASK                        (0xFFFFU)
18183 #define ENC_UPOS_POS_SHIFT                       (0U)
18184 /*! POS - POS
18185  */
18186 #define ENC_UPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
18187 /*! @} */
18188 
18189 /*! @name LPOS - Lower Position Counter Register */
18190 /*! @{ */
18191 
18192 #define ENC_LPOS_POS_MASK                        (0xFFFFU)
18193 #define ENC_LPOS_POS_SHIFT                       (0U)
18194 /*! POS - POS
18195  */
18196 #define ENC_LPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
18197 /*! @} */
18198 
18199 /*! @name UPOSH - Upper Position Hold Register */
18200 /*! @{ */
18201 
18202 #define ENC_UPOSH_POSH_MASK                      (0xFFFFU)
18203 #define ENC_UPOSH_POSH_SHIFT                     (0U)
18204 /*! POSH - POSH
18205  */
18206 #define ENC_UPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
18207 /*! @} */
18208 
18209 /*! @name LPOSH - Lower Position Hold Register */
18210 /*! @{ */
18211 
18212 #define ENC_LPOSH_POSH_MASK                      (0xFFFFU)
18213 #define ENC_LPOSH_POSH_SHIFT                     (0U)
18214 /*! POSH - POSH
18215  */
18216 #define ENC_LPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
18217 /*! @} */
18218 
18219 /*! @name UINIT - Upper Initialization Register */
18220 /*! @{ */
18221 
18222 #define ENC_UINIT_INIT_MASK                      (0xFFFFU)
18223 #define ENC_UINIT_INIT_SHIFT                     (0U)
18224 /*! INIT - INIT
18225  */
18226 #define ENC_UINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
18227 /*! @} */
18228 
18229 /*! @name LINIT - Lower Initialization Register */
18230 /*! @{ */
18231 
18232 #define ENC_LINIT_INIT_MASK                      (0xFFFFU)
18233 #define ENC_LINIT_INIT_SHIFT                     (0U)
18234 /*! INIT - INIT
18235  */
18236 #define ENC_LINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
18237 /*! @} */
18238 
18239 /*! @name IMR - Input Monitor Register */
18240 /*! @{ */
18241 
18242 #define ENC_IMR_HOME_MASK                        (0x1U)
18243 #define ENC_IMR_HOME_SHIFT                       (0U)
18244 /*! HOME - HOME
18245  */
18246 #define ENC_IMR_HOME(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
18247 
18248 #define ENC_IMR_INDEX_MASK                       (0x2U)
18249 #define ENC_IMR_INDEX_SHIFT                      (1U)
18250 /*! INDEX - INDEX
18251  */
18252 #define ENC_IMR_INDEX(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
18253 
18254 #define ENC_IMR_PHB_MASK                         (0x4U)
18255 #define ENC_IMR_PHB_SHIFT                        (2U)
18256 /*! PHB - PHB
18257  */
18258 #define ENC_IMR_PHB(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
18259 
18260 #define ENC_IMR_PHA_MASK                         (0x8U)
18261 #define ENC_IMR_PHA_SHIFT                        (3U)
18262 /*! PHA - PHA
18263  */
18264 #define ENC_IMR_PHA(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
18265 
18266 #define ENC_IMR_FHOM_MASK                        (0x10U)
18267 #define ENC_IMR_FHOM_SHIFT                       (4U)
18268 /*! FHOM - FHOM
18269  */
18270 #define ENC_IMR_FHOM(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
18271 
18272 #define ENC_IMR_FIND_MASK                        (0x20U)
18273 #define ENC_IMR_FIND_SHIFT                       (5U)
18274 /*! FIND - FIND
18275  */
18276 #define ENC_IMR_FIND(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
18277 
18278 #define ENC_IMR_FPHB_MASK                        (0x40U)
18279 #define ENC_IMR_FPHB_SHIFT                       (6U)
18280 /*! FPHB - FPHB
18281  */
18282 #define ENC_IMR_FPHB(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
18283 
18284 #define ENC_IMR_FPHA_MASK                        (0x80U)
18285 #define ENC_IMR_FPHA_SHIFT                       (7U)
18286 /*! FPHA - FPHA
18287  */
18288 #define ENC_IMR_FPHA(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
18289 /*! @} */
18290 
18291 /*! @name TST - Test Register */
18292 /*! @{ */
18293 
18294 #define ENC_TST_TEST_COUNT_MASK                  (0xFFU)
18295 #define ENC_TST_TEST_COUNT_SHIFT                 (0U)
18296 /*! TEST_COUNT - TEST_COUNT
18297  */
18298 #define ENC_TST_TEST_COUNT(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
18299 
18300 #define ENC_TST_TEST_PERIOD_MASK                 (0x1F00U)
18301 #define ENC_TST_TEST_PERIOD_SHIFT                (8U)
18302 /*! TEST_PERIOD - TEST_PERIOD
18303  */
18304 #define ENC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
18305 
18306 #define ENC_TST_QDN_MASK                         (0x2000U)
18307 #define ENC_TST_QDN_SHIFT                        (13U)
18308 /*! QDN - Quadrature Decoder Negative Signal
18309  *  0b0..Generates a positive quadrature decoder signal
18310  *  0b1..Generates a negative quadrature decoder signal
18311  */
18312 #define ENC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
18313 
18314 #define ENC_TST_TCE_MASK                         (0x4000U)
18315 #define ENC_TST_TCE_SHIFT                        (14U)
18316 /*! TCE - Test Counter Enable
18317  *  0b0..Disabled
18318  *  0b1..Enabled
18319  */
18320 #define ENC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
18321 
18322 #define ENC_TST_TEN_MASK                         (0x8000U)
18323 #define ENC_TST_TEN_SHIFT                        (15U)
18324 /*! TEN - Test Mode Enable
18325  *  0b0..Disabled
18326  *  0b1..Enabled
18327  */
18328 #define ENC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
18329 /*! @} */
18330 
18331 /*! @name CTRL2 - Control 2 Register */
18332 /*! @{ */
18333 
18334 #define ENC_CTRL2_UPDHLD_MASK                    (0x1U)
18335 #define ENC_CTRL2_UPDHLD_SHIFT                   (0U)
18336 /*! UPDHLD - Update Hold Registers
18337  *  0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal
18338  *  0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal
18339  */
18340 #define ENC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
18341 
18342 #define ENC_CTRL2_UPDPOS_MASK                    (0x2U)
18343 #define ENC_CTRL2_UPDPOS_SHIFT                   (1U)
18344 /*! UPDPOS - Update Position Registers
18345  *  0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
18346  *  0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
18347  */
18348 #define ENC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
18349 
18350 #define ENC_CTRL2_MOD_MASK                       (0x4U)
18351 #define ENC_CTRL2_MOD_SHIFT                      (2U)
18352 /*! MOD - Enable Modulo Counting
18353  *  0b0..Disable modulo counting
18354  *  0b1..Enable modulo counting
18355  */
18356 #define ENC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
18357 
18358 #define ENC_CTRL2_DIR_MASK                       (0x8U)
18359 #define ENC_CTRL2_DIR_SHIFT                      (3U)
18360 /*! DIR - Count Direction Flag
18361  *  0b0..Last count was in the down direction
18362  *  0b1..Last count was in the up direction
18363  */
18364 #define ENC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
18365 
18366 #define ENC_CTRL2_RUIE_MASK                      (0x10U)
18367 #define ENC_CTRL2_RUIE_SHIFT                     (4U)
18368 /*! RUIE - Roll-under Interrupt Enable
18369  *  0b0..Disabled
18370  *  0b1..Enabled
18371  */
18372 #define ENC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
18373 
18374 #define ENC_CTRL2_RUIRQ_MASK                     (0x20U)
18375 #define ENC_CTRL2_RUIRQ_SHIFT                    (5U)
18376 /*! RUIRQ - Roll-under Interrupt Request
18377  *  0b0..No roll-under has occurred
18378  *  0b1..Roll-under has occurred
18379  */
18380 #define ENC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
18381 
18382 #define ENC_CTRL2_ROIE_MASK                      (0x40U)
18383 #define ENC_CTRL2_ROIE_SHIFT                     (6U)
18384 /*! ROIE - Roll-over Interrupt Enable
18385  *  0b0..Disabled
18386  *  0b1..Enabled
18387  */
18388 #define ENC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
18389 
18390 #define ENC_CTRL2_ROIRQ_MASK                     (0x80U)
18391 #define ENC_CTRL2_ROIRQ_SHIFT                    (7U)
18392 /*! ROIRQ - Roll-over Interrupt Request
18393  *  0b0..No roll-over has occurred
18394  *  0b1..Roll-over has occurred
18395  */
18396 #define ENC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
18397 
18398 #define ENC_CTRL2_REVMOD_MASK                    (0x100U)
18399 #define ENC_CTRL2_REVMOD_SHIFT                   (8U)
18400 /*! REVMOD - Revolution Counter Modulus Enable
18401  *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
18402  *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
18403  */
18404 #define ENC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
18405 
18406 #define ENC_CTRL2_OUTCTL_MASK                    (0x200U)
18407 #define ENC_CTRL2_OUTCTL_SHIFT                   (9U)
18408 /*! OUTCTL - Output Control
18409  *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
18410  *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
18411  */
18412 #define ENC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
18413 /*! @} */
18414 
18415 /*! @name UMOD - Upper Modulus Register */
18416 /*! @{ */
18417 
18418 #define ENC_UMOD_MOD_MASK                        (0xFFFFU)
18419 #define ENC_UMOD_MOD_SHIFT                       (0U)
18420 /*! MOD - MOD
18421  */
18422 #define ENC_UMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
18423 /*! @} */
18424 
18425 /*! @name LMOD - Lower Modulus Register */
18426 /*! @{ */
18427 
18428 #define ENC_LMOD_MOD_MASK                        (0xFFFFU)
18429 #define ENC_LMOD_MOD_SHIFT                       (0U)
18430 /*! MOD - MOD
18431  */
18432 #define ENC_LMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
18433 /*! @} */
18434 
18435 /*! @name UCOMP - Upper Position Compare Register */
18436 /*! @{ */
18437 
18438 #define ENC_UCOMP_COMP_MASK                      (0xFFFFU)
18439 #define ENC_UCOMP_COMP_SHIFT                     (0U)
18440 /*! COMP - COMP
18441  */
18442 #define ENC_UCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
18443 /*! @} */
18444 
18445 /*! @name LCOMP - Lower Position Compare Register */
18446 /*! @{ */
18447 
18448 #define ENC_LCOMP_COMP_MASK                      (0xFFFFU)
18449 #define ENC_LCOMP_COMP_SHIFT                     (0U)
18450 /*! COMP - COMP
18451  */
18452 #define ENC_LCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
18453 /*! @} */
18454 
18455 
18456 /*!
18457  * @}
18458  */ /* end of group ENC_Register_Masks */
18459 
18460 
18461 /* ENC - Peripheral instance base addresses */
18462 /** Peripheral ENC1 base address */
18463 #define ENC1_BASE                                (0x403C8000u)
18464 /** Peripheral ENC1 base pointer */
18465 #define ENC1                                     ((ENC_Type *)ENC1_BASE)
18466 /** Peripheral ENC2 base address */
18467 #define ENC2_BASE                                (0x403CC000u)
18468 /** Peripheral ENC2 base pointer */
18469 #define ENC2                                     ((ENC_Type *)ENC2_BASE)
18470 /** Peripheral ENC3 base address */
18471 #define ENC3_BASE                                (0x403D0000u)
18472 /** Peripheral ENC3 base pointer */
18473 #define ENC3                                     ((ENC_Type *)ENC3_BASE)
18474 /** Peripheral ENC4 base address */
18475 #define ENC4_BASE                                (0x403D4000u)
18476 /** Peripheral ENC4 base pointer */
18477 #define ENC4                                     ((ENC_Type *)ENC4_BASE)
18478 /** Array initializer of ENC peripheral base addresses */
18479 #define ENC_BASE_ADDRS                           { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
18480 /** Array initializer of ENC peripheral base pointers */
18481 #define ENC_BASE_PTRS                            { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
18482 /** Interrupt vectors for the ENC peripheral type */
18483 #define ENC_COMPARE_IRQS                         { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18484 #define ENC_HOME_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18485 #define ENC_WDOG_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18486 #define ENC_INDEX_IRQS                           { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18487 #define ENC_INPUT_SWITCH_IRQS                    { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18488 
18489 /*!
18490  * @}
18491  */ /* end of group ENC_Peripheral_Access_Layer */
18492 
18493 
18494 /* ----------------------------------------------------------------------------
18495    -- ENET Peripheral Access Layer
18496    ---------------------------------------------------------------------------- */
18497 
18498 /*!
18499  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
18500  * @{
18501  */
18502 
18503 /** ENET - Register Layout Typedef */
18504 typedef struct {
18505        uint8_t RESERVED_0[4];
18506   __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
18507   __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
18508        uint8_t RESERVED_1[4];
18509   __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
18510   __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
18511        uint8_t RESERVED_2[12];
18512   __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
18513        uint8_t RESERVED_3[24];
18514   __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
18515   __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
18516        uint8_t RESERVED_4[28];
18517   __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
18518        uint8_t RESERVED_5[28];
18519   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
18520        uint8_t RESERVED_6[60];
18521   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
18522        uint8_t RESERVED_7[28];
18523   __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
18524   __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
18525   __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
18526   __IO uint32_t TXIC[1];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
18527        uint8_t RESERVED_8[12];
18528   __IO uint32_t RXIC[1];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
18529        uint8_t RESERVED_9[20];
18530   __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
18531   __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
18532   __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
18533   __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
18534        uint8_t RESERVED_10[28];
18535   __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
18536        uint8_t RESERVED_11[56];
18537   __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
18538   __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
18539   __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
18540        uint8_t RESERVED_12[4];
18541   __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
18542   __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
18543   __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
18544   __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
18545   __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
18546   __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
18547   __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
18548   __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
18549   __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
18550        uint8_t RESERVED_13[12];
18551   __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
18552   __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
18553        uint8_t RESERVED_14[60];
18554   __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
18555   __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
18556   __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
18557   __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
18558   __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
18559   __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
18560   __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
18561   __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
18562   __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
18563   __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
18564   __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
18565   __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
18566   __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
18567   __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
18568   __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
18569   __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
18570   __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
18571        uint8_t RESERVED_15[4];
18572   __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
18573   __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
18574   __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
18575   __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
18576   __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
18577   __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
18578   __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
18579   __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
18580   __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
18581   __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
18582   __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
18583        uint8_t RESERVED_16[12];
18584   __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
18585   __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
18586   __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
18587   __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
18588   __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
18589   __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
18590   __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
18591   __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
18592        uint8_t RESERVED_17[4];
18593   __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
18594   __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
18595   __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
18596   __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
18597   __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
18598   __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
18599   __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
18600   __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
18601   __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
18602   __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
18603   __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
18604   __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
18605   __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
18606   __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
18607   __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
18608        uint8_t RESERVED_18[284];
18609   __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
18610   __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
18611   __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
18612   __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
18613   __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
18614   __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
18615   __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
18616        uint8_t RESERVED_19[488];
18617   __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
18618   struct {                                         /* offset: 0x608, array step: 0x8 */
18619     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
18620     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
18621   } CHANNEL[4];
18622 } ENET_Type;
18623 
18624 /* ----------------------------------------------------------------------------
18625    -- ENET Register Masks
18626    ---------------------------------------------------------------------------- */
18627 
18628 /*!
18629  * @addtogroup ENET_Register_Masks ENET Register Masks
18630  * @{
18631  */
18632 
18633 /*! @name EIR - Interrupt Event Register */
18634 /*! @{ */
18635 
18636 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
18637 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
18638 /*! TS_TIMER - Timestamp Timer
18639  */
18640 #define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
18641 
18642 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
18643 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
18644 /*! TS_AVAIL - Transmit Timestamp Available
18645  */
18646 #define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
18647 
18648 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
18649 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
18650 /*! WAKEUP - Node Wakeup Request Indication
18651  */
18652 #define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
18653 
18654 #define ENET_EIR_PLR_MASK                        (0x40000U)
18655 #define ENET_EIR_PLR_SHIFT                       (18U)
18656 /*! PLR - Payload Receive Error
18657  */
18658 #define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
18659 
18660 #define ENET_EIR_UN_MASK                         (0x80000U)
18661 #define ENET_EIR_UN_SHIFT                        (19U)
18662 /*! UN - Transmit FIFO Underrun
18663  */
18664 #define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
18665 
18666 #define ENET_EIR_RL_MASK                         (0x100000U)
18667 #define ENET_EIR_RL_SHIFT                        (20U)
18668 /*! RL - Collision Retry Limit
18669  */
18670 #define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
18671 
18672 #define ENET_EIR_LC_MASK                         (0x200000U)
18673 #define ENET_EIR_LC_SHIFT                        (21U)
18674 /*! LC - Late Collision
18675  */
18676 #define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
18677 
18678 #define ENET_EIR_EBERR_MASK                      (0x400000U)
18679 #define ENET_EIR_EBERR_SHIFT                     (22U)
18680 /*! EBERR - Ethernet Bus Error
18681  */
18682 #define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
18683 
18684 #define ENET_EIR_MII_MASK                        (0x800000U)
18685 #define ENET_EIR_MII_SHIFT                       (23U)
18686 /*! MII - MII Interrupt.
18687  */
18688 #define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
18689 
18690 #define ENET_EIR_RXB_MASK                        (0x1000000U)
18691 #define ENET_EIR_RXB_SHIFT                       (24U)
18692 /*! RXB - Receive Buffer Interrupt
18693  */
18694 #define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
18695 
18696 #define ENET_EIR_RXF_MASK                        (0x2000000U)
18697 #define ENET_EIR_RXF_SHIFT                       (25U)
18698 /*! RXF - Receive Frame Interrupt
18699  */
18700 #define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
18701 
18702 #define ENET_EIR_TXB_MASK                        (0x4000000U)
18703 #define ENET_EIR_TXB_SHIFT                       (26U)
18704 /*! TXB - Transmit Buffer Interrupt
18705  */
18706 #define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
18707 
18708 #define ENET_EIR_TXF_MASK                        (0x8000000U)
18709 #define ENET_EIR_TXF_SHIFT                       (27U)
18710 /*! TXF - Transmit Frame Interrupt
18711  */
18712 #define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
18713 
18714 #define ENET_EIR_GRA_MASK                        (0x10000000U)
18715 #define ENET_EIR_GRA_SHIFT                       (28U)
18716 /*! GRA - Graceful Stop Complete
18717  */
18718 #define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
18719 
18720 #define ENET_EIR_BABT_MASK                       (0x20000000U)
18721 #define ENET_EIR_BABT_SHIFT                      (29U)
18722 /*! BABT - Babbling Transmit Error
18723  */
18724 #define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
18725 
18726 #define ENET_EIR_BABR_MASK                       (0x40000000U)
18727 #define ENET_EIR_BABR_SHIFT                      (30U)
18728 /*! BABR - Babbling Receive Error
18729  */
18730 #define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
18731 /*! @} */
18732 
18733 /*! @name EIMR - Interrupt Mask Register */
18734 /*! @{ */
18735 
18736 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
18737 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
18738 /*! TS_TIMER - TS_TIMER Interrupt Mask
18739  *  0b0..The corresponding interrupt source is masked.
18740  *  0b1..The corresponding interrupt source is not masked.
18741  */
18742 #define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
18743 
18744 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
18745 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
18746 /*! TS_AVAIL - TS_AVAIL Interrupt Mask
18747  *  0b0..The corresponding interrupt source is masked.
18748  *  0b1..The corresponding interrupt source is not masked.
18749  */
18750 #define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
18751 
18752 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
18753 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
18754 /*! WAKEUP - WAKEUP Interrupt Mask
18755  *  0b0..The corresponding interrupt source is masked.
18756  *  0b1..The corresponding interrupt source is not masked.
18757  */
18758 #define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
18759 
18760 #define ENET_EIMR_PLR_MASK                       (0x40000U)
18761 #define ENET_EIMR_PLR_SHIFT                      (18U)
18762 /*! PLR - PLR Interrupt Mask
18763  *  0b0..The corresponding interrupt source is masked.
18764  *  0b1..The corresponding interrupt source is not masked.
18765  */
18766 #define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
18767 
18768 #define ENET_EIMR_UN_MASK                        (0x80000U)
18769 #define ENET_EIMR_UN_SHIFT                       (19U)
18770 /*! UN - UN Interrupt Mask
18771  *  0b0..The corresponding interrupt source is masked.
18772  *  0b1..The corresponding interrupt source is not masked.
18773  */
18774 #define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
18775 
18776 #define ENET_EIMR_RL_MASK                        (0x100000U)
18777 #define ENET_EIMR_RL_SHIFT                       (20U)
18778 /*! RL - RL Interrupt Mask
18779  *  0b0..The corresponding interrupt source is masked.
18780  *  0b1..The corresponding interrupt source is not masked.
18781  */
18782 #define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
18783 
18784 #define ENET_EIMR_LC_MASK                        (0x200000U)
18785 #define ENET_EIMR_LC_SHIFT                       (21U)
18786 /*! LC - LC Interrupt Mask
18787  *  0b0..The corresponding interrupt source is masked.
18788  *  0b1..The corresponding interrupt source is not masked.
18789  */
18790 #define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
18791 
18792 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
18793 #define ENET_EIMR_EBERR_SHIFT                    (22U)
18794 /*! EBERR - EBERR Interrupt Mask
18795  *  0b0..The corresponding interrupt source is masked.
18796  *  0b1..The corresponding interrupt source is not masked.
18797  */
18798 #define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
18799 
18800 #define ENET_EIMR_MII_MASK                       (0x800000U)
18801 #define ENET_EIMR_MII_SHIFT                      (23U)
18802 /*! MII - MII Interrupt Mask
18803  *  0b0..The corresponding interrupt source is masked.
18804  *  0b1..The corresponding interrupt source is not masked.
18805  */
18806 #define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
18807 
18808 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
18809 #define ENET_EIMR_RXB_SHIFT                      (24U)
18810 /*! RXB - RXB Interrupt Mask
18811  *  0b0..The corresponding interrupt source is masked.
18812  *  0b1..The corresponding interrupt source is not masked.
18813  */
18814 #define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
18815 
18816 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
18817 #define ENET_EIMR_RXF_SHIFT                      (25U)
18818 /*! RXF - RXF Interrupt Mask
18819  *  0b0..The corresponding interrupt source is masked.
18820  *  0b1..The corresponding interrupt source is not masked.
18821  */
18822 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
18823 
18824 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
18825 #define ENET_EIMR_TXB_SHIFT                      (26U)
18826 /*! TXB - TXB Interrupt Mask
18827  *  0b0..The corresponding interrupt source is masked.
18828  *  0b1..The corresponding interrupt source is not masked.
18829  */
18830 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
18831 
18832 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
18833 #define ENET_EIMR_TXF_SHIFT                      (27U)
18834 /*! TXF - TXF Interrupt Mask
18835  *  0b0..The corresponding interrupt source is masked.
18836  *  0b1..The corresponding interrupt source is not masked.
18837  */
18838 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
18839 
18840 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
18841 #define ENET_EIMR_GRA_SHIFT                      (28U)
18842 /*! GRA - GRA Interrupt Mask
18843  *  0b0..The corresponding interrupt source is masked.
18844  *  0b1..The corresponding interrupt source is not masked.
18845  */
18846 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
18847 
18848 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
18849 #define ENET_EIMR_BABT_SHIFT                     (29U)
18850 /*! BABT - BABT Interrupt Mask
18851  *  0b0..The corresponding interrupt source is masked.
18852  *  0b1..The corresponding interrupt source is not masked.
18853  */
18854 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
18855 
18856 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
18857 #define ENET_EIMR_BABR_SHIFT                     (30U)
18858 /*! BABR - BABR Interrupt Mask
18859  *  0b0..The corresponding interrupt source is masked.
18860  *  0b1..The corresponding interrupt source is not masked.
18861  */
18862 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
18863 /*! @} */
18864 
18865 /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
18866 /*! @{ */
18867 
18868 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
18869 #define ENET_RDAR_RDAR_SHIFT                     (24U)
18870 /*! RDAR - Receive Descriptor Active
18871  */
18872 #define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
18873 /*! @} */
18874 
18875 /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
18876 /*! @{ */
18877 
18878 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
18879 #define ENET_TDAR_TDAR_SHIFT                     (24U)
18880 /*! TDAR - Transmit Descriptor Active
18881  */
18882 #define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
18883 /*! @} */
18884 
18885 /*! @name ECR - Ethernet Control Register */
18886 /*! @{ */
18887 
18888 #define ENET_ECR_RESET_MASK                      (0x1U)
18889 #define ENET_ECR_RESET_SHIFT                     (0U)
18890 /*! RESET - Ethernet MAC Reset
18891  */
18892 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
18893 
18894 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
18895 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
18896 /*! ETHEREN - Ethernet Enable
18897  *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
18898  *  0b1..MAC is enabled, and reception and transmission are possible.
18899  */
18900 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
18901 
18902 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
18903 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
18904 /*! MAGICEN - Magic Packet Detection Enable
18905  *  0b0..Magic detection logic disabled.
18906  *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
18907  */
18908 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
18909 
18910 #define ENET_ECR_SLEEP_MASK                      (0x8U)
18911 #define ENET_ECR_SLEEP_SHIFT                     (3U)
18912 /*! SLEEP - Sleep Mode Enable
18913  *  0b0..Normal operating mode.
18914  *  0b1..Sleep mode.
18915  */
18916 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
18917 
18918 #define ENET_ECR_EN1588_MASK                     (0x10U)
18919 #define ENET_ECR_EN1588_SHIFT                    (4U)
18920 /*! EN1588 - EN1588 Enable
18921  *  0b0..Legacy FEC buffer descriptors and functions enabled.
18922  *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
18923  */
18924 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
18925 
18926 #define ENET_ECR_DBGEN_MASK                      (0x40U)
18927 #define ENET_ECR_DBGEN_SHIFT                     (6U)
18928 /*! DBGEN - Debug Enable
18929  *  0b0..MAC continues operation in debug mode.
18930  *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
18931  */
18932 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
18933 
18934 #define ENET_ECR_DBSWP_MASK                      (0x100U)
18935 #define ENET_ECR_DBSWP_SHIFT                     (8U)
18936 /*! DBSWP - Descriptor Byte Swapping Enable
18937  *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
18938  *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
18939  */
18940 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
18941 /*! @} */
18942 
18943 /*! @name MMFR - MII Management Frame Register */
18944 /*! @{ */
18945 
18946 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
18947 #define ENET_MMFR_DATA_SHIFT                     (0U)
18948 /*! DATA - Management Frame Data
18949  */
18950 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
18951 
18952 #define ENET_MMFR_TA_MASK                        (0x30000U)
18953 #define ENET_MMFR_TA_SHIFT                       (16U)
18954 /*! TA - Turn Around
18955  */
18956 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
18957 
18958 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
18959 #define ENET_MMFR_RA_SHIFT                       (18U)
18960 /*! RA - Register Address
18961  */
18962 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
18963 
18964 #define ENET_MMFR_PA_MASK                        (0xF800000U)
18965 #define ENET_MMFR_PA_SHIFT                       (23U)
18966 /*! PA - PHY Address
18967  */
18968 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
18969 
18970 #define ENET_MMFR_OP_MASK                        (0x30000000U)
18971 #define ENET_MMFR_OP_SHIFT                       (28U)
18972 /*! OP - Operation Code
18973  */
18974 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
18975 
18976 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
18977 #define ENET_MMFR_ST_SHIFT                       (30U)
18978 /*! ST - Start Of Frame Delimiter
18979  */
18980 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
18981 /*! @} */
18982 
18983 /*! @name MSCR - MII Speed Control Register */
18984 /*! @{ */
18985 
18986 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
18987 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
18988 /*! MII_SPEED - MII Speed
18989  */
18990 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
18991 
18992 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
18993 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
18994 /*! DIS_PRE - Disable Preamble
18995  *  0b0..Preamble enabled.
18996  *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
18997  */
18998 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
18999 
19000 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
19001 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
19002 /*! HOLDTIME - Hold time On MDIO Output
19003  *  0b000..1 internal module clock cycle
19004  *  0b001..2 internal module clock cycles
19005  *  0b010..3 internal module clock cycles
19006  *  0b111..8 internal module clock cycles
19007  */
19008 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
19009 /*! @} */
19010 
19011 /*! @name MIBC - MIB Control Register */
19012 /*! @{ */
19013 
19014 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
19015 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
19016 /*! MIB_CLEAR - MIB Clear
19017  *  0b0..See note above.
19018  *  0b1..All statistics counters are reset to 0.
19019  */
19020 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
19021 
19022 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
19023 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
19024 /*! MIB_IDLE - MIB Idle
19025  *  0b0..The MIB block is updating MIB counters.
19026  *  0b1..The MIB block is not currently updating any MIB counters.
19027  */
19028 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
19029 
19030 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
19031 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
19032 /*! MIB_DIS - Disable MIB Logic
19033  *  0b0..MIB logic is enabled.
19034  *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
19035  */
19036 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
19037 /*! @} */
19038 
19039 /*! @name RCR - Receive Control Register */
19040 /*! @{ */
19041 
19042 #define ENET_RCR_LOOP_MASK                       (0x1U)
19043 #define ENET_RCR_LOOP_SHIFT                      (0U)
19044 /*! LOOP - Internal Loopback
19045  *  0b0..Loopback disabled.
19046  *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
19047  */
19048 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
19049 
19050 #define ENET_RCR_DRT_MASK                        (0x2U)
19051 #define ENET_RCR_DRT_SHIFT                       (1U)
19052 /*! DRT - Disable Receive On Transmit
19053  *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
19054  *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
19055  */
19056 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
19057 
19058 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
19059 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
19060 /*! MII_MODE - Media Independent Interface Mode
19061  *  0b0..Reserved.
19062  *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
19063  */
19064 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
19065 
19066 #define ENET_RCR_PROM_MASK                       (0x8U)
19067 #define ENET_RCR_PROM_SHIFT                      (3U)
19068 /*! PROM - Promiscuous Mode
19069  *  0b0..Disabled.
19070  *  0b1..Enabled.
19071  */
19072 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
19073 
19074 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
19075 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
19076 /*! BC_REJ - Broadcast Frame Reject
19077  *  0b0..Will not reject frames as described above
19078  *  0b1..Will reject frames as described above
19079  */
19080 #define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
19081 
19082 #define ENET_RCR_FCE_MASK                        (0x20U)
19083 #define ENET_RCR_FCE_SHIFT                       (5U)
19084 /*! FCE - Flow Control Enable
19085  *  0b0..Disable flow control
19086  *  0b1..Enable flow control
19087  */
19088 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
19089 
19090 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
19091 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
19092 /*! RMII_MODE - RMII Mode Enable
19093  *  0b0..MAC configured for MII mode.
19094  *  0b1..MAC configured for RMII operation.
19095  */
19096 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
19097 
19098 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
19099 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
19100 /*! RMII_10T
19101  *  0b0..100-Mbit/s operation.
19102  *  0b1..10-Mbit/s operation.
19103  */
19104 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
19105 
19106 #define ENET_RCR_PADEN_MASK                      (0x1000U)
19107 #define ENET_RCR_PADEN_SHIFT                     (12U)
19108 /*! PADEN - Enable Frame Padding Remove On Receive
19109  *  0b0..No padding is removed on receive by the MAC.
19110  *  0b1..Padding is removed from received frames.
19111  */
19112 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
19113 
19114 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
19115 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
19116 /*! PAUFWD - Terminate/Forward Pause Frames
19117  *  0b0..Pause frames are terminated and discarded in the MAC.
19118  *  0b1..Pause frames are forwarded to the user application.
19119  */
19120 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
19121 
19122 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
19123 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
19124 /*! CRCFWD - Terminate/Forward Received CRC
19125  *  0b0..The CRC field of received frames is transmitted to the user application.
19126  *  0b1..The CRC field is stripped from the frame.
19127  */
19128 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
19129 
19130 #define ENET_RCR_CFEN_MASK                       (0x8000U)
19131 #define ENET_RCR_CFEN_SHIFT                      (15U)
19132 /*! CFEN - MAC Control Frame Enable
19133  *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
19134  *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
19135  */
19136 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
19137 
19138 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
19139 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
19140 /*! MAX_FL - Maximum Frame Length
19141  */
19142 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
19143 
19144 #define ENET_RCR_NLC_MASK                        (0x40000000U)
19145 #define ENET_RCR_NLC_SHIFT                       (30U)
19146 /*! NLC - Payload Length Check Disable
19147  *  0b0..The payload length check is disabled.
19148  *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
19149  */
19150 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
19151 
19152 #define ENET_RCR_GRS_MASK                        (0x80000000U)
19153 #define ENET_RCR_GRS_SHIFT                       (31U)
19154 /*! GRS - Graceful Receive Stopped
19155  *  0b0..Receive not stopped
19156  *  0b1..Receive stopped
19157  */
19158 #define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
19159 /*! @} */
19160 
19161 /*! @name TCR - Transmit Control Register */
19162 /*! @{ */
19163 
19164 #define ENET_TCR_GTS_MASK                        (0x1U)
19165 #define ENET_TCR_GTS_SHIFT                       (0U)
19166 /*! GTS - Graceful Transmit Stop
19167  *  0b0..Disable graceful transmit stop
19168  *  0b1..Enable graceful transmit stop
19169  */
19170 #define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
19171 
19172 #define ENET_TCR_FDEN_MASK                       (0x4U)
19173 #define ENET_TCR_FDEN_SHIFT                      (2U)
19174 /*! FDEN - Full-Duplex Enable
19175  *  0b0..Disable full-duplex
19176  *  0b1..Enable full-duplex
19177  */
19178 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
19179 
19180 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
19181 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
19182 /*! TFC_PAUSE - Transmit Frame Control Pause
19183  *  0b0..No PAUSE frame transmitted.
19184  *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
19185  */
19186 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
19187 
19188 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
19189 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
19190 /*! RFC_PAUSE - Receive Frame Control Pause
19191  */
19192 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
19193 
19194 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
19195 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
19196 /*! ADDSEL - Source MAC Address Select On Transmit
19197  *  0b000..Node MAC address programmed on PADDR1/2 registers.
19198  *  0b100..Reserved.
19199  *  0b101..Reserved.
19200  *  0b110..Reserved.
19201  */
19202 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
19203 
19204 #define ENET_TCR_ADDINS_MASK                     (0x100U)
19205 #define ENET_TCR_ADDINS_SHIFT                    (8U)
19206 /*! ADDINS - Set MAC Address On Transmit
19207  *  0b0..The source MAC address is not modified by the MAC.
19208  *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
19209  */
19210 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
19211 
19212 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
19213 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
19214 /*! CRCFWD - Forward Frame From Application With CRC
19215  *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
19216  *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
19217  */
19218 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
19219 /*! @} */
19220 
19221 /*! @name PALR - Physical Address Lower Register */
19222 /*! @{ */
19223 
19224 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
19225 #define ENET_PALR_PADDR1_SHIFT                   (0U)
19226 /*! PADDR1 - Pause Address
19227  */
19228 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
19229 /*! @} */
19230 
19231 /*! @name PAUR - Physical Address Upper Register */
19232 /*! @{ */
19233 
19234 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
19235 #define ENET_PAUR_TYPE_SHIFT                     (0U)
19236 /*! TYPE - Type Field In PAUSE Frames
19237  */
19238 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
19239 
19240 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
19241 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
19242 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
19243 /*! @} */
19244 
19245 /*! @name OPD - Opcode/Pause Duration Register */
19246 /*! @{ */
19247 
19248 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
19249 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
19250 /*! PAUSE_DUR - Pause Duration
19251  */
19252 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
19253 
19254 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
19255 #define ENET_OPD_OPCODE_SHIFT                    (16U)
19256 /*! OPCODE - Opcode Field In PAUSE Frames
19257  */
19258 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
19259 /*! @} */
19260 
19261 /*! @name TXIC - Transmit Interrupt Coalescing Register */
19262 /*! @{ */
19263 
19264 #define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
19265 #define ENET_TXIC_ICTT_SHIFT                     (0U)
19266 /*! ICTT - Interrupt coalescing timer threshold
19267  */
19268 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
19269 
19270 #define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
19271 #define ENET_TXIC_ICFT_SHIFT                     (20U)
19272 /*! ICFT - Interrupt coalescing frame count threshold
19273  */
19274 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
19275 
19276 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
19277 #define ENET_TXIC_ICCS_SHIFT                     (30U)
19278 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
19279  *  0b0..Use MII/GMII TX clocks.
19280  *  0b1..Use ENET system clock.
19281  */
19282 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
19283 
19284 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
19285 #define ENET_TXIC_ICEN_SHIFT                     (31U)
19286 /*! ICEN - Interrupt Coalescing Enable
19287  *  0b0..Disable Interrupt coalescing.
19288  *  0b1..Enable Interrupt coalescing.
19289  */
19290 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
19291 /*! @} */
19292 
19293 /* The count of ENET_TXIC */
19294 #define ENET_TXIC_COUNT                          (1U)
19295 
19296 /*! @name RXIC - Receive Interrupt Coalescing Register */
19297 /*! @{ */
19298 
19299 #define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
19300 #define ENET_RXIC_ICTT_SHIFT                     (0U)
19301 /*! ICTT - Interrupt coalescing timer threshold
19302  */
19303 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
19304 
19305 #define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
19306 #define ENET_RXIC_ICFT_SHIFT                     (20U)
19307 /*! ICFT - Interrupt coalescing frame count threshold
19308  */
19309 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
19310 
19311 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
19312 #define ENET_RXIC_ICCS_SHIFT                     (30U)
19313 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
19314  *  0b0..Use MII/GMII TX clocks.
19315  *  0b1..Use ENET system clock.
19316  */
19317 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
19318 
19319 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
19320 #define ENET_RXIC_ICEN_SHIFT                     (31U)
19321 /*! ICEN - Interrupt Coalescing Enable
19322  *  0b0..Disable Interrupt coalescing.
19323  *  0b1..Enable Interrupt coalescing.
19324  */
19325 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
19326 /*! @} */
19327 
19328 /* The count of ENET_RXIC */
19329 #define ENET_RXIC_COUNT                          (1U)
19330 
19331 /*! @name IAUR - Descriptor Individual Upper Address Register */
19332 /*! @{ */
19333 
19334 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
19335 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
19336 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
19337 /*! @} */
19338 
19339 /*! @name IALR - Descriptor Individual Lower Address Register */
19340 /*! @{ */
19341 
19342 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
19343 #define ENET_IALR_IADDR2_SHIFT                   (0U)
19344 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
19345 /*! @} */
19346 
19347 /*! @name GAUR - Descriptor Group Upper Address Register */
19348 /*! @{ */
19349 
19350 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
19351 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
19352 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
19353 /*! @} */
19354 
19355 /*! @name GALR - Descriptor Group Lower Address Register */
19356 /*! @{ */
19357 
19358 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
19359 #define ENET_GALR_GADDR2_SHIFT                   (0U)
19360 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
19361 /*! @} */
19362 
19363 /*! @name TFWR - Transmit FIFO Watermark Register */
19364 /*! @{ */
19365 
19366 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
19367 #define ENET_TFWR_TFWR_SHIFT                     (0U)
19368 /*! TFWR - Transmit FIFO Write
19369  *  0b000000..64 bytes written.
19370  *  0b000001..64 bytes written.
19371  *  0b000010..128 bytes written.
19372  *  0b000011..192 bytes written.
19373  *  0b011111..1984 bytes written.
19374  */
19375 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
19376 
19377 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
19378 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
19379 /*! STRFWD - Store And Forward Enable
19380  *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
19381  *  0b1..Enabled.
19382  */
19383 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
19384 /*! @} */
19385 
19386 /*! @name RDSR - Receive Descriptor Ring 0 Start Register */
19387 /*! @{ */
19388 
19389 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
19390 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
19391 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
19392 /*! @} */
19393 
19394 /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
19395 /*! @{ */
19396 
19397 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
19398 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
19399 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
19400 /*! @} */
19401 
19402 /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
19403 /*! @{ */
19404 
19405 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)
19406 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
19407 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
19408 /*! @} */
19409 
19410 /*! @name RSFL - Receive FIFO Section Full Threshold */
19411 /*! @{ */
19412 
19413 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
19414 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
19415 /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
19416  */
19417 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
19418 /*! @} */
19419 
19420 /*! @name RSEM - Receive FIFO Section Empty Threshold */
19421 /*! @{ */
19422 
19423 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
19424 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
19425 /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
19426  */
19427 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
19428 
19429 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
19430 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
19431 /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
19432  */
19433 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
19434 /*! @} */
19435 
19436 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
19437 /*! @{ */
19438 
19439 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
19440 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
19441 /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
19442  */
19443 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
19444 /*! @} */
19445 
19446 /*! @name RAFL - Receive FIFO Almost Full Threshold */
19447 /*! @{ */
19448 
19449 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
19450 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
19451 /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
19452  */
19453 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
19454 /*! @} */
19455 
19456 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
19457 /*! @{ */
19458 
19459 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
19460 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
19461 /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
19462  */
19463 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
19464 /*! @} */
19465 
19466 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
19467 /*! @{ */
19468 
19469 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
19470 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
19471 /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
19472  */
19473 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
19474 /*! @} */
19475 
19476 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
19477 /*! @{ */
19478 
19479 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
19480 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
19481 /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
19482  */
19483 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
19484 /*! @} */
19485 
19486 /*! @name TIPG - Transmit Inter-Packet Gap */
19487 /*! @{ */
19488 
19489 #define ENET_TIPG_IPG_MASK                       (0x1FU)
19490 #define ENET_TIPG_IPG_SHIFT                      (0U)
19491 /*! IPG - Transmit Inter-Packet Gap
19492  */
19493 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
19494 /*! @} */
19495 
19496 /*! @name FTRL - Frame Truncation Length */
19497 /*! @{ */
19498 
19499 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
19500 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
19501 /*! TRUNC_FL - Frame Truncation Length
19502  */
19503 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
19504 /*! @} */
19505 
19506 /*! @name TACC - Transmit Accelerator Function Configuration */
19507 /*! @{ */
19508 
19509 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
19510 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
19511 /*! SHIFT16 - TX FIFO Shift-16
19512  *  0b0..Disabled.
19513  *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
19514  *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
19515  *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
19516  *       extended to a 16-byte header.
19517  */
19518 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
19519 
19520 #define ENET_TACC_IPCHK_MASK                     (0x8U)
19521 #define ENET_TACC_IPCHK_SHIFT                    (3U)
19522 /*! IPCHK
19523  *  0b0..Checksum is not inserted.
19524  *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
19525  *       be cleared. If a non-IP frame is transmitted the frame is not modified.
19526  */
19527 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
19528 
19529 #define ENET_TACC_PROCHK_MASK                    (0x10U)
19530 #define ENET_TACC_PROCHK_SHIFT                   (4U)
19531 /*! PROCHK
19532  *  0b0..Checksum not inserted.
19533  *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
19534  *       frame. The checksum field must be cleared. The other frames are not modified.
19535  */
19536 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
19537 /*! @} */
19538 
19539 /*! @name RACC - Receive Accelerator Function Configuration */
19540 /*! @{ */
19541 
19542 #define ENET_RACC_PADREM_MASK                    (0x1U)
19543 #define ENET_RACC_PADREM_SHIFT                   (0U)
19544 /*! PADREM - Enable Padding Removal For Short IP Frames
19545  *  0b0..Padding not removed.
19546  *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
19547  */
19548 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
19549 
19550 #define ENET_RACC_IPDIS_MASK                     (0x2U)
19551 #define ENET_RACC_IPDIS_SHIFT                    (1U)
19552 /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
19553  *  0b0..Frames with wrong IPv4 header checksum are not discarded.
19554  *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
19555  *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
19556  *       store and forward mode (RSFL cleared).
19557  */
19558 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
19559 
19560 #define ENET_RACC_PRODIS_MASK                    (0x4U)
19561 #define ENET_RACC_PRODIS_SHIFT                   (2U)
19562 /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
19563  *  0b0..Frames with wrong checksum are not discarded.
19564  *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
19565  *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
19566  *       cleared).
19567  */
19568 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
19569 
19570 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
19571 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
19572 /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
19573  *  0b0..Frames with errors are not discarded.
19574  *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
19575  */
19576 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
19577 
19578 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
19579 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
19580 /*! SHIFT16 - RX FIFO Shift-16
19581  *  0b0..Disabled.
19582  *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
19583  */
19584 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
19585 /*! @} */
19586 
19587 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
19588 /*! @{ */
19589 
19590 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
19591 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
19592 /*! TXPKTS - Packet count
19593  */
19594 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
19595 /*! @} */
19596 
19597 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
19598 /*! @{ */
19599 
19600 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
19601 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
19602 /*! TXPKTS - Number of broadcast packets
19603  */
19604 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
19605 /*! @} */
19606 
19607 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
19608 /*! @{ */
19609 
19610 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
19611 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
19612 /*! TXPKTS - Number of multicast packets
19613  */
19614 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
19615 /*! @} */
19616 
19617 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
19618 /*! @{ */
19619 
19620 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
19621 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
19622 /*! TXPKTS - Number of packets with CRC/align error
19623  */
19624 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
19625 /*! @} */
19626 
19627 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
19628 /*! @{ */
19629 
19630 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
19631 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
19632 /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
19633  */
19634 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
19635 /*! @} */
19636 
19637 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
19638 /*! @{ */
19639 
19640 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
19641 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
19642 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
19643  */
19644 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
19645 /*! @} */
19646 
19647 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
19648 /*! @{ */
19649 
19650 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
19651 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
19652 /*! TXPKTS - Number of packets less than 64 bytes with bad CRC
19653  */
19654 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
19655 /*! @} */
19656 
19657 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
19658 /*! @{ */
19659 
19660 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
19661 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
19662 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
19663  */
19664 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
19665 /*! @} */
19666 
19667 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
19668 /*! @{ */
19669 
19670 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
19671 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
19672 /*! TXPKTS - Number of transmit collisions
19673  */
19674 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
19675 /*! @} */
19676 
19677 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
19678 /*! @{ */
19679 
19680 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
19681 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
19682 /*! TXPKTS - Number of 64-byte transmit packets
19683  */
19684 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
19685 /*! @} */
19686 
19687 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
19688 /*! @{ */
19689 
19690 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
19691 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
19692 /*! TXPKTS - Number of 65- to 127-byte transmit packets
19693  */
19694 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
19695 /*! @} */
19696 
19697 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
19698 /*! @{ */
19699 
19700 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
19701 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
19702 /*! TXPKTS - Number of 128- to 255-byte transmit packets
19703  */
19704 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
19705 /*! @} */
19706 
19707 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
19708 /*! @{ */
19709 
19710 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
19711 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
19712 /*! TXPKTS - Number of 256- to 511-byte transmit packets
19713  */
19714 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
19715 /*! @} */
19716 
19717 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
19718 /*! @{ */
19719 
19720 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
19721 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
19722 /*! TXPKTS - Number of 512- to 1023-byte transmit packets
19723  */
19724 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
19725 /*! @} */
19726 
19727 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
19728 /*! @{ */
19729 
19730 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
19731 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
19732 /*! TXPKTS - Number of 1024- to 2047-byte transmit packets
19733  */
19734 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
19735 /*! @} */
19736 
19737 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
19738 /*! @{ */
19739 
19740 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
19741 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
19742 /*! TXPKTS - Number of transmit packets greater than 2048 bytes
19743  */
19744 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
19745 /*! @} */
19746 
19747 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
19748 /*! @{ */
19749 
19750 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
19751 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
19752 /*! TXOCTS - Number of transmit octets
19753  */
19754 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
19755 /*! @} */
19756 
19757 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
19758 /*! @{ */
19759 
19760 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
19761 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
19762 /*! COUNT - Number of frames transmitted OK
19763  */
19764 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
19765 /*! @} */
19766 
19767 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
19768 /*! @{ */
19769 
19770 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
19771 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
19772 /*! COUNT - Number of frames transmitted with one collision
19773  */
19774 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
19775 /*! @} */
19776 
19777 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
19778 /*! @{ */
19779 
19780 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
19781 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
19782 /*! COUNT - Number of frames transmitted with multiple collisions
19783  */
19784 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
19785 /*! @} */
19786 
19787 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
19788 /*! @{ */
19789 
19790 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
19791 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
19792 /*! COUNT - Number of frames transmitted with deferral delay
19793  */
19794 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
19795 /*! @} */
19796 
19797 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
19798 /*! @{ */
19799 
19800 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
19801 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
19802 /*! COUNT - Number of frames transmitted with late collision
19803  */
19804 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
19805 /*! @} */
19806 
19807 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
19808 /*! @{ */
19809 
19810 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
19811 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
19812 /*! COUNT - Number of frames transmitted with excessive collisions
19813  */
19814 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
19815 /*! @} */
19816 
19817 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
19818 /*! @{ */
19819 
19820 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
19821 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
19822 /*! COUNT - Number of frames transmitted with transmit FIFO underrun
19823  */
19824 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
19825 /*! @} */
19826 
19827 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
19828 /*! @{ */
19829 
19830 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
19831 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
19832 /*! COUNT - Number of frames transmitted with carrier sense error
19833  */
19834 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
19835 /*! @} */
19836 
19837 /*! @name IEEE_T_SQE - Reserved Statistic Register */
19838 /*! @{ */
19839 
19840 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
19841 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
19842 /*! COUNT - This read-only field is reserved and always has the value 0
19843  */
19844 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
19845 /*! @} */
19846 
19847 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
19848 /*! @{ */
19849 
19850 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
19851 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
19852 /*! COUNT - Number of flow-control pause frames transmitted
19853  */
19854 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
19855 /*! @} */
19856 
19857 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
19858 /*! @{ */
19859 
19860 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
19861 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
19862 /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
19863  */
19864 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
19865 /*! @} */
19866 
19867 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
19868 /*! @{ */
19869 
19870 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
19871 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
19872 /*! COUNT - Number of packets received
19873  */
19874 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
19875 /*! @} */
19876 
19877 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
19878 /*! @{ */
19879 
19880 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
19881 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
19882 /*! COUNT - Number of receive broadcast packets
19883  */
19884 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
19885 /*! @} */
19886 
19887 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
19888 /*! @{ */
19889 
19890 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
19891 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
19892 /*! COUNT - Number of receive multicast packets
19893  */
19894 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
19895 /*! @} */
19896 
19897 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
19898 /*! @{ */
19899 
19900 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
19901 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
19902 /*! COUNT - Number of receive packets with CRC or align error
19903  */
19904 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
19905 /*! @} */
19906 
19907 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
19908 /*! @{ */
19909 
19910 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
19911 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
19912 /*! COUNT - Number of receive packets with less than 64 bytes and good CRC
19913  */
19914 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
19915 /*! @} */
19916 
19917 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
19918 /*! @{ */
19919 
19920 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
19921 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
19922 /*! COUNT - Number of receive packets greater than MAX_FL and good CRC
19923  */
19924 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
19925 /*! @} */
19926 
19927 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
19928 /*! @{ */
19929 
19930 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
19931 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
19932 /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
19933  */
19934 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
19935 /*! @} */
19936 
19937 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
19938 /*! @{ */
19939 
19940 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
19941 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
19942 /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
19943  */
19944 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
19945 /*! @} */
19946 
19947 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
19948 /*! @{ */
19949 
19950 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
19951 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
19952 /*! COUNT - Number of 64-byte receive packets
19953  */
19954 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
19955 /*! @} */
19956 
19957 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
19958 /*! @{ */
19959 
19960 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
19961 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
19962 /*! COUNT - Number of 65- to 127-byte recieve packets
19963  */
19964 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
19965 /*! @} */
19966 
19967 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
19968 /*! @{ */
19969 
19970 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
19971 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
19972 /*! COUNT - Number of 128- to 255-byte recieve packets
19973  */
19974 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
19975 /*! @} */
19976 
19977 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
19978 /*! @{ */
19979 
19980 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
19981 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
19982 /*! COUNT - Number of 256- to 511-byte recieve packets
19983  */
19984 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
19985 /*! @} */
19986 
19987 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
19988 /*! @{ */
19989 
19990 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
19991 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
19992 /*! COUNT - Number of 512- to 1023-byte recieve packets
19993  */
19994 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
19995 /*! @} */
19996 
19997 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
19998 /*! @{ */
19999 
20000 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
20001 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
20002 /*! COUNT - Number of 1024- to 2047-byte recieve packets
20003  */
20004 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
20005 /*! @} */
20006 
20007 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
20008 /*! @{ */
20009 
20010 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
20011 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
20012 /*! COUNT - Number of greater-than-2048-byte recieve packets
20013  */
20014 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
20015 /*! @} */
20016 
20017 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
20018 /*! @{ */
20019 
20020 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
20021 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
20022 /*! COUNT - Number of receive octets
20023  */
20024 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
20025 /*! @} */
20026 
20027 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
20028 /*! @{ */
20029 
20030 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
20031 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
20032 /*! COUNT - Frame count
20033  */
20034 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
20035 /*! @} */
20036 
20037 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
20038 /*! @{ */
20039 
20040 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
20041 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
20042 /*! COUNT - Number of frames received OK
20043  */
20044 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
20045 /*! @} */
20046 
20047 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
20048 /*! @{ */
20049 
20050 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
20051 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
20052 /*! COUNT - Number of frames received with CRC error
20053  */
20054 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
20055 /*! @} */
20056 
20057 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
20058 /*! @{ */
20059 
20060 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
20061 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
20062 /*! COUNT - Number of frames received with alignment error
20063  */
20064 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
20065 /*! @} */
20066 
20067 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
20068 /*! @{ */
20069 
20070 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
20071 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
20072 /*! COUNT - Receive FIFO overflow count
20073  */
20074 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
20075 /*! @} */
20076 
20077 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
20078 /*! @{ */
20079 
20080 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
20081 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
20082 /*! COUNT - Number of flow-control pause frames received
20083  */
20084 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
20085 /*! @} */
20086 
20087 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
20088 /*! @{ */
20089 
20090 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
20091 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
20092 /*! COUNT - Number of octets for frames received without error
20093  */
20094 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
20095 /*! @} */
20096 
20097 /*! @name ATCR - Adjustable Timer Control Register */
20098 /*! @{ */
20099 
20100 #define ENET_ATCR_EN_MASK                        (0x1U)
20101 #define ENET_ATCR_EN_SHIFT                       (0U)
20102 /*! EN - Enable Timer
20103  *  0b0..The timer stops at the current value.
20104  *  0b1..The timer starts incrementing.
20105  */
20106 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
20107 
20108 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
20109 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
20110 /*! OFFEN - Enable One-Shot Offset Event
20111  *  0b0..Disable.
20112  *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
20113  *       when the offset event is reached, so no further event occurs until the field is set again. The timer
20114  *       offset value must be set before setting this field.
20115  */
20116 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
20117 
20118 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
20119 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
20120 /*! OFFRST - Reset Timer On Offset Event
20121  *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
20122  *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
20123  */
20124 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
20125 
20126 #define ENET_ATCR_PEREN_MASK                     (0x10U)
20127 #define ENET_ATCR_PEREN_SHIFT                    (4U)
20128 /*! PEREN - Enable Periodical Event
20129  *  0b0..Disable.
20130  *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
20131  *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
20132  *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
20133  */
20134 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
20135 
20136 #define ENET_ATCR_PINPER_MASK                    (0x80U)
20137 #define ENET_ATCR_PINPER_SHIFT                   (7U)
20138 /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
20139  *  0b0..Disable.
20140  *  0b1..Enable.
20141  */
20142 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
20143 
20144 #define ENET_ATCR_RESTART_MASK                   (0x200U)
20145 #define ENET_ATCR_RESTART_SHIFT                  (9U)
20146 /*! RESTART - Reset Timer
20147  */
20148 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
20149 
20150 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
20151 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
20152 /*! CAPTURE - Capture Timer Value
20153  *  0b0..No effect.
20154  *  0b1..The current time is captured and can be read from the ATVR register.
20155  */
20156 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
20157 
20158 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
20159 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
20160 /*! SLAVE - Enable Timer Slave Mode
20161  *  0b0..The timer is active and all configuration fields in this register are relevant.
20162  *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
20163  *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
20164  */
20165 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
20166 /*! @} */
20167 
20168 /*! @name ATVR - Timer Value Register */
20169 /*! @{ */
20170 
20171 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
20172 #define ENET_ATVR_ATIME_SHIFT                    (0U)
20173 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
20174 /*! @} */
20175 
20176 /*! @name ATOFF - Timer Offset Register */
20177 /*! @{ */
20178 
20179 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
20180 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
20181 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
20182 /*! @} */
20183 
20184 /*! @name ATPER - Timer Period Register */
20185 /*! @{ */
20186 
20187 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
20188 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
20189 /*! PERIOD - Value for generating periodic events
20190  */
20191 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
20192 /*! @} */
20193 
20194 /*! @name ATCOR - Timer Correction Register */
20195 /*! @{ */
20196 
20197 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
20198 #define ENET_ATCOR_COR_SHIFT                     (0U)
20199 /*! COR - Correction Counter Wrap-Around Value
20200  */
20201 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
20202 /*! @} */
20203 
20204 /*! @name ATINC - Time-Stamping Clock Period Register */
20205 /*! @{ */
20206 
20207 #define ENET_ATINC_INC_MASK                      (0x7FU)
20208 #define ENET_ATINC_INC_SHIFT                     (0U)
20209 /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
20210  */
20211 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
20212 
20213 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
20214 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
20215 /*! INC_CORR - Correction Increment Value
20216  */
20217 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
20218 /*! @} */
20219 
20220 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
20221 /*! @{ */
20222 
20223 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
20224 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
20225 /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
20226  *    ff_tx_ts_frm signal asserted from the user application
20227  */
20228 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
20229 /*! @} */
20230 
20231 /*! @name TGSR - Timer Global Status Register */
20232 /*! @{ */
20233 
20234 #define ENET_TGSR_TF0_MASK                       (0x1U)
20235 #define ENET_TGSR_TF0_SHIFT                      (0U)
20236 /*! TF0 - Copy Of Timer Flag For Channel 0
20237  *  0b0..Timer Flag for Channel 0 is clear
20238  *  0b1..Timer Flag for Channel 0 is set
20239  */
20240 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
20241 
20242 #define ENET_TGSR_TF1_MASK                       (0x2U)
20243 #define ENET_TGSR_TF1_SHIFT                      (1U)
20244 /*! TF1 - Copy Of Timer Flag For Channel 1
20245  *  0b0..Timer Flag for Channel 1 is clear
20246  *  0b1..Timer Flag for Channel 1 is set
20247  */
20248 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
20249 
20250 #define ENET_TGSR_TF2_MASK                       (0x4U)
20251 #define ENET_TGSR_TF2_SHIFT                      (2U)
20252 /*! TF2 - Copy Of Timer Flag For Channel 2
20253  *  0b0..Timer Flag for Channel 2 is clear
20254  *  0b1..Timer Flag for Channel 2 is set
20255  */
20256 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
20257 
20258 #define ENET_TGSR_TF3_MASK                       (0x8U)
20259 #define ENET_TGSR_TF3_SHIFT                      (3U)
20260 /*! TF3 - Copy Of Timer Flag For Channel 3
20261  *  0b0..Timer Flag for Channel 3 is clear
20262  *  0b1..Timer Flag for Channel 3 is set
20263  */
20264 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
20265 /*! @} */
20266 
20267 /*! @name TCSR - Timer Control Status Register */
20268 /*! @{ */
20269 
20270 #define ENET_TCSR_TDRE_MASK                      (0x1U)
20271 #define ENET_TCSR_TDRE_SHIFT                     (0U)
20272 /*! TDRE - Timer DMA Request Enable
20273  *  0b0..DMA request is disabled
20274  *  0b1..DMA request is enabled
20275  */
20276 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
20277 
20278 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
20279 #define ENET_TCSR_TMODE_SHIFT                    (2U)
20280 /*! TMODE - Timer Mode
20281  *  0b0000..Timer Channel is disabled.
20282  *  0b0001..Timer Channel is configured for Input Capture on rising edge.
20283  *  0b0010..Timer Channel is configured for Input Capture on falling edge.
20284  *  0b0011..Timer Channel is configured for Input Capture on both edges.
20285  *  0b0100..Timer Channel is configured for Output Compare - software only.
20286  *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
20287  *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
20288  *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
20289  *  0b1000..Reserved
20290  *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
20291  *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
20292  *  0b110x..Reserved
20293  *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
20294  *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
20295  */
20296 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
20297 
20298 #define ENET_TCSR_TIE_MASK                       (0x40U)
20299 #define ENET_TCSR_TIE_SHIFT                      (6U)
20300 /*! TIE - Timer Interrupt Enable
20301  *  0b0..Interrupt is disabled
20302  *  0b1..Interrupt is enabled
20303  */
20304 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
20305 
20306 #define ENET_TCSR_TF_MASK                        (0x80U)
20307 #define ENET_TCSR_TF_SHIFT                       (7U)
20308 /*! TF - Timer Flag
20309  *  0b0..Input Capture or Output Compare has not occurred.
20310  *  0b1..Input Capture or Output Compare has occurred.
20311  */
20312 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
20313 
20314 #define ENET_TCSR_TPWC_MASK                      (0xF800U)
20315 #define ENET_TCSR_TPWC_SHIFT                     (11U)
20316 /*! TPWC - Timer PulseWidth Control
20317  *  0b00000..Pulse width is one 1588-clock cycle.
20318  *  0b00001..Pulse width is two 1588-clock cycles.
20319  *  0b00010..Pulse width is three 1588-clock cycles.
20320  *  0b00011..Pulse width is four 1588-clock cycles.
20321  *  0b11111..Pulse width is 32 1588-clock cycles.
20322  */
20323 #define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
20324 /*! @} */
20325 
20326 /* The count of ENET_TCSR */
20327 #define ENET_TCSR_COUNT                          (4U)
20328 
20329 /*! @name TCCR - Timer Compare Capture Register */
20330 /*! @{ */
20331 
20332 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
20333 #define ENET_TCCR_TCC_SHIFT                      (0U)
20334 /*! TCC - Timer Capture Compare
20335  */
20336 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
20337 /*! @} */
20338 
20339 /* The count of ENET_TCCR */
20340 #define ENET_TCCR_COUNT                          (4U)
20341 
20342 
20343 /*!
20344  * @}
20345  */ /* end of group ENET_Register_Masks */
20346 
20347 
20348 /* ENET - Peripheral instance base addresses */
20349 /** Peripheral ENET base address */
20350 #define ENET_BASE                                (0x402D8000u)
20351 /** Peripheral ENET base pointer */
20352 #define ENET                                     ((ENET_Type *)ENET_BASE)
20353 /** Array initializer of ENET peripheral base addresses */
20354 #define ENET_BASE_ADDRS                          { ENET_BASE }
20355 /** Array initializer of ENET peripheral base pointers */
20356 #define ENET_BASE_PTRS                           { ENET }
20357 /** Interrupt vectors for the ENET peripheral type */
20358 #define ENET_Transmit_IRQS                       { ENET_IRQn }
20359 #define ENET_Receive_IRQS                        { ENET_IRQn }
20360 #define ENET_Error_IRQS                          { ENET_IRQn }
20361 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
20362 #define ENET_Ts_IRQS                             { ENET_IRQn }
20363 /* ENET Buffer Descriptor and Buffer Address Alignment. */
20364 #define ENET_BUFF_ALIGNMENT                      (64U)
20365 
20366 
20367 /*!
20368  * @}
20369  */ /* end of group ENET_Peripheral_Access_Layer */
20370 
20371 
20372 /* ----------------------------------------------------------------------------
20373    -- EWM Peripheral Access Layer
20374    ---------------------------------------------------------------------------- */
20375 
20376 /*!
20377  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
20378  * @{
20379  */
20380 
20381 /** EWM - Register Layout Typedef */
20382 typedef struct {
20383   __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
20384   __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
20385   __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
20386   __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
20387   __IO uint8_t CLKCTRL;                            /**< Clock Control Register, offset: 0x4 */
20388   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
20389 } EWM_Type;
20390 
20391 /* ----------------------------------------------------------------------------
20392    -- EWM Register Masks
20393    ---------------------------------------------------------------------------- */
20394 
20395 /*!
20396  * @addtogroup EWM_Register_Masks EWM Register Masks
20397  * @{
20398  */
20399 
20400 /*! @name CTRL - Control Register */
20401 /*! @{ */
20402 
20403 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
20404 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
20405 /*! EWMEN - EWM enable.
20406  */
20407 #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
20408 
20409 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
20410 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
20411 /*! ASSIN - EWM_in's Assertion State Select.
20412  */
20413 #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
20414 
20415 #define EWM_CTRL_INEN_MASK                       (0x4U)
20416 #define EWM_CTRL_INEN_SHIFT                      (2U)
20417 /*! INEN - Input Enable.
20418  */
20419 #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
20420 
20421 #define EWM_CTRL_INTEN_MASK                      (0x8U)
20422 #define EWM_CTRL_INTEN_SHIFT                     (3U)
20423 /*! INTEN - Interrupt Enable.
20424  */
20425 #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
20426 /*! @} */
20427 
20428 /*! @name SERV - Service Register */
20429 /*! @{ */
20430 
20431 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
20432 #define EWM_SERV_SERVICE_SHIFT                   (0U)
20433 /*! SERVICE - SERVICE
20434  */
20435 #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
20436 /*! @} */
20437 
20438 /*! @name CMPL - Compare Low Register */
20439 /*! @{ */
20440 
20441 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
20442 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
20443 /*! COMPAREL - COMPAREL
20444  */
20445 #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
20446 /*! @} */
20447 
20448 /*! @name CMPH - Compare High Register */
20449 /*! @{ */
20450 
20451 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
20452 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
20453 /*! COMPAREH - COMPAREH
20454  */
20455 #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
20456 /*! @} */
20457 
20458 /*! @name CLKCTRL - Clock Control Register */
20459 /*! @{ */
20460 
20461 #define EWM_CLKCTRL_CLKSEL_MASK                  (0x3U)
20462 #define EWM_CLKCTRL_CLKSEL_SHIFT                 (0U)
20463 /*! CLKSEL - CLKSEL
20464  */
20465 #define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
20466 /*! @} */
20467 
20468 /*! @name CLKPRESCALER - Clock Prescaler Register */
20469 /*! @{ */
20470 
20471 #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
20472 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
20473 /*! CLK_DIV - CLK_DIV
20474  */
20475 #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
20476 /*! @} */
20477 
20478 
20479 /*!
20480  * @}
20481  */ /* end of group EWM_Register_Masks */
20482 
20483 
20484 /* EWM - Peripheral instance base addresses */
20485 /** Peripheral EWM base address */
20486 #define EWM_BASE                                 (0x400B4000u)
20487 /** Peripheral EWM base pointer */
20488 #define EWM                                      ((EWM_Type *)EWM_BASE)
20489 /** Array initializer of EWM peripheral base addresses */
20490 #define EWM_BASE_ADDRS                           { EWM_BASE }
20491 /** Array initializer of EWM peripheral base pointers */
20492 #define EWM_BASE_PTRS                            { EWM }
20493 /** Interrupt vectors for the EWM peripheral type */
20494 #define EWM_IRQS                                 { EWM_IRQn }
20495 
20496 /*!
20497  * @}
20498  */ /* end of group EWM_Peripheral_Access_Layer */
20499 
20500 
20501 /* ----------------------------------------------------------------------------
20502    -- FLEXIO Peripheral Access Layer
20503    ---------------------------------------------------------------------------- */
20504 
20505 /*!
20506  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
20507  * @{
20508  */
20509 
20510 /** FLEXIO - Register Layout Typedef */
20511 typedef struct {
20512   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
20513   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
20514   __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
20515   __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
20516   __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
20517   __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
20518   __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
20519        uint8_t RESERVED_0[4];
20520   __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
20521   __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
20522   __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
20523        uint8_t RESERVED_1[4];
20524   __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
20525        uint8_t RESERVED_2[12];
20526   __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
20527        uint8_t RESERVED_3[60];
20528   __IO uint32_t SHIFTCTL[4];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
20529        uint8_t RESERVED_4[112];
20530   __IO uint32_t SHIFTCFG[4];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
20531        uint8_t RESERVED_5[240];
20532   __IO uint32_t SHIFTBUF[4];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
20533        uint8_t RESERVED_6[112];
20534   __IO uint32_t SHIFTBUFBIS[4];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
20535        uint8_t RESERVED_7[112];
20536   __IO uint32_t SHIFTBUFBYS[4];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
20537        uint8_t RESERVED_8[112];
20538   __IO uint32_t SHIFTBUFBBS[4];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
20539        uint8_t RESERVED_9[112];
20540   __IO uint32_t TIMCTL[4];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
20541        uint8_t RESERVED_10[112];
20542   __IO uint32_t TIMCFG[4];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
20543        uint8_t RESERVED_11[112];
20544   __IO uint32_t TIMCMP[4];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
20545        uint8_t RESERVED_12[368];
20546   __IO uint32_t SHIFTBUFNBS[4];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
20547        uint8_t RESERVED_13[112];
20548   __IO uint32_t SHIFTBUFHWS[4];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
20549        uint8_t RESERVED_14[112];
20550   __IO uint32_t SHIFTBUFNIS[4];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
20551 } FLEXIO_Type;
20552 
20553 /* ----------------------------------------------------------------------------
20554    -- FLEXIO Register Masks
20555    ---------------------------------------------------------------------------- */
20556 
20557 /*!
20558  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
20559  * @{
20560  */
20561 
20562 /*! @name VERID - Version ID Register */
20563 /*! @{ */
20564 
20565 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
20566 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
20567 /*! FEATURE - Feature Specification Number
20568  *  0b0000000000000000..Standard features implemented.
20569  *  0b0000000000000001..Supports state, logic and parallel modes.
20570  */
20571 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
20572 
20573 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
20574 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
20575 /*! MINOR - Minor Version Number
20576  */
20577 #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
20578 
20579 #define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
20580 #define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
20581 /*! MAJOR - Major Version Number
20582  */
20583 #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
20584 /*! @} */
20585 
20586 /*! @name PARAM - Parameter Register */
20587 /*! @{ */
20588 
20589 #define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
20590 #define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
20591 /*! SHIFTER - Shifter Number
20592  */
20593 #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
20594 
20595 #define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
20596 #define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
20597 /*! TIMER - Timer Number
20598  */
20599 #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
20600 
20601 #define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
20602 #define FLEXIO_PARAM_PIN_SHIFT                   (16U)
20603 /*! PIN - Pin Number
20604  */
20605 #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
20606 
20607 #define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
20608 #define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
20609 /*! TRIGGER - Trigger Number
20610  */
20611 #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
20612 /*! @} */
20613 
20614 /*! @name CTRL - FlexIO Control Register */
20615 /*! @{ */
20616 
20617 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
20618 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
20619 /*! FLEXEN - FlexIO Enable
20620  *  0b0..FlexIO module is disabled.
20621  *  0b1..FlexIO module is enabled.
20622  */
20623 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
20624 
20625 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
20626 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
20627 /*! SWRST - Software Reset
20628  *  0b0..Software reset is disabled
20629  *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
20630  */
20631 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
20632 
20633 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
20634 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
20635 /*! FASTACC - Fast Access
20636  *  0b0..Configures for normal register accesses to FlexIO
20637  *  0b1..Configures for fast register accesses to FlexIO
20638  */
20639 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
20640 
20641 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
20642 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
20643 /*! DBGE - Debug Enable
20644  *  0b0..FlexIO is disabled in debug modes.
20645  *  0b1..FlexIO is enabled in debug modes
20646  */
20647 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
20648 
20649 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
20650 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
20651 /*! DOZEN - Doze Enable
20652  *  0b0..FlexIO enabled in Doze modes.
20653  *  0b1..FlexIO disabled in Doze modes.
20654  */
20655 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
20656 /*! @} */
20657 
20658 /*! @name PIN - Pin State Register */
20659 /*! @{ */
20660 
20661 #define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
20662 #define FLEXIO_PIN_PDI_SHIFT                     (0U)
20663 /*! PDI - Pin Data Input
20664  */
20665 #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)  /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
20666 /*! @} */
20667 
20668 /*! @name SHIFTSTAT - Shifter Status Register */
20669 /*! @{ */
20670 
20671 #define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFU)
20672 #define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
20673 /*! SSF - Shifter Status Flag
20674  */
20675 #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
20676 /*! @} */
20677 
20678 /*! @name SHIFTERR - Shifter Error Register */
20679 /*! @{ */
20680 
20681 #define FLEXIO_SHIFTERR_SEF_MASK                 (0xFU)
20682 #define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
20683 /*! SEF - Shifter Error Flags
20684  */
20685 #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
20686 /*! @} */
20687 
20688 /*! @name TIMSTAT - Timer Status Register */
20689 /*! @{ */
20690 
20691 #define FLEXIO_TIMSTAT_TSF_MASK                  (0xFU)
20692 #define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
20693 /*! TSF - Timer Status Flags
20694  */
20695 #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
20696 /*! @} */
20697 
20698 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
20699 /*! @{ */
20700 
20701 #define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFU)
20702 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
20703 /*! SSIE - Shifter Status Interrupt Enable
20704  */
20705 #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
20706 /*! @} */
20707 
20708 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
20709 /*! @{ */
20710 
20711 #define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFU)
20712 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
20713 /*! SEIE - Shifter Error Interrupt Enable
20714  */
20715 #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
20716 /*! @} */
20717 
20718 /*! @name TIMIEN - Timer Interrupt Enable Register */
20719 /*! @{ */
20720 
20721 #define FLEXIO_TIMIEN_TEIE_MASK                  (0xFU)
20722 #define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
20723 /*! TEIE - Timer Status Interrupt Enable
20724  */
20725 #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
20726 /*! @} */
20727 
20728 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
20729 /*! @{ */
20730 
20731 #define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFU)
20732 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
20733 /*! SSDE - Shifter Status DMA Enable
20734  */
20735 #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
20736 /*! @} */
20737 
20738 /*! @name SHIFTSTATE - Shifter State Register */
20739 /*! @{ */
20740 
20741 #define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
20742 #define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
20743 /*! STATE - Current State Pointer
20744  */
20745 #define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
20746 /*! @} */
20747 
20748 /*! @name SHIFTCTL - Shifter Control N Register */
20749 /*! @{ */
20750 
20751 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
20752 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
20753 /*! SMOD - Shifter Mode
20754  *  0b000..Disabled.
20755  *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
20756  *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
20757  *  0b011..Reserved.
20758  *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
20759  *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
20760  *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
20761  *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
20762  */
20763 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
20764 
20765 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
20766 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
20767 /*! PINPOL - Shifter Pin Polarity
20768  *  0b0..Pin is active high
20769  *  0b1..Pin is active low
20770  */
20771 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
20772 
20773 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20774 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
20775 /*! PINSEL - Shifter Pin Select
20776  */
20777 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20778 
20779 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
20780 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
20781 /*! PINCFG - Shifter Pin Configuration
20782  *  0b00..Shifter pin output disabled
20783  *  0b01..Shifter pin open drain or bidirectional output enable
20784  *  0b10..Shifter pin bidirectional output data
20785  *  0b11..Shifter pin output
20786  */
20787 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
20788 
20789 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
20790 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
20791 /*! TIMPOL - Timer Polarity
20792  *  0b0..Shift on posedge of Shift clock
20793  *  0b1..Shift on negedge of Shift clock
20794  */
20795 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
20796 
20797 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x3000000U)
20798 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
20799 /*! TIMSEL - Timer Select
20800  */
20801 #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
20802 /*! @} */
20803 
20804 /* The count of FLEXIO_SHIFTCTL */
20805 #define FLEXIO_SHIFTCTL_COUNT                    (4U)
20806 
20807 /*! @name SHIFTCFG - Shifter Configuration N Register */
20808 /*! @{ */
20809 
20810 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
20811 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
20812 /*! SSTART - Shifter Start bit
20813  *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
20814  *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
20815  *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
20816  *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
20817  */
20818 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
20819 
20820 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
20821 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
20822 /*! SSTOP - Shifter Stop bit
20823  *  0b00..Stop bit disabled for transmitter/receiver/match store
20824  *  0b01..Reserved for transmitter/receiver/match store
20825  *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
20826  *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
20827  */
20828 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
20829 
20830 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
20831 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
20832 /*! INSRC - Input Source
20833  *  0b0..Pin
20834  *  0b1..Shifter N+1 Output
20835  */
20836 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
20837 
20838 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20839 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
20840 /*! PWIDTH - Parallel Width
20841  */
20842 #define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20843 /*! @} */
20844 
20845 /* The count of FLEXIO_SHIFTCFG */
20846 #define FLEXIO_SHIFTCFG_COUNT                    (4U)
20847 
20848 /*! @name SHIFTBUF - Shifter Buffer N Register */
20849 /*! @{ */
20850 
20851 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
20852 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
20853 /*! SHIFTBUF - Shift Buffer
20854  */
20855 #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
20856 /*! @} */
20857 
20858 /* The count of FLEXIO_SHIFTBUF */
20859 #define FLEXIO_SHIFTBUF_COUNT                    (4U)
20860 
20861 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
20862 /*! @{ */
20863 
20864 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
20865 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
20866 /*! SHIFTBUFBIS - Shift Buffer
20867  */
20868 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
20869 /*! @} */
20870 
20871 /* The count of FLEXIO_SHIFTBUFBIS */
20872 #define FLEXIO_SHIFTBUFBIS_COUNT                 (4U)
20873 
20874 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
20875 /*! @{ */
20876 
20877 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
20878 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
20879 /*! SHIFTBUFBYS - Shift Buffer
20880  */
20881 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
20882 /*! @} */
20883 
20884 /* The count of FLEXIO_SHIFTBUFBYS */
20885 #define FLEXIO_SHIFTBUFBYS_COUNT                 (4U)
20886 
20887 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
20888 /*! @{ */
20889 
20890 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
20891 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
20892 /*! SHIFTBUFBBS - Shift Buffer
20893  */
20894 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
20895 /*! @} */
20896 
20897 /* The count of FLEXIO_SHIFTBUFBBS */
20898 #define FLEXIO_SHIFTBUFBBS_COUNT                 (4U)
20899 
20900 /*! @name TIMCTL - Timer Control N Register */
20901 /*! @{ */
20902 
20903 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x3U)
20904 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
20905 /*! TIMOD - Timer Mode
20906  *  0b00..Timer Disabled.
20907  *  0b01..Dual 8-bit counters baud mode.
20908  *  0b10..Dual 8-bit counters PWM high mode.
20909  *  0b11..Single 16-bit counter mode.
20910  */
20911 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
20912 
20913 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
20914 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
20915 /*! PINPOL - Timer Pin Polarity
20916  *  0b0..Pin is active high
20917  *  0b1..Pin is active low
20918  */
20919 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
20920 
20921 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20922 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
20923 /*! PINSEL - Timer Pin Select
20924  */
20925 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20926 
20927 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
20928 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
20929 /*! PINCFG - Timer Pin Configuration
20930  *  0b00..Timer pin output disabled
20931  *  0b01..Timer pin open drain or bidirectional output enable
20932  *  0b10..Timer pin bidirectional output data
20933  *  0b11..Timer pin output
20934  */
20935 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
20936 
20937 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
20938 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
20939 /*! TRGSRC - Trigger Source
20940  *  0b0..External trigger selected
20941  *  0b1..Internal trigger selected
20942  */
20943 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
20944 
20945 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
20946 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
20947 /*! TRGPOL - Trigger Polarity
20948  *  0b0..Trigger active high
20949  *  0b1..Trigger active low
20950  */
20951 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
20952 
20953 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
20954 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
20955 /*! TRGSEL - Trigger Select
20956  */
20957 #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
20958 /*! @} */
20959 
20960 /* The count of FLEXIO_TIMCTL */
20961 #define FLEXIO_TIMCTL_COUNT                      (4U)
20962 
20963 /*! @name TIMCFG - Timer Configuration N Register */
20964 /*! @{ */
20965 
20966 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
20967 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
20968 /*! TSTART - Timer Start Bit
20969  *  0b0..Start bit disabled
20970  *  0b1..Start bit enabled
20971  */
20972 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
20973 
20974 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
20975 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
20976 /*! TSTOP - Timer Stop Bit
20977  *  0b00..Stop bit disabled
20978  *  0b01..Stop bit is enabled on timer compare
20979  *  0b10..Stop bit is enabled on timer disable
20980  *  0b11..Stop bit is enabled on timer compare and timer disable
20981  */
20982 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
20983 
20984 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
20985 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
20986 /*! TIMENA - Timer Enable
20987  *  0b000..Timer always enabled
20988  *  0b001..Timer enabled on Timer N-1 enable
20989  *  0b010..Timer enabled on Trigger high
20990  *  0b011..Timer enabled on Trigger high and Pin high
20991  *  0b100..Timer enabled on Pin rising edge
20992  *  0b101..Timer enabled on Pin rising edge and Trigger high
20993  *  0b110..Timer enabled on Trigger rising edge
20994  *  0b111..Timer enabled on Trigger rising or falling edge
20995  */
20996 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
20997 
20998 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
20999 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
21000 /*! TIMDIS - Timer Disable
21001  *  0b000..Timer never disabled
21002  *  0b001..Timer disabled on Timer N-1 disable
21003  *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
21004  *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
21005  *  0b100..Timer disabled on Pin rising or falling edge
21006  *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
21007  *  0b110..Timer disabled on Trigger falling edge
21008  *  0b111..Reserved
21009  */
21010 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
21011 
21012 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
21013 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
21014 /*! TIMRST - Timer Reset
21015  *  0b000..Timer never reset
21016  *  0b001..Reserved
21017  *  0b010..Timer reset on Timer Pin equal to Timer Output
21018  *  0b011..Timer reset on Timer Trigger equal to Timer Output
21019  *  0b100..Timer reset on Timer Pin rising edge
21020  *  0b101..Reserved
21021  *  0b110..Timer reset on Trigger rising edge
21022  *  0b111..Timer reset on Trigger rising or falling edge
21023  */
21024 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
21025 
21026 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x300000U)
21027 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
21028 /*! TIMDEC - Timer Decrement
21029  *  0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
21030  *  0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
21031  *  0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
21032  *  0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
21033  */
21034 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
21035 
21036 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
21037 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
21038 /*! TIMOUT - Timer Output
21039  *  0b00..Timer output is logic one when enabled and is not affected by timer reset
21040  *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
21041  *  0b10..Timer output is logic one when enabled and on timer reset
21042  *  0b11..Timer output is logic zero when enabled and on timer reset
21043  */
21044 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
21045 /*! @} */
21046 
21047 /* The count of FLEXIO_TIMCFG */
21048 #define FLEXIO_TIMCFG_COUNT                      (4U)
21049 
21050 /*! @name TIMCMP - Timer Compare N Register */
21051 /*! @{ */
21052 
21053 #define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
21054 #define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
21055 /*! CMP - Timer Compare Value
21056  */
21057 #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
21058 /*! @} */
21059 
21060 /* The count of FLEXIO_TIMCMP */
21061 #define FLEXIO_TIMCMP_COUNT                      (4U)
21062 
21063 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
21064 /*! @{ */
21065 
21066 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
21067 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
21068 /*! SHIFTBUFNBS - Shift Buffer
21069  */
21070 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
21071 /*! @} */
21072 
21073 /* The count of FLEXIO_SHIFTBUFNBS */
21074 #define FLEXIO_SHIFTBUFNBS_COUNT                 (4U)
21075 
21076 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
21077 /*! @{ */
21078 
21079 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
21080 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
21081 /*! SHIFTBUFHWS - Shift Buffer
21082  */
21083 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
21084 /*! @} */
21085 
21086 /* The count of FLEXIO_SHIFTBUFHWS */
21087 #define FLEXIO_SHIFTBUFHWS_COUNT                 (4U)
21088 
21089 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
21090 /*! @{ */
21091 
21092 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
21093 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
21094 /*! SHIFTBUFNIS - Shift Buffer
21095  */
21096 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
21097 /*! @} */
21098 
21099 /* The count of FLEXIO_SHIFTBUFNIS */
21100 #define FLEXIO_SHIFTBUFNIS_COUNT                 (4U)
21101 
21102 
21103 /*!
21104  * @}
21105  */ /* end of group FLEXIO_Register_Masks */
21106 
21107 
21108 /* FLEXIO - Peripheral instance base addresses */
21109 /** Peripheral FLEXIO1 base address */
21110 #define FLEXIO1_BASE                             (0x401AC000u)
21111 /** Peripheral FLEXIO1 base pointer */
21112 #define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
21113 /** Peripheral FLEXIO2 base address */
21114 #define FLEXIO2_BASE                             (0x401B0000u)
21115 /** Peripheral FLEXIO2 base pointer */
21116 #define FLEXIO2                                  ((FLEXIO_Type *)FLEXIO2_BASE)
21117 /** Array initializer of FLEXIO peripheral base addresses */
21118 #define FLEXIO_BASE_ADDRS                        { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
21119 /** Array initializer of FLEXIO peripheral base pointers */
21120 #define FLEXIO_BASE_PTRS                         { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
21121 /** Interrupt vectors for the FLEXIO peripheral type */
21122 #define FLEXIO_IRQS                              { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
21123 
21124 /*!
21125  * @}
21126  */ /* end of group FLEXIO_Peripheral_Access_Layer */
21127 
21128 
21129 /* ----------------------------------------------------------------------------
21130    -- FLEXRAM Peripheral Access Layer
21131    ---------------------------------------------------------------------------- */
21132 
21133 /*!
21134  * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
21135  * @{
21136  */
21137 
21138 /** FLEXRAM - Register Layout Typedef */
21139 typedef struct {
21140   __IO uint32_t TCM_CTRL;                          /**< TCM CRTL Register, offset: 0x0 */
21141        uint8_t RESERVED_0[12];
21142   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x10 */
21143   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable Register, offset: 0x14 */
21144   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable Register, offset: 0x18 */
21145 } FLEXRAM_Type;
21146 
21147 /* ----------------------------------------------------------------------------
21148    -- FLEXRAM Register Masks
21149    ---------------------------------------------------------------------------- */
21150 
21151 /*!
21152  * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
21153  * @{
21154  */
21155 
21156 /*! @name TCM_CTRL - TCM CRTL Register */
21157 /*! @{ */
21158 
21159 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK       (0x1U)
21160 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT      (0U)
21161 /*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
21162  *  0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
21163  *  0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
21164  */
21165 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
21166 
21167 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK       (0x2U)
21168 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT      (1U)
21169 /*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
21170  *  0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
21171  *  0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
21172  */
21173 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
21174 
21175 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK       (0x4U)
21176 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT      (2U)
21177 /*! FORCE_CLK_ON - Force RAM Clock Always On
21178  */
21179 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
21180 /*! @} */
21181 
21182 /*! @name INT_STATUS - Interrupt Status Register */
21183 /*! @{ */
21184 
21185 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK  (0x8U)
21186 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
21187 /*! ITCM_ERR_STATUS - ITCM Access Error Status
21188  *  0b0..ITCM access error does not happen
21189  *  0b1..ITCM access error happens.
21190  */
21191 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
21192 
21193 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK  (0x10U)
21194 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
21195 /*! DTCM_ERR_STATUS - DTCM Access Error Status
21196  *  0b0..DTCM access error does not happen
21197  *  0b1..DTCM access error happens.
21198  */
21199 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
21200 
21201 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
21202 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
21203 /*! OCRAM_ERR_STATUS - OCRAM Access Error Status
21204  *  0b0..OCRAM access error does not happen
21205  *  0b1..OCRAM access error happens.
21206  */
21207 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
21208 /*! @} */
21209 
21210 /*! @name INT_STAT_EN - Interrupt Status Enable Register */
21211 /*! @{ */
21212 
21213 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
21214 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
21215 /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
21216  *  0b0..Masked
21217  *  0b1..Enabled
21218  */
21219 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
21220 
21221 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
21222 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
21223 /*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
21224  *  0b0..Masked
21225  *  0b1..Enabled
21226  */
21227 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
21228 
21229 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
21230 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
21231 /*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
21232  *  0b0..Masked
21233  *  0b1..Enabled
21234  */
21235 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
21236 /*! @} */
21237 
21238 /*! @name INT_SIG_EN - Interrupt Enable Register */
21239 /*! @{ */
21240 
21241 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK  (0x8U)
21242 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
21243 /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
21244  *  0b0..Masked
21245  *  0b1..Enabled
21246  */
21247 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
21248 
21249 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK  (0x10U)
21250 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
21251 /*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
21252  *  0b0..Masked
21253  *  0b1..Enabled
21254  */
21255 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
21256 
21257 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
21258 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
21259 /*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
21260  *  0b0..Masked
21261  *  0b1..Enabled
21262  */
21263 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
21264 /*! @} */
21265 
21266 
21267 /*!
21268  * @}
21269  */ /* end of group FLEXRAM_Register_Masks */
21270 
21271 
21272 /* FLEXRAM - Peripheral instance base addresses */
21273 /** Peripheral FLEXRAM base address */
21274 #define FLEXRAM_BASE                             (0x400B0000u)
21275 /** Peripheral FLEXRAM base pointer */
21276 #define FLEXRAM                                  ((FLEXRAM_Type *)FLEXRAM_BASE)
21277 /** Array initializer of FLEXRAM peripheral base addresses */
21278 #define FLEXRAM_BASE_ADDRS                       { FLEXRAM_BASE }
21279 /** Array initializer of FLEXRAM peripheral base pointers */
21280 #define FLEXRAM_BASE_PTRS                        { FLEXRAM }
21281 /** Interrupt vectors for the FLEXRAM peripheral type */
21282 #define FLEXRAM_IRQS                             { FLEXRAM_IRQn }
21283 
21284 /*!
21285  * @}
21286  */ /* end of group FLEXRAM_Peripheral_Access_Layer */
21287 
21288 
21289 /* ----------------------------------------------------------------------------
21290    -- FLEXSPI Peripheral Access Layer
21291    ---------------------------------------------------------------------------- */
21292 
21293 /*!
21294  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
21295  * @{
21296  */
21297 
21298 /** FLEXSPI - Register Layout Typedef */
21299 typedef struct {
21300   __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
21301   __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
21302   __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
21303   __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
21304   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
21305   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
21306   __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
21307   __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
21308   __IO uint32_t AHBRXBUFCR0[4];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */
21309        uint8_t RESERVED_0[48];
21310   __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
21311   __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
21312   __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
21313        uint8_t RESERVED_1[4];
21314   __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
21315        uint8_t RESERVED_2[8];
21316   __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
21317   __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
21318        uint8_t RESERVED_3[8];
21319   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
21320        uint8_t RESERVED_4[4];
21321   __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
21322   __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
21323   __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
21324        uint8_t RESERVED_5[24];
21325   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
21326   __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
21327   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
21328   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
21329   __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
21330   __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
21331        uint8_t RESERVED_6[8];
21332   __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
21333   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
21334   __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
21335 } FLEXSPI_Type;
21336 
21337 /* ----------------------------------------------------------------------------
21338    -- FLEXSPI Register Masks
21339    ---------------------------------------------------------------------------- */
21340 
21341 /*!
21342  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
21343  * @{
21344  */
21345 
21346 /*! @name MCR0 - Module Control Register 0 */
21347 /*! @{ */
21348 
21349 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
21350 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
21351 /*! SWRESET - Software Reset
21352  */
21353 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
21354 
21355 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
21356 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
21357 /*! MDIS - Module Disable
21358  */
21359 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
21360 
21361 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
21362 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
21363 /*! RXCLKSRC - Sample Clock source selection for Flash Reading
21364  *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
21365  *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
21366  *  0b10..Reserved
21367  *  0b11..Flash provided Read strobe and input from DQS pad
21368  */
21369 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
21370 
21371 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
21372 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
21373 /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
21374  *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
21375  *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
21376  */
21377 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
21378 
21379 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
21380 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
21381 /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
21382  *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
21383  *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
21384  */
21385 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
21386 
21387 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
21388 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
21389 /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
21390  *  0b000..Divided by 1
21391  *  0b001..Divided by 2
21392  *  0b010..Divided by 3
21393  *  0b011..Divided by 4
21394  *  0b100..Divided by 5
21395  *  0b101..Divided by 6
21396  *  0b110..Divided by 7
21397  *  0b111..Divided by 8
21398  */
21399 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
21400 
21401 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
21402 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
21403 /*! HSEN - Half Speed Serial Flash access Enable.
21404  *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
21405  *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
21406  */
21407 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
21408 
21409 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
21410 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
21411 /*! DOZEEN - Doze mode enable bit
21412  *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
21413  *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
21414  */
21415 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
21416 
21417 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
21418 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
21419 /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
21420  *  0b0..Disable.
21421  *  0b1..Enable.
21422  */
21423 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
21424 
21425 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
21426 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
21427 /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
21428  *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
21429  *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
21430  *  0b0..Disable.
21431  *  0b1..Enable.
21432  */
21433 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
21434 
21435 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
21436 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
21437 /*! IPGRANTWAIT - Time out wait cycle for IP command grant.
21438  */
21439 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
21440 
21441 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
21442 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
21443 /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
21444  */
21445 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
21446 /*! @} */
21447 
21448 /*! @name MCR1 - Module Control Register 1 */
21449 /*! @{ */
21450 
21451 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
21452 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
21453 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
21454 
21455 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
21456 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
21457 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
21458 /*! @} */
21459 
21460 /*! @name MCR2 - Module Control Register 2 */
21461 /*! @{ */
21462 
21463 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
21464 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
21465 /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
21466  *    automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
21467  *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
21468  *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
21469  *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
21470  *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
21471  */
21472 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
21473 
21474 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
21475 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
21476 /*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
21477  *    written with 0x1. This bit will be auto-cleared immediately.
21478  */
21479 #define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
21480 
21481 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
21482 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
21483 /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
21484  *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
21485  *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
21486  *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
21487  *       ignored.
21488  *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
21489  */
21490 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
21491 
21492 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
21493 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
21494 /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
21495  *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
21496  *    field, MCR0[SWRESET] should be set.
21497  *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
21498  *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
21499  */
21500 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
21501 
21502 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
21503 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
21504 /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
21505  */
21506 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
21507 /*! @} */
21508 
21509 /*! @name AHBCR - AHB Bus Control Register */
21510 /*! @{ */
21511 
21512 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
21513 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
21514 /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
21515  *  0b0..Flash will be accessed in Individual mode.
21516  *  0b1..Flash will be accessed in Parallel mode.
21517  */
21518 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
21519 
21520 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
21521 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
21522 /*! CACHABLEEN - Enable AHB bus cachable read access support.
21523  *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
21524  *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
21525  */
21526 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
21527 
21528 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
21529 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
21530 /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
21531  *    of AHB write access, refer for more details about AHB bufferable write.
21532  *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
21533  *       ready after all data is transmitted to External device and AHB command finished.
21534  *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
21535  *       granted by arbitrator and will not wait for AHB command finished.
21536  */
21537 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
21538 
21539 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
21540 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
21541 /*! PREFETCHEN - AHB Read Prefetch Enable.
21542  */
21543 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
21544 
21545 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
21546 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
21547 /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
21548  *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
21549  *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
21550  *       burst required to meet the alignment requirement.
21551  */
21552 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
21553 /*! @} */
21554 
21555 /*! @name INTEN - Interrupt Enable Register */
21556 /*! @{ */
21557 
21558 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
21559 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
21560 /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
21561  */
21562 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
21563 
21564 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
21565 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
21566 /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
21567  */
21568 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
21569 
21570 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
21571 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
21572 /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
21573  */
21574 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
21575 
21576 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
21577 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
21578 /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
21579  */
21580 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
21581 
21582 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
21583 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
21584 /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
21585  */
21586 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
21587 
21588 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
21589 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
21590 /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
21591  */
21592 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
21593 
21594 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
21595 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
21596 /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
21597  */
21598 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
21599 
21600 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
21601 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
21602 /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
21603  */
21604 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
21605 
21606 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
21607 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
21608 /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
21609  */
21610 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
21611 
21612 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
21613 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
21614 /*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
21615  */
21616 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
21617 
21618 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
21619 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
21620 /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
21621  */
21622 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
21623 /*! @} */
21624 
21625 /*! @name INTR - Interrupt Register */
21626 /*! @{ */
21627 
21628 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
21629 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
21630 /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
21631  *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
21632  */
21633 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
21634 
21635 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
21636 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
21637 /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
21638  */
21639 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
21640 
21641 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
21642 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
21643 /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
21644  */
21645 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
21646 
21647 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
21648 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
21649 /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
21650  *    IP command, this command will be ignored and not executed at all.
21651  */
21652 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
21653 
21654 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
21655 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
21656 /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
21657  *    AHB command, this command will be ignored and not executed at all.
21658  */
21659 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
21660 
21661 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
21662 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
21663 /*! IPRXWA - IP RX FIFO watermark available interrupt.
21664  */
21665 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
21666 
21667 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
21668 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
21669 /*! IPTXWE - IP TX FIFO watermark empty interrupt.
21670  */
21671 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
21672 
21673 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
21674 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
21675 /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
21676  */
21677 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
21678 
21679 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
21680 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
21681 /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
21682  */
21683 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
21684 
21685 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
21686 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
21687 /*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
21688  */
21689 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
21690 
21691 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
21692 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
21693 /*! SEQTIMEOUT - Sequence execution timeout interrupt.
21694  */
21695 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
21696 /*! @} */
21697 
21698 /*! @name LUTKEY - LUT Key Register */
21699 /*! @{ */
21700 
21701 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
21702 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
21703 /*! KEY - The Key to lock or unlock LUT.
21704  */
21705 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
21706 /*! @} */
21707 
21708 /*! @name LUTCR - LUT Control Register */
21709 /*! @{ */
21710 
21711 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
21712 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
21713 /*! LOCK - Lock LUT
21714  */
21715 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
21716 
21717 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
21718 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
21719 /*! UNLOCK - Unlock LUT
21720  */
21721 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
21722 /*! @} */
21723 
21724 /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */
21725 /*! @{ */
21726 
21727 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0xFFU)
21728 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
21729 /*! BUFSZ - AHB RX Buffer Size in 64 bits.
21730  */
21731 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
21732 
21733 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
21734 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
21735 /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
21736  */
21737 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
21738 
21739 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x3000000U)
21740 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
21741 /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned.
21742  */
21743 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
21744 
21745 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
21746 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
21747 /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
21748  */
21749 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
21750 /*! @} */
21751 
21752 /* The count of FLEXSPI_AHBRXBUFCR0 */
21753 #define FLEXSPI_AHBRXBUFCR0_COUNT                (4U)
21754 
21755 /*! @name FLSHCR0 - Flash Control Register 0 */
21756 /*! @{ */
21757 
21758 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
21759 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
21760 /*! FLSHSZ - Flash Size in KByte.
21761  */
21762 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
21763 /*! @} */
21764 
21765 /* The count of FLEXSPI_FLSHCR0 */
21766 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
21767 
21768 /*! @name FLSHCR1 - Flash Control Register 1 */
21769 /*! @{ */
21770 
21771 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
21772 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
21773 /*! TCSS - Serial Flash CS setup time.
21774  */
21775 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
21776 
21777 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
21778 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
21779 /*! TCSH - Serial Flash CS Hold time.
21780  */
21781 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
21782 
21783 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
21784 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
21785 /*! WA - Word Addressable.
21786  */
21787 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
21788 
21789 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
21790 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
21791 /*! CAS - Column Address Size.
21792  */
21793 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
21794 
21795 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
21796 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
21797 /*! CSINTERVALUNIT - CS interval unit
21798  *  0b0..The CS interval unit is 1 serial clock cycle
21799  *  0b1..The CS interval unit is 256 serial clock cycle
21800  */
21801 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
21802 
21803 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
21804 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
21805 /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
21806  *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
21807  *    the interval between command sequences, this field should be set accordingly. If there is no
21808  *    limitation, set this field with value 0x0.
21809  */
21810 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
21811 /*! @} */
21812 
21813 /* The count of FLEXSPI_FLSHCR1 */
21814 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
21815 
21816 /*! @name FLSHCR2 - Flash Control Register 2 */
21817 /*! @{ */
21818 
21819 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
21820 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
21821 /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
21822  */
21823 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
21824 
21825 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
21826 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
21827 /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
21828  */
21829 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
21830 
21831 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
21832 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
21833 /*! AWRSEQID - Sequence Index for AHB Write triggered Command.
21834  */
21835 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
21836 
21837 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
21838 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
21839 /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
21840  */
21841 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
21842 
21843 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
21844 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
21845 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
21846 
21847 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
21848 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
21849 /*! AWRWAITUNIT - AWRWAIT unit
21850  *  0b000..The AWRWAIT unit is 2 ahb clock cycle
21851  *  0b001..The AWRWAIT unit is 8 ahb clock cycle
21852  *  0b010..The AWRWAIT unit is 32 ahb clock cycle
21853  *  0b011..The AWRWAIT unit is 128 ahb clock cycle
21854  *  0b100..The AWRWAIT unit is 512 ahb clock cycle
21855  *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
21856  *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
21857  *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
21858  */
21859 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
21860 
21861 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
21862 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
21863 /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
21864  *    Refer Programmable Sequence Engine for details.
21865  */
21866 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
21867 /*! @} */
21868 
21869 /* The count of FLEXSPI_FLSHCR2 */
21870 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
21871 
21872 /*! @name FLSHCR4 - Flash Control Register 4 */
21873 /*! @{ */
21874 
21875 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
21876 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
21877 /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
21878  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
21879  *       burst start address alignment when flash is accessed in individual mode.
21880  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
21881  *       burst start address alignment when flash is accessed in individual mode.
21882  */
21883 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
21884 
21885 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
21886 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
21887 /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
21888  *    memory device on port A, this bit must be set.
21889  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
21890  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
21891  */
21892 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
21893 
21894 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
21895 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
21896 /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
21897  *    memory device on port B, this bit must be set.
21898  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
21899  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
21900  */
21901 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
21902 /*! @} */
21903 
21904 /*! @name IPCR0 - IP Control Register 0 */
21905 /*! @{ */
21906 
21907 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
21908 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
21909 /*! SFAR - Serial Flash Address for IP command.
21910  */
21911 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
21912 /*! @} */
21913 
21914 /*! @name IPCR1 - IP Control Register 1 */
21915 /*! @{ */
21916 
21917 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
21918 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
21919 /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
21920  */
21921 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
21922 
21923 #define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
21924 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
21925 /*! ISEQID - Sequence Index in LUT for IP command.
21926  */
21927 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
21928 
21929 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
21930 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
21931 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
21932  */
21933 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
21934 
21935 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
21936 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
21937 /*! IPAREN - Parallel mode Enabled for IP command.
21938  *  0b0..Flash will be accessed in Individual mode.
21939  *  0b1..Flash will be accessed in Parallel mode.
21940  */
21941 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
21942 /*! @} */
21943 
21944 /*! @name IPCMD - IP Command Register */
21945 /*! @{ */
21946 
21947 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
21948 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
21949 /*! TRG - Setting this bit will trigger an IP Command.
21950  */
21951 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
21952 /*! @} */
21953 
21954 /*! @name IPRXFCR - IP RX FIFO Control Register */
21955 /*! @{ */
21956 
21957 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
21958 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
21959 /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
21960  */
21961 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
21962 
21963 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
21964 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
21965 /*! RXDMAEN - IP RX FIFO reading by DMA enabled.
21966  *  0b0..IP RX FIFO would be read by processor.
21967  *  0b1..IP RX FIFO would be read by DMA.
21968  */
21969 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
21970 
21971 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x3CU)
21972 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
21973 /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
21974  */
21975 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
21976 /*! @} */
21977 
21978 /*! @name IPTXFCR - IP TX FIFO Control Register */
21979 /*! @{ */
21980 
21981 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
21982 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
21983 /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
21984  */
21985 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
21986 
21987 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
21988 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
21989 /*! TXDMAEN - IP TX FIFO filling by DMA enabled.
21990  *  0b0..IP TX FIFO would be filled by processor.
21991  *  0b1..IP TX FIFO would be filled by DMA.
21992  */
21993 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
21994 
21995 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x3CU)
21996 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
21997 /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
21998  */
21999 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
22000 /*! @} */
22001 
22002 /*! @name DLLCR - DLL Control Register 0 */
22003 /*! @{ */
22004 
22005 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
22006 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
22007 /*! DLLEN - DLL calibration enable.
22008  */
22009 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
22010 
22011 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
22012 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
22013 /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
22014  *    DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
22015  *    action is edge triggered, so software need to clear this bit after set this bit (no delay
22016  *    limitation).
22017  */
22018 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
22019 
22020 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
22021 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
22022 /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock).
22023  */
22024 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
22025 
22026 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
22027 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
22028 /*! OVRDEN - Slave clock delay line delay cell number selection override enable.
22029  */
22030 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
22031 
22032 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
22033 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
22034 /*! OVRDVAL - Slave clock delay line delay cell number selection override value.
22035  */
22036 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
22037 /*! @} */
22038 
22039 /* The count of FLEXSPI_DLLCR */
22040 #define FLEXSPI_DLLCR_COUNT                      (2U)
22041 
22042 /*! @name STS0 - Status Register 0 */
22043 /*! @{ */
22044 
22045 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
22046 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
22047 /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
22048  *    sequence executing on FlexSPI interface.
22049  */
22050 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
22051 
22052 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
22053 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
22054 /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
22055  *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
22056  *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
22057  *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
22058  */
22059 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
22060 
22061 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
22062 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
22063 /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
22064  *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
22065  *  0b00..Triggered by AHB read command (triggered by AHB read).
22066  *  0b01..Triggered by AHB write command (triggered by AHB Write).
22067  *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
22068  *  0b11..Triggered by suspended command (resumed).
22069  */
22070 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
22071 /*! @} */
22072 
22073 /*! @name STS1 - Status Register 1 */
22074 /*! @{ */
22075 
22076 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
22077 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
22078 /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
22079  *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
22080  */
22081 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
22082 
22083 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
22084 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
22085 /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
22086  *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
22087  *  0b0000..No error.
22088  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
22089  *  0b0011..There is unknown instruction opcode in the sequence.
22090  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
22091  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
22092  *  0b1110..Sequence execution timeout.
22093  */
22094 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
22095 
22096 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
22097 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
22098 /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
22099  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
22100  */
22101 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
22102 
22103 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
22104 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
22105 /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
22106  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
22107  *  0b0000..No error.
22108  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
22109  *  0b0011..There is unknown instruction opcode in the sequence.
22110  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
22111  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
22112  *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
22113  *  0b1110..Sequence execution timeout.
22114  *  0b1111..Flash boundary crossed.
22115  */
22116 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
22117 /*! @} */
22118 
22119 /*! @name STS2 - Status Register 2 */
22120 /*! @{ */
22121 
22122 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
22123 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
22124 /*! ASLVLOCK - Flash A sample clock slave delay line locked.
22125  */
22126 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
22127 
22128 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
22129 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
22130 /*! AREFLOCK - Flash A sample clock reference delay line locked.
22131  */
22132 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
22133 
22134 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
22135 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
22136 /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
22137  */
22138 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
22139 
22140 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
22141 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
22142 /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
22143  */
22144 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
22145 
22146 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
22147 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
22148 /*! BSLVLOCK - Flash B sample clock slave delay line locked.
22149  */
22150 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
22151 
22152 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
22153 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
22154 /*! BREFLOCK - Flash B sample clock reference delay line locked.
22155  */
22156 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
22157 
22158 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
22159 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
22160 /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
22161  */
22162 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
22163 
22164 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
22165 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
22166 /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
22167  */
22168 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
22169 /*! @} */
22170 
22171 /*! @name AHBSPNDSTS - AHB Suspend Status Register */
22172 /*! @{ */
22173 
22174 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
22175 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
22176 /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
22177  */
22178 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
22179 
22180 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
22181 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
22182 /*! BUFID - AHB RX BUF ID for suspended command sequence.
22183  */
22184 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
22185 
22186 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
22187 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
22188 /*! DATLFT - Left Data size for suspended command sequence (in byte).
22189  */
22190 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
22191 /*! @} */
22192 
22193 /*! @name IPRXFSTS - IP RX FIFO Status Register */
22194 /*! @{ */
22195 
22196 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
22197 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
22198 /*! FILL - Fill level of IP RX FIFO.
22199  */
22200 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
22201 
22202 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
22203 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
22204 /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
22205  */
22206 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
22207 /*! @} */
22208 
22209 /*! @name IPTXFSTS - IP TX FIFO Status Register */
22210 /*! @{ */
22211 
22212 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
22213 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
22214 /*! FILL - Fill level of IP TX FIFO.
22215  */
22216 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
22217 
22218 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
22219 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
22220 /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
22221  */
22222 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
22223 /*! @} */
22224 
22225 /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
22226 /*! @{ */
22227 
22228 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
22229 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
22230 /*! RXDATA - RX Data
22231  */
22232 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
22233 /*! @} */
22234 
22235 /* The count of FLEXSPI_RFDR */
22236 #define FLEXSPI_RFDR_COUNT                       (32U)
22237 
22238 /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
22239 /*! @{ */
22240 
22241 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
22242 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
22243 /*! TXDATA - TX Data
22244  */
22245 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
22246 /*! @} */
22247 
22248 /* The count of FLEXSPI_TFDR */
22249 #define FLEXSPI_TFDR_COUNT                       (32U)
22250 
22251 /*! @name LUT - LUT 0..LUT 63 */
22252 /*! @{ */
22253 
22254 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
22255 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
22256 /*! OPERAND0 - OPERAND0
22257  */
22258 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
22259 
22260 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
22261 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
22262 /*! NUM_PADS0 - NUM_PADS0
22263  */
22264 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
22265 
22266 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
22267 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
22268 /*! OPCODE0 - OPCODE
22269  */
22270 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
22271 
22272 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
22273 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
22274 /*! OPERAND1 - OPERAND1
22275  */
22276 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
22277 
22278 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
22279 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
22280 /*! NUM_PADS1 - NUM_PADS1
22281  */
22282 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
22283 
22284 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
22285 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
22286 /*! OPCODE1 - OPCODE1
22287  */
22288 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
22289 /*! @} */
22290 
22291 /* The count of FLEXSPI_LUT */
22292 #define FLEXSPI_LUT_COUNT                        (64U)
22293 
22294 
22295 /*!
22296  * @}
22297  */ /* end of group FLEXSPI_Register_Masks */
22298 
22299 
22300 /* FLEXSPI - Peripheral instance base addresses */
22301 /** Peripheral FLEXSPI base address */
22302 #define FLEXSPI_BASE                             (0x402A8000u)
22303 /** Peripheral FLEXSPI base pointer */
22304 #define FLEXSPI                                  ((FLEXSPI_Type *)FLEXSPI_BASE)
22305 /** Array initializer of FLEXSPI peripheral base addresses */
22306 #define FLEXSPI_BASE_ADDRS                       { FLEXSPI_BASE }
22307 /** Array initializer of FLEXSPI peripheral base pointers */
22308 #define FLEXSPI_BASE_PTRS                        { FLEXSPI }
22309 /** Interrupt vectors for the FLEXSPI peripheral type */
22310 #define FLEXSPI_IRQS                             { FLEXSPI_IRQn }
22311 /* FlexSPI AMBA address. */
22312 #define FlexSPI_AMBA_BASE                       (0x60000000U)
22313 /* FlexSPI ASFM address. */
22314 #define FlexSPI_ASFM_BASE                        (0x00000000U)
22315 /* Base Address of AHB address space mapped to IP RX FIFO. */
22316 #define FlexSPI_ARDF_BASE                        (0x7FC00000U)
22317 /* Base Address of AHB address space mapped to IP TX FIFO. */
22318 #define FlexSPI_ATDF_BASE                        (0x7F800000U)
22319 
22320 
22321 /*!
22322  * @}
22323  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
22324 
22325 
22326 /* ----------------------------------------------------------------------------
22327    -- GPC Peripheral Access Layer
22328    ---------------------------------------------------------------------------- */
22329 
22330 /*!
22331  * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
22332  * @{
22333  */
22334 
22335 /** GPC - Register Layout Typedef */
22336 typedef struct {
22337   __IO uint32_t CNTR;                              /**< GPC Interface control register, offset: 0x0 */
22338        uint8_t RESERVED_0[4];
22339   __IO uint32_t IMR[4];                            /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */
22340   __I  uint32_t ISR[4];                            /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */
22341        uint8_t RESERVED_1[12];
22342   __IO uint32_t IMR5;                              /**< IRQ masking register 5, offset: 0x34 */
22343   __I  uint32_t ISR5;                              /**< IRQ status resister 5, offset: 0x38 */
22344 } GPC_Type;
22345 
22346 /* ----------------------------------------------------------------------------
22347    -- GPC Register Masks
22348    ---------------------------------------------------------------------------- */
22349 
22350 /*!
22351  * @addtogroup GPC_Register_Masks GPC Register Masks
22352  * @{
22353  */
22354 
22355 /*! @name CNTR - GPC Interface control register */
22356 /*! @{ */
22357 
22358 #define GPC_CNTR_MEGA_PDN_REQ_MASK               (0x4U)
22359 #define GPC_CNTR_MEGA_PDN_REQ_SHIFT              (2U)
22360 /*! MEGA_PDN_REQ
22361  *  0b0..No Request
22362  *  0b1..Request power down sequence
22363  */
22364 #define GPC_CNTR_MEGA_PDN_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
22365 
22366 #define GPC_CNTR_MEGA_PUP_REQ_MASK               (0x8U)
22367 #define GPC_CNTR_MEGA_PUP_REQ_SHIFT              (3U)
22368 /*! MEGA_PUP_REQ
22369  *  0b0..No Request
22370  *  0b1..Request power up sequence
22371  */
22372 #define GPC_CNTR_MEGA_PUP_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
22373 
22374 #define GPC_CNTR_PDRAM0_PGE_MASK                 (0x400000U)
22375 #define GPC_CNTR_PDRAM0_PGE_SHIFT                (22U)
22376 /*! PDRAM0_PGE
22377  *  0b1..FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down..
22378  *  0b0..FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down.
22379  */
22380 #define GPC_CNTR_PDRAM0_PGE(x)                   (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
22381 /*! @} */
22382 
22383 /*! @name IMR - IRQ masking register 1..IRQ masking register 4 */
22384 /*! @{ */
22385 
22386 #define GPC_IMR_IMR1_MASK                        (0xFFFFFFFFU)
22387 #define GPC_IMR_IMR1_SHIFT                       (0U)
22388 #define GPC_IMR_IMR1(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
22389 
22390 #define GPC_IMR_IMR2_MASK                        (0xFFFFFFFFU)
22391 #define GPC_IMR_IMR2_SHIFT                       (0U)
22392 #define GPC_IMR_IMR2(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
22393 
22394 #define GPC_IMR_IMR3_MASK                        (0xFFFFFFFFU)
22395 #define GPC_IMR_IMR3_SHIFT                       (0U)
22396 #define GPC_IMR_IMR3(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
22397 
22398 #define GPC_IMR_IMR4_MASK                        (0xFFFFFFFFU)
22399 #define GPC_IMR_IMR4_SHIFT                       (0U)
22400 #define GPC_IMR_IMR4(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
22401 /*! @} */
22402 
22403 /* The count of GPC_IMR */
22404 #define GPC_IMR_COUNT                            (4U)
22405 
22406 /*! @name ISR - IRQ status resister 1..IRQ status resister 4 */
22407 /*! @{ */
22408 
22409 #define GPC_ISR_ISR1_MASK                        (0xFFFFFFFFU)
22410 #define GPC_ISR_ISR1_SHIFT                       (0U)
22411 #define GPC_ISR_ISR1(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
22412 
22413 #define GPC_ISR_ISR2_MASK                        (0xFFFFFFFFU)
22414 #define GPC_ISR_ISR2_SHIFT                       (0U)
22415 #define GPC_ISR_ISR2(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
22416 
22417 #define GPC_ISR_ISR3_MASK                        (0xFFFFFFFFU)
22418 #define GPC_ISR_ISR3_SHIFT                       (0U)
22419 #define GPC_ISR_ISR3(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
22420 
22421 #define GPC_ISR_ISR4_MASK                        (0xFFFFFFFFU)
22422 #define GPC_ISR_ISR4_SHIFT                       (0U)
22423 #define GPC_ISR_ISR4(x)                          (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
22424 /*! @} */
22425 
22426 /* The count of GPC_ISR */
22427 #define GPC_ISR_COUNT                            (4U)
22428 
22429 /*! @name IMR5 - IRQ masking register 5 */
22430 /*! @{ */
22431 
22432 #define GPC_IMR5_IMR5_MASK                       (0xFFFFFFFFU)
22433 #define GPC_IMR5_IMR5_SHIFT                      (0U)
22434 #define GPC_IMR5_IMR5(x)                         (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
22435 /*! @} */
22436 
22437 /*! @name ISR5 - IRQ status resister 5 */
22438 /*! @{ */
22439 
22440 #define GPC_ISR5_ISR5_MASK                       (0xFFFFFFFFU)
22441 #define GPC_ISR5_ISR5_SHIFT                      (0U)
22442 #define GPC_ISR5_ISR5(x)                         (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR5_SHIFT)) & GPC_ISR5_ISR5_MASK)
22443 /*! @} */
22444 
22445 
22446 /*!
22447  * @}
22448  */ /* end of group GPC_Register_Masks */
22449 
22450 
22451 /* GPC - Peripheral instance base addresses */
22452 /** Peripheral GPC base address */
22453 #define GPC_BASE                                 (0x400F4000u)
22454 /** Peripheral GPC base pointer */
22455 #define GPC                                      ((GPC_Type *)GPC_BASE)
22456 /** Array initializer of GPC peripheral base addresses */
22457 #define GPC_BASE_ADDRS                           { GPC_BASE }
22458 /** Array initializer of GPC peripheral base pointers */
22459 #define GPC_BASE_PTRS                            { GPC }
22460 /** Interrupt vectors for the GPC peripheral type */
22461 #define GPC_IRQS                                 { GPC_IRQn }
22462 
22463 /*!
22464  * @}
22465  */ /* end of group GPC_Peripheral_Access_Layer */
22466 
22467 
22468 /* ----------------------------------------------------------------------------
22469    -- GPIO Peripheral Access Layer
22470    ---------------------------------------------------------------------------- */
22471 
22472 /*!
22473  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
22474  * @{
22475  */
22476 
22477 /** GPIO - Register Layout Typedef */
22478 typedef struct {
22479   __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
22480   __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
22481   __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
22482   __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
22483   __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
22484   __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
22485   __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
22486   __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
22487        uint8_t RESERVED_0[100];
22488   __O  uint32_t DR_SET;                            /**< GPIO data register SET, offset: 0x84 */
22489   __O  uint32_t DR_CLEAR;                          /**< GPIO data register CLEAR, offset: 0x88 */
22490   __O  uint32_t DR_TOGGLE;                         /**< GPIO data register TOGGLE, offset: 0x8C */
22491 } GPIO_Type;
22492 
22493 /* ----------------------------------------------------------------------------
22494    -- GPIO Register Masks
22495    ---------------------------------------------------------------------------- */
22496 
22497 /*!
22498  * @addtogroup GPIO_Register_Masks GPIO Register Masks
22499  * @{
22500  */
22501 
22502 /*! @name DR - GPIO data register */
22503 /*! @{ */
22504 
22505 #define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
22506 #define GPIO_DR_DR_SHIFT                         (0U)
22507 /*! DR - DR
22508  */
22509 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
22510 /*! @} */
22511 
22512 /*! @name GDIR - GPIO direction register */
22513 /*! @{ */
22514 
22515 #define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
22516 #define GPIO_GDIR_GDIR_SHIFT                     (0U)
22517 /*! GDIR - GDIR
22518  */
22519 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
22520 /*! @} */
22521 
22522 /*! @name PSR - GPIO pad status register */
22523 /*! @{ */
22524 
22525 #define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
22526 #define GPIO_PSR_PSR_SHIFT                       (0U)
22527 /*! PSR - PSR
22528  */
22529 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
22530 /*! @} */
22531 
22532 /*! @name ICR1 - GPIO interrupt configuration register1 */
22533 /*! @{ */
22534 
22535 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
22536 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
22537 /*! ICR0 - ICR0
22538  *  0b00..Interrupt n is low-level sensitive.
22539  *  0b01..Interrupt n is high-level sensitive.
22540  *  0b10..Interrupt n is rising-edge sensitive.
22541  *  0b11..Interrupt n is falling-edge sensitive.
22542  */
22543 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
22544 
22545 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
22546 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
22547 /*! ICR1 - ICR1
22548  *  0b00..Interrupt n is low-level sensitive.
22549  *  0b01..Interrupt n is high-level sensitive.
22550  *  0b10..Interrupt n is rising-edge sensitive.
22551  *  0b11..Interrupt n is falling-edge sensitive.
22552  */
22553 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
22554 
22555 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
22556 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
22557 /*! ICR2 - ICR2
22558  *  0b00..Interrupt n is low-level sensitive.
22559  *  0b01..Interrupt n is high-level sensitive.
22560  *  0b10..Interrupt n is rising-edge sensitive.
22561  *  0b11..Interrupt n is falling-edge sensitive.
22562  */
22563 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
22564 
22565 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
22566 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
22567 /*! ICR3 - ICR3
22568  *  0b00..Interrupt n is low-level sensitive.
22569  *  0b01..Interrupt n is high-level sensitive.
22570  *  0b10..Interrupt n is rising-edge sensitive.
22571  *  0b11..Interrupt n is falling-edge sensitive.
22572  */
22573 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
22574 
22575 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
22576 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
22577 /*! ICR4 - ICR4
22578  *  0b00..Interrupt n is low-level sensitive.
22579  *  0b01..Interrupt n is high-level sensitive.
22580  *  0b10..Interrupt n is rising-edge sensitive.
22581  *  0b11..Interrupt n is falling-edge sensitive.
22582  */
22583 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
22584 
22585 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
22586 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
22587 /*! ICR5 - ICR5
22588  *  0b00..Interrupt n is low-level sensitive.
22589  *  0b01..Interrupt n is high-level sensitive.
22590  *  0b10..Interrupt n is rising-edge sensitive.
22591  *  0b11..Interrupt n is falling-edge sensitive.
22592  */
22593 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
22594 
22595 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
22596 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
22597 /*! ICR6 - ICR6
22598  *  0b00..Interrupt n is low-level sensitive.
22599  *  0b01..Interrupt n is high-level sensitive.
22600  *  0b10..Interrupt n is rising-edge sensitive.
22601  *  0b11..Interrupt n is falling-edge sensitive.
22602  */
22603 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
22604 
22605 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
22606 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
22607 /*! ICR7 - ICR7
22608  *  0b00..Interrupt n is low-level sensitive.
22609  *  0b01..Interrupt n is high-level sensitive.
22610  *  0b10..Interrupt n is rising-edge sensitive.
22611  *  0b11..Interrupt n is falling-edge sensitive.
22612  */
22613 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
22614 
22615 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
22616 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
22617 /*! ICR8 - ICR8
22618  *  0b00..Interrupt n is low-level sensitive.
22619  *  0b01..Interrupt n is high-level sensitive.
22620  *  0b10..Interrupt n is rising-edge sensitive.
22621  *  0b11..Interrupt n is falling-edge sensitive.
22622  */
22623 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
22624 
22625 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
22626 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
22627 /*! ICR9 - ICR9
22628  *  0b00..Interrupt n is low-level sensitive.
22629  *  0b01..Interrupt n is high-level sensitive.
22630  *  0b10..Interrupt n is rising-edge sensitive.
22631  *  0b11..Interrupt n is falling-edge sensitive.
22632  */
22633 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
22634 
22635 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
22636 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
22637 /*! ICR10 - ICR10
22638  *  0b00..Interrupt n is low-level sensitive.
22639  *  0b01..Interrupt n is high-level sensitive.
22640  *  0b10..Interrupt n is rising-edge sensitive.
22641  *  0b11..Interrupt n is falling-edge sensitive.
22642  */
22643 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
22644 
22645 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
22646 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
22647 /*! ICR11 - ICR11
22648  *  0b00..Interrupt n is low-level sensitive.
22649  *  0b01..Interrupt n is high-level sensitive.
22650  *  0b10..Interrupt n is rising-edge sensitive.
22651  *  0b11..Interrupt n is falling-edge sensitive.
22652  */
22653 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
22654 
22655 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
22656 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
22657 /*! ICR12 - ICR12
22658  *  0b00..Interrupt n is low-level sensitive.
22659  *  0b01..Interrupt n is high-level sensitive.
22660  *  0b10..Interrupt n is rising-edge sensitive.
22661  *  0b11..Interrupt n is falling-edge sensitive.
22662  */
22663 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
22664 
22665 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
22666 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
22667 /*! ICR13 - ICR13
22668  *  0b00..Interrupt n is low-level sensitive.
22669  *  0b01..Interrupt n is high-level sensitive.
22670  *  0b10..Interrupt n is rising-edge sensitive.
22671  *  0b11..Interrupt n is falling-edge sensitive.
22672  */
22673 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
22674 
22675 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
22676 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
22677 /*! ICR14 - ICR14
22678  *  0b00..Interrupt n is low-level sensitive.
22679  *  0b01..Interrupt n is high-level sensitive.
22680  *  0b10..Interrupt n is rising-edge sensitive.
22681  *  0b11..Interrupt n is falling-edge sensitive.
22682  */
22683 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
22684 
22685 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
22686 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
22687 /*! ICR15 - ICR15
22688  *  0b00..Interrupt n is low-level sensitive.
22689  *  0b01..Interrupt n is high-level sensitive.
22690  *  0b10..Interrupt n is rising-edge sensitive.
22691  *  0b11..Interrupt n is falling-edge sensitive.
22692  */
22693 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
22694 /*! @} */
22695 
22696 /*! @name ICR2 - GPIO interrupt configuration register2 */
22697 /*! @{ */
22698 
22699 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
22700 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
22701 /*! ICR16 - ICR16
22702  *  0b00..Interrupt n is low-level sensitive.
22703  *  0b01..Interrupt n is high-level sensitive.
22704  *  0b10..Interrupt n is rising-edge sensitive.
22705  *  0b11..Interrupt n is falling-edge sensitive.
22706  */
22707 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
22708 
22709 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
22710 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
22711 /*! ICR17 - ICR17
22712  *  0b00..Interrupt n is low-level sensitive.
22713  *  0b01..Interrupt n is high-level sensitive.
22714  *  0b10..Interrupt n is rising-edge sensitive.
22715  *  0b11..Interrupt n is falling-edge sensitive.
22716  */
22717 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
22718 
22719 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
22720 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
22721 /*! ICR18 - ICR18
22722  *  0b00..Interrupt n is low-level sensitive.
22723  *  0b01..Interrupt n is high-level sensitive.
22724  *  0b10..Interrupt n is rising-edge sensitive.
22725  *  0b11..Interrupt n is falling-edge sensitive.
22726  */
22727 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
22728 
22729 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
22730 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
22731 /*! ICR19 - ICR19
22732  *  0b00..Interrupt n is low-level sensitive.
22733  *  0b01..Interrupt n is high-level sensitive.
22734  *  0b10..Interrupt n is rising-edge sensitive.
22735  *  0b11..Interrupt n is falling-edge sensitive.
22736  */
22737 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
22738 
22739 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
22740 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
22741 /*! ICR20 - ICR20
22742  *  0b00..Interrupt n is low-level sensitive.
22743  *  0b01..Interrupt n is high-level sensitive.
22744  *  0b10..Interrupt n is rising-edge sensitive.
22745  *  0b11..Interrupt n is falling-edge sensitive.
22746  */
22747 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
22748 
22749 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
22750 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
22751 /*! ICR21 - ICR21
22752  *  0b00..Interrupt n is low-level sensitive.
22753  *  0b01..Interrupt n is high-level sensitive.
22754  *  0b10..Interrupt n is rising-edge sensitive.
22755  *  0b11..Interrupt n is falling-edge sensitive.
22756  */
22757 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
22758 
22759 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
22760 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
22761 /*! ICR22 - ICR22
22762  *  0b00..Interrupt n is low-level sensitive.
22763  *  0b01..Interrupt n is high-level sensitive.
22764  *  0b10..Interrupt n is rising-edge sensitive.
22765  *  0b11..Interrupt n is falling-edge sensitive.
22766  */
22767 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
22768 
22769 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
22770 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
22771 /*! ICR23 - ICR23
22772  *  0b00..Interrupt n is low-level sensitive.
22773  *  0b01..Interrupt n is high-level sensitive.
22774  *  0b10..Interrupt n is rising-edge sensitive.
22775  *  0b11..Interrupt n is falling-edge sensitive.
22776  */
22777 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
22778 
22779 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
22780 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
22781 /*! ICR24 - ICR24
22782  *  0b00..Interrupt n is low-level sensitive.
22783  *  0b01..Interrupt n is high-level sensitive.
22784  *  0b10..Interrupt n is rising-edge sensitive.
22785  *  0b11..Interrupt n is falling-edge sensitive.
22786  */
22787 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
22788 
22789 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
22790 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
22791 /*! ICR25 - ICR25
22792  *  0b00..Interrupt n is low-level sensitive.
22793  *  0b01..Interrupt n is high-level sensitive.
22794  *  0b10..Interrupt n is rising-edge sensitive.
22795  *  0b11..Interrupt n is falling-edge sensitive.
22796  */
22797 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
22798 
22799 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
22800 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
22801 /*! ICR26 - ICR26
22802  *  0b00..Interrupt n is low-level sensitive.
22803  *  0b01..Interrupt n is high-level sensitive.
22804  *  0b10..Interrupt n is rising-edge sensitive.
22805  *  0b11..Interrupt n is falling-edge sensitive.
22806  */
22807 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
22808 
22809 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
22810 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
22811 /*! ICR27 - ICR27
22812  *  0b00..Interrupt n is low-level sensitive.
22813  *  0b01..Interrupt n is high-level sensitive.
22814  *  0b10..Interrupt n is rising-edge sensitive.
22815  *  0b11..Interrupt n is falling-edge sensitive.
22816  */
22817 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
22818 
22819 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
22820 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
22821 /*! ICR28 - ICR28
22822  *  0b00..Interrupt n is low-level sensitive.
22823  *  0b01..Interrupt n is high-level sensitive.
22824  *  0b10..Interrupt n is rising-edge sensitive.
22825  *  0b11..Interrupt n is falling-edge sensitive.
22826  */
22827 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
22828 
22829 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
22830 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
22831 /*! ICR29 - ICR29
22832  *  0b00..Interrupt n is low-level sensitive.
22833  *  0b01..Interrupt n is high-level sensitive.
22834  *  0b10..Interrupt n is rising-edge sensitive.
22835  *  0b11..Interrupt n is falling-edge sensitive.
22836  */
22837 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
22838 
22839 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
22840 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
22841 /*! ICR30 - ICR30
22842  *  0b00..Interrupt n is low-level sensitive.
22843  *  0b01..Interrupt n is high-level sensitive.
22844  *  0b10..Interrupt n is rising-edge sensitive.
22845  *  0b11..Interrupt n is falling-edge sensitive.
22846  */
22847 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
22848 
22849 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
22850 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
22851 /*! ICR31 - ICR31
22852  *  0b00..Interrupt n is low-level sensitive.
22853  *  0b01..Interrupt n is high-level sensitive.
22854  *  0b10..Interrupt n is rising-edge sensitive.
22855  *  0b11..Interrupt n is falling-edge sensitive.
22856  */
22857 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
22858 /*! @} */
22859 
22860 /*! @name IMR - GPIO interrupt mask register */
22861 /*! @{ */
22862 
22863 #define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
22864 #define GPIO_IMR_IMR_SHIFT                       (0U)
22865 /*! IMR - IMR
22866  */
22867 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
22868 /*! @} */
22869 
22870 /*! @name ISR - GPIO interrupt status register */
22871 /*! @{ */
22872 
22873 #define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
22874 #define GPIO_ISR_ISR_SHIFT                       (0U)
22875 /*! ISR - ISR
22876  */
22877 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
22878 /*! @} */
22879 
22880 /*! @name EDGE_SEL - GPIO edge select register */
22881 /*! @{ */
22882 
22883 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
22884 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
22885 /*! GPIO_EDGE_SEL - GPIO_EDGE_SEL
22886  */
22887 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
22888 /*! @} */
22889 
22890 /*! @name DR_SET - GPIO data register SET */
22891 /*! @{ */
22892 
22893 #define GPIO_DR_SET_DR_SET_MASK                  (0xFFFFFFFFU)
22894 #define GPIO_DR_SET_DR_SET_SHIFT                 (0U)
22895 /*! DR_SET - DR_SET
22896  */
22897 #define GPIO_DR_SET_DR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
22898 /*! @} */
22899 
22900 /*! @name DR_CLEAR - GPIO data register CLEAR */
22901 /*! @{ */
22902 
22903 #define GPIO_DR_CLEAR_DR_CLEAR_MASK              (0xFFFFFFFFU)
22904 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT             (0U)
22905 /*! DR_CLEAR - DR_CLEAR
22906  */
22907 #define GPIO_DR_CLEAR_DR_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
22908 /*! @} */
22909 
22910 /*! @name DR_TOGGLE - GPIO data register TOGGLE */
22911 /*! @{ */
22912 
22913 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK            (0xFFFFFFFFU)
22914 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT           (0U)
22915 /*! DR_TOGGLE - DR_TOGGLE
22916  */
22917 #define GPIO_DR_TOGGLE_DR_TOGGLE(x)              (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
22918 /*! @} */
22919 
22920 
22921 /*!
22922  * @}
22923  */ /* end of group GPIO_Register_Masks */
22924 
22925 
22926 /* GPIO - Peripheral instance base addresses */
22927 /** Peripheral GPIO1 base address */
22928 #define GPIO1_BASE                               (0x401B8000u)
22929 /** Peripheral GPIO1 base pointer */
22930 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
22931 /** Peripheral GPIO2 base address */
22932 #define GPIO2_BASE                               (0x401BC000u)
22933 /** Peripheral GPIO2 base pointer */
22934 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
22935 /** Peripheral GPIO3 base address */
22936 #define GPIO3_BASE                               (0x401C0000u)
22937 /** Peripheral GPIO3 base pointer */
22938 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
22939 /** Peripheral GPIO4 base address */
22940 #define GPIO4_BASE                               (0x401C4000u)
22941 /** Peripheral GPIO4 base pointer */
22942 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
22943 /** Peripheral GPIO5 base address */
22944 #define GPIO5_BASE                               (0x400C0000u)
22945 /** Peripheral GPIO5 base pointer */
22946 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
22947 /** Array initializer of GPIO peripheral base addresses */
22948 #define GPIO_BASE_ADDRS                          { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
22949 /** Array initializer of GPIO peripheral base pointers */
22950 #define GPIO_BASE_PTRS                           { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
22951 /** Interrupt vectors for the GPIO peripheral type */
22952 #define GPIO_IRQS                                { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
22953 #define GPIO_COMBINED_LOW_IRQS                   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
22954 #define GPIO_COMBINED_HIGH_IRQS                  { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
22955 
22956 /*!
22957  * @}
22958  */ /* end of group GPIO_Peripheral_Access_Layer */
22959 
22960 
22961 /* ----------------------------------------------------------------------------
22962    -- GPT Peripheral Access Layer
22963    ---------------------------------------------------------------------------- */
22964 
22965 /*!
22966  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
22967  * @{
22968  */
22969 
22970 /** GPT - Register Layout Typedef */
22971 typedef struct {
22972   __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
22973   __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
22974   __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
22975   __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
22976   __IO uint32_t OCR[3];                            /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
22977   __I  uint32_t ICR[2];                            /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
22978   __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
22979 } GPT_Type;
22980 
22981 /* ----------------------------------------------------------------------------
22982    -- GPT Register Masks
22983    ---------------------------------------------------------------------------- */
22984 
22985 /*!
22986  * @addtogroup GPT_Register_Masks GPT Register Masks
22987  * @{
22988  */
22989 
22990 /*! @name CR - GPT Control Register */
22991 /*! @{ */
22992 
22993 #define GPT_CR_EN_MASK                           (0x1U)
22994 #define GPT_CR_EN_SHIFT                          (0U)
22995 /*! EN
22996  *  0b0..GPT is disabled.
22997  *  0b1..GPT is enabled.
22998  */
22999 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
23000 
23001 #define GPT_CR_ENMOD_MASK                        (0x2U)
23002 #define GPT_CR_ENMOD_SHIFT                       (1U)
23003 /*! ENMOD
23004  *  0b0..GPT counter will retain its value when it is disabled.
23005  *  0b1..GPT counter value is reset to 0 when it is disabled.
23006  */
23007 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
23008 
23009 #define GPT_CR_DBGEN_MASK                        (0x4U)
23010 #define GPT_CR_DBGEN_SHIFT                       (2U)
23011 /*! DBGEN
23012  *  0b0..GPT is disabled in debug mode.
23013  *  0b1..GPT is enabled in debug mode.
23014  */
23015 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
23016 
23017 #define GPT_CR_WAITEN_MASK                       (0x8U)
23018 #define GPT_CR_WAITEN_SHIFT                      (3U)
23019 /*! WAITEN
23020  *  0b0..GPT is disabled in wait mode.
23021  *  0b1..GPT is enabled in wait mode.
23022  */
23023 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
23024 
23025 #define GPT_CR_DOZEEN_MASK                       (0x10U)
23026 #define GPT_CR_DOZEEN_SHIFT                      (4U)
23027 /*! DOZEEN
23028  *  0b0..GPT is disabled in doze mode.
23029  *  0b1..GPT is enabled in doze mode.
23030  */
23031 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
23032 
23033 #define GPT_CR_STOPEN_MASK                       (0x20U)
23034 #define GPT_CR_STOPEN_SHIFT                      (5U)
23035 /*! STOPEN
23036  *  0b0..GPT is disabled in Stop mode.
23037  *  0b1..GPT is enabled in Stop mode.
23038  */
23039 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
23040 
23041 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
23042 #define GPT_CR_CLKSRC_SHIFT                      (6U)
23043 /*! CLKSRC
23044  *  0b000..No clock
23045  *  0b001..Peripheral Clock (ipg_clk)
23046  *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
23047  *  0b011..External Clock
23048  *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
23049  *  0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
23050  */
23051 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
23052 
23053 #define GPT_CR_FRR_MASK                          (0x200U)
23054 #define GPT_CR_FRR_SHIFT                         (9U)
23055 /*! FRR
23056  *  0b0..Restart mode
23057  *  0b1..Free-Run mode
23058  */
23059 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
23060 
23061 #define GPT_CR_EN_24M_MASK                       (0x400U)
23062 #define GPT_CR_EN_24M_SHIFT                      (10U)
23063 /*! EN_24M
23064  *  0b0..24M clock disabled
23065  *  0b1..24M clock enabled
23066  */
23067 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
23068 
23069 #define GPT_CR_SWR_MASK                          (0x8000U)
23070 #define GPT_CR_SWR_SHIFT                         (15U)
23071 /*! SWR
23072  *  0b0..GPT is not in reset state
23073  *  0b1..GPT is in reset state
23074  */
23075 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
23076 
23077 #define GPT_CR_IM1_MASK                          (0x30000U)
23078 #define GPT_CR_IM1_SHIFT                         (16U)
23079 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
23080 
23081 #define GPT_CR_IM2_MASK                          (0xC0000U)
23082 #define GPT_CR_IM2_SHIFT                         (18U)
23083 /*! IM2
23084  *  0b00..capture disabled
23085  *  0b01..capture on rising edge only
23086  *  0b10..capture on falling edge only
23087  *  0b11..capture on both edges
23088  */
23089 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
23090 
23091 #define GPT_CR_OM1_MASK                          (0x700000U)
23092 #define GPT_CR_OM1_SHIFT                         (20U)
23093 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
23094 
23095 #define GPT_CR_OM2_MASK                          (0x3800000U)
23096 #define GPT_CR_OM2_SHIFT                         (23U)
23097 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
23098 
23099 #define GPT_CR_OM3_MASK                          (0x1C000000U)
23100 #define GPT_CR_OM3_SHIFT                         (26U)
23101 /*! OM3
23102  *  0b000..Output disconnected. No response on pin.
23103  *  0b001..Toggle output pin
23104  *  0b010..Clear output pin
23105  *  0b011..Set output pin
23106  *  0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
23107  */
23108 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
23109 
23110 #define GPT_CR_FO1_MASK                          (0x20000000U)
23111 #define GPT_CR_FO1_SHIFT                         (29U)
23112 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
23113 
23114 #define GPT_CR_FO2_MASK                          (0x40000000U)
23115 #define GPT_CR_FO2_SHIFT                         (30U)
23116 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
23117 
23118 #define GPT_CR_FO3_MASK                          (0x80000000U)
23119 #define GPT_CR_FO3_SHIFT                         (31U)
23120 /*! FO3
23121  *  0b0..Writing a 0 has no effect.
23122  *  0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
23123  */
23124 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
23125 /*! @} */
23126 
23127 /*! @name PR - GPT Prescaler Register */
23128 /*! @{ */
23129 
23130 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
23131 #define GPT_PR_PRESCALER_SHIFT                   (0U)
23132 /*! PRESCALER
23133  *  0b000000000000..Divide by 1
23134  *  0b000000000001..Divide by 2
23135  *  0b111111111111..Divide by 4096
23136  */
23137 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
23138 
23139 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
23140 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
23141 /*! PRESCALER24M
23142  *  0b0000..Divide by 1
23143  *  0b0001..Divide by 2
23144  *  0b1111..Divide by 16
23145  */
23146 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
23147 /*! @} */
23148 
23149 /*! @name SR - GPT Status Register */
23150 /*! @{ */
23151 
23152 #define GPT_SR_OF1_MASK                          (0x1U)
23153 #define GPT_SR_OF1_SHIFT                         (0U)
23154 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
23155 
23156 #define GPT_SR_OF2_MASK                          (0x2U)
23157 #define GPT_SR_OF2_SHIFT                         (1U)
23158 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
23159 
23160 #define GPT_SR_OF3_MASK                          (0x4U)
23161 #define GPT_SR_OF3_SHIFT                         (2U)
23162 /*! OF3
23163  *  0b0..Compare event has not occurred.
23164  *  0b1..Compare event has occurred.
23165  */
23166 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
23167 
23168 #define GPT_SR_IF1_MASK                          (0x8U)
23169 #define GPT_SR_IF1_SHIFT                         (3U)
23170 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
23171 
23172 #define GPT_SR_IF2_MASK                          (0x10U)
23173 #define GPT_SR_IF2_SHIFT                         (4U)
23174 /*! IF2
23175  *  0b0..Capture event has not occurred.
23176  *  0b1..Capture event has occurred.
23177  */
23178 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
23179 
23180 #define GPT_SR_ROV_MASK                          (0x20U)
23181 #define GPT_SR_ROV_SHIFT                         (5U)
23182 /*! ROV
23183  *  0b0..Rollover has not occurred.
23184  *  0b1..Rollover has occurred.
23185  */
23186 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
23187 /*! @} */
23188 
23189 /*! @name IR - GPT Interrupt Register */
23190 /*! @{ */
23191 
23192 #define GPT_IR_OF1IE_MASK                        (0x1U)
23193 #define GPT_IR_OF1IE_SHIFT                       (0U)
23194 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
23195 
23196 #define GPT_IR_OF2IE_MASK                        (0x2U)
23197 #define GPT_IR_OF2IE_SHIFT                       (1U)
23198 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
23199 
23200 #define GPT_IR_OF3IE_MASK                        (0x4U)
23201 #define GPT_IR_OF3IE_SHIFT                       (2U)
23202 /*! OF3IE
23203  *  0b0..Output Compare Channel n interrupt is disabled.
23204  *  0b1..Output Compare Channel n interrupt is enabled.
23205  */
23206 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
23207 
23208 #define GPT_IR_IF1IE_MASK                        (0x8U)
23209 #define GPT_IR_IF1IE_SHIFT                       (3U)
23210 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
23211 
23212 #define GPT_IR_IF2IE_MASK                        (0x10U)
23213 #define GPT_IR_IF2IE_SHIFT                       (4U)
23214 /*! IF2IE
23215  *  0b0..IF2IE Input Capture n Interrupt Enable is disabled.
23216  *  0b1..IF2IE Input Capture n Interrupt Enable is enabled.
23217  */
23218 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
23219 
23220 #define GPT_IR_ROVIE_MASK                        (0x20U)
23221 #define GPT_IR_ROVIE_SHIFT                       (5U)
23222 /*! ROVIE
23223  *  0b0..Rollover interrupt is disabled.
23224  *  0b1..Rollover interrupt enabled.
23225  */
23226 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
23227 /*! @} */
23228 
23229 /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
23230 /*! @{ */
23231 
23232 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
23233 #define GPT_OCR_COMP_SHIFT                       (0U)
23234 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
23235 /*! @} */
23236 
23237 /* The count of GPT_OCR */
23238 #define GPT_OCR_COUNT                            (3U)
23239 
23240 /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
23241 /*! @{ */
23242 
23243 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
23244 #define GPT_ICR_CAPT_SHIFT                       (0U)
23245 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
23246 /*! @} */
23247 
23248 /* The count of GPT_ICR */
23249 #define GPT_ICR_COUNT                            (2U)
23250 
23251 /*! @name CNT - GPT Counter Register */
23252 /*! @{ */
23253 
23254 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
23255 #define GPT_CNT_COUNT_SHIFT                      (0U)
23256 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
23257 /*! @} */
23258 
23259 
23260 /*!
23261  * @}
23262  */ /* end of group GPT_Register_Masks */
23263 
23264 
23265 /* GPT - Peripheral instance base addresses */
23266 /** Peripheral GPT1 base address */
23267 #define GPT1_BASE                                (0x401EC000u)
23268 /** Peripheral GPT1 base pointer */
23269 #define GPT1                                     ((GPT_Type *)GPT1_BASE)
23270 /** Peripheral GPT2 base address */
23271 #define GPT2_BASE                                (0x401F0000u)
23272 /** Peripheral GPT2 base pointer */
23273 #define GPT2                                     ((GPT_Type *)GPT2_BASE)
23274 /** Array initializer of GPT peripheral base addresses */
23275 #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE }
23276 /** Array initializer of GPT peripheral base pointers */
23277 #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2 }
23278 /** Interrupt vectors for the GPT peripheral type */
23279 #define GPT_IRQS                                 { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
23280 
23281 /*!
23282  * @}
23283  */ /* end of group GPT_Peripheral_Access_Layer */
23284 
23285 
23286 /* ----------------------------------------------------------------------------
23287    -- I2S Peripheral Access Layer
23288    ---------------------------------------------------------------------------- */
23289 
23290 /*!
23291  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
23292  * @{
23293  */
23294 
23295 /** I2S - Register Layout Typedef */
23296 typedef struct {
23297   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
23298   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
23299   __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x8 */
23300   __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0xC */
23301   __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
23302   __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
23303   __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
23304   __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
23305   __O  uint32_t TDR[4];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
23306        uint8_t RESERVED_0[16];
23307   __I  uint32_t TFR[4];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
23308        uint8_t RESERVED_1[16];
23309   __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
23310        uint8_t RESERVED_2[36];
23311   __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x88 */
23312   __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x8C */
23313   __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x90 */
23314   __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x94 */
23315   __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x98 */
23316   __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x9C */
23317   __I  uint32_t RDR[4];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
23318        uint8_t RESERVED_3[16];
23319   __I  uint32_t RFR[4];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
23320        uint8_t RESERVED_4[16];
23321   __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
23322 } I2S_Type;
23323 
23324 /* ----------------------------------------------------------------------------
23325    -- I2S Register Masks
23326    ---------------------------------------------------------------------------- */
23327 
23328 /*!
23329  * @addtogroup I2S_Register_Masks I2S Register Masks
23330  * @{
23331  */
23332 
23333 /*! @name VERID - Version ID Register */
23334 /*! @{ */
23335 
23336 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
23337 #define I2S_VERID_FEATURE_SHIFT                  (0U)
23338 /*! FEATURE - Feature Specification Number
23339  *  0b0000000000000000..Standard feature set.
23340  */
23341 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
23342 
23343 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
23344 #define I2S_VERID_MINOR_SHIFT                    (16U)
23345 /*! MINOR - Minor Version Number
23346  */
23347 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
23348 
23349 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
23350 #define I2S_VERID_MAJOR_SHIFT                    (24U)
23351 /*! MAJOR - Major Version Number
23352  */
23353 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
23354 /*! @} */
23355 
23356 /*! @name PARAM - Parameter Register */
23357 /*! @{ */
23358 
23359 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
23360 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
23361 /*! DATALINE - Number of Datalines
23362  */
23363 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
23364 
23365 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
23366 #define I2S_PARAM_FIFO_SHIFT                     (8U)
23367 /*! FIFO - FIFO Size
23368  */
23369 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
23370 
23371 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
23372 #define I2S_PARAM_FRAME_SHIFT                    (16U)
23373 /*! FRAME - Frame Size
23374  */
23375 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
23376 /*! @} */
23377 
23378 /*! @name TCSR - SAI Transmit Control Register */
23379 /*! @{ */
23380 
23381 #define I2S_TCSR_FRDE_MASK                       (0x1U)
23382 #define I2S_TCSR_FRDE_SHIFT                      (0U)
23383 /*! FRDE - FIFO Request DMA Enable
23384  *  0b0..Disables the DMA request.
23385  *  0b1..Enables the DMA request.
23386  */
23387 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
23388 
23389 #define I2S_TCSR_FWDE_MASK                       (0x2U)
23390 #define I2S_TCSR_FWDE_SHIFT                      (1U)
23391 /*! FWDE - FIFO Warning DMA Enable
23392  *  0b0..Disables the DMA request.
23393  *  0b1..Enables the DMA request.
23394  */
23395 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
23396 
23397 #define I2S_TCSR_FRIE_MASK                       (0x100U)
23398 #define I2S_TCSR_FRIE_SHIFT                      (8U)
23399 /*! FRIE - FIFO Request Interrupt Enable
23400  *  0b0..Disables the interrupt.
23401  *  0b1..Enables the interrupt.
23402  */
23403 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
23404 
23405 #define I2S_TCSR_FWIE_MASK                       (0x200U)
23406 #define I2S_TCSR_FWIE_SHIFT                      (9U)
23407 /*! FWIE - FIFO Warning Interrupt Enable
23408  *  0b0..Disables the interrupt.
23409  *  0b1..Enables the interrupt.
23410  */
23411 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
23412 
23413 #define I2S_TCSR_FEIE_MASK                       (0x400U)
23414 #define I2S_TCSR_FEIE_SHIFT                      (10U)
23415 /*! FEIE - FIFO Error Interrupt Enable
23416  *  0b0..Disables the interrupt.
23417  *  0b1..Enables the interrupt.
23418  */
23419 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
23420 
23421 #define I2S_TCSR_SEIE_MASK                       (0x800U)
23422 #define I2S_TCSR_SEIE_SHIFT                      (11U)
23423 /*! SEIE - Sync Error Interrupt Enable
23424  *  0b0..Disables interrupt.
23425  *  0b1..Enables interrupt.
23426  */
23427 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
23428 
23429 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
23430 #define I2S_TCSR_WSIE_SHIFT                      (12U)
23431 /*! WSIE - Word Start Interrupt Enable
23432  *  0b0..Disables interrupt.
23433  *  0b1..Enables interrupt.
23434  */
23435 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
23436 
23437 #define I2S_TCSR_FRF_MASK                        (0x10000U)
23438 #define I2S_TCSR_FRF_SHIFT                       (16U)
23439 /*! FRF - FIFO Request Flag
23440  *  0b0..Transmit FIFO watermark has not been reached.
23441  *  0b1..Transmit FIFO watermark has been reached.
23442  */
23443 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
23444 
23445 #define I2S_TCSR_FWF_MASK                        (0x20000U)
23446 #define I2S_TCSR_FWF_SHIFT                       (17U)
23447 /*! FWF - FIFO Warning Flag
23448  *  0b0..No enabled transmit FIFO is empty.
23449  *  0b1..Enabled transmit FIFO is empty.
23450  */
23451 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
23452 
23453 #define I2S_TCSR_FEF_MASK                        (0x40000U)
23454 #define I2S_TCSR_FEF_SHIFT                       (18U)
23455 /*! FEF - FIFO Error Flag
23456  *  0b0..Transmit underrun not detected.
23457  *  0b1..Transmit underrun detected.
23458  */
23459 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
23460 
23461 #define I2S_TCSR_SEF_MASK                        (0x80000U)
23462 #define I2S_TCSR_SEF_SHIFT                       (19U)
23463 /*! SEF - Sync Error Flag
23464  *  0b0..Sync error not detected.
23465  *  0b1..Frame sync error detected.
23466  */
23467 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
23468 
23469 #define I2S_TCSR_WSF_MASK                        (0x100000U)
23470 #define I2S_TCSR_WSF_SHIFT                       (20U)
23471 /*! WSF - Word Start Flag
23472  *  0b0..Start of word not detected.
23473  *  0b1..Start of word detected.
23474  */
23475 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
23476 
23477 #define I2S_TCSR_SR_MASK                         (0x1000000U)
23478 #define I2S_TCSR_SR_SHIFT                        (24U)
23479 /*! SR - Software Reset
23480  *  0b0..No effect.
23481  *  0b1..Software reset.
23482  */
23483 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
23484 
23485 #define I2S_TCSR_FR_MASK                         (0x2000000U)
23486 #define I2S_TCSR_FR_SHIFT                        (25U)
23487 /*! FR - FIFO Reset
23488  *  0b0..No effect.
23489  *  0b1..FIFO reset.
23490  */
23491 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
23492 
23493 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
23494 #define I2S_TCSR_BCE_SHIFT                       (28U)
23495 /*! BCE - Bit Clock Enable
23496  *  0b0..Transmit bit clock is disabled.
23497  *  0b1..Transmit bit clock is enabled.
23498  */
23499 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
23500 
23501 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
23502 #define I2S_TCSR_DBGE_SHIFT                      (29U)
23503 /*! DBGE - Debug Enable
23504  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
23505  *  0b1..Transmitter is enabled in Debug mode.
23506  */
23507 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
23508 
23509 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
23510 #define I2S_TCSR_STOPE_SHIFT                     (30U)
23511 /*! STOPE - Stop Enable
23512  *  0b0..Transmitter disabled in Stop mode.
23513  *  0b1..Transmitter enabled in Stop mode.
23514  */
23515 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
23516 
23517 #define I2S_TCSR_TE_MASK                         (0x80000000U)
23518 #define I2S_TCSR_TE_SHIFT                        (31U)
23519 /*! TE - Transmitter Enable
23520  *  0b0..Transmitter is disabled.
23521  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
23522  */
23523 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
23524 /*! @} */
23525 
23526 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
23527 /*! @{ */
23528 
23529 #define I2S_TCR1_TFW_MASK                        (0x1FU)
23530 #define I2S_TCR1_TFW_SHIFT                       (0U)
23531 /*! TFW - Transmit FIFO Watermark
23532  */
23533 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
23534 /*! @} */
23535 
23536 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
23537 /*! @{ */
23538 
23539 #define I2S_TCR2_DIV_MASK                        (0xFFU)
23540 #define I2S_TCR2_DIV_SHIFT                       (0U)
23541 /*! DIV - Bit Clock Divide
23542  */
23543 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
23544 
23545 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
23546 #define I2S_TCR2_BCD_SHIFT                       (24U)
23547 /*! BCD - Bit Clock Direction
23548  *  0b0..Bit clock is generated externally in Slave mode.
23549  *  0b1..Bit clock is generated internally in Master mode.
23550  */
23551 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
23552 
23553 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
23554 #define I2S_TCR2_BCP_SHIFT                       (25U)
23555 /*! BCP - Bit Clock Polarity
23556  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
23557  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
23558  */
23559 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
23560 
23561 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
23562 #define I2S_TCR2_MSEL_SHIFT                      (26U)
23563 /*! MSEL - MCLK Select
23564  *  0b00..Bus Clock selected.
23565  *  0b01..Master Clock (MCLK) 1 option selected.
23566  *  0b10..Master Clock (MCLK) 2 option selected.
23567  *  0b11..Master Clock (MCLK) 3 option selected.
23568  */
23569 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
23570 
23571 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
23572 #define I2S_TCR2_BCI_SHIFT                       (28U)
23573 /*! BCI - Bit Clock Input
23574  *  0b0..No effect.
23575  *  0b1..Internal logic is clocked as if bit clock was externally generated.
23576  */
23577 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
23578 
23579 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
23580 #define I2S_TCR2_BCS_SHIFT                       (29U)
23581 /*! BCS - Bit Clock Swap
23582  *  0b0..Use the normal bit clock source.
23583  *  0b1..Swap the bit clock source.
23584  */
23585 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
23586 
23587 #define I2S_TCR2_SYNC_MASK                       (0x40000000U)
23588 #define I2S_TCR2_SYNC_SHIFT                      (30U)
23589 /*! SYNC - Synchronous Mode
23590  *  0b0..Asynchronous mode.
23591  *  0b1..Synchronous with receiver.
23592  */
23593 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
23594 /*! @} */
23595 
23596 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
23597 /*! @{ */
23598 
23599 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
23600 #define I2S_TCR3_WDFL_SHIFT                      (0U)
23601 /*! WDFL - Word Flag Configuration
23602  */
23603 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
23604 
23605 #define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
23606 #define I2S_TCR3_TCE_SHIFT                       (16U)
23607 /*! TCE - Transmit Channel Enable
23608  */
23609 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
23610 
23611 #define I2S_TCR3_CFR_MASK                        (0xF000000U)
23612 #define I2S_TCR3_CFR_SHIFT                       (24U)
23613 /*! CFR - Channel FIFO Reset
23614  */
23615 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
23616 /*! @} */
23617 
23618 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
23619 /*! @{ */
23620 
23621 #define I2S_TCR4_FSD_MASK                        (0x1U)
23622 #define I2S_TCR4_FSD_SHIFT                       (0U)
23623 /*! FSD - Frame Sync Direction
23624  *  0b0..Frame sync is generated externally in Slave mode.
23625  *  0b1..Frame sync is generated internally in Master mode.
23626  */
23627 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
23628 
23629 #define I2S_TCR4_FSP_MASK                        (0x2U)
23630 #define I2S_TCR4_FSP_SHIFT                       (1U)
23631 /*! FSP - Frame Sync Polarity
23632  *  0b0..Frame sync is active high.
23633  *  0b1..Frame sync is active low.
23634  */
23635 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
23636 
23637 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
23638 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
23639 /*! ONDEM - On Demand Mode
23640  *  0b0..Internal frame sync is generated continuously.
23641  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
23642  */
23643 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
23644 
23645 #define I2S_TCR4_FSE_MASK                        (0x8U)
23646 #define I2S_TCR4_FSE_SHIFT                       (3U)
23647 /*! FSE - Frame Sync Early
23648  *  0b0..Frame sync asserts with the first bit of the frame.
23649  *  0b1..Frame sync asserts one bit before the first bit of the frame.
23650  */
23651 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
23652 
23653 #define I2S_TCR4_MF_MASK                         (0x10U)
23654 #define I2S_TCR4_MF_SHIFT                        (4U)
23655 /*! MF - MSB First
23656  *  0b0..LSB is transmitted first.
23657  *  0b1..MSB is transmitted first.
23658  */
23659 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
23660 
23661 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
23662 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
23663 /*! CHMOD - Channel Mode
23664  *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
23665  *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
23666  */
23667 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
23668 
23669 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
23670 #define I2S_TCR4_SYWD_SHIFT                      (8U)
23671 /*! SYWD - Sync Width
23672  */
23673 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
23674 
23675 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
23676 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
23677 /*! FRSZ - Frame size
23678  */
23679 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
23680 
23681 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
23682 #define I2S_TCR4_FPACK_SHIFT                     (24U)
23683 /*! FPACK - FIFO Packing Mode
23684  *  0b00..FIFO packing is disabled
23685  *  0b01..Reserved
23686  *  0b10..8-bit FIFO packing is enabled
23687  *  0b11..16-bit FIFO packing is enabled
23688  */
23689 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
23690 
23691 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
23692 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
23693 /*! FCOMB - FIFO Combine Mode
23694  *  0b00..FIFO combine mode disabled.
23695  *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
23696  *  0b10..FIFO combine mode enabled on FIFO writes (by software).
23697  *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
23698  */
23699 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
23700 
23701 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
23702 #define I2S_TCR4_FCONT_SHIFT                     (28U)
23703 /*! FCONT - FIFO Continue on Error
23704  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
23705  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
23706  */
23707 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
23708 /*! @} */
23709 
23710 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
23711 /*! @{ */
23712 
23713 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
23714 #define I2S_TCR5_FBT_SHIFT                       (8U)
23715 /*! FBT - First Bit Shifted
23716  */
23717 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
23718 
23719 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
23720 #define I2S_TCR5_W0W_SHIFT                       (16U)
23721 /*! W0W - Word 0 Width
23722  */
23723 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
23724 
23725 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
23726 #define I2S_TCR5_WNW_SHIFT                       (24U)
23727 /*! WNW - Word N Width
23728  */
23729 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
23730 /*! @} */
23731 
23732 /*! @name TDR - SAI Transmit Data Register */
23733 /*! @{ */
23734 
23735 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
23736 #define I2S_TDR_TDR_SHIFT                        (0U)
23737 /*! TDR - Transmit Data Register
23738  */
23739 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
23740 /*! @} */
23741 
23742 /* The count of I2S_TDR */
23743 #define I2S_TDR_COUNT                            (4U)
23744 
23745 /*! @name TFR - SAI Transmit FIFO Register */
23746 /*! @{ */
23747 
23748 #define I2S_TFR_RFP_MASK                         (0x3FU)
23749 #define I2S_TFR_RFP_SHIFT                        (0U)
23750 /*! RFP - Read FIFO Pointer
23751  */
23752 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
23753 
23754 #define I2S_TFR_WFP_MASK                         (0x3F0000U)
23755 #define I2S_TFR_WFP_SHIFT                        (16U)
23756 /*! WFP - Write FIFO Pointer
23757  */
23758 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
23759 
23760 #define I2S_TFR_WCP_MASK                         (0x80000000U)
23761 #define I2S_TFR_WCP_SHIFT                        (31U)
23762 /*! WCP - Write Channel Pointer
23763  *  0b0..No effect.
23764  *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
23765  */
23766 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
23767 /*! @} */
23768 
23769 /* The count of I2S_TFR */
23770 #define I2S_TFR_COUNT                            (4U)
23771 
23772 /*! @name TMR - SAI Transmit Mask Register */
23773 /*! @{ */
23774 
23775 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
23776 #define I2S_TMR_TWM_SHIFT                        (0U)
23777 /*! TWM - Transmit Word Mask
23778  *  0b00000000000000000000000000000000..Word N is enabled.
23779  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
23780  */
23781 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
23782 /*! @} */
23783 
23784 /*! @name RCSR - SAI Receive Control Register */
23785 /*! @{ */
23786 
23787 #define I2S_RCSR_FRDE_MASK                       (0x1U)
23788 #define I2S_RCSR_FRDE_SHIFT                      (0U)
23789 /*! FRDE - FIFO Request DMA Enable
23790  *  0b0..Disables the DMA request.
23791  *  0b1..Enables the DMA request.
23792  */
23793 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
23794 
23795 #define I2S_RCSR_FWDE_MASK                       (0x2U)
23796 #define I2S_RCSR_FWDE_SHIFT                      (1U)
23797 /*! FWDE - FIFO Warning DMA Enable
23798  *  0b0..Disables the DMA request.
23799  *  0b1..Enables the DMA request.
23800  */
23801 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
23802 
23803 #define I2S_RCSR_FRIE_MASK                       (0x100U)
23804 #define I2S_RCSR_FRIE_SHIFT                      (8U)
23805 /*! FRIE - FIFO Request Interrupt Enable
23806  *  0b0..Disables the interrupt.
23807  *  0b1..Enables the interrupt.
23808  */
23809 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
23810 
23811 #define I2S_RCSR_FWIE_MASK                       (0x200U)
23812 #define I2S_RCSR_FWIE_SHIFT                      (9U)
23813 /*! FWIE - FIFO Warning Interrupt Enable
23814  *  0b0..Disables the interrupt.
23815  *  0b1..Enables the interrupt.
23816  */
23817 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
23818 
23819 #define I2S_RCSR_FEIE_MASK                       (0x400U)
23820 #define I2S_RCSR_FEIE_SHIFT                      (10U)
23821 /*! FEIE - FIFO Error Interrupt Enable
23822  *  0b0..Disables the interrupt.
23823  *  0b1..Enables the interrupt.
23824  */
23825 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
23826 
23827 #define I2S_RCSR_SEIE_MASK                       (0x800U)
23828 #define I2S_RCSR_SEIE_SHIFT                      (11U)
23829 /*! SEIE - Sync Error Interrupt Enable
23830  *  0b0..Disables interrupt.
23831  *  0b1..Enables interrupt.
23832  */
23833 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
23834 
23835 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
23836 #define I2S_RCSR_WSIE_SHIFT                      (12U)
23837 /*! WSIE - Word Start Interrupt Enable
23838  *  0b0..Disables interrupt.
23839  *  0b1..Enables interrupt.
23840  */
23841 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
23842 
23843 #define I2S_RCSR_FRF_MASK                        (0x10000U)
23844 #define I2S_RCSR_FRF_SHIFT                       (16U)
23845 /*! FRF - FIFO Request Flag
23846  *  0b0..Receive FIFO watermark not reached.
23847  *  0b1..Receive FIFO watermark has been reached.
23848  */
23849 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
23850 
23851 #define I2S_RCSR_FWF_MASK                        (0x20000U)
23852 #define I2S_RCSR_FWF_SHIFT                       (17U)
23853 /*! FWF - FIFO Warning Flag
23854  *  0b0..No enabled receive FIFO is full.
23855  *  0b1..Enabled receive FIFO is full.
23856  */
23857 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
23858 
23859 #define I2S_RCSR_FEF_MASK                        (0x40000U)
23860 #define I2S_RCSR_FEF_SHIFT                       (18U)
23861 /*! FEF - FIFO Error Flag
23862  *  0b0..Receive overflow not detected.
23863  *  0b1..Receive overflow detected.
23864  */
23865 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
23866 
23867 #define I2S_RCSR_SEF_MASK                        (0x80000U)
23868 #define I2S_RCSR_SEF_SHIFT                       (19U)
23869 /*! SEF - Sync Error Flag
23870  *  0b0..Sync error not detected.
23871  *  0b1..Frame sync error detected.
23872  */
23873 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
23874 
23875 #define I2S_RCSR_WSF_MASK                        (0x100000U)
23876 #define I2S_RCSR_WSF_SHIFT                       (20U)
23877 /*! WSF - Word Start Flag
23878  *  0b0..Start of word not detected.
23879  *  0b1..Start of word detected.
23880  */
23881 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
23882 
23883 #define I2S_RCSR_SR_MASK                         (0x1000000U)
23884 #define I2S_RCSR_SR_SHIFT                        (24U)
23885 /*! SR - Software Reset
23886  *  0b0..No effect.
23887  *  0b1..Software reset.
23888  */
23889 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
23890 
23891 #define I2S_RCSR_FR_MASK                         (0x2000000U)
23892 #define I2S_RCSR_FR_SHIFT                        (25U)
23893 /*! FR - FIFO Reset
23894  *  0b0..No effect.
23895  *  0b1..FIFO reset.
23896  */
23897 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
23898 
23899 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
23900 #define I2S_RCSR_BCE_SHIFT                       (28U)
23901 /*! BCE - Bit Clock Enable
23902  *  0b0..Receive bit clock is disabled.
23903  *  0b1..Receive bit clock is enabled.
23904  */
23905 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
23906 
23907 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
23908 #define I2S_RCSR_DBGE_SHIFT                      (29U)
23909 /*! DBGE - Debug Enable
23910  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
23911  *  0b1..Receiver is enabled in Debug mode.
23912  */
23913 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
23914 
23915 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
23916 #define I2S_RCSR_STOPE_SHIFT                     (30U)
23917 /*! STOPE - Stop Enable
23918  *  0b0..Receiver disabled in Stop mode.
23919  *  0b1..Receiver enabled in Stop mode.
23920  */
23921 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
23922 
23923 #define I2S_RCSR_RE_MASK                         (0x80000000U)
23924 #define I2S_RCSR_RE_SHIFT                        (31U)
23925 /*! RE - Receiver Enable
23926  *  0b0..Receiver is disabled.
23927  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
23928  */
23929 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
23930 /*! @} */
23931 
23932 /*! @name RCR1 - SAI Receive Configuration 1 Register */
23933 /*! @{ */
23934 
23935 #define I2S_RCR1_RFW_MASK                        (0x1FU)
23936 #define I2S_RCR1_RFW_SHIFT                       (0U)
23937 /*! RFW - Receive FIFO Watermark
23938  */
23939 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
23940 /*! @} */
23941 
23942 /*! @name RCR2 - SAI Receive Configuration 2 Register */
23943 /*! @{ */
23944 
23945 #define I2S_RCR2_DIV_MASK                        (0xFFU)
23946 #define I2S_RCR2_DIV_SHIFT                       (0U)
23947 /*! DIV - Bit Clock Divide
23948  */
23949 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
23950 
23951 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
23952 #define I2S_RCR2_BCD_SHIFT                       (24U)
23953 /*! BCD - Bit Clock Direction
23954  *  0b0..Bit clock is generated externally in Slave mode.
23955  *  0b1..Bit clock is generated internally in Master mode.
23956  */
23957 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
23958 
23959 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
23960 #define I2S_RCR2_BCP_SHIFT                       (25U)
23961 /*! BCP - Bit Clock Polarity
23962  *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
23963  *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
23964  */
23965 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
23966 
23967 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
23968 #define I2S_RCR2_MSEL_SHIFT                      (26U)
23969 /*! MSEL - MCLK Select
23970  *  0b00..Bus Clock selected.
23971  *  0b01..Master Clock (MCLK) 1 option selected.
23972  *  0b10..Master Clock (MCLK) 2 option selected.
23973  *  0b11..Master Clock (MCLK) 3 option selected.
23974  */
23975 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
23976 
23977 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
23978 #define I2S_RCR2_BCI_SHIFT                       (28U)
23979 /*! BCI - Bit Clock Input
23980  *  0b0..No effect.
23981  *  0b1..Internal logic is clocked as if bit clock was externally generated.
23982  */
23983 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
23984 
23985 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
23986 #define I2S_RCR2_BCS_SHIFT                       (29U)
23987 /*! BCS - Bit Clock Swap
23988  *  0b0..Use the normal bit clock source.
23989  *  0b1..Swap the bit clock source.
23990  */
23991 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
23992 
23993 #define I2S_RCR2_SYNC_MASK                       (0x40000000U)
23994 #define I2S_RCR2_SYNC_SHIFT                      (30U)
23995 /*! SYNC - Synchronous Mode
23996  *  0b0..Asynchronous mode.
23997  *  0b1..Synchronous with transmitter.
23998  */
23999 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
24000 /*! @} */
24001 
24002 /*! @name RCR3 - SAI Receive Configuration 3 Register */
24003 /*! @{ */
24004 
24005 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
24006 #define I2S_RCR3_WDFL_SHIFT                      (0U)
24007 /*! WDFL - Word Flag Configuration
24008  */
24009 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
24010 
24011 #define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
24012 #define I2S_RCR3_RCE_SHIFT                       (16U)
24013 /*! RCE - Receive Channel Enable
24014  */
24015 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
24016 
24017 #define I2S_RCR3_CFR_MASK                        (0xF000000U)
24018 #define I2S_RCR3_CFR_SHIFT                       (24U)
24019 /*! CFR - Channel FIFO Reset
24020  */
24021 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
24022 /*! @} */
24023 
24024 /*! @name RCR4 - SAI Receive Configuration 4 Register */
24025 /*! @{ */
24026 
24027 #define I2S_RCR4_FSD_MASK                        (0x1U)
24028 #define I2S_RCR4_FSD_SHIFT                       (0U)
24029 /*! FSD - Frame Sync Direction
24030  *  0b0..Frame Sync is generated externally in Slave mode.
24031  *  0b1..Frame Sync is generated internally in Master mode.
24032  */
24033 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
24034 
24035 #define I2S_RCR4_FSP_MASK                        (0x2U)
24036 #define I2S_RCR4_FSP_SHIFT                       (1U)
24037 /*! FSP - Frame Sync Polarity
24038  *  0b0..Frame sync is active high.
24039  *  0b1..Frame sync is active low.
24040  */
24041 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
24042 
24043 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
24044 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
24045 /*! ONDEM - On Demand Mode
24046  *  0b0..Internal frame sync is generated continuously.
24047  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
24048  */
24049 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
24050 
24051 #define I2S_RCR4_FSE_MASK                        (0x8U)
24052 #define I2S_RCR4_FSE_SHIFT                       (3U)
24053 /*! FSE - Frame Sync Early
24054  *  0b0..Frame sync asserts with the first bit of the frame.
24055  *  0b1..Frame sync asserts one bit before the first bit of the frame.
24056  */
24057 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
24058 
24059 #define I2S_RCR4_MF_MASK                         (0x10U)
24060 #define I2S_RCR4_MF_SHIFT                        (4U)
24061 /*! MF - MSB First
24062  *  0b0..LSB is received first.
24063  *  0b1..MSB is received first.
24064  */
24065 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
24066 
24067 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
24068 #define I2S_RCR4_SYWD_SHIFT                      (8U)
24069 /*! SYWD - Sync Width
24070  */
24071 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
24072 
24073 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
24074 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
24075 /*! FRSZ - Frame Size
24076  */
24077 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
24078 
24079 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
24080 #define I2S_RCR4_FPACK_SHIFT                     (24U)
24081 /*! FPACK - FIFO Packing Mode
24082  *  0b00..FIFO packing is disabled
24083  *  0b01..Reserved.
24084  *  0b10..8-bit FIFO packing is enabled
24085  *  0b11..16-bit FIFO packing is enabled
24086  */
24087 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
24088 
24089 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
24090 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
24091 /*! FCOMB - FIFO Combine Mode
24092  *  0b00..FIFO combine mode disabled.
24093  *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
24094  *  0b10..FIFO combine mode enabled on FIFO reads (by software).
24095  *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
24096  */
24097 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
24098 
24099 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
24100 #define I2S_RCR4_FCONT_SHIFT                     (28U)
24101 /*! FCONT - FIFO Continue on Error
24102  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
24103  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
24104  */
24105 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
24106 /*! @} */
24107 
24108 /*! @name RCR5 - SAI Receive Configuration 5 Register */
24109 /*! @{ */
24110 
24111 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
24112 #define I2S_RCR5_FBT_SHIFT                       (8U)
24113 /*! FBT - First Bit Shifted
24114  */
24115 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
24116 
24117 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
24118 #define I2S_RCR5_W0W_SHIFT                       (16U)
24119 /*! W0W - Word 0 Width
24120  */
24121 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
24122 
24123 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
24124 #define I2S_RCR5_WNW_SHIFT                       (24U)
24125 /*! WNW - Word N Width
24126  */
24127 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
24128 /*! @} */
24129 
24130 /*! @name RDR - SAI Receive Data Register */
24131 /*! @{ */
24132 
24133 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
24134 #define I2S_RDR_RDR_SHIFT                        (0U)
24135 /*! RDR - Receive Data Register
24136  */
24137 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
24138 /*! @} */
24139 
24140 /* The count of I2S_RDR */
24141 #define I2S_RDR_COUNT                            (4U)
24142 
24143 /*! @name RFR - SAI Receive FIFO Register */
24144 /*! @{ */
24145 
24146 #define I2S_RFR_RFP_MASK                         (0x3FU)
24147 #define I2S_RFR_RFP_SHIFT                        (0U)
24148 /*! RFP - Read FIFO Pointer
24149  */
24150 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
24151 
24152 #define I2S_RFR_RCP_MASK                         (0x8000U)
24153 #define I2S_RFR_RCP_SHIFT                        (15U)
24154 /*! RCP - Receive Channel Pointer
24155  *  0b0..No effect.
24156  *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
24157  */
24158 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
24159 
24160 #define I2S_RFR_WFP_MASK                         (0x3F0000U)
24161 #define I2S_RFR_WFP_SHIFT                        (16U)
24162 /*! WFP - Write FIFO Pointer
24163  */
24164 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
24165 /*! @} */
24166 
24167 /* The count of I2S_RFR */
24168 #define I2S_RFR_COUNT                            (4U)
24169 
24170 /*! @name RMR - SAI Receive Mask Register */
24171 /*! @{ */
24172 
24173 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
24174 #define I2S_RMR_RWM_SHIFT                        (0U)
24175 /*! RWM - Receive Word Mask
24176  *  0b00000000000000000000000000000000..Word N is enabled.
24177  *  0b00000000000000000000000000000001..Word N is masked.
24178  */
24179 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
24180 /*! @} */
24181 
24182 
24183 /*!
24184  * @}
24185  */ /* end of group I2S_Register_Masks */
24186 
24187 
24188 /* I2S - Peripheral instance base addresses */
24189 /** Peripheral SAI1 base address */
24190 #define SAI1_BASE                                (0x40384000u)
24191 /** Peripheral SAI1 base pointer */
24192 #define SAI1                                     ((I2S_Type *)SAI1_BASE)
24193 /** Peripheral SAI2 base address */
24194 #define SAI2_BASE                                (0x40388000u)
24195 /** Peripheral SAI2 base pointer */
24196 #define SAI2                                     ((I2S_Type *)SAI2_BASE)
24197 /** Peripheral SAI3 base address */
24198 #define SAI3_BASE                                (0x4038C000u)
24199 /** Peripheral SAI3 base pointer */
24200 #define SAI3                                     ((I2S_Type *)SAI3_BASE)
24201 /** Array initializer of I2S peripheral base addresses */
24202 #define I2S_BASE_ADDRS                           { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
24203 /** Array initializer of I2S peripheral base pointers */
24204 #define I2S_BASE_PTRS                            { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
24205 /** Interrupt vectors for the I2S peripheral type */
24206 #define I2S_RX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
24207 #define I2S_TX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
24208 
24209 /*!
24210  * @}
24211  */ /* end of group I2S_Peripheral_Access_Layer */
24212 
24213 
24214 /* ----------------------------------------------------------------------------
24215    -- IOMUXC Peripheral Access Layer
24216    ---------------------------------------------------------------------------- */
24217 
24218 /*!
24219  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
24220  * @{
24221  */
24222 
24223 /** IOMUXC - Register Layout Typedef */
24224 typedef struct {
24225        uint8_t RESERVED_0[20];
24226   __IO uint32_t SW_MUX_CTL_PAD[124];               /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */
24227   __IO uint32_t SW_PAD_CTL_PAD[124];               /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */
24228   __IO uint32_t SELECT_INPUT[154];                 /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR_INOUT23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */
24229 } IOMUXC_Type;
24230 
24231 /* ----------------------------------------------------------------------------
24232    -- IOMUXC Register Masks
24233    ---------------------------------------------------------------------------- */
24234 
24235 /*!
24236  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
24237  * @{
24238  */
24239 
24240 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */
24241 /*! @{ */
24242 
24243 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0x7U)
24244 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
24245 /*! MUX_MODE - MUX Mode Select Field. Note: Some functions are available on multiple pins. A given
24246  *    function should not be selected for more than one pin.
24247  *  0b000..Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: usb
24248  *  0b001..Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1
24249  *  0b010..Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1
24250  *  0b011..Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet
24251  *  0b100..Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi
24252  *  0b101..Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1
24253  *  0b110..Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2
24254  *  0b111..Select mux mode: ALT7 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1
24255  */
24256 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
24257 
24258 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
24259 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
24260 /*! SION - Software Input On Field.
24261  *  0b1..Force input path of pad GPIO_AD_B0_00
24262  *  0b0..Input Path is determined by functionality
24263  */
24264 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
24265 /*! @} */
24266 
24267 /* The count of IOMUXC_SW_MUX_CTL_PAD */
24268 #define IOMUXC_SW_MUX_CTL_PAD_COUNT              (124U)
24269 
24270 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */
24271 /*! @{ */
24272 
24273 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK           (0x1U)
24274 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT          (0U)
24275 /*! SRE - Slew Rate Field
24276  *  0b0..Slow Slew Rate
24277  *  0b1..Fast Slew Rate
24278  */
24279 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
24280 
24281 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x38U)
24282 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (3U)
24283 /*! DSE - Drive Strength Field
24284  *  0b000..HI-Z
24285  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
24286  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
24287  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
24288  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
24289  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
24290  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
24291  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
24292  */
24293 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
24294 
24295 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK         (0xC0U)
24296 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT        (6U)
24297 /*! SPEED - Speed Field
24298  *  0b00..50MHz
24299  *  0b01..100MHz - 150MHz
24300  *  0b10..100MHz - 150MHz
24301  *  0b11..150MHz - 200MHz
24302  */
24303 #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
24304 
24305 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x800U)
24306 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (11U)
24307 /*! ODE - Open Drain Enable Field
24308  *  0b0..Open Drain Disabled (Output is CMOS)
24309  *  0b1..Open Drain Enabled (Output is Open Drain)
24310  */
24311 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
24312 
24313 #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK           (0x1000U)
24314 #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT          (12U)
24315 /*! PKE - Pull / Keep Enable Field
24316  *  0b0..Pull/Keeper Disabled
24317  *  0b1..Pull/Keeper Enabled
24318  */
24319 #define IOMUXC_SW_PAD_CTL_PAD_PKE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
24320 
24321 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x2000U)
24322 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (13U)
24323 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
24324  *  0b0..Keep the previous output value when the output driver is disabled.
24325  *  0b1..Pull-up or pull-down (determined by PUS field).
24326  */
24327 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
24328 
24329 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK           (0xC000U)
24330 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT          (14U)
24331 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
24332  *  0b00..100K Ohm Pull Down
24333  *  0b01..47K Ohm Pull Up
24334  *  0b10..100K Ohm Pull Up
24335  *  0b11..22K Ohm Pull Up
24336  */
24337 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
24338 
24339 #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK           (0x10000U)
24340 #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT          (16U)
24341 /*! HYS - Hyst. Enable Field
24342  *  0b0..Hysteresis Disabled (CMOS input)
24343  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
24344  */
24345 #define IOMUXC_SW_PAD_CTL_PAD_HYS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
24346 /*! @} */
24347 
24348 /* The count of IOMUXC_SW_PAD_CTL_PAD */
24349 #define IOMUXC_SW_PAD_CTL_PAD_COUNT              (124U)
24350 
24351 /*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR_INOUT23_SELECT_INPUT DAISY Register */
24352 /*! @{ */
24353 
24354 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0x7U)  /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
24355 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
24356 /*! DAISY - Selecting Pads Involved in Daisy Chain.
24357  *  0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6
24358  *  0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1
24359  *  0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4
24360  *  0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3
24361  *  0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3
24362  */
24363 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
24364 /*! @} */
24365 
24366 /* The count of IOMUXC_SELECT_INPUT */
24367 #define IOMUXC_SELECT_INPUT_COUNT                (154U)
24368 
24369 
24370 /*!
24371  * @}
24372  */ /* end of group IOMUXC_Register_Masks */
24373 
24374 
24375 /* IOMUXC - Peripheral instance base addresses */
24376 /** Peripheral IOMUXC base address */
24377 #define IOMUXC_BASE                              (0x401F8000u)
24378 /** Peripheral IOMUXC base pointer */
24379 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
24380 /** Array initializer of IOMUXC peripheral base addresses */
24381 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
24382 /** Array initializer of IOMUXC peripheral base pointers */
24383 #define IOMUXC_BASE_PTRS                         { IOMUXC }
24384 
24385 /*!
24386  * @}
24387  */ /* end of group IOMUXC_Peripheral_Access_Layer */
24388 
24389 
24390 /* ----------------------------------------------------------------------------
24391    -- IOMUXC_GPR Peripheral Access Layer
24392    ---------------------------------------------------------------------------- */
24393 
24394 /*!
24395  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
24396  * @{
24397  */
24398 
24399 /** IOMUXC_GPR - Register Layout Typedef */
24400 typedef struct {
24401        uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
24402   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
24403   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
24404   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
24405   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
24406   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
24407   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
24408   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
24409   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
24410        uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
24411   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
24412   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
24413   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
24414   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
24415   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
24416        uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
24417   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
24418   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
24419   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
24420   __IO uint32_t GPR19;                             /**< GPR19 General Purpose Register, offset: 0x4C */
24421   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
24422   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
24423   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
24424   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
24425   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
24426   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
24427 } IOMUXC_GPR_Type;
24428 
24429 /* ----------------------------------------------------------------------------
24430    -- IOMUXC_GPR Register Masks
24431    ---------------------------------------------------------------------------- */
24432 
24433 /*!
24434  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
24435  * @{
24436  */
24437 
24438 /*! @name GPR1 - GPR1 General Purpose Register */
24439 /*! @{ */
24440 
24441 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK      (0x7U)
24442 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT     (0U)
24443 /*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select
24444  *  0b000..SAI1_CLK_ROOT
24445  *  0b001..SAI2_CLK_ROOT
24446  *  0b010..SAI3_CLK_ROOT
24447  *  0b011..iomux.sai1_ipg_clk_sai_mclk
24448  *  0b100..iomux.sai2_ipg_clk_sai_mclk
24449  *  0b101..iomux.sai3_ipg_clk_sai_mclk
24450  *  0b110..Reserved
24451  *  0b111..Reserved
24452  */
24453 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
24454 
24455 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK      (0x38U)
24456 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT     (3U)
24457 /*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select
24458  *  0b000..SAI1_CLK_ROOT
24459  *  0b001..SAI2_CLK_ROOT
24460  *  0b010..SAI3_CLK_ROOT
24461  *  0b011..iomux.sai1_ipg_clk_sai_mclk
24462  *  0b100..iomux.sai2_ipg_clk_sai_mclk
24463  *  0b101..iomux.sai3_ipg_clk_sai_mclk
24464  *  0b110..Reserved
24465  *  0b111..Reserved
24466  */
24467 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
24468 
24469 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK      (0xC0U)
24470 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT     (6U)
24471 /*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select
24472  *  0b00..ccm.spdif0_clk_root
24473  *  0b01..iomux.spdif_tx_clk2
24474  *  0b10..spdif.spdif_srclk
24475  *  0b11..spdif.spdif_outclock
24476  */
24477 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
24478 
24479 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK      (0x300U)
24480 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT     (8U)
24481 /*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select
24482  *  0b00..ccm.spdif0_clk_root
24483  *  0b01..iomux.spdif_tx_clk2
24484  *  0b10..spdif.spdif_srclk
24485  *  0b11..spdif.spdif_outclock
24486  */
24487 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
24488 
24489 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK      (0xC00U)
24490 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT     (10U)
24491 /*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select
24492  *  0b00..ccm.spdif0_clk_root
24493  *  0b01..iomux.spdif_tx_clk2
24494  *  0b10..spdif.spdif_srclk
24495  *  0b11..spdif.spdif_outclock
24496  */
24497 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
24498 
24499 #define IOMUXC_GPR_GPR1_GINT_MASK                (0x1000U)
24500 #define IOMUXC_GPR_GPR1_GINT_SHIFT               (12U)
24501 /*! GINT - Global Interrupt
24502  *  0b0..Global interrupt request is not asserted
24503  *  0b1..Global interrupt request is asserted. Interrupt is issued to Arm M7 IRQ#41 and GPC
24504  */
24505 #define IOMUXC_GPR_GPR1_GINT(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
24506 
24507 #define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK     (0x2000U)
24508 #define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT    (13U)
24509 /*! ENET_TX_CLK_SEL - ENET_TX_CLK select
24510  *  0b0..Do not use
24511  *  0b1..ENET_TX_CLK is the 25MHz MII clock
24512  */
24513 #define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK)
24514 
24515 #define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK    (0x20000U)
24516 #define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT   (17U)
24517 /*! ENET_REF_CLK_DIR - ENET_REF_CLK direction control
24518  *  0b0..ENET_REF_CLK is input
24519  *  0b1..ENET_REF_CLK is output driven by ref_enetpll0
24520  */
24521 #define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
24522 
24523 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK       (0x80000U)
24524 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT      (19U)
24525 /*! SAI1_MCLK_DIR - SAI1_MCLK signal direction control. Sets the direction for the SAI1_MCLK pin function.
24526  *  0b0..SAI1_MCLK is input signal
24527  *  0b1..SAI1_MCLK is output signal
24528  */
24529 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
24530 
24531 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK       (0x100000U)
24532 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT      (20U)
24533 /*! SAI2_MCLK_DIR - SAI2_MCLK signal direction control. Sets the direction for the SAI2_MCLK pin function.
24534  *  0b0..SAI2_MCLK is input signal
24535  *  0b1..SAI2_MCLK is output signal
24536  */
24537 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
24538 
24539 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK       (0x200000U)
24540 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT      (21U)
24541 /*! SAI3_MCLK_DIR - SAI3_MCLK signal direction control. Sets the direction for the SAI3_MCLK pin function.
24542  *  0b0..SAI3_MCLK is input signal
24543  *  0b1..SAI3_MCLK is output signal
24544  */
24545 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
24546 
24547 #define IOMUXC_GPR_GPR1_EXC_MON_MASK             (0x400000U)
24548 #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT            (22U)
24549 /*! EXC_MON - Exclusive monitor response select of illegal command
24550  *  0b0..OKAY response
24551  *  0b1..SLVError response
24552  */
24553 #define IOMUXC_GPR_GPR1_EXC_MON(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
24554 
24555 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK   (0x80000000U)
24556 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT  (31U)
24557 /*! CM7_FORCE_HCLK_EN - Arm CM7 platform AHB clock enable
24558  *  0b0..AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible
24559  *  0b1..AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible
24560  */
24561 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
24562 /*! @} */
24563 
24564 /*! @name GPR2 - GPR2 General Purpose Register */
24565 /*! @{ */
24566 
24567 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
24568 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
24569 /*! L2_MEM_EN_POWERSAVING - Enable power saving features on memory
24570  *  0b0..Enters power saving mode only when chip is in SUSPEND mode
24571  *  0b1..Controlled by L2_MEM_DEEPSLEEP bitfield
24572  */
24573 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
24574 
24575 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK    (0x4000U)
24576 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT   (14U)
24577 /*! L2_MEM_DEEPSLEEP
24578  *  0b0..No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)
24579  *  0b1..Force memory into deep sleep mode (OCRAM in power saving mode)
24580  */
24581 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
24582 
24583 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK         (0xFF0000U)
24584 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT        (16U)
24585 /*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency.
24586  *  0b00000000..mclk frequency = 1/1 * hmclk frequency
24587  *  0b00000001..mclk frequency = 1/2 * hmclk frequency
24588  *  0b00000010..mclk frequency = 1/3 * hmclk frequency
24589  *  0b00000011..mclk frequency = 1/4 * hmclk frequency
24590  *  0b00000100..mclk frequency = 1/5 * hmclk frequency
24591  *  0b00000101..mclk frequency = 1/6 * hmclk frequency
24592  *  0b00000110..mclk frequency = 1/7 * hmclk frequency
24593  *  0b00000111..mclk frequency = 1/8 * hmclk frequency
24594  *  0b00001000..mclk frequency = 1/9 * hmclk frequency
24595  *  0b00001001..mclk frequency = 1/10 * hmclk frequency
24596  *  0b00001010..mclk frequency = 1/11 * hmclk frequency
24597  *  0b00001011..mclk frequency = 1/12 * hmclk frequency
24598  *  0b00001100..mclk frequency = 1/13 * hmclk frequency
24599  *  0b00001101..mclk frequency = 1/14 * hmclk frequency
24600  *  0b00001110..mclk frequency = 1/15 * hmclk frequency
24601  *  0b00001111..mclk frequency = 1/16 * hmclk frequency
24602  *  0b00010000..mclk frequency = 1/17 * hmclk frequency
24603  *  0b00010001..mclk frequency = 1/18 * hmclk frequency
24604  *  0b00010010..mclk frequency = 1/19 * hmclk frequency
24605  *  0b00010011..mclk frequency = 1/20 * hmclk frequency
24606  *  0b00010100..mclk frequency = 1/21 * hmclk frequency
24607  *  0b00010101..mclk frequency = 1/22 * hmclk frequency
24608  *  0b00010110..mclk frequency = 1/23 * hmclk frequency
24609  *  0b00010111..mclk frequency = 1/24 * hmclk frequency
24610  *  0b00011000..mclk frequency = 1/25 * hmclk frequency
24611  *  0b00011001..mclk frequency = 1/26 * hmclk frequency
24612  *  0b00011010..mclk frequency = 1/27 * hmclk frequency
24613  *  0b00011011..mclk frequency = 1/28 * hmclk frequency
24614  *  0b00011100..mclk frequency = 1/29 * hmclk frequency
24615  *  0b00011101..mclk frequency = 1/30 * hmclk frequency
24616  *  0b00011110..mclk frequency = 1/31 * hmclk frequency
24617  *  0b00011111..mclk frequency = 1/32 * hmclk frequency
24618  *  0b00100000..mclk frequency = 1/33 * hmclk frequency
24619  *  0b00100001..mclk frequency = 1/34 * hmclk frequency
24620  *  0b00100010..mclk frequency = 1/35 * hmclk frequency
24621  *  0b00100011..mclk frequency = 1/36 * hmclk frequency
24622  *  0b00100100..mclk frequency = 1/37 * hmclk frequency
24623  *  0b00100101..mclk frequency = 1/38 * hmclk frequency
24624  *  0b00100110..mclk frequency = 1/39 * hmclk frequency
24625  *  0b00100111..mclk frequency = 1/40 * hmclk frequency
24626  *  0b00101000..mclk frequency = 1/41 * hmclk frequency
24627  *  0b00101001..mclk frequency = 1/42 * hmclk frequency
24628  *  0b00101010..mclk frequency = 1/43 * hmclk frequency
24629  *  0b00101011..mclk frequency = 1/44 * hmclk frequency
24630  *  0b00101100..mclk frequency = 1/45 * hmclk frequency
24631  *  0b00101101..mclk frequency = 1/46 * hmclk frequency
24632  *  0b00101110..mclk frequency = 1/47 * hmclk frequency
24633  *  0b00101111..mclk frequency = 1/48 * hmclk frequency
24634  *  0b00110000..mclk frequency = 1/49 * hmclk frequency
24635  *  0b00110001..mclk frequency = 1/50 * hmclk frequency
24636  *  0b00110010..mclk frequency = 1/51 * hmclk frequency
24637  *  0b00110011..mclk frequency = 1/52 * hmclk frequency
24638  *  0b00110100..mclk frequency = 1/53 * hmclk frequency
24639  *  0b00110101..mclk frequency = 1/54 * hmclk frequency
24640  *  0b00110110..mclk frequency = 1/55 * hmclk frequency
24641  *  0b00110111..mclk frequency = 1/56 * hmclk frequency
24642  *  0b00111000..mclk frequency = 1/57 * hmclk frequency
24643  *  0b00111001..mclk frequency = 1/58 * hmclk frequency
24644  *  0b00111010..mclk frequency = 1/59 * hmclk frequency
24645  *  0b00111011..mclk frequency = 1/60 * hmclk frequency
24646  *  0b00111100..mclk frequency = 1/61 * hmclk frequency
24647  *  0b00111101..mclk frequency = 1/62 * hmclk frequency
24648  *  0b00111110..mclk frequency = 1/63 * hmclk frequency
24649  *  0b00111111..mclk frequency = 1/64 * hmclk frequency
24650  *  0b01000000..mclk frequency = 1/65 * hmclk frequency
24651  *  0b01000001..mclk frequency = 1/66 * hmclk frequency
24652  *  0b01000010..mclk frequency = 1/67 * hmclk frequency
24653  *  0b01000011..mclk frequency = 1/68 * hmclk frequency
24654  *  0b01000100..mclk frequency = 1/69 * hmclk frequency
24655  *  0b01000101..mclk frequency = 1/70 * hmclk frequency
24656  *  0b01000110..mclk frequency = 1/71 * hmclk frequency
24657  *  0b01000111..mclk frequency = 1/72 * hmclk frequency
24658  *  0b01001000..mclk frequency = 1/73 * hmclk frequency
24659  *  0b01001001..mclk frequency = 1/74 * hmclk frequency
24660  *  0b01001010..mclk frequency = 1/75 * hmclk frequency
24661  *  0b01001011..mclk frequency = 1/76 * hmclk frequency
24662  *  0b01001100..mclk frequency = 1/77 * hmclk frequency
24663  *  0b01001101..mclk frequency = 1/78 * hmclk frequency
24664  *  0b01001110..mclk frequency = 1/79 * hmclk frequency
24665  *  0b01001111..mclk frequency = 1/80 * hmclk frequency
24666  *  0b01010000..mclk frequency = 1/81 * hmclk frequency
24667  *  0b01010001..mclk frequency = 1/82 * hmclk frequency
24668  *  0b01010010..mclk frequency = 1/83 * hmclk frequency
24669  *  0b01010011..mclk frequency = 1/84 * hmclk frequency
24670  *  0b01010100..mclk frequency = 1/85 * hmclk frequency
24671  *  0b01010101..mclk frequency = 1/86 * hmclk frequency
24672  *  0b01010110..mclk frequency = 1/87 * hmclk frequency
24673  *  0b01010111..mclk frequency = 1/88 * hmclk frequency
24674  *  0b01011000..mclk frequency = 1/89 * hmclk frequency
24675  *  0b01011001..mclk frequency = 1/90 * hmclk frequency
24676  *  0b01011010..mclk frequency = 1/91 * hmclk frequency
24677  *  0b01011011..mclk frequency = 1/92 * hmclk frequency
24678  *  0b01011100..mclk frequency = 1/93 * hmclk frequency
24679  *  0b01011101..mclk frequency = 1/94 * hmclk frequency
24680  *  0b01011110..mclk frequency = 1/95 * hmclk frequency
24681  *  0b01011111..mclk frequency = 1/96 * hmclk frequency
24682  *  0b01100000..mclk frequency = 1/97 * hmclk frequency
24683  *  0b01100001..mclk frequency = 1/98 * hmclk frequency
24684  *  0b01100010..mclk frequency = 1/99 * hmclk frequency
24685  *  0b01100011..mclk frequency = 1/100 * hmclk frequency
24686  *  0b01100100..mclk frequency = 1/101 * hmclk frequency
24687  *  0b01100101..mclk frequency = 1/102 * hmclk frequency
24688  *  0b01100110..mclk frequency = 1/103 * hmclk frequency
24689  *  0b01100111..mclk frequency = 1/104 * hmclk frequency
24690  *  0b01101000..mclk frequency = 1/105 * hmclk frequency
24691  *  0b01101001..mclk frequency = 1/106 * hmclk frequency
24692  *  0b01101010..mclk frequency = 1/107 * hmclk frequency
24693  *  0b01101011..mclk frequency = 1/108 * hmclk frequency
24694  *  0b01101100..mclk frequency = 1/109 * hmclk frequency
24695  *  0b01101101..mclk frequency = 1/110 * hmclk frequency
24696  *  0b01101110..mclk frequency = 1/111 * hmclk frequency
24697  *  0b01101111..mclk frequency = 1/112 * hmclk frequency
24698  *  0b01110000..mclk frequency = 1/113 * hmclk frequency
24699  *  0b01110001..mclk frequency = 1/114 * hmclk frequency
24700  *  0b01110010..mclk frequency = 1/115 * hmclk frequency
24701  *  0b01110011..mclk frequency = 1/116 * hmclk frequency
24702  *  0b01110100..mclk frequency = 1/117 * hmclk frequency
24703  *  0b01110101..mclk frequency = 1/118 * hmclk frequency
24704  *  0b01110110..mclk frequency = 1/119 * hmclk frequency
24705  *  0b01110111..mclk frequency = 1/120 * hmclk frequency
24706  *  0b01111000..mclk frequency = 1/121 * hmclk frequency
24707  *  0b01111001..mclk frequency = 1/122 * hmclk frequency
24708  *  0b01111010..mclk frequency = 1/123 * hmclk frequency
24709  *  0b01111011..mclk frequency = 1/124 * hmclk frequency
24710  *  0b01111100..mclk frequency = 1/125 * hmclk frequency
24711  *  0b01111101..mclk frequency = 1/126 * hmclk frequency
24712  *  0b01111110..mclk frequency = 1/127 * hmclk frequency
24713  *  0b01111111..mclk frequency = 1/128 * hmclk frequency
24714  *  0b10000000..mclk frequency = 1/129 * hmclk frequency
24715  *  0b10000001..mclk frequency = 1/130 * hmclk frequency
24716  *  0b10000010..mclk frequency = 1/131 * hmclk frequency
24717  *  0b10000011..mclk frequency = 1/132 * hmclk frequency
24718  *  0b10000100..mclk frequency = 1/133 * hmclk frequency
24719  *  0b10000101..mclk frequency = 1/134 * hmclk frequency
24720  *  0b10000110..mclk frequency = 1/135 * hmclk frequency
24721  *  0b10000111..mclk frequency = 1/136 * hmclk frequency
24722  *  0b10001000..mclk frequency = 1/137 * hmclk frequency
24723  *  0b10001001..mclk frequency = 1/138 * hmclk frequency
24724  *  0b10001010..mclk frequency = 1/139 * hmclk frequency
24725  *  0b10001011..mclk frequency = 1/140 * hmclk frequency
24726  *  0b10001100..mclk frequency = 1/141 * hmclk frequency
24727  *  0b10001101..mclk frequency = 1/142 * hmclk frequency
24728  *  0b10001110..mclk frequency = 1/143 * hmclk frequency
24729  *  0b10001111..mclk frequency = 1/144 * hmclk frequency
24730  *  0b10010000..mclk frequency = 1/145 * hmclk frequency
24731  *  0b10010001..mclk frequency = 1/146 * hmclk frequency
24732  *  0b10010010..mclk frequency = 1/147 * hmclk frequency
24733  *  0b10010011..mclk frequency = 1/148 * hmclk frequency
24734  *  0b10010100..mclk frequency = 1/149 * hmclk frequency
24735  *  0b10010101..mclk frequency = 1/150 * hmclk frequency
24736  *  0b10010110..mclk frequency = 1/151 * hmclk frequency
24737  *  0b10010111..mclk frequency = 1/152 * hmclk frequency
24738  *  0b10011000..mclk frequency = 1/153 * hmclk frequency
24739  *  0b10011001..mclk frequency = 1/154 * hmclk frequency
24740  *  0b10011010..mclk frequency = 1/155 * hmclk frequency
24741  *  0b10011011..mclk frequency = 1/156 * hmclk frequency
24742  *  0b10011100..mclk frequency = 1/157 * hmclk frequency
24743  *  0b10011101..mclk frequency = 1/158 * hmclk frequency
24744  *  0b10011110..mclk frequency = 1/159 * hmclk frequency
24745  *  0b10011111..mclk frequency = 1/160 * hmclk frequency
24746  *  0b10100000..mclk frequency = 1/161 * hmclk frequency
24747  *  0b10100001..mclk frequency = 1/162 * hmclk frequency
24748  *  0b10100010..mclk frequency = 1/163 * hmclk frequency
24749  *  0b10100011..mclk frequency = 1/164 * hmclk frequency
24750  *  0b10100100..mclk frequency = 1/165 * hmclk frequency
24751  *  0b10100101..mclk frequency = 1/166 * hmclk frequency
24752  *  0b10100110..mclk frequency = 1/167 * hmclk frequency
24753  *  0b10100111..mclk frequency = 1/168 * hmclk frequency
24754  *  0b10101000..mclk frequency = 1/169 * hmclk frequency
24755  *  0b10101001..mclk frequency = 1/170 * hmclk frequency
24756  *  0b10101010..mclk frequency = 1/171 * hmclk frequency
24757  *  0b10101011..mclk frequency = 1/172 * hmclk frequency
24758  *  0b10101100..mclk frequency = 1/173 * hmclk frequency
24759  *  0b10101101..mclk frequency = 1/174 * hmclk frequency
24760  *  0b10101110..mclk frequency = 1/175 * hmclk frequency
24761  *  0b10101111..mclk frequency = 1/176 * hmclk frequency
24762  *  0b10110000..mclk frequency = 1/177 * hmclk frequency
24763  *  0b10110001..mclk frequency = 1/178 * hmclk frequency
24764  *  0b10110010..mclk frequency = 1/179 * hmclk frequency
24765  *  0b10110011..mclk frequency = 1/180 * hmclk frequency
24766  *  0b10110100..mclk frequency = 1/181 * hmclk frequency
24767  *  0b10110101..mclk frequency = 1/182 * hmclk frequency
24768  *  0b10110110..mclk frequency = 1/183 * hmclk frequency
24769  *  0b10110111..mclk frequency = 1/184 * hmclk frequency
24770  *  0b10111000..mclk frequency = 1/185 * hmclk frequency
24771  *  0b10111001..mclk frequency = 1/186 * hmclk frequency
24772  *  0b10111010..mclk frequency = 1/187 * hmclk frequency
24773  *  0b10111011..mclk frequency = 1/188 * hmclk frequency
24774  *  0b10111100..mclk frequency = 1/189 * hmclk frequency
24775  *  0b10111101..mclk frequency = 1/190 * hmclk frequency
24776  *  0b10111110..mclk frequency = 1/191 * hmclk frequency
24777  *  0b10111111..mclk frequency = 1/192 * hmclk frequency
24778  *  0b11000000..mclk frequency = 1/193 * hmclk frequency
24779  *  0b11000001..mclk frequency = 1/194 * hmclk frequency
24780  *  0b11000010..mclk frequency = 1/195 * hmclk frequency
24781  *  0b11000011..mclk frequency = 1/196 * hmclk frequency
24782  *  0b11000100..mclk frequency = 1/197 * hmclk frequency
24783  *  0b11000101..mclk frequency = 1/198 * hmclk frequency
24784  *  0b11000110..mclk frequency = 1/199 * hmclk frequency
24785  *  0b11000111..mclk frequency = 1/200 * hmclk frequency
24786  *  0b11001000..mclk frequency = 1/201 * hmclk frequency
24787  *  0b11001001..mclk frequency = 1/202 * hmclk frequency
24788  *  0b11001010..mclk frequency = 1/203 * hmclk frequency
24789  *  0b11001011..mclk frequency = 1/204 * hmclk frequency
24790  *  0b11001100..mclk frequency = 1/205 * hmclk frequency
24791  *  0b11001101..mclk frequency = 1/206 * hmclk frequency
24792  *  0b11001110..mclk frequency = 1/207 * hmclk frequency
24793  *  0b11001111..mclk frequency = 1/208 * hmclk frequency
24794  *  0b11010000..mclk frequency = 1/209 * hmclk frequency
24795  *  0b11010001..mclk frequency = 1/210 * hmclk frequency
24796  *  0b11010010..mclk frequency = 1/211 * hmclk frequency
24797  *  0b11010011..mclk frequency = 1/212 * hmclk frequency
24798  *  0b11010100..mclk frequency = 1/213 * hmclk frequency
24799  *  0b11010101..mclk frequency = 1/214 * hmclk frequency
24800  *  0b11010110..mclk frequency = 1/215 * hmclk frequency
24801  *  0b11010111..mclk frequency = 1/216 * hmclk frequency
24802  *  0b11011000..mclk frequency = 1/217 * hmclk frequency
24803  *  0b11011001..mclk frequency = 1/218 * hmclk frequency
24804  *  0b11011010..mclk frequency = 1/219 * hmclk frequency
24805  *  0b11011011..mclk frequency = 1/220 * hmclk frequency
24806  *  0b11011100..mclk frequency = 1/221 * hmclk frequency
24807  *  0b11011101..mclk frequency = 1/222 * hmclk frequency
24808  *  0b11011110..mclk frequency = 1/223 * hmclk frequency
24809  *  0b11011111..mclk frequency = 1/224 * hmclk frequency
24810  *  0b11100000..mclk frequency = 1/225 * hmclk frequency
24811  *  0b11100001..mclk frequency = 1/226 * hmclk frequency
24812  *  0b11100010..mclk frequency = 1/227 * hmclk frequency
24813  *  0b11100011..mclk frequency = 1/228 * hmclk frequency
24814  *  0b11100100..mclk frequency = 1/229 * hmclk frequency
24815  *  0b11100101..mclk frequency = 1/230 * hmclk frequency
24816  *  0b11100110..mclk frequency = 1/231 * hmclk frequency
24817  *  0b11100111..mclk frequency = 1/232 * hmclk frequency
24818  *  0b11101000..mclk frequency = 1/233 * hmclk frequency
24819  *  0b11101001..mclk frequency = 1/234 * hmclk frequency
24820  *  0b11101010..mclk frequency = 1/235 * hmclk frequency
24821  *  0b11101011..mclk frequency = 1/236 * hmclk frequency
24822  *  0b11101100..mclk frequency = 1/237 * hmclk frequency
24823  *  0b11101101..mclk frequency = 1/238 * hmclk frequency
24824  *  0b11101110..mclk frequency = 1/239 * hmclk frequency
24825  *  0b11101111..mclk frequency = 1/240 * hmclk frequency
24826  *  0b11110000..mclk frequency = 1/241 * hmclk frequency
24827  *  0b11110001..mclk frequency = 1/242 * hmclk frequency
24828  *  0b11110010..mclk frequency = 1/243 * hmclk frequency
24829  *  0b11110011..mclk frequency = 1/244 * hmclk frequency
24830  *  0b11110100..mclk frequency = 1/245 * hmclk frequency
24831  *  0b11110101..mclk frequency = 1/246 * hmclk frequency
24832  *  0b11110110..mclk frequency = 1/247 * hmclk frequency
24833  *  0b11110111..mclk frequency = 1/248 * hmclk frequency
24834  *  0b11111000..mclk frequency = 1/249 * hmclk frequency
24835  *  0b11111001..mclk frequency = 1/250 * hmclk frequency
24836  *  0b11111010..mclk frequency = 1/251 * hmclk frequency
24837  *  0b11111011..mclk frequency = 1/252 * hmclk frequency
24838  *  0b11111100..mclk frequency = 1/253 * hmclk frequency
24839  *  0b11111101..mclk frequency = 1/254 * hmclk frequency
24840  *  0b11111110..mclk frequency = 1/255 * hmclk frequency
24841  *  0b11111111..mclk frequency = 1/256 * hmclk frequency
24842  */
24843 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
24844 
24845 #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK          (0x1000000U)
24846 #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT         (24U)
24847 /*! MQS_SW_RST
24848  *  0b0..Exit software reset for MQS
24849  *  0b1..Enable software reset for MQS
24850  */
24851 #define IOMUXC_GPR_GPR2_MQS_SW_RST(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
24852 
24853 #define IOMUXC_GPR_GPR2_MQS_EN_MASK              (0x2000000U)
24854 #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT             (25U)
24855 /*! MQS_EN
24856  *  0b0..Disable MQS
24857  *  0b1..Enable MQS
24858  */
24859 #define IOMUXC_GPR_GPR2_MQS_EN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
24860 
24861 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK      (0x4000000U)
24862 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT     (26U)
24863 /*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample
24864  *  0b0..32
24865  *  0b1..64
24866  */
24867 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
24868 
24869 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
24870 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
24871 /*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze
24872  *  0b0..Timer counter works normally
24873  *  0b1..Reset counter and ouput flags
24874  */
24875 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
24876 
24877 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
24878 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
24879 /*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze
24880  *  0b0..Timer counter works normally
24881  *  0b1..Reset counter and ouput flags
24882  */
24883 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
24884 
24885 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
24886 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
24887 /*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze
24888  *  0b0..Timer counter works normally
24889  *  0b1..Reset counter and ouput flags
24890  */
24891 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
24892 
24893 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
24894 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
24895 /*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze
24896  *  0b0..Timer counter works normally
24897  *  0b1..Reset counter and ouput flags
24898  */
24899 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
24900 /*! @} */
24901 
24902 /*! @name GPR3 - GPR3 General Purpose Register */
24903 /*! @{ */
24904 
24905 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK         (0x10U)
24906 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT        (4U)
24907 /*! DCP_KEY_SEL - Select 128-bit DCP key from 256-bit key from SNVS Master Key
24908  *  0b0..Select [127:0] from SNVS Master Key as DCP key
24909  *  0b1..Select [255:128] from SNVS Master Key as DCP key
24910  */
24911 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
24912 /*! @} */
24913 
24914 /*! @name GPR4 - GPR4 General Purpose Register */
24915 /*! @{ */
24916 
24917 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK       (0x1U)
24918 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT      (0U)
24919 /*! EDMA_STOP_REQ - EDMA stop request
24920  *  0b0..stop request off
24921  *  0b1..stop request on
24922  */
24923 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
24924 
24925 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK       (0x2U)
24926 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT      (1U)
24927 /*! CAN1_STOP_REQ - CAN1 stop request
24928  *  0b0..stop request off
24929  *  0b1..stop request on
24930  */
24931 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
24932 
24933 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK       (0x4U)
24934 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT      (2U)
24935 /*! CAN2_STOP_REQ - CAN2 stop request
24936  *  0b0..stop request off
24937  *  0b1..stop request on
24938  */
24939 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
24940 
24941 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK       (0x8U)
24942 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT      (3U)
24943 /*! TRNG_STOP_REQ - TRNG stop request
24944  *  0b0..stop request off
24945  *  0b1..stop request on
24946  */
24947 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
24948 
24949 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK       (0x10U)
24950 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT      (4U)
24951 /*! ENET_STOP_REQ - ENET stop request
24952  *  0b0..stop request off
24953  *  0b1..stop request on
24954  */
24955 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
24956 
24957 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK       (0x20U)
24958 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT      (5U)
24959 /*! SAI1_STOP_REQ - SAI1 stop request
24960  *  0b0..stop request off
24961  *  0b1..stop request on
24962  */
24963 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
24964 
24965 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK       (0x40U)
24966 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT      (6U)
24967 /*! SAI2_STOP_REQ - SAI2 stop request
24968  *  0b0..stop request off
24969  *  0b1..stop request on
24970  */
24971 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
24972 
24973 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK       (0x80U)
24974 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT      (7U)
24975 /*! SAI3_STOP_REQ - SAI3 stop request
24976  *  0b0..stop request off
24977  *  0b1..stop request on
24978  */
24979 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
24980 
24981 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK       (0x200U)
24982 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT      (9U)
24983 /*! SEMC_STOP_REQ - SEMC stop request
24984  *  0b0..stop request off
24985  *  0b1..stop request on
24986  */
24987 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
24988 
24989 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK        (0x400U)
24990 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT       (10U)
24991 /*! PIT_STOP_REQ - PIT stop request
24992  *  0b0..stop request off
24993  *  0b1..stop request on
24994  */
24995 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
24996 
24997 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK    (0x800U)
24998 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT   (11U)
24999 /*! FLEXSPI_STOP_REQ - FlexSPI stop request
25000  *  0b0..stop request off
25001  *  0b1..stop request on
25002  */
25003 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
25004 
25005 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK    (0x1000U)
25006 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT   (12U)
25007 /*! FLEXIO1_STOP_REQ - FlexIO1 stop request
25008  *  0b0..stop request off
25009  *  0b1..stop request on
25010  */
25011 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
25012 
25013 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK    (0x2000U)
25014 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT   (13U)
25015 /*! FLEXIO2_STOP_REQ - FlexIO2 stop request
25016  *  0b0..stop request off
25017  *  0b1..stop request on
25018  */
25019 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
25020 
25021 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK       (0x10000U)
25022 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT      (16U)
25023 /*! EDMA_STOP_ACK - EDMA stop acknowledge
25024  *  0b0..EDMA stop acknowledge is not asserted
25025  *  0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode)
25026  */
25027 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
25028 
25029 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK       (0x20000U)
25030 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT      (17U)
25031 /*! CAN1_STOP_ACK - CAN1 stop acknowledge
25032  *  0b0..CAN1 stop acknowledge is not asserted
25033  *  0b1..CAN1 stop acknowledge is asserted
25034  */
25035 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
25036 
25037 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK       (0x40000U)
25038 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT      (18U)
25039 /*! CAN2_STOP_ACK - CAN2 stop acknowledge
25040  *  0b0..CAN2 stop acknowledge is not asserted
25041  *  0b1..CAN2 stop acknowledge is asserted
25042  */
25043 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
25044 
25045 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK       (0x80000U)
25046 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT      (19U)
25047 /*! TRNG_STOP_ACK - TRNG stop acknowledge
25048  *  0b0..TRNG stop acknowledge is not asserted
25049  *  0b1..TRNG stop acknowledge is asserted
25050  */
25051 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
25052 
25053 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK       (0x100000U)
25054 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT      (20U)
25055 /*! ENET_STOP_ACK - ENET stop acknowledge
25056  *  0b0..ENET stop acknowledge is not asserted
25057  *  0b1..ENET stop acknowledge is asserted
25058  */
25059 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
25060 
25061 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK       (0x200000U)
25062 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT      (21U)
25063 /*! SAI1_STOP_ACK - SAI1 stop acknowledge
25064  *  0b0..SAI1 stop acknowledge is not asserted
25065  *  0b1..SAI1 stop acknowledge is asserted
25066  */
25067 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
25068 
25069 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK       (0x400000U)
25070 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT      (22U)
25071 /*! SAI2_STOP_ACK - SAI2 stop acknowledge
25072  *  0b0..SAI2 stop acknowledge is not asserted
25073  *  0b1..SAI2 stop acknowledge is asserted
25074  */
25075 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
25076 
25077 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK       (0x800000U)
25078 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT      (23U)
25079 /*! SAI3_STOP_ACK - SAI3 stop acknowledge
25080  *  0b0..SAI3 stop acknowledge is not asserted
25081  *  0b1..SAI3 stop acknowledge is asserted
25082  */
25083 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
25084 
25085 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK       (0x2000000U)
25086 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT      (25U)
25087 /*! SEMC_STOP_ACK - SEMC stop acknowledge
25088  *  0b0..SEMC stop acknowledge is not asserted
25089  *  0b1..SEMC stop acknowledge is asserted
25090  */
25091 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
25092 
25093 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK        (0x4000000U)
25094 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT       (26U)
25095 /*! PIT_STOP_ACK - PIT stop acknowledge
25096  *  0b0..PIT stop acknowledge is not asserted
25097  *  0b1..PIT stop acknowledge is asserted
25098  */
25099 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
25100 
25101 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK    (0x8000000U)
25102 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT   (27U)
25103 /*! FLEXSPI_STOP_ACK - FLEXSPI stop acknowledge
25104  *  0b0..FLEXSPI stop acknowledge is not asserted
25105  *  0b1..FLEXSPI stop acknowledge is asserted
25106  */
25107 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
25108 
25109 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK    (0x10000000U)
25110 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT   (28U)
25111 /*! FLEXIO1_STOP_ACK - FLEXIO1 stop acknowledge
25112  *  0b0..FLEXIO1 stop acknowledge is not asserted
25113  *  0b1..FLEXIO1 stop acknowledge is asserted
25114  */
25115 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
25116 
25117 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK    (0x20000000U)
25118 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT   (29U)
25119 /*! FLEXIO2_STOP_ACK - FLEXIO2 stop acknowledge
25120  *  0b0..FLEXIO2 stop acknowledge is not asserted
25121  *  0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)
25122  */
25123 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
25124 /*! @} */
25125 
25126 /*! @name GPR5 - GPR5 General Purpose Register */
25127 /*! @{ */
25128 
25129 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK          (0x40U)
25130 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT         (6U)
25131 /*! WDOG1_MASK
25132  *  0b0..WDOG1 Timeout behaves normally
25133  *  0b1..WDOG1 Timeout is masked
25134  */
25135 #define IOMUXC_GPR_GPR5_WDOG1_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
25136 
25137 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK          (0x80U)
25138 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT         (7U)
25139 /*! WDOG2_MASK
25140  *  0b0..WDOG2 Timeout behaves normally
25141  *  0b1..WDOG2 Timeout is masked
25142  */
25143 #define IOMUXC_GPR_GPR5_WDOG2_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
25144 
25145 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK     (0x800000U)
25146 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT    (23U)
25147 /*! GPT2_CAPIN1_SEL
25148  *  0b0..source from pad
25149  *  0b1..source from enet1.ipp_do_mac0_timer[3]
25150  */
25151 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
25152 
25153 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK   (0x2000000U)
25154 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT  (25U)
25155 /*! ENET_EVENT3IN_SEL
25156  *  0b0..event3 source input from pad
25157  *  0b1..event3 source input from gpt2.ipp_do_cmpout1
25158  */
25159 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
25160 
25161 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK    (0x10000000U)
25162 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT   (28U)
25163 /*! VREF_1M_CLK_GPT1
25164  *  0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK. IPG_PERCLK is derived from either BUS clock or OSC_24M clock.
25165  *       See CCM chapter for more information
25166  *  0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock. Anatop 1M clock is derived from the OSC_RC_24M clock.
25167  *       It has two versions: corrected by 32k clock or un-corrected. See the XTALOSC24M_OSC_CONFIG2 register for
25168  *       more details
25169  */
25170 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
25171 
25172 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK    (0x20000000U)
25173 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT   (29U)
25174 /*! VREF_1M_CLK_GPT2
25175  *  0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK. IPG_PERCLK is derived from either BUS clock or OSC_24M clock.
25176  *       See CCM chapter for more information
25177  *  0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock. Anatop 1M clock is derived from the OSC_RC_24M clock.
25178  *       It has two versions: corrected by 32k clock or un-corrected. See the XTALOSC24M_OSC_CONFIG2 register for
25179  *       more details
25180  */
25181 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
25182 /*! @} */
25183 
25184 /*! @name GPR6 - GPR6 General Purpose Register */
25185 /*! @{ */
25186 
25187 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
25188 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
25189 /*! QTIMER1_TRM0_INPUT_SEL
25190  *  0b0..input from IOMUX
25191  *  0b1..input from XBAR
25192  */
25193 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
25194 
25195 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
25196 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
25197 /*! QTIMER1_TRM1_INPUT_SEL
25198  *  0b0..input from IOMUX
25199  *  0b1..input from XBAR
25200  */
25201 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
25202 
25203 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
25204 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
25205 /*! QTIMER1_TRM2_INPUT_SEL
25206  *  0b0..input from IOMUX
25207  *  0b1..input from XBAR
25208  */
25209 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
25210 
25211 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
25212 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
25213 /*! QTIMER1_TRM3_INPUT_SEL
25214  *  0b0..input from IOMUX
25215  *  0b1..input from XBAR
25216  */
25217 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
25218 
25219 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
25220 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
25221 /*! QTIMER2_TRM0_INPUT_SEL
25222  *  0b0..input from IOMUX
25223  *  0b1..input from XBAR
25224  */
25225 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
25226 
25227 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
25228 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
25229 /*! QTIMER2_TRM1_INPUT_SEL
25230  *  0b0..input from IOMUX
25231  *  0b1..input from XBAR
25232  */
25233 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
25234 
25235 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
25236 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
25237 /*! QTIMER2_TRM2_INPUT_SEL
25238  *  0b0..input from IOMUX
25239  *  0b1..input from XBAR
25240  */
25241 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
25242 
25243 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
25244 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
25245 /*! QTIMER2_TRM3_INPUT_SEL
25246  *  0b0..input from IOMUX
25247  *  0b1..input from XBAR
25248  */
25249 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
25250 
25251 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
25252 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
25253 /*! QTIMER3_TRM0_INPUT_SEL
25254  *  0b0..input from IOMUX
25255  *  0b1..input from XBAR
25256  */
25257 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
25258 
25259 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
25260 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
25261 /*! QTIMER3_TRM1_INPUT_SEL
25262  *  0b0..input from IOMUX
25263  *  0b1..input from XBAR
25264  */
25265 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
25266 
25267 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
25268 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
25269 /*! QTIMER3_TRM2_INPUT_SEL
25270  *  0b0..input from IOMUX
25271  *  0b1..input from XBAR
25272  */
25273 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
25274 
25275 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
25276 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
25277 /*! QTIMER3_TRM3_INPUT_SEL
25278  *  0b0..input from IOMUX
25279  *  0b1..input from XBAR
25280  */
25281 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
25282 
25283 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
25284 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
25285 /*! QTIMER4_TRM0_INPUT_SEL
25286  *  0b0..input from IOMUX
25287  *  0b1..input from XBAR
25288  */
25289 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
25290 
25291 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
25292 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
25293 /*! QTIMER4_TRM1_INPUT_SEL
25294  *  0b0..input from IOMUX
25295  *  0b1..input from XBAR
25296  */
25297 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
25298 
25299 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
25300 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
25301 /*! QTIMER4_TRM2_INPUT_SEL
25302  *  0b0..input from IOMUX
25303  *  0b1..input from XBAR
25304  */
25305 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
25306 
25307 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
25308 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
25309 /*! QTIMER4_TRM3_INPUT_SEL
25310  *  0b0..input from IOMUX
25311  *  0b1..input from XBAR
25312  */
25313 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
25314 
25315 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
25316 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
25317 /*! IOMUXC_XBAR_DIR_SEL_4
25318  *  0b0..XBAR1_INOUT as input
25319  *  0b1..XBAR1_INOUT as output
25320  */
25321 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
25322 
25323 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
25324 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
25325 /*! IOMUXC_XBAR_DIR_SEL_5
25326  *  0b0..XBAR1_INOUT as input
25327  *  0b1..XBAR1_INOUT as output
25328  */
25329 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
25330 
25331 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
25332 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
25333 /*! IOMUXC_XBAR_DIR_SEL_6
25334  *  0b0..XBAR1_INOUT as input
25335  *  0b1..XBAR1_INOUT as output
25336  */
25337 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
25338 
25339 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
25340 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
25341 /*! IOMUXC_XBAR_DIR_SEL_7
25342  *  0b0..XBAR1_INOUT as input
25343  *  0b1..XBAR1_INOUT as output
25344  */
25345 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
25346 
25347 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
25348 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
25349 /*! IOMUXC_XBAR_DIR_SEL_8
25350  *  0b0..XBAR1_INOUT as input
25351  *  0b1..XBAR1_INOUT as output
25352  */
25353 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
25354 
25355 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
25356 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
25357 /*! IOMUXC_XBAR_DIR_SEL_9
25358  *  0b0..XBAR1_INOUT as input
25359  *  0b1..XBAR1_INOUT as output
25360  */
25361 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
25362 
25363 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
25364 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
25365 /*! IOMUXC_XBAR_DIR_SEL_10
25366  *  0b0..XBAR1_INOUT as input
25367  *  0b1..XBAR1_INOUT as output
25368  */
25369 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
25370 
25371 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
25372 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
25373 /*! IOMUXC_XBAR_DIR_SEL_11
25374  *  0b0..XBAR1_INOUT as input
25375  *  0b1..XBAR1_INOUT as output
25376  */
25377 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
25378 
25379 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
25380 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
25381 /*! IOMUXC_XBAR_DIR_SEL_12
25382  *  0b0..XBAR1_INOUT as input
25383  *  0b1..XBAR1_INOUT as output
25384  */
25385 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
25386 
25387 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
25388 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
25389 /*! IOMUXC_XBAR_DIR_SEL_13
25390  *  0b0..XBAR1_INOUT as input
25391  *  0b1..XBAR1_INOUT as output
25392  */
25393 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
25394 
25395 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
25396 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
25397 /*! IOMUXC_XBAR_DIR_SEL_14
25398  *  0b0..XBAR1_INOUT as input
25399  *  0b1..XBAR1_INOUT as output
25400  */
25401 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
25402 
25403 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
25404 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
25405 /*! IOMUXC_XBAR_DIR_SEL_15
25406  *  0b0..XBAR1_INOUT as input
25407  *  0b1..XBAR1_INOUT as output
25408  */
25409 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
25410 
25411 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
25412 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
25413 /*! IOMUXC_XBAR_DIR_SEL_16
25414  *  0b0..XBAR1_INOUT as input
25415  *  0b1..XBAR1_INOUT as output
25416  */
25417 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
25418 
25419 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
25420 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
25421 /*! IOMUXC_XBAR_DIR_SEL_17
25422  *  0b0..XBAR1_INOUT as input
25423  *  0b1..XBAR1_INOUT as output
25424  */
25425 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
25426 
25427 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
25428 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
25429 /*! IOMUXC_XBAR_DIR_SEL_18
25430  *  0b0..XBAR1_INOUT as input
25431  *  0b1..XBAR1_INOUT as output
25432  */
25433 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
25434 
25435 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
25436 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
25437 /*! IOMUXC_XBAR_DIR_SEL_19
25438  *  0b0..XBAR1_INOUT as input
25439  *  0b1..XBAR1_INOUT as output
25440  */
25441 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
25442 /*! @} */
25443 
25444 /*! @name GPR7 - GPR7 General Purpose Register */
25445 /*! @{ */
25446 
25447 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK     (0x1U)
25448 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT    (0U)
25449 /*! LPI2C1_STOP_REQ - LPI2C1 stop request
25450  *  0b0..stop request off
25451  *  0b1..stop request on
25452  */
25453 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
25454 
25455 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK     (0x2U)
25456 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT    (1U)
25457 /*! LPI2C2_STOP_REQ - LPI2C2 stop request
25458  *  0b0..stop request off
25459  *  0b1..stop request on
25460  */
25461 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
25462 
25463 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK     (0x4U)
25464 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT    (2U)
25465 /*! LPI2C3_STOP_REQ - LPI2C3 stop request
25466  *  0b0..stop request off
25467  *  0b1..stop request on
25468  */
25469 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
25470 
25471 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK     (0x8U)
25472 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT    (3U)
25473 /*! LPI2C4_STOP_REQ - LPI2C4 stop request
25474  *  0b0..stop request off
25475  *  0b1..stop request on
25476  */
25477 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
25478 
25479 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK     (0x10U)
25480 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT    (4U)
25481 /*! LPSPI1_STOP_REQ - LPSPI1 stop request
25482  *  0b0..stop request off
25483  *  0b1..stop request on
25484  */
25485 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
25486 
25487 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK     (0x20U)
25488 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT    (5U)
25489 /*! LPSPI2_STOP_REQ - LPSPI2 stop request
25490  *  0b0..stop request off
25491  *  0b1..stop request on
25492  */
25493 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
25494 
25495 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK     (0x40U)
25496 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT    (6U)
25497 /*! LPSPI3_STOP_REQ - LPSPI3 stop request
25498  *  0b0..stop request off
25499  *  0b1..stop request on
25500  */
25501 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
25502 
25503 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK     (0x80U)
25504 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT    (7U)
25505 /*! LPSPI4_STOP_REQ - LPSPI4 stop request
25506  *  0b0..stop request off
25507  *  0b1..stop request on
25508  */
25509 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
25510 
25511 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK    (0x100U)
25512 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT   (8U)
25513 /*! LPUART1_STOP_REQ - LPUART1 stop request
25514  *  0b0..stop request off
25515  *  0b1..stop request on
25516  */
25517 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
25518 
25519 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK    (0x200U)
25520 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT   (9U)
25521 /*! LPUART2_STOP_REQ - LPUART2 stop request
25522  *  0b0..stop request off
25523  *  0b1..stop request on
25524  */
25525 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
25526 
25527 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK    (0x400U)
25528 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT   (10U)
25529 /*! LPUART3_STOP_REQ - LPUART3 stop request
25530  *  0b0..stop request off
25531  *  0b1..stop request on
25532  */
25533 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
25534 
25535 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK    (0x800U)
25536 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT   (11U)
25537 /*! LPUART4_STOP_REQ - LPUART4 stop request
25538  *  0b0..stop request off
25539  *  0b1..stop request on
25540  */
25541 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
25542 
25543 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK    (0x1000U)
25544 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT   (12U)
25545 /*! LPUART5_STOP_REQ - LPUART5 stop request
25546  *  0b0..stop request off
25547  *  0b1..stop request on
25548  */
25549 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
25550 
25551 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK    (0x2000U)
25552 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT   (13U)
25553 /*! LPUART6_STOP_REQ - LPUART6 stop request
25554  *  0b0..stop request off
25555  *  0b1..stop request on
25556  */
25557 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
25558 
25559 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK    (0x4000U)
25560 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT   (14U)
25561 /*! LPUART7_STOP_REQ - LPUART7 stop request
25562  *  0b0..stop request off
25563  *  0b1..stop request on
25564  */
25565 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
25566 
25567 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK    (0x8000U)
25568 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT   (15U)
25569 /*! LPUART8_STOP_REQ - LPUART8 stop request
25570  *  0b0..stop request off
25571  *  0b1..stop request on
25572  */
25573 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
25574 
25575 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK     (0x10000U)
25576 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT    (16U)
25577 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
25578  *  0b0..stop acknowledge is not asserted
25579  *  0b1..stop acknowledge is asserted (the module is in Stop mode)
25580  */
25581 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
25582 
25583 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK     (0x20000U)
25584 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT    (17U)
25585 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
25586  *  0b0..stop acknowledge is not asserted
25587  *  0b1..stop acknowledge is asserted
25588  */
25589 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
25590 
25591 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK     (0x40000U)
25592 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT    (18U)
25593 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
25594  *  0b0..stop acknowledge is not asserted
25595  *  0b1..stop acknowledge is asserted
25596  */
25597 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
25598 
25599 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK     (0x80000U)
25600 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT    (19U)
25601 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
25602  *  0b0..stop acknowledge is not asserted
25603  *  0b1..stop acknowledge is asserted
25604  */
25605 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
25606 
25607 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK     (0x100000U)
25608 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT    (20U)
25609 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
25610  *  0b0..stop acknowledge is not asserted
25611  *  0b1..stop acknowledge is asserted
25612  */
25613 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
25614 
25615 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK     (0x200000U)
25616 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT    (21U)
25617 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
25618  *  0b0..stop acknowledge is not asserted
25619  *  0b1..stop acknowledge is asserted
25620  */
25621 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
25622 
25623 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK     (0x400000U)
25624 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT    (22U)
25625 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
25626  *  0b0..stop acknowledge is not asserted
25627  *  0b1..stop acknowledge is asserted
25628  */
25629 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
25630 
25631 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK     (0x800000U)
25632 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT    (23U)
25633 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
25634  *  0b0..stop acknowledge is not asserted
25635  *  0b1..stop acknowledge is asserted
25636  */
25637 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
25638 
25639 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK    (0x1000000U)
25640 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT   (24U)
25641 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
25642  *  0b0..stop acknowledge is not asserted
25643  *  0b1..stop acknowledge is asserted
25644  */
25645 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
25646 
25647 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK    (0x2000000U)
25648 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT   (25U)
25649 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
25650  *  0b0..stop acknowledge is not asserted
25651  *  0b1..stop acknowledge is asserted
25652  */
25653 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
25654 
25655 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK    (0x4000000U)
25656 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT   (26U)
25657 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
25658  *  0b0..stop acknowledge is not asserted
25659  *  0b1..stop acknowledge is asserted
25660  */
25661 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
25662 
25663 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK    (0x8000000U)
25664 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT   (27U)
25665 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
25666  *  0b0..stop acknowledge is not asserted
25667  *  0b1..stop acknowledge is asserted
25668  */
25669 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
25670 
25671 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK    (0x10000000U)
25672 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT   (28U)
25673 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
25674  *  0b0..stop acknowledge is not asserted
25675  *  0b1..stop acknowledge is asserted
25676  */
25677 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
25678 
25679 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK    (0x20000000U)
25680 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT   (29U)
25681 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
25682  *  0b0..stop acknowledge is not asserted
25683  *  0b1..stop acknowledge is asserted
25684  */
25685 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
25686 
25687 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK    (0x40000000U)
25688 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT   (30U)
25689 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
25690  *  0b0..stop acknowledge is not asserted
25691  *  0b1..stop acknowledge is asserted
25692  */
25693 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
25694 
25695 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK    (0x80000000U)
25696 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT   (31U)
25697 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
25698  *  0b0..stop acknowledge is not asserted
25699  *  0b1..stop acknowledge is asserted (the module is in Stop mode)
25700  */
25701 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
25702 /*! @} */
25703 
25704 /*! @name GPR8 - GPR8 General Purpose Register */
25705 /*! @{ */
25706 
25707 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
25708 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
25709 /*! LPI2C1_IPG_STOP_MODE
25710  *  0b0..the module is functional in Stop mode
25711  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25712  */
25713 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
25714 
25715 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK     (0x2U)
25716 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT    (1U)
25717 /*! LPI2C1_IPG_DOZE
25718  *  0b0..not in doze mode
25719  *  0b1..in doze mode
25720  */
25721 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
25722 
25723 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
25724 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
25725 /*! LPI2C2_IPG_STOP_MODE
25726  *  0b0..the module is functional in Stop mode
25727  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25728  */
25729 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
25730 
25731 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK     (0x8U)
25732 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT    (3U)
25733 /*! LPI2C2_IPG_DOZE
25734  *  0b0..not in doze mode
25735  *  0b1..in doze mode
25736  */
25737 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
25738 
25739 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
25740 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
25741 /*! LPI2C3_IPG_STOP_MODE
25742  *  0b0..the module is functional in Stop mode
25743  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25744  */
25745 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
25746 
25747 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK     (0x20U)
25748 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT    (5U)
25749 /*! LPI2C3_IPG_DOZE
25750  *  0b0..not in doze mode
25751  *  0b1..in doze mode
25752  */
25753 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
25754 
25755 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
25756 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
25757 /*! LPI2C4_IPG_STOP_MODE
25758  *  0b0..the module is functional in Stop mode
25759  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25760  */
25761 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
25762 
25763 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK     (0x80U)
25764 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT    (7U)
25765 /*! LPI2C4_IPG_DOZE
25766  *  0b0..not in doze mode
25767  *  0b1..in doze mode
25768  */
25769 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
25770 
25771 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
25772 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
25773 /*! LPSPI1_IPG_STOP_MODE
25774  *  0b0..the module is functional in Stop mode
25775  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25776  */
25777 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
25778 
25779 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK     (0x200U)
25780 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT    (9U)
25781 /*! LPSPI1_IPG_DOZE
25782  *  0b0..not in doze mode
25783  *  0b1..in doze mode
25784  */
25785 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
25786 
25787 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
25788 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
25789 /*! LPSPI2_IPG_STOP_MODE
25790  *  0b0..the module is functional in Stop mode
25791  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25792  */
25793 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
25794 
25795 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK     (0x800U)
25796 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT    (11U)
25797 /*! LPSPI2_IPG_DOZE
25798  *  0b0..not in doze mode
25799  *  0b1..in doze mode
25800  */
25801 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
25802 
25803 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
25804 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
25805 /*! LPSPI3_IPG_STOP_MODE
25806  *  0b0..the module is functional in Stop mode
25807  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25808  */
25809 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
25810 
25811 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK     (0x2000U)
25812 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT    (13U)
25813 /*! LPSPI3_IPG_DOZE
25814  *  0b0..not in doze mode
25815  *  0b1..in doze mode
25816  */
25817 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
25818 
25819 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
25820 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
25821 /*! LPSPI4_IPG_STOP_MODE
25822  *  0b0..the module is functional in Stop mode
25823  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25824  */
25825 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
25826 
25827 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK     (0x8000U)
25828 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT    (15U)
25829 /*! LPSPI4_IPG_DOZE
25830  *  0b0..not in doze mode
25831  *  0b1..in doze mode
25832  */
25833 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
25834 
25835 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
25836 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
25837 /*! LPUART1_IPG_STOP_MODE
25838  *  0b0..the module is functional in Stop mode
25839  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25840  */
25841 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
25842 
25843 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK    (0x20000U)
25844 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT   (17U)
25845 /*! LPUART1_IPG_DOZE
25846  *  0b0..not in doze mode
25847  *  0b1..in doze mode
25848  */
25849 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
25850 
25851 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
25852 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
25853 /*! LPUART2_IPG_STOP_MODE
25854  *  0b0..the module is functional in Stop mode
25855  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25856  */
25857 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
25858 
25859 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK    (0x80000U)
25860 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT   (19U)
25861 /*! LPUART2_IPG_DOZE
25862  *  0b0..not in doze mode
25863  *  0b1..in doze mode
25864  */
25865 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
25866 
25867 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
25868 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
25869 /*! LPUART3_IPG_STOP_MODE
25870  *  0b0..the module is functional in Stop mode
25871  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25872  */
25873 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
25874 
25875 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK    (0x200000U)
25876 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT   (21U)
25877 /*! LPUART3_IPG_DOZE
25878  *  0b0..not in doze mode
25879  *  0b1..in doze mode
25880  */
25881 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
25882 
25883 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
25884 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
25885 /*! LPUART4_IPG_STOP_MODE
25886  *  0b0..the module is functional in Stop mode
25887  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25888  */
25889 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
25890 
25891 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK    (0x800000U)
25892 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT   (23U)
25893 /*! LPUART4_IPG_DOZE
25894  *  0b0..not in doze mode
25895  *  0b1..in doze mode
25896  */
25897 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
25898 
25899 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
25900 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
25901 /*! LPUART5_IPG_STOP_MODE
25902  *  0b0..the module is functional in Stop mode
25903  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25904  */
25905 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
25906 
25907 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK    (0x2000000U)
25908 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT   (25U)
25909 /*! LPUART5_IPG_DOZE
25910  *  0b0..not in doze mode
25911  *  0b1..in doze mode
25912  */
25913 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
25914 
25915 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
25916 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
25917 /*! LPUART6_IPG_STOP_MODE
25918  *  0b0..the module is functional in Stop mode
25919  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25920  */
25921 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
25922 
25923 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK    (0x8000000U)
25924 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT   (27U)
25925 /*! LPUART6_IPG_DOZE
25926  *  0b0..not in doze mode
25927  *  0b1..in doze mode
25928  */
25929 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
25930 
25931 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
25932 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
25933 /*! LPUART7_IPG_STOP_MODE
25934  *  0b0..the module is functional in Stop mode
25935  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25936  */
25937 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
25938 
25939 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK    (0x20000000U)
25940 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT   (29U)
25941 /*! LPUART7_IPG_DOZE
25942  *  0b0..not in doze mode
25943  *  0b1..in doze mode
25944  */
25945 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
25946 
25947 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
25948 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
25949 /*! LPUART8_IPG_STOP_MODE
25950  *  0b0..the module is functional in Stop mode
25951  *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
25952  */
25953 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
25954 
25955 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK    (0x80000000U)
25956 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT   (31U)
25957 /*! LPUART8_IPG_DOZE
25958  *  0b0..not in doze mode
25959  *  0b1..in doze mode
25960  */
25961 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
25962 /*! @} */
25963 
25964 /*! @name GPR10 - GPR10 General Purpose Register */
25965 /*! @{ */
25966 
25967 #define IOMUXC_GPR_GPR10_NIDEN_MASK              (0x1U)
25968 #define IOMUXC_GPR_GPR10_NIDEN_SHIFT             (0U)
25969 /*! NIDEN - Arm non-secure (non-invasive) debug enable
25970  *  0b0..Debug turned off
25971  *  0b1..Debug enabled (default)
25972  */
25973 #define IOMUXC_GPR_GPR10_NIDEN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
25974 
25975 #define IOMUXC_GPR_GPR10_DBG_EN_MASK             (0x2U)
25976 #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT            (1U)
25977 /*! DBG_EN - Arm invasive debug enable
25978  *  0b0..Debug turned off
25979  *  0b1..Debug enabled (default)
25980  */
25981 #define IOMUXC_GPR_GPR10_DBG_EN(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
25982 
25983 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK       (0x4U)
25984 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT      (2U)
25985 /*! SEC_ERR_RESP - Security error response enable
25986  *  0b0..OKEY response
25987  *  0b1..SLVError (default)
25988  */
25989 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
25990 
25991 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
25992 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
25993 /*! DCPKEY_OCOTP_OR_KEYMUX
25994  *  0b0..Select key from SNVS Master Key
25995  *  0b1..Select key from OCOTP (SW_GP2)
25996  */
25997 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
25998 
25999 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK        (0x100U)
26000 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT       (8U)
26001 /*! OCRAM_TZ_EN
26002  *  0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor)
26003  *  0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows
26004  *       the execution mode access policy described in CSU chapter
26005  */
26006 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
26007 
26008 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK      (0xFE00U)
26009 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT     (9U)
26010 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
26011 
26012 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK         (0x10000U)
26013 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT        (16U)
26014 /*! LOCK_NIDEN
26015  *  0b0..Field is not locked
26016  *  0b1..Field is locked (read access only)
26017  */
26018 #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
26019 
26020 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK        (0x20000U)
26021 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT       (17U)
26022 /*! LOCK_DBG_EN
26023  *  0b0..Field is not locked
26024  *  0b1..Field is locked (read access only)
26025  */
26026 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
26027 
26028 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK  (0x40000U)
26029 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
26030 /*! LOCK_SEC_ERR_RESP
26031  *  0b0..Field is not locked
26032  *  0b1..Field is locked (read access only)
26033  */
26034 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
26035 
26036 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
26037 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
26038 /*! LOCK_DCPKEY_OCOTP_OR_KEYMUX
26039  *  0b0..Field is not locked
26040  *  0b1..Field is locked (read access only)
26041  */
26042 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
26043 
26044 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK   (0x1000000U)
26045 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT  (24U)
26046 /*! LOCK_OCRAM_TZ_EN
26047  *  0b0..Field is not locked
26048  *  0b1..Field is locked (read access only)
26049  */
26050 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
26051 
26052 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
26053 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
26054 /*! LOCK_OCRAM_TZ_ADDR
26055  *  0b0000000..Field is not locked
26056  *  0b0000001..Field is locked (read access only)
26057  */
26058 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
26059 /*! @} */
26060 
26061 /*! @name GPR11 - GPR11 General Purpose Register */
26062 /*! @{ */
26063 
26064 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK  (0x3U)
26065 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
26066 /*! M7_APC_AC_R0_CTRL
26067  *  0b00..No access protection - All accesses are allowed
26068  *  0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the
26069  *        GPR_M7_APC_AC_R0_TOP/BOT specified region (IOMUXC_GPR_GPR18 - IOMUXC_GPR_GPR19)
26070  *  0b10..Reserved
26071  *  0b11..Reserved
26072  */
26073 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
26074 
26075 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK  (0xCU)
26076 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
26077 /*! M7_APC_AC_R1_CTRL
26078  *  0b00..No access protection - All accesses are allowed
26079  *  0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the
26080  *        GPR_M7_APC_AC_R1_TOP/BOT specified region (IOMUXC_GPR_GPR20 - IOMUXC_GPR_GPR21)
26081  *  0b10..Reserved
26082  *  0b11..Reserved
26083  */
26084 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
26085 
26086 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK  (0x30U)
26087 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
26088 /*! M7_APC_AC_R2_CTRL
26089  *  0b00..No access protection - All accesses are allowed
26090  *  0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the
26091  *        GPR_M7_APC_AC_R2_TOP/BOT specified region (IOMUXC_GPR_GPR22 - IOMUXC_GPR_GPR23)
26092  *  0b10..Reserved
26093  *  0b11..Reserved
26094  */
26095 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
26096 
26097 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK  (0xC0U)
26098 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
26099 /*! M7_APC_AC_R3_CTRL
26100  *  0b00..No access protection - All accesses are allowed
26101  *  0b01..M7 debug protection enabled - The APC block will block CM7 breakpoints, watchpoints and trace to the
26102  *        GPR_M7_APC_AC_R3_TOP/BOT specified region (IOMUXC_GPR_GPR24 - IOMUXC_GPR_GPR25)
26103  *  0b10..Reserved
26104  *  0b11..Reserved
26105  */
26106 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
26107 
26108 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK       (0xF00U)
26109 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT      (8U)
26110 /*! BEE_DE_RX_EN
26111  *  0b0000..FlexSPI data decryption disabled
26112  *  0b0001..FlexSPI data decryption enabled
26113  */
26114 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
26115 
26116 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)
26117 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)
26118 /*! LOCK_M7_APC_AC_R0_CTRL
26119  *  0b00..Field is not locked
26120  *  0b01..Field is locked (read access only)
26121  */
26122 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
26123 
26124 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)
26125 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)
26126 /*! LOCK_M7_APC_AC_R1_CTRL
26127  *  0b00..Field is not locked
26128  *  0b01..Field is locked (read access only)
26129  */
26130 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
26131 
26132 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)
26133 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)
26134 /*! LOCK_M7_APC_AC_R2_CTRL
26135  *  0b00..Field is not locked
26136  *  0b01..Field is locked (read access only)
26137  */
26138 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
26139 
26140 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)
26141 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)
26142 /*! LOCK_M7_APC_AC_R3_CTRL
26143  *  0b00..Field is not locked
26144  *  0b01..Field is locked (read access only)
26145  */
26146 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
26147 
26148 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK  (0xF000000U)
26149 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)
26150 /*! LOCK_BEE_DE_RX_EN
26151  *  0b0000..Field is not locked
26152  *  0b0001..Field is locked (read access only)
26153  */
26154 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
26155 /*! @} */
26156 
26157 /*! @name GPR12 - GPR12 General Purpose Register */
26158 /*! @{ */
26159 
26160 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
26161 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
26162 /*! FLEXIO1_IPG_STOP_MODE
26163  *  0b0..FlexIO1 is functional in Stop mode
26164  *  0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode
26165  */
26166 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
26167 
26168 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK   (0x2U)
26169 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT  (1U)
26170 /*! FLEXIO1_IPG_DOZE
26171  *  0b0..FLEXIO1 is not in doze mode
26172  *  0b1..FLEXIO1 is in doze mode
26173  */
26174 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
26175 
26176 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
26177 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
26178 /*! FLEXIO2_IPG_STOP_MODE
26179  *  0b0..FlexIO2 is functional in Stop mode
26180  *  0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode
26181  */
26182 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
26183 
26184 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK   (0x8U)
26185 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT  (3U)
26186 /*! FLEXIO2_IPG_DOZE
26187  *  0b0..FLEXIO2 is not in doze mode
26188  *  0b1..FLEXIO2 is in doze mode
26189  */
26190 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
26191 
26192 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
26193 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
26194 /*! ACMP_IPG_STOP_MODE
26195  *  0b0..ACMP is functional in Stop mode
26196  *  0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode
26197  */
26198 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
26199 /*! @} */
26200 
26201 /*! @name GPR13 - GPR13 General Purpose Register */
26202 /*! @{ */
26203 
26204 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK      (0x1U)
26205 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT     (0U)
26206 /*! ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions
26207  *  0b0..Cacheable attribute is off for read transactions
26208  *  0b1..Cacheable attribute is on for read transactions
26209  */
26210 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
26211 
26212 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK      (0x2U)
26213 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT     (1U)
26214 /*! AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions
26215  *  0b0..Cacheable attribute is off for write transactions
26216  *  0b1..Cacheable attribute is on for write transactions
26217  */
26218 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
26219 
26220 #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK         (0x80U)
26221 #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT        (7U)
26222 /*! CACHE_ENET - ENET block cacheable attribute value of AXI transactions
26223  *  0b0..Cacheable attribute is off for read/write transactions
26224  *  0b1..Cacheable attribute is on for read/write transactions
26225  */
26226 #define IOMUXC_GPR_GPR13_CACHE_ENET(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
26227 
26228 #define IOMUXC_GPR_GPR13_CACHE_USB_MASK          (0x2000U)
26229 #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT         (13U)
26230 /*! CACHE_USB - USB block cacheable attribute value of AXI transactions
26231  *  0b0..Cacheable attribute is off for read/write transactions
26232  *  0b1..Cacheable attribute is on for read/write transactions
26233  */
26234 #define IOMUXC_GPR_GPR13_CACHE_USB(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
26235 /*! @} */
26236 
26237 /*! @name GPR14 - GPR14 General Purpose Register */
26238 /*! @{ */
26239 
26240 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
26241 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
26242 /*! ACMP1_CMP_IGEN_TRIM_DN
26243  *  0b0..no reduce
26244  *  0b1..reduces
26245  */
26246 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
26247 
26248 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
26249 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
26250 /*! ACMP2_CMP_IGEN_TRIM_DN
26251  *  0b0..no reduce
26252  *  0b1..reduces
26253  */
26254 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
26255 
26256 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
26257 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
26258 /*! ACMP3_CMP_IGEN_TRIM_DN
26259  *  0b0..no reduce
26260  *  0b1..reduces
26261  */
26262 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
26263 
26264 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
26265 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
26266 /*! ACMP4_CMP_IGEN_TRIM_DN
26267  *  0b0..no reduce
26268  *  0b1..reduces
26269  */
26270 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
26271 
26272 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
26273 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
26274 /*! ACMP1_CMP_IGEN_TRIM_UP
26275  *  0b0..no increase
26276  *  0b1..increases
26277  */
26278 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
26279 
26280 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
26281 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
26282 /*! ACMP2_CMP_IGEN_TRIM_UP
26283  *  0b0..no increase
26284  *  0b1..increases
26285  */
26286 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
26287 
26288 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
26289 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
26290 /*! ACMP3_CMP_IGEN_TRIM_UP
26291  *  0b0..no increase
26292  *  0b1..increases
26293  */
26294 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
26295 
26296 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
26297 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
26298 /*! ACMP4_CMP_IGEN_TRIM_UP
26299  *  0b0..no increase
26300  *  0b1..increases
26301  */
26302 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
26303 
26304 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
26305 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
26306 /*! ACMP1_SAMPLE_SYNC_EN
26307  *  0b0..select XBAR output
26308  *  0b1..select synced sample_lv
26309  */
26310 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
26311 
26312 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
26313 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
26314 /*! ACMP2_SAMPLE_SYNC_EN
26315  *  0b0..select XBAR output
26316  *  0b1..select synced sample_lv
26317  */
26318 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
26319 
26320 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
26321 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
26322 /*! ACMP3_SAMPLE_SYNC_EN
26323  *  0b0..select XBAR output
26324  *  0b1..select synced sample_lv
26325  */
26326 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
26327 
26328 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
26329 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
26330 /*! ACMP4_SAMPLE_SYNC_EN
26331  *  0b0..select XBAR output
26332  *  0b1..select synced sample_lv
26333  */
26334 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
26335 /*! @} */
26336 
26337 /*! @name GPR16 - GPR16 General Purpose Register */
26338 /*! @{ */
26339 
26340 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
26341 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
26342 /*! FLEXRAM_BANK_CFG_SEL
26343  *  0b0..use fuse value to config
26344  *  0b1..use FLEXRAM_BANK_CFG to config
26345  */
26346 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
26347 
26348 #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK      (0xFFFFFF80U)
26349 #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT     (7U)
26350 #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)
26351 /*! @} */
26352 
26353 /*! @name GPR17 - GPR17 General Purpose Register */
26354 /*! @{ */
26355 
26356 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK   (0xFFFFFFFFU)
26357 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT  (0U)
26358 /*! FLEXRAM_BANK_CFG - FlexRAM bank config value
26359  */
26360 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
26361 /*! @} */
26362 
26363 /*! @name GPR18 - GPR18 General Purpose Register */
26364 /*! @{ */
26365 
26366 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
26367 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
26368 /*! LOCK_M7_APC_AC_R0_BOT
26369  *  0b0..M7_APC_AC_R0_BOT is not locked
26370  *  0b1..M7_APC_AC_R0_BOT is locked (read access only)
26371  */
26372 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
26373 
26374 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
26375 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT  (3U)
26376 /*! M7_APC_AC_R0_BOT - Access Permission Controller (APC) end address of memory region-0
26377  */
26378 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
26379 /*! @} */
26380 
26381 /*! @name GPR19 - GPR19 General Purpose Register */
26382 /*! @{ */
26383 
26384 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
26385 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
26386 /*! LOCK_M7_APC_AC_R0_TOP
26387  *  0b0..M7_APC_AC_R0_TOP is not locked
26388  *  0b1..M7_APC_AC_R0_TOP is locked (read access only)
26389  */
26390 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
26391 
26392 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
26393 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT  (3U)
26394 /*! M7_APC_AC_R0_TOP - Access Permission Controller (APC) start address of memory region-0
26395  */
26396 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
26397 /*! @} */
26398 
26399 /*! @name GPR20 - GPR20 General Purpose Register */
26400 /*! @{ */
26401 
26402 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
26403 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
26404 /*! LOCK_M7_APC_AC_R1_BOT
26405  *  0b0..M7_APC_AC_R1_BOT is not locked
26406  *  0b1..M7_APC_AC_R1_BOT is locked (read access only)
26407  */
26408 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
26409 
26410 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
26411 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT  (3U)
26412 /*! M7_APC_AC_R1_BOT - Access Permission Controller (APC) end address of memory region-1
26413  */
26414 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
26415 /*! @} */
26416 
26417 /*! @name GPR21 - GPR21 General Purpose Register */
26418 /*! @{ */
26419 
26420 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
26421 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
26422 /*! LOCK_M7_APC_AC_R1_TOP
26423  *  0b0..M7_APC_AC_R1_TOP is not locked
26424  *  0b1..M7_APC_AC_R1_TOP is locked (read access only)
26425  */
26426 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
26427 
26428 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
26429 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT  (3U)
26430 /*! M7_APC_AC_R1_TOP - Access Permission Controller (APC) start address of memory region-1
26431  */
26432 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
26433 /*! @} */
26434 
26435 /*! @name GPR22 - GPR22 General Purpose Register */
26436 /*! @{ */
26437 
26438 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
26439 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
26440 /*! LOCK_M7_APC_AC_R2_BOT
26441  *  0b0..M7_APC_AC_R2_BOT is not locked
26442  *  0b1..M7_APC_AC_R2_BOT is locked (read access only)
26443  */
26444 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
26445 
26446 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)
26447 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT  (3U)
26448 /*! M7_APC_AC_R2_BOT - Access Permission Controller (APC) end address of memory region-2
26449  */
26450 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
26451 /*! @} */
26452 
26453 /*! @name GPR23 - GPR23 General Purpose Register */
26454 /*! @{ */
26455 
26456 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
26457 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
26458 /*! LOCK_M7_APC_AC_R2_TOP
26459  *  0b0..M7_APC_AC_R2_TOP is not locked
26460  *  0b1..M7_APC_AC_R2_TOP is locked (read access only)
26461  */
26462 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
26463 
26464 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
26465 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT  (3U)
26466 /*! M7_APC_AC_R2_TOP - Access Permission Controller (APC) start address of memory region-2
26467  */
26468 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
26469 /*! @} */
26470 
26471 /*! @name GPR24 - GPR24 General Purpose Register */
26472 /*! @{ */
26473 
26474 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
26475 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
26476 /*! LOCK_M7_APC_AC_R3_BOT
26477  *  0b0..M7_APC_AC_R3_BOT is not locked
26478  *  0b1..M7_APC_AC_R3_BOT is locked (read access only)
26479  */
26480 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
26481 
26482 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
26483 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT  (3U)
26484 /*! M7_APC_AC_R3_BOT - Access Permission Controller (APC) end address of memory region-3
26485  */
26486 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
26487 /*! @} */
26488 
26489 /*! @name GPR25 - GPR25 General Purpose Register */
26490 /*! @{ */
26491 
26492 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
26493 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
26494 /*! LOCK_M7_APC_AC_R3_TOP
26495  *  0b0..M7_APC_AC_R3_TOP is not locked
26496  *  0b1..M7_APC_AC_R3_TOP is locked (read access only)
26497  */
26498 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
26499 
26500 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
26501 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT  (3U)
26502 /*! M7_APC_AC_R3_TOP - Access Permission Controller (APC) start address of memory region-3
26503  */
26504 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
26505 /*! @} */
26506 
26507 
26508 /*!
26509  * @}
26510  */ /* end of group IOMUXC_GPR_Register_Masks */
26511 
26512 
26513 /* IOMUXC_GPR - Peripheral instance base addresses */
26514 /** Peripheral IOMUXC_GPR base address */
26515 #define IOMUXC_GPR_BASE                          (0x400AC000u)
26516 /** Peripheral IOMUXC_GPR base pointer */
26517 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
26518 /** Array initializer of IOMUXC_GPR peripheral base addresses */
26519 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
26520 /** Array initializer of IOMUXC_GPR peripheral base pointers */
26521 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
26522 
26523 /*!
26524  * @}
26525  */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
26526 
26527 
26528 /* ----------------------------------------------------------------------------
26529    -- IOMUXC_SNVS Peripheral Access Layer
26530    ---------------------------------------------------------------------------- */
26531 
26532 /*!
26533  * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
26534  * @{
26535  */
26536 
26537 /** IOMUXC_SNVS - Register Layout Typedef */
26538 typedef struct {
26539   __IO uint32_t SW_MUX_CTL_PAD_WAKEUP;             /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */
26540   __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ;        /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */
26541   __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ;      /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */
26542   __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE;          /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */
26543   __IO uint32_t SW_PAD_CTL_PAD_POR_B;              /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */
26544   __IO uint32_t SW_PAD_CTL_PAD_ONOFF;              /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */
26545   __IO uint32_t SW_PAD_CTL_PAD_WAKEUP;             /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */
26546   __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ;        /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */
26547   __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ;      /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */
26548 } IOMUXC_SNVS_Type;
26549 
26550 /* ----------------------------------------------------------------------------
26551    -- IOMUXC_SNVS Register Masks
26552    ---------------------------------------------------------------------------- */
26553 
26554 /*!
26555  * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
26556  * @{
26557  */
26558 
26559 /*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */
26560 /*! @{ */
26561 
26562 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
26563 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
26564 /*! MUX_MODE - MUX Mode Select Field.
26565  *  0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5
26566  *  0b111..Select mux mode: ALT7 mux port: NMI of instance: CM7
26567  */
26568 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
26569 
26570 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
26571 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
26572 /*! SION - Software Input On Field.
26573  *  0b1..Force input path of pad WAKEUP
26574  *  0b0..Input Path is determined by functionality
26575  */
26576 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
26577 /*! @} */
26578 
26579 /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */
26580 /*! @{ */
26581 
26582 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
26583 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
26584 /*! MUX_MODE - MUX Mode Select Field.
26585  *  0b000..Select mux mode: ALT0 mux port: SNVS_PMIC_ON_REQ of instance: snvs
26586  *  0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5
26587  */
26588 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
26589 
26590 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
26591 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
26592 /*! SION - Software Input On Field.
26593  *  0b1..Force input path of pad PMIC_ON_REQ
26594  *  0b0..Input Path is determined by functionality
26595  */
26596 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
26597 /*! @} */
26598 
26599 /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */
26600 /*! @{ */
26601 
26602 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
26603 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
26604 /*! MUX_MODE - MUX Mode Select Field.
26605  *  0b000..Select mux mode: ALT0 mux port: CCM_PMIC_STBY_REQ of instance: ccm
26606  *  0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
26607  */
26608 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
26609 
26610 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
26611 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
26612 /*! SION - Software Input On Field.
26613  *  0b1..Force input path of pad PMIC_STBY_REQ
26614  *  0b0..Input Path is determined by functionality
26615  */
26616 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
26617 /*! @} */
26618 
26619 /*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */
26620 /*! @{ */
26621 
26622 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
26623 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
26624 /*! SRE - Slew Rate Field
26625  *  0b0..Slow Slew Rate
26626  *  0b1..Fast Slew Rate
26627  */
26628 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
26629 
26630 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
26631 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
26632 /*! DSE - Drive Strength Field
26633  *  0b000..HI-Z
26634  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
26635  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
26636  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
26637  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
26638  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
26639  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
26640  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
26641  */
26642 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
26643 
26644 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
26645 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
26646 /*! SPEED - Speed Field
26647  *  0b10..100MHz
26648  */
26649 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
26650 
26651 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
26652 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
26653 /*! ODE - Open Drain Enable Field
26654  *  0b0..Open Drain Disabled (Output is CMOS)
26655  *  0b1..Open Drain Enabled (Output is Open Drain)
26656  */
26657 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
26658 
26659 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
26660 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
26661 /*! PKE - Pull / Keep Enable Field
26662  *  0b0..Pull/Keeper Disabled
26663  *  0b1..Pull/Keeper Enabled
26664  */
26665 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
26666 
26667 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
26668 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
26669 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
26670  *  0b0..Keep the previous output value when the output driver is disabled.
26671  *  0b1..Pull-up or pull-down (determined by PUS field).
26672  */
26673 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
26674 
26675 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
26676 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
26677 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
26678  *  0b00..100K Ohm Pull Down
26679  *  0b01..47K Ohm Pull Up
26680  *  0b10..100K Ohm Pull Up
26681  *  0b11..22K Ohm Pull Up
26682  */
26683 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
26684 
26685 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
26686 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
26687 /*! HYS - Hyst. Enable Field
26688  *  0b0..Hysteresis Disabled (CMOS input)
26689  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
26690  */
26691 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
26692 /*! @} */
26693 
26694 /*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */
26695 /*! @{ */
26696 
26697 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
26698 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
26699 /*! SRE - Slew Rate Field
26700  *  0b0..Slow Slew Rate
26701  *  0b1..Fast Slew Rate
26702  */
26703 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
26704 
26705 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
26706 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
26707 /*! DSE - Drive Strength Field
26708  *  0b000..HI-Z
26709  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
26710  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
26711  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
26712  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
26713  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
26714  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
26715  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
26716  */
26717 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
26718 
26719 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
26720 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
26721 /*! SPEED - Speed Field
26722  *  0b10..100MHz
26723  */
26724 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
26725 
26726 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
26727 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
26728 /*! ODE - Open Drain Enable Field
26729  *  0b0..Open Drain Disabled (Output is CMOS)
26730  *  0b1..Open Drain Enabled (Output is Open Drain)
26731  */
26732 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
26733 
26734 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
26735 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
26736 /*! PKE - Pull / Keep Enable Field
26737  *  0b0..Pull/Keeper Disabled
26738  *  0b1..Pull/Keeper Enabled
26739  */
26740 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
26741 
26742 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
26743 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
26744 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
26745  *  0b0..Keep the previous output value when the output driver is disabled.
26746  *  0b1..Pull-up or pull-down (determined by PUS field).
26747  */
26748 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
26749 
26750 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
26751 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
26752 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
26753  *  0b00..100K Ohm Pull Down
26754  *  0b01..47K Ohm Pull Up
26755  *  0b10..100K Ohm Pull Up
26756  *  0b11..22K Ohm Pull Up
26757  */
26758 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
26759 
26760 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
26761 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
26762 /*! HYS - Hyst. Enable Field
26763  *  0b0..Hysteresis Disabled (CMOS input)
26764  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
26765  */
26766 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
26767 /*! @} */
26768 
26769 /*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */
26770 /*! @{ */
26771 
26772 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
26773 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
26774 /*! SRE - Slew Rate Field
26775  *  0b0..Slow Slew Rate
26776  *  0b1..Fast Slew Rate
26777  */
26778 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
26779 
26780 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
26781 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
26782 /*! DSE - Drive Strength Field
26783  *  0b000..HI-Z
26784  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
26785  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
26786  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
26787  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
26788  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
26789  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
26790  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
26791  */
26792 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
26793 
26794 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
26795 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
26796 /*! SPEED - Speed Field
26797  *  0b10..100MHz
26798  */
26799 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
26800 
26801 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
26802 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
26803 /*! ODE - Open Drain Enable Field
26804  *  0b0..Open Drain Disabled (Output is CMOS)
26805  *  0b1..Open Drain Enabled (Output is Open Drain)
26806  */
26807 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
26808 
26809 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
26810 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
26811 /*! PKE - Pull / Keep Enable Field
26812  *  0b0..Pull/Keeper Disabled
26813  *  0b1..Pull/Keeper Enabled
26814  */
26815 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
26816 
26817 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
26818 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
26819 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
26820  *  0b0..Keep the previous output value when the output driver is disabled.
26821  *  0b1..Pull-up or pull-down (determined by PUS field).
26822  */
26823 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
26824 
26825 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
26826 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
26827 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
26828  *  0b00..100K Ohm Pull Down
26829  *  0b01..47K Ohm Pull Up
26830  *  0b10..100K Ohm Pull Up
26831  *  0b11..22K Ohm Pull Up
26832  */
26833 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
26834 
26835 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
26836 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
26837 /*! HYS - Hyst. Enable Field
26838  *  0b0..Hysteresis Disabled (CMOS input)
26839  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
26840  */
26841 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
26842 /*! @} */
26843 
26844 /*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */
26845 /*! @{ */
26846 
26847 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
26848 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
26849 /*! SRE - Slew Rate Field
26850  *  0b0..Slow Slew Rate
26851  *  0b1..Fast Slew Rate
26852  */
26853 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
26854 
26855 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
26856 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
26857 /*! DSE - Drive Strength Field
26858  *  0b000..HI-Z
26859  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
26860  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
26861  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
26862  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
26863  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
26864  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
26865  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
26866  */
26867 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
26868 
26869 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
26870 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
26871 /*! SPEED - Speed Field
26872  *  0b10..100MHz
26873  */
26874 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
26875 
26876 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
26877 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
26878 /*! ODE - Open Drain Enable Field
26879  *  0b0..Open Drain Disabled (Output is CMOS)
26880  *  0b1..Open Drain Enabled (Output is Open Drain)
26881  */
26882 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
26883 
26884 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
26885 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
26886 /*! PKE - Pull / Keep Enable Field
26887  *  0b0..Pull/Keeper Disabled
26888  *  0b1..Pull/Keeper Enabled
26889  */
26890 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
26891 
26892 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
26893 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
26894 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
26895  *  0b0..Keep the previous output value when the output driver is disabled.
26896  *  0b1..Pull-up or pull-down (determined by PUS field).
26897  */
26898 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
26899 
26900 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
26901 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
26902 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
26903  *  0b00..100K Ohm Pull Down
26904  *  0b01..47K Ohm Pull Up
26905  *  0b10..100K Ohm Pull Up
26906  *  0b11..22K Ohm Pull Up
26907  */
26908 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
26909 
26910 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
26911 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
26912 /*! HYS - Hyst. Enable Field
26913  *  0b0..Hysteresis Disabled (CMOS input)
26914  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
26915  */
26916 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
26917 /*! @} */
26918 
26919 /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */
26920 /*! @{ */
26921 
26922 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
26923 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
26924 /*! SRE - Slew Rate Field
26925  *  0b0..Slow Slew Rate
26926  *  0b1..Fast Slew Rate
26927  */
26928 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
26929 
26930 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
26931 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
26932 /*! DSE - Drive Strength Field
26933  *  0b000..HI-Z
26934  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
26935  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
26936  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
26937  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
26938  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
26939  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
26940  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
26941  */
26942 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
26943 
26944 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
26945 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
26946 /*! SPEED - Speed Field
26947  *  0b10..100MHz
26948  */
26949 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
26950 
26951 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
26952 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
26953 /*! ODE - Open Drain Enable Field
26954  *  0b0..Open Drain Disabled (Output is CMOS)
26955  *  0b1..Open Drain Enabled (Output is Open Drain)
26956  */
26957 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
26958 
26959 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
26960 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
26961 /*! PKE - Pull / Keep Enable Field
26962  *  0b0..Pull/Keeper Disabled
26963  *  0b1..Pull/Keeper Enabled
26964  */
26965 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
26966 
26967 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
26968 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
26969 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
26970  *  0b0..Keep the previous output value when the output driver is disabled.
26971  *  0b1..Pull-up or pull-down (determined by PUS field).
26972  */
26973 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
26974 
26975 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
26976 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
26977 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
26978  *  0b00..100K Ohm Pull Down
26979  *  0b01..47K Ohm Pull Up
26980  *  0b10..100K Ohm Pull Up
26981  *  0b11..22K Ohm Pull Up
26982  */
26983 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
26984 
26985 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
26986 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
26987 /*! HYS - Hyst. Enable Field
26988  *  0b0..Hysteresis Disabled (CMOS input)
26989  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
26990  */
26991 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
26992 /*! @} */
26993 
26994 /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */
26995 /*! @{ */
26996 
26997 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
26998 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
26999 /*! SRE - Slew Rate Field
27000  *  0b0..Slow Slew Rate
27001  *  0b1..Fast Slew Rate
27002  */
27003 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
27004 
27005 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
27006 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
27007 /*! DSE - Drive Strength Field
27008  *  0b000..HI-Z
27009  *  0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
27010  *  0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
27011  *  0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
27012  *  0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
27013  *  0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
27014  *  0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
27015  *  0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
27016  */
27017 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
27018 
27019 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
27020 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
27021 /*! SPEED - Speed Field
27022  *  0b10..100MHz
27023  */
27024 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
27025 
27026 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
27027 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
27028 /*! ODE - Open Drain Enable Field
27029  *  0b0..Open Drain Disabled (Output is CMOS)
27030  *  0b1..Open Drain Enabled (Output is Open Drain)
27031  */
27032 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
27033 
27034 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
27035 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
27036 /*! PKE - Pull / Keep Enable Field
27037  *  0b0..Pull/Keeper Disabled
27038  *  0b1..Pull/Keeper Enabled
27039  */
27040 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
27041 
27042 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
27043 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
27044 /*! PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality.
27045  *  0b0..Keep the previous output value when the output driver is disabled.
27046  *  0b1..Pull-up or pull-down (determined by PUS field).
27047  */
27048 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
27049 
27050 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
27051 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
27052 /*! PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength.
27053  *  0b00..100K Ohm Pull Down
27054  *  0b01..47K Ohm Pull Up
27055  *  0b10..100K Ohm Pull Up
27056  *  0b11..22K Ohm Pull Up
27057  */
27058 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
27059 
27060 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
27061 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
27062 /*! HYS - Hyst. Enable Field
27063  *  0b0..Hysteresis Disabled (CMOS input)
27064  *  0b1..Hysteresis Enabled (Schmitt Trigger input)
27065  */
27066 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
27067 /*! @} */
27068 
27069 
27070 /*!
27071  * @}
27072  */ /* end of group IOMUXC_SNVS_Register_Masks */
27073 
27074 
27075 /* IOMUXC_SNVS - Peripheral instance base addresses */
27076 /** Peripheral IOMUXC_SNVS base address */
27077 #define IOMUXC_SNVS_BASE                         (0x400A8000u)
27078 /** Peripheral IOMUXC_SNVS base pointer */
27079 #define IOMUXC_SNVS                              ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
27080 /** Array initializer of IOMUXC_SNVS peripheral base addresses */
27081 #define IOMUXC_SNVS_BASE_ADDRS                   { IOMUXC_SNVS_BASE }
27082 /** Array initializer of IOMUXC_SNVS peripheral base pointers */
27083 #define IOMUXC_SNVS_BASE_PTRS                    { IOMUXC_SNVS }
27084 
27085 /*!
27086  * @}
27087  */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
27088 
27089 
27090 /* ----------------------------------------------------------------------------
27091    -- IOMUXC_SNVS_GPR Peripheral Access Layer
27092    ---------------------------------------------------------------------------- */
27093 
27094 /*!
27095  * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
27096  * @{
27097  */
27098 
27099 /** IOMUXC_SNVS_GPR - Register Layout Typedef */
27100 typedef struct {
27101        uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
27102        uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
27103        uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
27104   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
27105 } IOMUXC_SNVS_GPR_Type;
27106 
27107 /* ----------------------------------------------------------------------------
27108    -- IOMUXC_SNVS_GPR Register Masks
27109    ---------------------------------------------------------------------------- */
27110 
27111 /*!
27112  * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
27113  * @{
27114  */
27115 
27116 /*! @name GPR3 - GPR3 General Purpose Register */
27117 /*! @{ */
27118 
27119 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
27120 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
27121 /*! LPSR_MODE_ENABLE
27122  *  0b0..SNVS domain will reset when system reset happens
27123  *  0b1..SNVS domain will only reset with SNVS POR
27124  */
27125 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
27126 
27127 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
27128 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
27129 /*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear
27130  */
27131 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
27132 
27133 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK  (0xCU)
27134 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
27135 /*! POR_PULL_TYPE
27136  *  0b00..100 Ohm pull up enabled for POR_B always
27137  *  0b01..Disable pull in SNVS mode, 100 Ohm pull up enabled otherwise
27138  *  0b10..Disable pull of POR_B always
27139  *  0b11..100 Ohm pull down enabled in SNVS mode, 100 Ohm pull up enabled otherwise
27140  */
27141 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
27142 
27143 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
27144 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
27145 /*! DCDC_IN_LOW_VOL
27146  *  0b0..DCDC_IN is ok
27147  *  0b1..DCDC_IN is too low
27148  */
27149 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
27150 
27151 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK  (0x20000U)
27152 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
27153 /*! DCDC_OVER_CUR
27154  *  0b0..No over current detected
27155  *  0b1..Over current detected
27156  */
27157 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
27158 
27159 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK  (0x40000U)
27160 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
27161 /*! DCDC_OVER_VOL
27162  *  0b0..No over voltage detected
27163  *  0b1..Over voltage detected
27164  */
27165 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
27166 
27167 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
27168 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
27169 /*! DCDC_STS_DC_OK
27170  *  0b0..DCDC is ramping up and not ready
27171  *  0b1..DCDC is ready
27172  */
27173 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
27174 /*! @} */
27175 
27176 
27177 /*!
27178  * @}
27179  */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
27180 
27181 
27182 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
27183 /** Peripheral IOMUXC_SNVS_GPR base address */
27184 #define IOMUXC_SNVS_GPR_BASE                     (0x400A4000u)
27185 /** Peripheral IOMUXC_SNVS_GPR base pointer */
27186 #define IOMUXC_SNVS_GPR                          ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
27187 /** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
27188 #define IOMUXC_SNVS_GPR_BASE_ADDRS               { IOMUXC_SNVS_GPR_BASE }
27189 /** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
27190 #define IOMUXC_SNVS_GPR_BASE_PTRS                { IOMUXC_SNVS_GPR }
27191 
27192 /*!
27193  * @}
27194  */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
27195 
27196 
27197 /* ----------------------------------------------------------------------------
27198    -- KPP Peripheral Access Layer
27199    ---------------------------------------------------------------------------- */
27200 
27201 /*!
27202  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
27203  * @{
27204  */
27205 
27206 /** KPP - Register Layout Typedef */
27207 typedef struct {
27208   __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
27209   __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
27210   __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
27211   __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
27212 } KPP_Type;
27213 
27214 /* ----------------------------------------------------------------------------
27215    -- KPP Register Masks
27216    ---------------------------------------------------------------------------- */
27217 
27218 /*!
27219  * @addtogroup KPP_Register_Masks KPP Register Masks
27220  * @{
27221  */
27222 
27223 /*! @name KPCR - Keypad Control Register */
27224 /*! @{ */
27225 
27226 #define KPP_KPCR_KRE_MASK                        (0xFFU)
27227 #define KPP_KPCR_KRE_SHIFT                       (0U)
27228 /*! KRE
27229  *  0b00000000..Row is not included in the keypad key press detect.
27230  *  0b00000001..Row is included in the keypad key press detect.
27231  */
27232 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
27233 
27234 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
27235 #define KPP_KPCR_KCO_SHIFT                       (8U)
27236 /*! KCO
27237  *  0b00000000..Column strobe output is totem pole drive.
27238  *  0b00000001..Column strobe output is open drain.
27239  */
27240 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
27241 /*! @} */
27242 
27243 /*! @name KPSR - Keypad Status Register */
27244 /*! @{ */
27245 
27246 #define KPP_KPSR_KPKD_MASK                       (0x1U)
27247 #define KPP_KPSR_KPKD_SHIFT                      (0U)
27248 /*! KPKD
27249  *  0b0..No key presses detected
27250  *  0b1..A key has been depressed
27251  */
27252 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
27253 
27254 #define KPP_KPSR_KPKR_MASK                       (0x2U)
27255 #define KPP_KPSR_KPKR_SHIFT                      (1U)
27256 /*! KPKR
27257  *  0b0..No key release detected
27258  *  0b1..All keys have been released
27259  */
27260 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
27261 
27262 #define KPP_KPSR_KDSC_MASK                       (0x4U)
27263 #define KPP_KPSR_KDSC_SHIFT                      (2U)
27264 /*! KDSC
27265  *  0b0..No effect
27266  *  0b1..Set bits that clear the keypad depress synchronizer chain
27267  */
27268 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
27269 
27270 #define KPP_KPSR_KRSS_MASK                       (0x8U)
27271 #define KPP_KPSR_KRSS_SHIFT                      (3U)
27272 /*! KRSS
27273  *  0b0..No effect
27274  *  0b1..Set bits which sets keypad release synchronizer chain
27275  */
27276 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
27277 
27278 #define KPP_KPSR_KDIE_MASK                       (0x100U)
27279 #define KPP_KPSR_KDIE_SHIFT                      (8U)
27280 /*! KDIE
27281  *  0b0..No interrupt request is generated when KPKD is set.
27282  *  0b1..An interrupt request is generated when KPKD is set.
27283  */
27284 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
27285 
27286 #define KPP_KPSR_KRIE_MASK                       (0x200U)
27287 #define KPP_KPSR_KRIE_SHIFT                      (9U)
27288 /*! KRIE
27289  *  0b0..No interrupt request is generated when KPKR is set.
27290  *  0b1..An interrupt request is generated when KPKR is set.
27291  */
27292 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
27293 /*! @} */
27294 
27295 /*! @name KDDR - Keypad Data Direction Register */
27296 /*! @{ */
27297 
27298 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
27299 #define KPP_KDDR_KRDD_SHIFT                      (0U)
27300 /*! KRDD
27301  *  0b00000000..ROWn pin configured as an input.
27302  *  0b00000001..ROWn pin configured as an output.
27303  */
27304 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
27305 
27306 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
27307 #define KPP_KDDR_KCDD_SHIFT                      (8U)
27308 /*! KCDD
27309  *  0b00000000..COLn pin is configured as an input.
27310  *  0b00000001..COLn pin is configured as an output.
27311  */
27312 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
27313 /*! @} */
27314 
27315 /*! @name KPDR - Keypad Data Register */
27316 /*! @{ */
27317 
27318 #define KPP_KPDR_KRD_MASK                        (0xFFU)
27319 #define KPP_KPDR_KRD_SHIFT                       (0U)
27320 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
27321 
27322 #define KPP_KPDR_KCD_MASK                        (0xFF00U)
27323 #define KPP_KPDR_KCD_SHIFT                       (8U)
27324 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
27325 /*! @} */
27326 
27327 
27328 /*!
27329  * @}
27330  */ /* end of group KPP_Register_Masks */
27331 
27332 
27333 /* KPP - Peripheral instance base addresses */
27334 /** Peripheral KPP base address */
27335 #define KPP_BASE                                 (0x401FC000u)
27336 /** Peripheral KPP base pointer */
27337 #define KPP                                      ((KPP_Type *)KPP_BASE)
27338 /** Array initializer of KPP peripheral base addresses */
27339 #define KPP_BASE_ADDRS                           { KPP_BASE }
27340 /** Array initializer of KPP peripheral base pointers */
27341 #define KPP_BASE_PTRS                            { KPP }
27342 /** Interrupt vectors for the KPP peripheral type */
27343 #define KPP_IRQS                                 { KPP_IRQn }
27344 
27345 /*!
27346  * @}
27347  */ /* end of group KPP_Peripheral_Access_Layer */
27348 
27349 
27350 /* ----------------------------------------------------------------------------
27351    -- LCDIF Peripheral Access Layer
27352    ---------------------------------------------------------------------------- */
27353 
27354 /*!
27355  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
27356  * @{
27357  */
27358 
27359 /** LCDIF - Register Layout Typedef */
27360 typedef struct {
27361   __IO uint32_t CTRL;                              /**< LCDIF General Control Register, offset: 0x0 */
27362   __IO uint32_t CTRL_SET;                          /**< LCDIF General Control Register, offset: 0x4 */
27363   __IO uint32_t CTRL_CLR;                          /**< LCDIF General Control Register, offset: 0x8 */
27364   __IO uint32_t CTRL_TOG;                          /**< LCDIF General Control Register, offset: 0xC */
27365   __IO uint32_t CTRL1;                             /**< LCDIF General Control1 Register, offset: 0x10 */
27366   __IO uint32_t CTRL1_SET;                         /**< LCDIF General Control1 Register, offset: 0x14 */
27367   __IO uint32_t CTRL1_CLR;                         /**< LCDIF General Control1 Register, offset: 0x18 */
27368   __IO uint32_t CTRL1_TOG;                         /**< LCDIF General Control1 Register, offset: 0x1C */
27369   __IO uint32_t CTRL2;                             /**< LCDIF General Control2 Register, offset: 0x20 */
27370   __IO uint32_t CTRL2_SET;                         /**< LCDIF General Control2 Register, offset: 0x24 */
27371   __IO uint32_t CTRL2_CLR;                         /**< LCDIF General Control2 Register, offset: 0x28 */
27372   __IO uint32_t CTRL2_TOG;                         /**< LCDIF General Control2 Register, offset: 0x2C */
27373   __IO uint32_t TRANSFER_COUNT;                    /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
27374        uint8_t RESERVED_0[12];
27375   __IO uint32_t CUR_BUF;                           /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
27376        uint8_t RESERVED_1[12];
27377   __IO uint32_t NEXT_BUF;                          /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
27378        uint8_t RESERVED_2[28];
27379   __IO uint32_t VDCTRL0;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
27380   __IO uint32_t VDCTRL0_SET;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
27381   __IO uint32_t VDCTRL0_CLR;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
27382   __IO uint32_t VDCTRL0_TOG;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
27383   __IO uint32_t VDCTRL1;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
27384        uint8_t RESERVED_3[12];
27385   __IO uint32_t VDCTRL2;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
27386        uint8_t RESERVED_4[12];
27387   __IO uint32_t VDCTRL3;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
27388        uint8_t RESERVED_5[12];
27389   __IO uint32_t VDCTRL4;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
27390        uint8_t RESERVED_6[220];
27391   __IO uint32_t BM_ERROR_STAT;                     /**< Bus Master Error Status Register, offset: 0x190 */
27392        uint8_t RESERVED_7[12];
27393   __IO uint32_t CRC_STAT;                          /**< CRC Status Register, offset: 0x1A0 */
27394        uint8_t RESERVED_8[12];
27395   __I  uint32_t STAT;                              /**< LCD Interface Status Register, offset: 0x1B0 */
27396        uint8_t RESERVED_9[236];
27397   __IO uint32_t RGB_ADJUST;                        /**< RGB Color Range Adjust, offset: 0x2A0 */
27398   __IO uint32_t RGB_ADJUST_SET;                    /**< RGB Color Range Adjust, offset: 0x2A4 */
27399   __IO uint32_t RGB_ADJUST_CLR;                    /**< RGB Color Range Adjust, offset: 0x2A8 */
27400   __IO uint32_t RGB_ADJUST_TOG;                    /**< RGB Color Range Adjust, offset: 0x2AC */
27401        uint8_t RESERVED_10[208];
27402   __IO uint32_t PIGEONCTRL0;                       /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
27403   __IO uint32_t PIGEONCTRL0_SET;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
27404   __IO uint32_t PIGEONCTRL0_CLR;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
27405   __IO uint32_t PIGEONCTRL0_TOG;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
27406   __IO uint32_t PIGEONCTRL1;                       /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
27407   __IO uint32_t PIGEONCTRL1_SET;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
27408   __IO uint32_t PIGEONCTRL1_CLR;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
27409   __IO uint32_t PIGEONCTRL1_TOG;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
27410   __IO uint32_t PIGEONCTRL2;                       /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
27411   __IO uint32_t PIGEONCTRL2_SET;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
27412   __IO uint32_t PIGEONCTRL2_CLR;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
27413   __IO uint32_t PIGEONCTRL2_TOG;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
27414        uint8_t RESERVED_11[1104];
27415   struct {                                         /* offset: 0x800, array step: 0x40 */
27416     __IO uint32_t PIGEON_0;                          /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
27417          uint8_t RESERVED_0[12];
27418     __IO uint32_t PIGEON_1;                          /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
27419          uint8_t RESERVED_1[12];
27420     __IO uint32_t PIGEON_2;                          /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
27421          uint8_t RESERVED_2[28];
27422   } PIGEON[12];
27423   __IO uint32_t LUT_CTRL;                          /**< Look Up Table Control Register, offset: 0xB00 */
27424        uint8_t RESERVED_12[12];
27425   __IO uint32_t LUT0_ADDR;                         /**< Lookup Table 0 Index Register, offset: 0xB10 */
27426        uint8_t RESERVED_13[12];
27427   __IO uint32_t LUT0_DATA;                         /**< Lookup Table 0 Data Register, offset: 0xB20 */
27428        uint8_t RESERVED_14[12];
27429   __IO uint32_t LUT1_ADDR;                         /**< Lookup Table 1 Index Register, offset: 0xB30 */
27430        uint8_t RESERVED_15[12];
27431   __IO uint32_t LUT1_DATA;                         /**< Lookup Table 1 Data Register, offset: 0xB40 */
27432 } LCDIF_Type;
27433 
27434 /* ----------------------------------------------------------------------------
27435    -- LCDIF Register Masks
27436    ---------------------------------------------------------------------------- */
27437 
27438 /*!
27439  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
27440  * @{
27441  */
27442 
27443 /*! @name CTRL - LCDIF General Control Register */
27444 /*! @{ */
27445 
27446 #define LCDIF_CTRL_RUN_MASK                      (0x1U)
27447 #define LCDIF_CTRL_RUN_SHIFT                     (0U)
27448 #define LCDIF_CTRL_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
27449 
27450 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK       (0x2U)
27451 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT      (1U)
27452 /*! DATA_FORMAT_24_BIT
27453  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27454  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
27455  *       each byte do not contain any useful data, and should be dropped.
27456  */
27457 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
27458 
27459 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK       (0x4U)
27460 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT      (2U)
27461 /*! DATA_FORMAT_18_BIT
27462  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27463  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27464  */
27465 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
27466 
27467 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK       (0x8U)
27468 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT      (3U)
27469 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
27470 
27471 #define LCDIF_CTRL_RSRVD0_MASK                   (0x10U)
27472 #define LCDIF_CTRL_RSRVD0_SHIFT                  (4U)
27473 #define LCDIF_CTRL_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
27474 
27475 #define LCDIF_CTRL_MASTER_MASK                   (0x20U)
27476 #define LCDIF_CTRL_MASTER_SHIFT                  (5U)
27477 #define LCDIF_CTRL_MASTER(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
27478 
27479 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK     (0x40U)
27480 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT    (6U)
27481 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
27482 
27483 #define LCDIF_CTRL_WORD_LENGTH_MASK              (0x300U)
27484 #define LCDIF_CTRL_WORD_LENGTH_SHIFT             (8U)
27485 /*! WORD_LENGTH
27486  *  0b00..Input data is 16 bits per pixel.
27487  *  0b01..Input data is 8 bits wide.
27488  *  0b10..Input data is 18 bits per pixel.
27489  *  0b11..Input data is 24 bits per pixel.
27490  */
27491 #define LCDIF_CTRL_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
27492 
27493 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK        (0xC00U)
27494 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT       (10U)
27495 /*! LCD_DATABUS_WIDTH
27496  *  0b00..16-bit data bus mode.
27497  *  0b01..8-bit data bus mode.
27498  *  0b10..18-bit data bus mode.
27499  *  0b11..24-bit data bus mode.
27500  */
27501 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
27502 
27503 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK         (0x3000U)
27504 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT        (12U)
27505 /*! CSC_DATA_SWIZZLE
27506  *  0b00..No byte swapping.(Little endian)
27507  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27508  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27509  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27510  *  0b10..Swap half-words.
27511  *  0b11..Swap bytes within each half-word.
27512  */
27513 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
27514 
27515 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK       (0xC000U)
27516 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT      (14U)
27517 /*! INPUT_DATA_SWIZZLE
27518  *  0b00..No byte swapping.(Little endian)
27519  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27520  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27521  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27522  *  0b10..Swap half-words.
27523  *  0b11..Swap bytes within each half-word.
27524  */
27525 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
27526 
27527 #define LCDIF_CTRL_DOTCLK_MODE_MASK              (0x20000U)
27528 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT             (17U)
27529 #define LCDIF_CTRL_DOTCLK_MODE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
27530 
27531 #define LCDIF_CTRL_BYPASS_COUNT_MASK             (0x80000U)
27532 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT            (19U)
27533 #define LCDIF_CTRL_BYPASS_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
27534 
27535 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK           (0x3E00000U)
27536 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT          (21U)
27537 #define LCDIF_CTRL_SHIFT_NUM_BITS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
27538 
27539 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK           (0x4000000U)
27540 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT          (26U)
27541 /*! DATA_SHIFT_DIR
27542  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27543  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27544  */
27545 #define LCDIF_CTRL_DATA_SHIFT_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
27546 
27547 #define LCDIF_CTRL_CLKGATE_MASK                  (0x40000000U)
27548 #define LCDIF_CTRL_CLKGATE_SHIFT                 (30U)
27549 #define LCDIF_CTRL_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
27550 
27551 #define LCDIF_CTRL_SFTRST_MASK                   (0x80000000U)
27552 #define LCDIF_CTRL_SFTRST_SHIFT                  (31U)
27553 #define LCDIF_CTRL_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
27554 /*! @} */
27555 
27556 /*! @name CTRL_SET - LCDIF General Control Register */
27557 /*! @{ */
27558 
27559 #define LCDIF_CTRL_SET_RUN_MASK                  (0x1U)
27560 #define LCDIF_CTRL_SET_RUN_SHIFT                 (0U)
27561 #define LCDIF_CTRL_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
27562 
27563 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
27564 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT  (1U)
27565 /*! DATA_FORMAT_24_BIT
27566  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27567  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
27568  *       each byte do not contain any useful data, and should be dropped.
27569  */
27570 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
27571 
27572 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
27573 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT  (2U)
27574 /*! DATA_FORMAT_18_BIT
27575  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27576  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27577  */
27578 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
27579 
27580 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
27581 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT  (3U)
27582 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
27583 
27584 #define LCDIF_CTRL_SET_RSRVD0_MASK               (0x10U)
27585 #define LCDIF_CTRL_SET_RSRVD0_SHIFT              (4U)
27586 #define LCDIF_CTRL_SET_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
27587 
27588 #define LCDIF_CTRL_SET_MASTER_MASK               (0x20U)
27589 #define LCDIF_CTRL_SET_MASTER_SHIFT              (5U)
27590 #define LCDIF_CTRL_SET_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
27591 
27592 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27593 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27594 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
27595 
27596 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK          (0x300U)
27597 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT         (8U)
27598 /*! WORD_LENGTH
27599  *  0b00..Input data is 16 bits per pixel.
27600  *  0b01..Input data is 8 bits wide.
27601  *  0b10..Input data is 18 bits per pixel.
27602  *  0b11..Input data is 24 bits per pixel.
27603  */
27604 #define LCDIF_CTRL_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
27605 
27606 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK    (0xC00U)
27607 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
27608 /*! LCD_DATABUS_WIDTH
27609  *  0b00..16-bit data bus mode.
27610  *  0b01..8-bit data bus mode.
27611  *  0b10..18-bit data bus mode.
27612  *  0b11..24-bit data bus mode.
27613  */
27614 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
27615 
27616 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK     (0x3000U)
27617 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT    (12U)
27618 /*! CSC_DATA_SWIZZLE
27619  *  0b00..No byte swapping.(Little endian)
27620  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27621  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27622  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27623  *  0b10..Swap half-words.
27624  *  0b11..Swap bytes within each half-word.
27625  */
27626 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
27627 
27628 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
27629 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT  (14U)
27630 /*! INPUT_DATA_SWIZZLE
27631  *  0b00..No byte swapping.(Little endian)
27632  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27633  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27634  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27635  *  0b10..Swap half-words.
27636  *  0b11..Swap bytes within each half-word.
27637  */
27638 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
27639 
27640 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK          (0x20000U)
27641 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT         (17U)
27642 #define LCDIF_CTRL_SET_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
27643 
27644 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK         (0x80000U)
27645 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT        (19U)
27646 #define LCDIF_CTRL_SET_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
27647 
27648 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK       (0x3E00000U)
27649 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT      (21U)
27650 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
27651 
27652 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK       (0x4000000U)
27653 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT      (26U)
27654 /*! DATA_SHIFT_DIR
27655  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27656  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27657  */
27658 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
27659 
27660 #define LCDIF_CTRL_SET_CLKGATE_MASK              (0x40000000U)
27661 #define LCDIF_CTRL_SET_CLKGATE_SHIFT             (30U)
27662 #define LCDIF_CTRL_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
27663 
27664 #define LCDIF_CTRL_SET_SFTRST_MASK               (0x80000000U)
27665 #define LCDIF_CTRL_SET_SFTRST_SHIFT              (31U)
27666 #define LCDIF_CTRL_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
27667 /*! @} */
27668 
27669 /*! @name CTRL_CLR - LCDIF General Control Register */
27670 /*! @{ */
27671 
27672 #define LCDIF_CTRL_CLR_RUN_MASK                  (0x1U)
27673 #define LCDIF_CTRL_CLR_RUN_SHIFT                 (0U)
27674 #define LCDIF_CTRL_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
27675 
27676 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
27677 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT  (1U)
27678 /*! DATA_FORMAT_24_BIT
27679  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27680  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
27681  *       each byte do not contain any useful data, and should be dropped.
27682  */
27683 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
27684 
27685 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
27686 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT  (2U)
27687 /*! DATA_FORMAT_18_BIT
27688  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27689  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27690  */
27691 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
27692 
27693 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
27694 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT  (3U)
27695 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
27696 
27697 #define LCDIF_CTRL_CLR_RSRVD0_MASK               (0x10U)
27698 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT              (4U)
27699 #define LCDIF_CTRL_CLR_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
27700 
27701 #define LCDIF_CTRL_CLR_MASTER_MASK               (0x20U)
27702 #define LCDIF_CTRL_CLR_MASTER_SHIFT              (5U)
27703 #define LCDIF_CTRL_CLR_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
27704 
27705 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27706 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27707 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
27708 
27709 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK          (0x300U)
27710 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT         (8U)
27711 /*! WORD_LENGTH
27712  *  0b00..Input data is 16 bits per pixel.
27713  *  0b01..Input data is 8 bits wide.
27714  *  0b10..Input data is 18 bits per pixel.
27715  *  0b11..Input data is 24 bits per pixel.
27716  */
27717 #define LCDIF_CTRL_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
27718 
27719 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK    (0xC00U)
27720 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
27721 /*! LCD_DATABUS_WIDTH
27722  *  0b00..16-bit data bus mode.
27723  *  0b01..8-bit data bus mode.
27724  *  0b10..18-bit data bus mode.
27725  *  0b11..24-bit data bus mode.
27726  */
27727 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
27728 
27729 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK     (0x3000U)
27730 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT    (12U)
27731 /*! CSC_DATA_SWIZZLE
27732  *  0b00..No byte swapping.(Little endian)
27733  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27734  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27735  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27736  *  0b10..Swap half-words.
27737  *  0b11..Swap bytes within each half-word.
27738  */
27739 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
27740 
27741 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
27742 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT  (14U)
27743 /*! INPUT_DATA_SWIZZLE
27744  *  0b00..No byte swapping.(Little endian)
27745  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27746  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27747  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27748  *  0b10..Swap half-words.
27749  *  0b11..Swap bytes within each half-word.
27750  */
27751 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
27752 
27753 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK          (0x20000U)
27754 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT         (17U)
27755 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
27756 
27757 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK         (0x80000U)
27758 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT        (19U)
27759 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
27760 
27761 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK       (0x3E00000U)
27762 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT      (21U)
27763 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
27764 
27765 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK       (0x4000000U)
27766 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT      (26U)
27767 /*! DATA_SHIFT_DIR
27768  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27769  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27770  */
27771 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
27772 
27773 #define LCDIF_CTRL_CLR_CLKGATE_MASK              (0x40000000U)
27774 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT             (30U)
27775 #define LCDIF_CTRL_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
27776 
27777 #define LCDIF_CTRL_CLR_SFTRST_MASK               (0x80000000U)
27778 #define LCDIF_CTRL_CLR_SFTRST_SHIFT              (31U)
27779 #define LCDIF_CTRL_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
27780 /*! @} */
27781 
27782 /*! @name CTRL_TOG - LCDIF General Control Register */
27783 /*! @{ */
27784 
27785 #define LCDIF_CTRL_TOG_RUN_MASK                  (0x1U)
27786 #define LCDIF_CTRL_TOG_RUN_SHIFT                 (0U)
27787 #define LCDIF_CTRL_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
27788 
27789 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
27790 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT  (1U)
27791 /*! DATA_FORMAT_24_BIT
27792  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27793  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
27794  *       each byte do not contain any useful data, and should be dropped.
27795  */
27796 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
27797 
27798 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
27799 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT  (2U)
27800 /*! DATA_FORMAT_18_BIT
27801  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27802  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27803  */
27804 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
27805 
27806 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
27807 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT  (3U)
27808 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
27809 
27810 #define LCDIF_CTRL_TOG_RSRVD0_MASK               (0x10U)
27811 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT              (4U)
27812 #define LCDIF_CTRL_TOG_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
27813 
27814 #define LCDIF_CTRL_TOG_MASTER_MASK               (0x20U)
27815 #define LCDIF_CTRL_TOG_MASTER_SHIFT              (5U)
27816 #define LCDIF_CTRL_TOG_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
27817 
27818 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27819 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27820 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
27821 
27822 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK          (0x300U)
27823 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT         (8U)
27824 /*! WORD_LENGTH
27825  *  0b00..Input data is 16 bits per pixel.
27826  *  0b01..Input data is 8 bits wide.
27827  *  0b10..Input data is 18 bits per pixel.
27828  *  0b11..Input data is 24 bits per pixel.
27829  */
27830 #define LCDIF_CTRL_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
27831 
27832 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK    (0xC00U)
27833 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
27834 /*! LCD_DATABUS_WIDTH
27835  *  0b00..16-bit data bus mode.
27836  *  0b01..8-bit data bus mode.
27837  *  0b10..18-bit data bus mode.
27838  *  0b11..24-bit data bus mode.
27839  */
27840 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
27841 
27842 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK     (0x3000U)
27843 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT    (12U)
27844 /*! CSC_DATA_SWIZZLE
27845  *  0b00..No byte swapping.(Little endian)
27846  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27847  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27848  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27849  *  0b10..Swap half-words.
27850  *  0b11..Swap bytes within each half-word.
27851  */
27852 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
27853 
27854 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
27855 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT  (14U)
27856 /*! INPUT_DATA_SWIZZLE
27857  *  0b00..No byte swapping.(Little endian)
27858  *  0b00..Little Endian byte ordering (same as NO_SWAP).
27859  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27860  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27861  *  0b10..Swap half-words.
27862  *  0b11..Swap bytes within each half-word.
27863  */
27864 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
27865 
27866 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK          (0x20000U)
27867 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT         (17U)
27868 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
27869 
27870 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK         (0x80000U)
27871 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT        (19U)
27872 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
27873 
27874 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK       (0x3E00000U)
27875 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT      (21U)
27876 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
27877 
27878 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK       (0x4000000U)
27879 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT      (26U)
27880 /*! DATA_SHIFT_DIR
27881  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27882  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27883  */
27884 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
27885 
27886 #define LCDIF_CTRL_TOG_CLKGATE_MASK              (0x40000000U)
27887 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT             (30U)
27888 #define LCDIF_CTRL_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
27889 
27890 #define LCDIF_CTRL_TOG_SFTRST_MASK               (0x80000000U)
27891 #define LCDIF_CTRL_TOG_SFTRST_SHIFT              (31U)
27892 #define LCDIF_CTRL_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
27893 /*! @} */
27894 
27895 /*! @name CTRL1 - LCDIF General Control1 Register */
27896 /*! @{ */
27897 
27898 #define LCDIF_CTRL1_RSRVD0_MASK                  (0xF8U)
27899 #define LCDIF_CTRL1_RSRVD0_SHIFT                 (3U)
27900 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
27901 
27902 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          (0x100U)
27903 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         (8U)
27904 /*! VSYNC_EDGE_IRQ
27905  *  0b0..No Interrupt Request Pending.
27906  *  0b1..Interrupt Request Pending.
27907  */
27908 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
27909 
27910 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      (0x200U)
27911 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     (9U)
27912 /*! CUR_FRAME_DONE_IRQ
27913  *  0b0..No Interrupt Request Pending.
27914  *  0b1..Interrupt Request Pending.
27915  */
27916 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
27917 
27918 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           (0x400U)
27919 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          (10U)
27920 /*! UNDERFLOW_IRQ
27921  *  0b0..No Interrupt Request Pending.
27922  *  0b1..Interrupt Request Pending.
27923  */
27924 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
27925 
27926 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            (0x800U)
27927 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           (11U)
27928 /*! OVERFLOW_IRQ
27929  *  0b0..No Interrupt Request Pending.
27930  *  0b1..Interrupt Request Pending.
27931  */
27932 #define LCDIF_CTRL1_OVERFLOW_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
27933 
27934 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       (0x1000U)
27935 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      (12U)
27936 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
27937 
27938 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
27939 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  (13U)
27940 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
27941 
27942 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        (0x4000U)
27943 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       (14U)
27944 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
27945 
27946 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         (0x8000U)
27947 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        (15U)
27948 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
27949 
27950 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     (0xF0000U)
27951 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    (16U)
27952 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
27953 
27954 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
27955 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
27956 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
27957 
27958 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              (0x200000U)
27959 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             (21U)
27960 #define LCDIF_CTRL1_FIFO_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
27961 
27962 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
27963 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
27964 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
27965 
27966 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        (0x800000U)
27967 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       (23U)
27968 #define LCDIF_CTRL1_INTERLACE_FIELDS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
27969 
27970 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    (0x1000000U)
27971 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
27972 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
27973 
27974 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            (0x2000000U)
27975 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           (25U)
27976 /*! BM_ERROR_IRQ
27977  *  0b0..No Interrupt Request Pending.
27978  *  0b1..Interrupt Request Pending.
27979  */
27980 #define LCDIF_CTRL1_BM_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
27981 
27982 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         (0x4000000U)
27983 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        (26U)
27984 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
27985 
27986 #define LCDIF_CTRL1_CS_OUT_SELECT_MASK           (0x40000000U)
27987 #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT          (30U)
27988 #define LCDIF_CTRL1_CS_OUT_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
27989 
27990 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK       (0x80000000U)
27991 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT      (31U)
27992 #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
27993 /*! @} */
27994 
27995 /*! @name CTRL1_SET - LCDIF General Control1 Register */
27996 /*! @{ */
27997 
27998 #define LCDIF_CTRL1_SET_RSRVD0_MASK              (0xF8U)
27999 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             (3U)
28000 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
28001 
28002 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      (0x100U)
28003 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     (8U)
28004 /*! VSYNC_EDGE_IRQ
28005  *  0b0..No Interrupt Request Pending.
28006  *  0b1..Interrupt Request Pending.
28007  */
28008 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
28009 
28010 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
28011 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28012 /*! CUR_FRAME_DONE_IRQ
28013  *  0b0..No Interrupt Request Pending.
28014  *  0b1..Interrupt Request Pending.
28015  */
28016 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
28017 
28018 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       (0x400U)
28019 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      (10U)
28020 /*! UNDERFLOW_IRQ
28021  *  0b0..No Interrupt Request Pending.
28022  *  0b1..Interrupt Request Pending.
28023  */
28024 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
28025 
28026 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        (0x800U)
28027 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       (11U)
28028 /*! OVERFLOW_IRQ
28029  *  0b0..No Interrupt Request Pending.
28030  *  0b1..Interrupt Request Pending.
28031  */
28032 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
28033 
28034 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
28035 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
28036 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
28037 
28038 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28039 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28040 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
28041 
28042 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
28043 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   (14U)
28044 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
28045 
28046 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     (0x8000U)
28047 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    (15U)
28048 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
28049 
28050 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28051 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
28052 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
28053 
28054 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28055 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28056 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
28057 
28058 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          (0x200000U)
28059 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         (21U)
28060 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
28061 
28062 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28063 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28064 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28065 
28066 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    (0x800000U)
28067 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   (23U)
28068 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
28069 
28070 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28071 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28072 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
28073 
28074 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        (0x2000000U)
28075 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       (25U)
28076 /*! BM_ERROR_IRQ
28077  *  0b0..No Interrupt Request Pending.
28078  *  0b1..Interrupt Request Pending.
28079  */
28080 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
28081 
28082 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
28083 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    (26U)
28084 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
28085 
28086 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK       (0x40000000U)
28087 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT      (30U)
28088 #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
28089 
28090 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK   (0x80000000U)
28091 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT  (31U)
28092 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
28093 /*! @} */
28094 
28095 /*! @name CTRL1_CLR - LCDIF General Control1 Register */
28096 /*! @{ */
28097 
28098 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              (0xF8U)
28099 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             (3U)
28100 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
28101 
28102 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      (0x100U)
28103 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     (8U)
28104 /*! VSYNC_EDGE_IRQ
28105  *  0b0..No Interrupt Request Pending.
28106  *  0b1..Interrupt Request Pending.
28107  */
28108 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
28109 
28110 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
28111 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28112 /*! CUR_FRAME_DONE_IRQ
28113  *  0b0..No Interrupt Request Pending.
28114  *  0b1..Interrupt Request Pending.
28115  */
28116 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
28117 
28118 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       (0x400U)
28119 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      (10U)
28120 /*! UNDERFLOW_IRQ
28121  *  0b0..No Interrupt Request Pending.
28122  *  0b1..Interrupt Request Pending.
28123  */
28124 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
28125 
28126 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        (0x800U)
28127 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       (11U)
28128 /*! OVERFLOW_IRQ
28129  *  0b0..No Interrupt Request Pending.
28130  *  0b1..Interrupt Request Pending.
28131  */
28132 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
28133 
28134 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
28135 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
28136 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
28137 
28138 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28139 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28140 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
28141 
28142 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
28143 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   (14U)
28144 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
28145 
28146 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     (0x8000U)
28147 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    (15U)
28148 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
28149 
28150 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28151 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
28152 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
28153 
28154 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28155 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28156 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
28157 
28158 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          (0x200000U)
28159 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         (21U)
28160 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
28161 
28162 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28163 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28164 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28165 
28166 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    (0x800000U)
28167 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   (23U)
28168 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
28169 
28170 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28171 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28172 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
28173 
28174 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        (0x2000000U)
28175 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       (25U)
28176 /*! BM_ERROR_IRQ
28177  *  0b0..No Interrupt Request Pending.
28178  *  0b1..Interrupt Request Pending.
28179  */
28180 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
28181 
28182 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
28183 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    (26U)
28184 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
28185 
28186 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK       (0x40000000U)
28187 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT      (30U)
28188 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
28189 
28190 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK   (0x80000000U)
28191 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT  (31U)
28192 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
28193 /*! @} */
28194 
28195 /*! @name CTRL1_TOG - LCDIF General Control1 Register */
28196 /*! @{ */
28197 
28198 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              (0xF8U)
28199 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             (3U)
28200 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
28201 
28202 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      (0x100U)
28203 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     (8U)
28204 /*! VSYNC_EDGE_IRQ
28205  *  0b0..No Interrupt Request Pending.
28206  *  0b1..Interrupt Request Pending.
28207  */
28208 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
28209 
28210 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
28211 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28212 /*! CUR_FRAME_DONE_IRQ
28213  *  0b0..No Interrupt Request Pending.
28214  *  0b1..Interrupt Request Pending.
28215  */
28216 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
28217 
28218 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       (0x400U)
28219 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      (10U)
28220 /*! UNDERFLOW_IRQ
28221  *  0b0..No Interrupt Request Pending.
28222  *  0b1..Interrupt Request Pending.
28223  */
28224 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
28225 
28226 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        (0x800U)
28227 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       (11U)
28228 /*! OVERFLOW_IRQ
28229  *  0b0..No Interrupt Request Pending.
28230  *  0b1..Interrupt Request Pending.
28231  */
28232 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
28233 
28234 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
28235 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
28236 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
28237 
28238 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28239 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28240 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
28241 
28242 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
28243 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   (14U)
28244 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
28245 
28246 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     (0x8000U)
28247 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    (15U)
28248 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
28249 
28250 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28251 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
28252 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
28253 
28254 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28255 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28256 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
28257 
28258 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          (0x200000U)
28259 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         (21U)
28260 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
28261 
28262 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28263 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28264 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28265 
28266 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    (0x800000U)
28267 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   (23U)
28268 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
28269 
28270 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28271 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28272 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
28273 
28274 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        (0x2000000U)
28275 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       (25U)
28276 /*! BM_ERROR_IRQ
28277  *  0b0..No Interrupt Request Pending.
28278  *  0b1..Interrupt Request Pending.
28279  */
28280 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
28281 
28282 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
28283 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    (26U)
28284 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
28285 
28286 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK       (0x40000000U)
28287 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT      (30U)
28288 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
28289 
28290 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK   (0x80000000U)
28291 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT  (31U)
28292 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
28293 /*! @} */
28294 
28295 /*! @name CTRL2 - LCDIF General Control2 Register */
28296 /*! @{ */
28297 
28298 #define LCDIF_CTRL2_RSRVD0_MASK                  (0xFFFU)
28299 #define LCDIF_CTRL2_RSRVD0_SHIFT                 (0U)
28300 #define LCDIF_CTRL2_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
28301 
28302 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       (0x7000U)
28303 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      (12U)
28304 /*! EVEN_LINE_PATTERN
28305  *  0b000..RGB
28306  *  0b001..RBG
28307  *  0b010..GBR
28308  *  0b011..GRB
28309  *  0b100..BRG
28310  *  0b101..BGR
28311  */
28312 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
28313 
28314 #define LCDIF_CTRL2_RSRVD3_MASK                  (0x8000U)
28315 #define LCDIF_CTRL2_RSRVD3_SHIFT                 (15U)
28316 #define LCDIF_CTRL2_RSRVD3(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
28317 
28318 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        (0x70000U)
28319 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       (16U)
28320 /*! ODD_LINE_PATTERN
28321  *  0b000..RGB
28322  *  0b001..RBG
28323  *  0b010..GBR
28324  *  0b011..GRB
28325  *  0b100..BRG
28326  *  0b101..BGR
28327  */
28328 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
28329 
28330 #define LCDIF_CTRL2_RSRVD4_MASK                  (0x80000U)
28331 #define LCDIF_CTRL2_RSRVD4_SHIFT                 (19U)
28332 #define LCDIF_CTRL2_RSRVD4(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
28333 
28334 #define LCDIF_CTRL2_BURST_LEN_8_MASK             (0x100000U)
28335 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            (20U)
28336 #define LCDIF_CTRL2_BURST_LEN_8(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
28337 
28338 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        (0xE00000U)
28339 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       (21U)
28340 /*! OUTSTANDING_REQS
28341  *  0b000..REQ_1
28342  *  0b001..REQ_2
28343  *  0b010..REQ_4
28344  *  0b011..REQ_8
28345  *  0b100..REQ_16
28346  */
28347 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
28348 
28349 #define LCDIF_CTRL2_RSRVD5_MASK                  (0xFF000000U)
28350 #define LCDIF_CTRL2_RSRVD5_SHIFT                 (24U)
28351 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
28352 /*! @} */
28353 
28354 /*! @name CTRL2_SET - LCDIF General Control2 Register */
28355 /*! @{ */
28356 
28357 #define LCDIF_CTRL2_SET_RSRVD0_MASK              (0xFFFU)
28358 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             (0U)
28359 #define LCDIF_CTRL2_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
28360 
28361 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
28362 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  (12U)
28363 /*! EVEN_LINE_PATTERN
28364  *  0b000..RGB
28365  *  0b001..RBG
28366  *  0b010..GBR
28367  *  0b011..GRB
28368  *  0b100..BRG
28369  *  0b101..BGR
28370  */
28371 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
28372 
28373 #define LCDIF_CTRL2_SET_RSRVD3_MASK              (0x8000U)
28374 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             (15U)
28375 #define LCDIF_CTRL2_SET_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
28376 
28377 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    (0x70000U)
28378 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
28379 /*! ODD_LINE_PATTERN
28380  *  0b000..RGB
28381  *  0b001..RBG
28382  *  0b010..GBR
28383  *  0b011..GRB
28384  *  0b100..BRG
28385  *  0b101..BGR
28386  */
28387 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
28388 
28389 #define LCDIF_CTRL2_SET_RSRVD4_MASK              (0x80000U)
28390 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             (19U)
28391 #define LCDIF_CTRL2_SET_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
28392 
28393 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         (0x100000U)
28394 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        (20U)
28395 #define LCDIF_CTRL2_SET_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
28396 
28397 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    (0xE00000U)
28398 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
28399 /*! OUTSTANDING_REQS
28400  *  0b000..REQ_1
28401  *  0b001..REQ_2
28402  *  0b010..REQ_4
28403  *  0b011..REQ_8
28404  *  0b100..REQ_16
28405  */
28406 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
28407 
28408 #define LCDIF_CTRL2_SET_RSRVD5_MASK              (0xFF000000U)
28409 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             (24U)
28410 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
28411 /*! @} */
28412 
28413 /*! @name CTRL2_CLR - LCDIF General Control2 Register */
28414 /*! @{ */
28415 
28416 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              (0xFFFU)
28417 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             (0U)
28418 #define LCDIF_CTRL2_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
28419 
28420 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
28421 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  (12U)
28422 /*! EVEN_LINE_PATTERN
28423  *  0b000..RGB
28424  *  0b001..RBG
28425  *  0b010..GBR
28426  *  0b011..GRB
28427  *  0b100..BRG
28428  *  0b101..BGR
28429  */
28430 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
28431 
28432 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              (0x8000U)
28433 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             (15U)
28434 #define LCDIF_CTRL2_CLR_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
28435 
28436 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    (0x70000U)
28437 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
28438 /*! ODD_LINE_PATTERN
28439  *  0b000..RGB
28440  *  0b001..RBG
28441  *  0b010..GBR
28442  *  0b011..GRB
28443  *  0b100..BRG
28444  *  0b101..BGR
28445  */
28446 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
28447 
28448 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              (0x80000U)
28449 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             (19U)
28450 #define LCDIF_CTRL2_CLR_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
28451 
28452 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         (0x100000U)
28453 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        (20U)
28454 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
28455 
28456 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    (0xE00000U)
28457 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
28458 /*! OUTSTANDING_REQS
28459  *  0b000..REQ_1
28460  *  0b001..REQ_2
28461  *  0b010..REQ_4
28462  *  0b011..REQ_8
28463  *  0b100..REQ_16
28464  */
28465 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
28466 
28467 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              (0xFF000000U)
28468 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             (24U)
28469 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
28470 /*! @} */
28471 
28472 /*! @name CTRL2_TOG - LCDIF General Control2 Register */
28473 /*! @{ */
28474 
28475 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              (0xFFFU)
28476 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             (0U)
28477 #define LCDIF_CTRL2_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
28478 
28479 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
28480 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  (12U)
28481 /*! EVEN_LINE_PATTERN
28482  *  0b000..RGB
28483  *  0b001..RBG
28484  *  0b010..GBR
28485  *  0b011..GRB
28486  *  0b100..BRG
28487  *  0b101..BGR
28488  */
28489 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
28490 
28491 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              (0x8000U)
28492 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             (15U)
28493 #define LCDIF_CTRL2_TOG_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
28494 
28495 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    (0x70000U)
28496 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
28497 /*! ODD_LINE_PATTERN
28498  *  0b000..RGB
28499  *  0b001..RBG
28500  *  0b010..GBR
28501  *  0b011..GRB
28502  *  0b100..BRG
28503  *  0b101..BGR
28504  */
28505 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
28506 
28507 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              (0x80000U)
28508 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             (19U)
28509 #define LCDIF_CTRL2_TOG_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
28510 
28511 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         (0x100000U)
28512 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        (20U)
28513 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
28514 
28515 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    (0xE00000U)
28516 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
28517 /*! OUTSTANDING_REQS
28518  *  0b000..REQ_1
28519  *  0b001..REQ_2
28520  *  0b010..REQ_4
28521  *  0b011..REQ_8
28522  *  0b100..REQ_16
28523  */
28524 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
28525 
28526 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              (0xFF000000U)
28527 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             (24U)
28528 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
28529 /*! @} */
28530 
28531 /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
28532 /*! @{ */
28533 
28534 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        (0xFFFFU)
28535 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       (0U)
28536 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
28537 
28538 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        (0xFFFF0000U)
28539 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       (16U)
28540 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
28541 /*! @} */
28542 
28543 /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
28544 /*! @{ */
28545 
28546 #define LCDIF_CUR_BUF_ADDR_MASK                  (0xFFFFFFFFU)
28547 #define LCDIF_CUR_BUF_ADDR_SHIFT                 (0U)
28548 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
28549 /*! @} */
28550 
28551 /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
28552 /*! @{ */
28553 
28554 #define LCDIF_NEXT_BUF_ADDR_MASK                 (0xFFFFFFFFU)
28555 #define LCDIF_NEXT_BUF_ADDR_SHIFT                (0U)
28556 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
28557 /*! @} */
28558 
28559 /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28560 /*! @{ */
28561 
28562 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     (0x3FFFFU)
28563 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    (0U)
28564 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
28565 
28566 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        (0x40000U)
28567 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       (18U)
28568 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
28569 
28570 #define LCDIF_VDCTRL0_HALF_LINE_MASK             (0x80000U)
28571 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            (19U)
28572 #define LCDIF_VDCTRL0_HALF_LINE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
28573 
28574 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28575 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28576 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
28577 
28578 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     (0x200000U)
28579 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    (21U)
28580 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
28581 
28582 #define LCDIF_VDCTRL0_RSRVD1_MASK                (0xC00000U)
28583 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               (22U)
28584 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
28585 
28586 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            (0x1000000U)
28587 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           (24U)
28588 #define LCDIF_VDCTRL0_ENABLE_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
28589 
28590 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            (0x2000000U)
28591 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           (25U)
28592 #define LCDIF_VDCTRL0_DOTCLK_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
28593 
28594 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             (0x4000000U)
28595 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            (26U)
28596 #define LCDIF_VDCTRL0_HSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
28597 
28598 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             (0x8000000U)
28599 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            (27U)
28600 #define LCDIF_VDCTRL0_VSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
28601 
28602 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        (0x10000000U)
28603 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       (28U)
28604 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
28605 
28606 #define LCDIF_VDCTRL0_RSRVD2_MASK                (0xE0000000U)
28607 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               (29U)
28608 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
28609 /*! @} */
28610 
28611 /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28612 /*! @{ */
28613 
28614 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28615 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
28616 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
28617 
28618 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    (0x40000U)
28619 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   (18U)
28620 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
28621 
28622 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         (0x80000U)
28623 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        (19U)
28624 #define LCDIF_VDCTRL0_SET_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
28625 
28626 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28627 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28628 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
28629 
28630 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28631 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
28632 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
28633 
28634 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            (0xC00000U)
28635 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           (22U)
28636 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
28637 
28638 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        (0x1000000U)
28639 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       (24U)
28640 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
28641 
28642 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        (0x2000000U)
28643 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       (25U)
28644 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
28645 
28646 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         (0x4000000U)
28647 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        (26U)
28648 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
28649 
28650 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         (0x8000000U)
28651 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        (27U)
28652 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
28653 
28654 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    (0x10000000U)
28655 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   (28U)
28656 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
28657 
28658 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            (0xE0000000U)
28659 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           (29U)
28660 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
28661 /*! @} */
28662 
28663 /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28664 /*! @{ */
28665 
28666 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28667 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
28668 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
28669 
28670 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    (0x40000U)
28671 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   (18U)
28672 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
28673 
28674 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         (0x80000U)
28675 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        (19U)
28676 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
28677 
28678 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28679 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28680 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
28681 
28682 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28683 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
28684 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
28685 
28686 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            (0xC00000U)
28687 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           (22U)
28688 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
28689 
28690 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        (0x1000000U)
28691 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       (24U)
28692 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
28693 
28694 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        (0x2000000U)
28695 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       (25U)
28696 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
28697 
28698 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         (0x4000000U)
28699 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        (26U)
28700 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
28701 
28702 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         (0x8000000U)
28703 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        (27U)
28704 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
28705 
28706 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    (0x10000000U)
28707 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   (28U)
28708 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
28709 
28710 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            (0xE0000000U)
28711 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           (29U)
28712 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
28713 /*! @} */
28714 
28715 /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28716 /*! @{ */
28717 
28718 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28719 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
28720 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
28721 
28722 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    (0x40000U)
28723 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   (18U)
28724 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
28725 
28726 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         (0x80000U)
28727 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        (19U)
28728 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
28729 
28730 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28731 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28732 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
28733 
28734 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28735 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
28736 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
28737 
28738 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            (0xC00000U)
28739 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           (22U)
28740 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
28741 
28742 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        (0x1000000U)
28743 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       (24U)
28744 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
28745 
28746 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        (0x2000000U)
28747 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       (25U)
28748 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
28749 
28750 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         (0x4000000U)
28751 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        (26U)
28752 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
28753 
28754 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         (0x8000000U)
28755 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        (27U)
28756 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
28757 
28758 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    (0x10000000U)
28759 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   (28U)
28760 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
28761 
28762 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            (0xE0000000U)
28763 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           (29U)
28764 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
28765 /*! @} */
28766 
28767 /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
28768 /*! @{ */
28769 
28770 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          (0xFFFFFFFFU)
28771 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         (0U)
28772 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
28773 /*! @} */
28774 
28775 /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
28776 /*! @{ */
28777 
28778 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          (0x3FFFFU)
28779 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         (0U)
28780 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
28781 
28782 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     (0xFFFC0000U)
28783 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    (18U)
28784 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
28785 /*! @} */
28786 
28787 /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
28788 /*! @{ */
28789 
28790 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     (0xFFFFU)
28791 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    (0U)
28792 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
28793 
28794 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   (0xFFF0000U)
28795 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  (16U)
28796 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
28797 
28798 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            (0x10000000U)
28799 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           (28U)
28800 #define LCDIF_VDCTRL3_VSYNC_ONLY(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
28801 
28802 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      (0x20000000U)
28803 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     (29U)
28804 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
28805 
28806 #define LCDIF_VDCTRL3_RSRVD0_MASK                (0xC0000000U)
28807 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               (30U)
28808 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
28809 /*! @} */
28810 
28811 /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
28812 /*! @{ */
28813 
28814 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
28815 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
28816 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
28817 
28818 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       (0x40000U)
28819 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      (18U)
28820 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
28821 
28822 #define LCDIF_VDCTRL4_RSRVD0_MASK                (0x1FF80000U)
28823 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               (19U)
28824 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
28825 
28826 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        (0xE0000000U)
28827 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       (29U)
28828 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
28829 /*! @} */
28830 
28831 /*! @name BM_ERROR_STAT - Bus Master Error Status Register */
28832 /*! @{ */
28833 
28834 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            (0xFFFFFFFFU)
28835 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           (0U)
28836 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
28837 /*! @} */
28838 
28839 /*! @name CRC_STAT - CRC Status Register */
28840 /*! @{ */
28841 
28842 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            (0xFFFFFFFFU)
28843 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           (0U)
28844 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
28845 /*! @} */
28846 
28847 /*! @name STAT - LCD Interface Status Register */
28848 /*! @{ */
28849 
28850 #define LCDIF_STAT_LFIFO_COUNT_MASK              (0x1FFU)
28851 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             (0U)
28852 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
28853 
28854 #define LCDIF_STAT_RSRVD0_MASK                   (0x1FFFE00U)
28855 #define LCDIF_STAT_RSRVD0_SHIFT                  (9U)
28856 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
28857 
28858 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             (0x4000000U)
28859 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            (26U)
28860 #define LCDIF_STAT_TXFIFO_EMPTY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
28861 
28862 #define LCDIF_STAT_TXFIFO_FULL_MASK              (0x8000000U)
28863 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             (27U)
28864 #define LCDIF_STAT_TXFIFO_FULL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
28865 
28866 #define LCDIF_STAT_LFIFO_EMPTY_MASK              (0x10000000U)
28867 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             (28U)
28868 #define LCDIF_STAT_LFIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
28869 
28870 #define LCDIF_STAT_LFIFO_FULL_MASK               (0x20000000U)
28871 #define LCDIF_STAT_LFIFO_FULL_SHIFT              (29U)
28872 #define LCDIF_STAT_LFIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
28873 
28874 #define LCDIF_STAT_PRESENT_MASK                  (0x80000000U)
28875 #define LCDIF_STAT_PRESENT_SHIFT                 (31U)
28876 #define LCDIF_STAT_PRESENT(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
28877 /*! @} */
28878 
28879 /*! @name RGB_ADJUST - RGB Color Range Adjust */
28880 /*! @{ */
28881 
28882 #define LCDIF_RGB_ADJUST_PIXEL_MASK              (0xFFFFFFU)
28883 #define LCDIF_RGB_ADJUST_PIXEL_SHIFT             (0U)
28884 #define LCDIF_RGB_ADJUST_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_PIXEL_MASK)
28885 
28886 #define LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK       (0xC0000000U)
28887 #define LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT      (30U)
28888 /*! RGB_ADJ_MODE
28889  *  0b00..No Adjust
28890  *  0b01..Increment RGB
28891  *  0b10..Decrement RGB
28892  *  0b11..Multiply RGB
28893  */
28894 #define LCDIF_RGB_ADJUST_RGB_ADJ_MODE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK)
28895 /*! @} */
28896 
28897 /*! @name RGB_ADJUST_SET - RGB Color Range Adjust */
28898 /*! @{ */
28899 
28900 #define LCDIF_RGB_ADJUST_SET_PIXEL_MASK          (0xFFFFFFU)
28901 #define LCDIF_RGB_ADJUST_SET_PIXEL_SHIFT         (0U)
28902 #define LCDIF_RGB_ADJUST_SET_PIXEL(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_SET_PIXEL_MASK)
28903 
28904 #define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK   (0xC0000000U)
28905 #define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT  (30U)
28906 /*! RGB_ADJ_MODE
28907  *  0b00..No Adjust
28908  *  0b01..Increment RGB
28909  *  0b10..Decrement RGB
28910  *  0b11..Multiply RGB
28911  */
28912 #define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK)
28913 /*! @} */
28914 
28915 /*! @name RGB_ADJUST_CLR - RGB Color Range Adjust */
28916 /*! @{ */
28917 
28918 #define LCDIF_RGB_ADJUST_CLR_PIXEL_MASK          (0xFFFFFFU)
28919 #define LCDIF_RGB_ADJUST_CLR_PIXEL_SHIFT         (0U)
28920 #define LCDIF_RGB_ADJUST_CLR_PIXEL(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_CLR_PIXEL_MASK)
28921 
28922 #define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK   (0xC0000000U)
28923 #define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT  (30U)
28924 /*! RGB_ADJ_MODE
28925  *  0b00..No Adjust
28926  *  0b01..Increment RGB
28927  *  0b10..Decrement RGB
28928  *  0b11..Multiply RGB
28929  */
28930 #define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK)
28931 /*! @} */
28932 
28933 /*! @name RGB_ADJUST_TOG - RGB Color Range Adjust */
28934 /*! @{ */
28935 
28936 #define LCDIF_RGB_ADJUST_TOG_PIXEL_MASK          (0xFFFFFFU)
28937 #define LCDIF_RGB_ADJUST_TOG_PIXEL_SHIFT         (0U)
28938 #define LCDIF_RGB_ADJUST_TOG_PIXEL(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_TOG_PIXEL_MASK)
28939 
28940 #define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK   (0xC0000000U)
28941 #define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT  (30U)
28942 /*! RGB_ADJ_MODE
28943  *  0b00..No Adjust
28944  *  0b01..Increment RGB
28945  *  0b10..Decrement RGB
28946  *  0b11..Multiply RGB
28947  */
28948 #define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK)
28949 /*! @} */
28950 
28951 /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
28952 /*! @{ */
28953 
28954 #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK         (0xFFFU)
28955 #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT        (0U)
28956 #define LCDIF_PIGEONCTRL0_FD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
28957 
28958 #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK         (0xFFF0000U)
28959 #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT        (16U)
28960 #define LCDIF_PIGEONCTRL0_LD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
28961 /*! @} */
28962 
28963 /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
28964 /*! @{ */
28965 
28966 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK     (0xFFFU)
28967 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT    (0U)
28968 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
28969 
28970 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK     (0xFFF0000U)
28971 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT    (16U)
28972 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
28973 /*! @} */
28974 
28975 /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
28976 /*! @{ */
28977 
28978 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK     (0xFFFU)
28979 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT    (0U)
28980 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
28981 
28982 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK     (0xFFF0000U)
28983 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT    (16U)
28984 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
28985 /*! @} */
28986 
28987 /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
28988 /*! @{ */
28989 
28990 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK     (0xFFFU)
28991 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT    (0U)
28992 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
28993 
28994 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK     (0xFFF0000U)
28995 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT    (16U)
28996 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
28997 /*! @} */
28998 
28999 /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
29000 /*! @{ */
29001 
29002 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK  (0xFFFU)
29003 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
29004 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
29005 
29006 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK  (0xFFF0000U)
29007 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
29008 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
29009 /*! @} */
29010 
29011 /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
29012 /*! @{ */
29013 
29014 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
29015 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
29016 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
29017 
29018 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29019 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
29020 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
29021 /*! @} */
29022 
29023 /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
29024 /*! @{ */
29025 
29026 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
29027 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
29028 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
29029 
29030 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29031 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
29032 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
29033 /*! @} */
29034 
29035 /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
29036 /*! @{ */
29037 
29038 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
29039 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
29040 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
29041 
29042 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29043 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
29044 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
29045 /*! @} */
29046 
29047 /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
29048 /*! @{ */
29049 
29050 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK    (0x1U)
29051 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT   (0U)
29052 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
29053 
29054 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK   (0x2U)
29055 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT  (1U)
29056 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
29057 /*! @} */
29058 
29059 /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
29060 /*! @{ */
29061 
29062 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
29063 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
29064 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
29065 
29066 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
29067 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
29068 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
29069 /*! @} */
29070 
29071 /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
29072 /*! @{ */
29073 
29074 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
29075 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
29076 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
29077 
29078 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
29079 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
29080 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
29081 /*! @} */
29082 
29083 /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
29084 /*! @{ */
29085 
29086 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
29087 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
29088 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
29089 
29090 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
29091 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
29092 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
29093 /*! @} */
29094 
29095 /*! @name PIGEON_0 - Panel Interface Signal Generator Register */
29096 /*! @{ */
29097 
29098 #define LCDIF_PIGEON_0_EN_MASK                   (0x1U)
29099 #define LCDIF_PIGEON_0_EN_SHIFT                  (0U)
29100 #define LCDIF_PIGEON_0_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
29101 
29102 #define LCDIF_PIGEON_0_POL_MASK                  (0x2U)
29103 #define LCDIF_PIGEON_0_POL_SHIFT                 (1U)
29104 /*! POL
29105  *  0b0..Normal Signal (Active high)
29106  *  0b1..Inverted signal (Active low)
29107  */
29108 #define LCDIF_PIGEON_0_POL(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
29109 
29110 #define LCDIF_PIGEON_0_INC_SEL_MASK              (0xCU)
29111 #define LCDIF_PIGEON_0_INC_SEL_SHIFT             (2U)
29112 /*! INC_SEL
29113  *  0b00..pclk
29114  *  0b01..Line start pulse
29115  *  0b10..Frame start pulse
29116  *  0b11..Use another signal as tick event
29117  */
29118 #define LCDIF_PIGEON_0_INC_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
29119 
29120 #define LCDIF_PIGEON_0_OFFSET_MASK               (0xF0U)
29121 #define LCDIF_PIGEON_0_OFFSET_SHIFT              (4U)
29122 #define LCDIF_PIGEON_0_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
29123 
29124 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK         (0xF00U)
29125 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT        (8U)
29126 /*! MASK_CNT_SEL
29127  *  0b0000..pclk counter within one hscan state
29128  *  0b0001..pclk cycle within one hscan state
29129  *  0b0010..line counter within one vscan state
29130  *  0b0011..line cycle within one vscan state
29131  *  0b0100..frame counter
29132  *  0b0101..frame cycle
29133  *  0b0110..horizontal counter (pclk counter within one line )
29134  *  0b0111..vertical counter (line counter within one frame)
29135  */
29136 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
29137 
29138 #define LCDIF_PIGEON_0_MASK_CNT_MASK             (0xFFF000U)
29139 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT            (12U)
29140 #define LCDIF_PIGEON_0_MASK_CNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
29141 
29142 #define LCDIF_PIGEON_0_STATE_MASK_MASK           (0xFF000000U)
29143 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT          (24U)
29144 /*! STATE_MASK
29145  *  0b00000001..FRAME SYNC
29146  *  0b00000010..FRAME BEGIN
29147  *  0b00000100..FRAME DATA
29148  *  0b00001000..FRAME END
29149  *  0b00010000..LINE SYNC
29150  *  0b00100000..LINE BEGIN
29151  *  0b01000000..LINE DATA
29152  *  0b10000000..LINE END
29153  */
29154 #define LCDIF_PIGEON_0_STATE_MASK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
29155 /*! @} */
29156 
29157 /* The count of LCDIF_PIGEON_0 */
29158 #define LCDIF_PIGEON_0_COUNT                     (12U)
29159 
29160 /*! @name PIGEON_1 - Panel Interface Signal Generator Register */
29161 /*! @{ */
29162 
29163 #define LCDIF_PIGEON_1_SET_CNT_MASK              (0xFFFFU)
29164 #define LCDIF_PIGEON_1_SET_CNT_SHIFT             (0U)
29165 /*! SET_CNT
29166  *  0b0000000000000000..Start as active
29167  */
29168 #define LCDIF_PIGEON_1_SET_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
29169 
29170 #define LCDIF_PIGEON_1_CLR_CNT_MASK              (0xFFFF0000U)
29171 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT             (16U)
29172 /*! CLR_CNT
29173  *  0b0000000000000000..Keep active until mask off
29174  */
29175 #define LCDIF_PIGEON_1_CLR_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
29176 /*! @} */
29177 
29178 /* The count of LCDIF_PIGEON_1 */
29179 #define LCDIF_PIGEON_1_COUNT                     (12U)
29180 
29181 /*! @name PIGEON_2 - Panel Interface Signal Generator Register */
29182 /*! @{ */
29183 
29184 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK            (0xFU)
29185 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT           (0U)
29186 /*! SIG_LOGIC
29187  *  0b0000..No logic operation
29188  *  0b0001..sigout = sig_another AND this_sig
29189  *  0b0010..sigout = sig_another OR this_sig
29190  *  0b0011..mask = sig_another AND other_masks
29191  */
29192 #define LCDIF_PIGEON_2_SIG_LOGIC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
29193 
29194 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK          (0x1F0U)
29195 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT         (4U)
29196 /*! SIG_ANOTHER
29197  *  0b00000..Keep active until mask off
29198  */
29199 #define LCDIF_PIGEON_2_SIG_ANOTHER(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
29200 
29201 #define LCDIF_PIGEON_2_RSVD_MASK                 (0xFFFFFE00U)
29202 #define LCDIF_PIGEON_2_RSVD_SHIFT                (9U)
29203 #define LCDIF_PIGEON_2_RSVD(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
29204 /*! @} */
29205 
29206 /* The count of LCDIF_PIGEON_2 */
29207 #define LCDIF_PIGEON_2_COUNT                     (12U)
29208 
29209 /*! @name LUT_CTRL - Look Up Table Control Register */
29210 /*! @{ */
29211 
29212 #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK           (0x1U)
29213 #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT          (0U)
29214 #define LCDIF_LUT_CTRL_LUT_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
29215 /*! @} */
29216 
29217 /*! @name LUT0_ADDR - Lookup Table 0 Index Register */
29218 /*! @{ */
29219 
29220 #define LCDIF_LUT0_ADDR_ADDR_MASK                (0xFFU)
29221 #define LCDIF_LUT0_ADDR_ADDR_SHIFT               (0U)
29222 #define LCDIF_LUT0_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
29223 /*! @} */
29224 
29225 /*! @name LUT0_DATA - Lookup Table 0 Data Register */
29226 /*! @{ */
29227 
29228 #define LCDIF_LUT0_DATA_DATA_MASK                (0xFFFFFFFFU)
29229 #define LCDIF_LUT0_DATA_DATA_SHIFT               (0U)
29230 #define LCDIF_LUT0_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
29231 /*! @} */
29232 
29233 /*! @name LUT1_ADDR - Lookup Table 1 Index Register */
29234 /*! @{ */
29235 
29236 #define LCDIF_LUT1_ADDR_ADDR_MASK                (0xFFU)
29237 #define LCDIF_LUT1_ADDR_ADDR_SHIFT               (0U)
29238 #define LCDIF_LUT1_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
29239 /*! @} */
29240 
29241 /*! @name LUT1_DATA - Lookup Table 1 Data Register */
29242 /*! @{ */
29243 
29244 #define LCDIF_LUT1_DATA_DATA_MASK                (0xFFFFFFFFU)
29245 #define LCDIF_LUT1_DATA_DATA_SHIFT               (0U)
29246 #define LCDIF_LUT1_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
29247 /*! @} */
29248 
29249 
29250 /*!
29251  * @}
29252  */ /* end of group LCDIF_Register_Masks */
29253 
29254 
29255 /* LCDIF - Peripheral instance base addresses */
29256 /** Peripheral LCDIF base address */
29257 #define LCDIF_BASE                               (0x402B8000u)
29258 /** Peripheral LCDIF base pointer */
29259 #define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
29260 /** Array initializer of LCDIF peripheral base addresses */
29261 #define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
29262 /** Array initializer of LCDIF peripheral base pointers */
29263 #define LCDIF_BASE_PTRS                          { LCDIF }
29264 /** Interrupt vectors for the LCDIF peripheral type */
29265 #define LCDIF_IRQ0_IRQS                          { LCDIF_IRQn }
29266 
29267 /*!
29268  * @}
29269  */ /* end of group LCDIF_Peripheral_Access_Layer */
29270 
29271 
29272 /* ----------------------------------------------------------------------------
29273    -- LPI2C Peripheral Access Layer
29274    ---------------------------------------------------------------------------- */
29275 
29276 /*!
29277  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
29278  * @{
29279  */
29280 
29281 /** LPI2C - Register Layout Typedef */
29282 typedef struct {
29283   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
29284   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
29285        uint8_t RESERVED_0[8];
29286   __IO uint32_t MCR;                               /**< Master Control Register, offset: 0x10 */
29287   __IO uint32_t MSR;                               /**< Master Status Register, offset: 0x14 */
29288   __IO uint32_t MIER;                              /**< Master Interrupt Enable Register, offset: 0x18 */
29289   __IO uint32_t MDER;                              /**< Master DMA Enable Register, offset: 0x1C */
29290   __IO uint32_t MCFGR0;                            /**< Master Configuration Register 0, offset: 0x20 */
29291   __IO uint32_t MCFGR1;                            /**< Master Configuration Register 1, offset: 0x24 */
29292   __IO uint32_t MCFGR2;                            /**< Master Configuration Register 2, offset: 0x28 */
29293   __IO uint32_t MCFGR3;                            /**< Master Configuration Register 3, offset: 0x2C */
29294        uint8_t RESERVED_1[16];
29295   __IO uint32_t MDMR;                              /**< Master Data Match Register, offset: 0x40 */
29296        uint8_t RESERVED_2[4];
29297   __IO uint32_t MCCR0;                             /**< Master Clock Configuration Register 0, offset: 0x48 */
29298        uint8_t RESERVED_3[4];
29299   __IO uint32_t MCCR1;                             /**< Master Clock Configuration Register 1, offset: 0x50 */
29300        uint8_t RESERVED_4[4];
29301   __IO uint32_t MFCR;                              /**< Master FIFO Control Register, offset: 0x58 */
29302   __I  uint32_t MFSR;                              /**< Master FIFO Status Register, offset: 0x5C */
29303   __O  uint32_t MTDR;                              /**< Master Transmit Data Register, offset: 0x60 */
29304        uint8_t RESERVED_5[12];
29305   __I  uint32_t MRDR;                              /**< Master Receive Data Register, offset: 0x70 */
29306        uint8_t RESERVED_6[156];
29307   __IO uint32_t SCR;                               /**< Slave Control Register, offset: 0x110 */
29308   __IO uint32_t SSR;                               /**< Slave Status Register, offset: 0x114 */
29309   __IO uint32_t SIER;                              /**< Slave Interrupt Enable Register, offset: 0x118 */
29310   __IO uint32_t SDER;                              /**< Slave DMA Enable Register, offset: 0x11C */
29311        uint8_t RESERVED_7[4];
29312   __IO uint32_t SCFGR1;                            /**< Slave Configuration Register 1, offset: 0x124 */
29313   __IO uint32_t SCFGR2;                            /**< Slave Configuration Register 2, offset: 0x128 */
29314        uint8_t RESERVED_8[20];
29315   __IO uint32_t SAMR;                              /**< Slave Address Match Register, offset: 0x140 */
29316        uint8_t RESERVED_9[12];
29317   __I  uint32_t SASR;                              /**< Slave Address Status Register, offset: 0x150 */
29318   __IO uint32_t STAR;                              /**< Slave Transmit ACK Register, offset: 0x154 */
29319        uint8_t RESERVED_10[8];
29320   __O  uint32_t STDR;                              /**< Slave Transmit Data Register, offset: 0x160 */
29321        uint8_t RESERVED_11[12];
29322   __I  uint32_t SRDR;                              /**< Slave Receive Data Register, offset: 0x170 */
29323 } LPI2C_Type;
29324 
29325 /* ----------------------------------------------------------------------------
29326    -- LPI2C Register Masks
29327    ---------------------------------------------------------------------------- */
29328 
29329 /*!
29330  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
29331  * @{
29332  */
29333 
29334 /*! @name VERID - Version ID Register */
29335 /*! @{ */
29336 
29337 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
29338 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
29339 /*! FEATURE - Feature Specification Number
29340  *  0b0000000000000010..Master only, with standard feature set
29341  *  0b0000000000000011..Master and slave, with standard feature set
29342  */
29343 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
29344 
29345 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
29346 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
29347 /*! MINOR - Minor Version Number
29348  */
29349 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
29350 
29351 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
29352 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
29353 /*! MAJOR - Major Version Number
29354  */
29355 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
29356 /*! @} */
29357 
29358 /*! @name PARAM - Parameter Register */
29359 /*! @{ */
29360 
29361 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
29362 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
29363 /*! MTXFIFO - Master Transmit FIFO Size
29364  */
29365 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
29366 
29367 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
29368 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
29369 /*! MRXFIFO - Master Receive FIFO Size
29370  */
29371 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
29372 /*! @} */
29373 
29374 /*! @name MCR - Master Control Register */
29375 /*! @{ */
29376 
29377 #define LPI2C_MCR_MEN_MASK                       (0x1U)
29378 #define LPI2C_MCR_MEN_SHIFT                      (0U)
29379 /*! MEN - Master Enable
29380  *  0b0..Master logic is disabled
29381  *  0b1..Master logic is enabled
29382  */
29383 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
29384 
29385 #define LPI2C_MCR_RST_MASK                       (0x2U)
29386 #define LPI2C_MCR_RST_SHIFT                      (1U)
29387 /*! RST - Software Reset
29388  *  0b0..Master logic is not reset
29389  *  0b1..Master logic is reset
29390  */
29391 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
29392 
29393 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
29394 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
29395 /*! DOZEN - Doze mode enable
29396  *  0b0..Master is enabled in Doze mode
29397  *  0b1..Master is disabled in Doze mode
29398  */
29399 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
29400 
29401 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
29402 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
29403 /*! DBGEN - Debug Enable
29404  *  0b0..Master is disabled in debug mode
29405  *  0b1..Master is enabled in debug mode
29406  */
29407 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
29408 
29409 #define LPI2C_MCR_RTF_MASK                       (0x100U)
29410 #define LPI2C_MCR_RTF_SHIFT                      (8U)
29411 /*! RTF - Reset Transmit FIFO
29412  *  0b0..No effect
29413  *  0b1..Transmit FIFO is reset
29414  */
29415 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
29416 
29417 #define LPI2C_MCR_RRF_MASK                       (0x200U)
29418 #define LPI2C_MCR_RRF_SHIFT                      (9U)
29419 /*! RRF - Reset Receive FIFO
29420  *  0b0..No effect
29421  *  0b1..Receive FIFO is reset
29422  */
29423 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
29424 /*! @} */
29425 
29426 /*! @name MSR - Master Status Register */
29427 /*! @{ */
29428 
29429 #define LPI2C_MSR_TDF_MASK                       (0x1U)
29430 #define LPI2C_MSR_TDF_SHIFT                      (0U)
29431 /*! TDF - Transmit Data Flag
29432  *  0b0..Transmit data is not requested
29433  *  0b1..Transmit data is requested
29434  */
29435 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
29436 
29437 #define LPI2C_MSR_RDF_MASK                       (0x2U)
29438 #define LPI2C_MSR_RDF_SHIFT                      (1U)
29439 /*! RDF - Receive Data Flag
29440  *  0b0..Receive Data is not ready
29441  *  0b1..Receive data is ready
29442  */
29443 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
29444 
29445 #define LPI2C_MSR_EPF_MASK                       (0x100U)
29446 #define LPI2C_MSR_EPF_SHIFT                      (8U)
29447 /*! EPF - End Packet Flag
29448  *  0b0..Master has not generated a STOP or Repeated START condition
29449  *  0b1..Master has generated a STOP or Repeated START condition
29450  */
29451 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
29452 
29453 #define LPI2C_MSR_SDF_MASK                       (0x200U)
29454 #define LPI2C_MSR_SDF_SHIFT                      (9U)
29455 /*! SDF - STOP Detect Flag
29456  *  0b0..Master has not generated a STOP condition
29457  *  0b1..Master has generated a STOP condition
29458  */
29459 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
29460 
29461 #define LPI2C_MSR_NDF_MASK                       (0x400U)
29462 #define LPI2C_MSR_NDF_SHIFT                      (10U)
29463 /*! NDF - NACK Detect Flag
29464  *  0b0..Unexpected NACK was not detected
29465  *  0b1..Unexpected NACK was detected
29466  */
29467 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
29468 
29469 #define LPI2C_MSR_ALF_MASK                       (0x800U)
29470 #define LPI2C_MSR_ALF_SHIFT                      (11U)
29471 /*! ALF - Arbitration Lost Flag
29472  *  0b0..Master has not lost arbitration
29473  *  0b1..Master has lost arbitration
29474  */
29475 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
29476 
29477 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
29478 #define LPI2C_MSR_FEF_SHIFT                      (12U)
29479 /*! FEF - FIFO Error Flag
29480  *  0b0..No error
29481  *  0b1..Master sending or receiving data without a START condition
29482  */
29483 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
29484 
29485 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
29486 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
29487 /*! PLTF - Pin Low Timeout Flag
29488  *  0b0..Pin low timeout has not occurred or is disabled
29489  *  0b1..Pin low timeout has occurred
29490  */
29491 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
29492 
29493 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
29494 #define LPI2C_MSR_DMF_SHIFT                      (14U)
29495 /*! DMF - Data Match Flag
29496  *  0b0..Have not received matching data
29497  *  0b1..Have received matching data
29498  */
29499 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
29500 
29501 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
29502 #define LPI2C_MSR_MBF_SHIFT                      (24U)
29503 /*! MBF - Master Busy Flag
29504  *  0b0..I2C Master is idle
29505  *  0b1..I2C Master is busy
29506  */
29507 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
29508 
29509 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
29510 #define LPI2C_MSR_BBF_SHIFT                      (25U)
29511 /*! BBF - Bus Busy Flag
29512  *  0b0..I2C Bus is idle
29513  *  0b1..I2C Bus is busy
29514  */
29515 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
29516 /*! @} */
29517 
29518 /*! @name MIER - Master Interrupt Enable Register */
29519 /*! @{ */
29520 
29521 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
29522 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
29523 /*! TDIE - Transmit Data Interrupt Enable
29524  *  0b0..Disabled
29525  *  0b1..Enabled
29526  */
29527 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
29528 
29529 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
29530 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
29531 /*! RDIE - Receive Data Interrupt Enable
29532  *  0b0..Disabled
29533  *  0b1..Enabled
29534  */
29535 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
29536 
29537 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
29538 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
29539 /*! EPIE - End Packet Interrupt Enable
29540  *  0b0..Disabled
29541  *  0b1..Enabled
29542  */
29543 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
29544 
29545 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
29546 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
29547 /*! SDIE - STOP Detect Interrupt Enable
29548  *  0b0..Disabled
29549  *  0b1..Enabled
29550  */
29551 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
29552 
29553 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
29554 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
29555 /*! NDIE - NACK Detect Interrupt Enable
29556  *  0b0..Disabled
29557  *  0b1..Enabled
29558  */
29559 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
29560 
29561 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
29562 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
29563 /*! ALIE - Arbitration Lost Interrupt Enable
29564  *  0b0..Disabled
29565  *  0b1..Enabled
29566  */
29567 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
29568 
29569 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
29570 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
29571 /*! FEIE - FIFO Error Interrupt Enable
29572  *  0b0..Enabled
29573  *  0b1..Disabled
29574  */
29575 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
29576 
29577 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
29578 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
29579 /*! PLTIE - Pin Low Timeout Interrupt Enable
29580  *  0b0..Disabled
29581  *  0b1..Enabled
29582  */
29583 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
29584 
29585 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
29586 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
29587 /*! DMIE - Data Match Interrupt Enable
29588  *  0b0..Disabled
29589  *  0b1..Enabled
29590  */
29591 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
29592 /*! @} */
29593 
29594 /*! @name MDER - Master DMA Enable Register */
29595 /*! @{ */
29596 
29597 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
29598 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
29599 /*! TDDE - Transmit Data DMA Enable
29600  *  0b0..DMA request is disabled
29601  *  0b1..DMA request is enabled
29602  */
29603 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
29604 
29605 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
29606 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
29607 /*! RDDE - Receive Data DMA Enable
29608  *  0b0..DMA request is disabled
29609  *  0b1..DMA request is enabled
29610  */
29611 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
29612 /*! @} */
29613 
29614 /*! @name MCFGR0 - Master Configuration Register 0 */
29615 /*! @{ */
29616 
29617 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
29618 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
29619 /*! HREN - Host Request Enable
29620  *  0b0..Host request input is disabled
29621  *  0b1..Host request input is enabled
29622  */
29623 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
29624 
29625 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
29626 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
29627 /*! HRPOL - Host Request Polarity
29628  *  0b0..Active low
29629  *  0b1..Active high
29630  */
29631 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
29632 
29633 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
29634 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
29635 /*! HRSEL - Host Request Select
29636  *  0b0..Host request input is pin HREQ
29637  *  0b1..Host request input is input trigger
29638  */
29639 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
29640 
29641 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
29642 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
29643 /*! CIRFIFO - Circular FIFO Enable
29644  *  0b0..Circular FIFO is disabled
29645  *  0b1..Circular FIFO is enabled
29646  */
29647 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
29648 
29649 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
29650 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
29651 /*! RDMO - Receive Data Match Only
29652  *  0b0..Received data is stored in the receive FIFO
29653  *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
29654  */
29655 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
29656 /*! @} */
29657 
29658 /*! @name MCFGR1 - Master Configuration Register 1 */
29659 /*! @{ */
29660 
29661 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
29662 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
29663 /*! PRESCALE - Prescaler
29664  *  0b000..Divide by 1
29665  *  0b001..Divide by 2
29666  *  0b010..Divide by 4
29667  *  0b011..Divide by 8
29668  *  0b100..Divide by 16
29669  *  0b101..Divide by 32
29670  *  0b110..Divide by 64
29671  *  0b111..Divide by 128
29672  */
29673 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
29674 
29675 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
29676 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
29677 /*! AUTOSTOP - Automatic STOP Generation
29678  *  0b0..No effect
29679  *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
29680  */
29681 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
29682 
29683 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
29684 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
29685 /*! IGNACK - IGNACK
29686  *  0b0..LPI2C Master will receive ACK and NACK normally
29687  *  0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
29688  */
29689 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
29690 
29691 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
29692 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
29693 /*! TIMECFG - Timeout Configuration
29694  *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
29695  *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
29696  */
29697 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
29698 
29699 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
29700 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
29701 /*! MATCFG - Match Configuration
29702  *  0b000..Match is disabled
29703  *  0b001..Reserved
29704  *  0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
29705  *  0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
29706  *  0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
29707  *  0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
29708  *  0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
29709  *  0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
29710  */
29711 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
29712 
29713 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
29714 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
29715 /*! PINCFG - Pin Configuration
29716  *  0b000..2-pin open drain mode
29717  *  0b001..2-pin output only mode (ultra-fast mode)
29718  *  0b010..2-pin push-pull mode
29719  *  0b011..4-pin push-pull mode
29720  *  0b100..2-pin open drain mode with separate LPI2C slave
29721  *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
29722  *  0b110..2-pin push-pull mode with separate LPI2C slave
29723  *  0b111..4-pin push-pull mode (inverted outputs)
29724  */
29725 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
29726 /*! @} */
29727 
29728 /*! @name MCFGR2 - Master Configuration Register 2 */
29729 /*! @{ */
29730 
29731 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
29732 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
29733 /*! BUSIDLE - Bus Idle Timeout
29734  */
29735 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
29736 
29737 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
29738 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
29739 /*! FILTSCL - Glitch Filter SCL
29740  */
29741 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
29742 
29743 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
29744 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
29745 /*! FILTSDA - Glitch Filter SDA
29746  */
29747 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
29748 /*! @} */
29749 
29750 /*! @name MCFGR3 - Master Configuration Register 3 */
29751 /*! @{ */
29752 
29753 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
29754 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
29755 /*! PINLOW - Pin Low Timeout
29756  */
29757 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
29758 /*! @} */
29759 
29760 /*! @name MDMR - Master Data Match Register */
29761 /*! @{ */
29762 
29763 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
29764 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
29765 /*! MATCH0 - Match 0 Value
29766  */
29767 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
29768 
29769 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
29770 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
29771 /*! MATCH1 - Match 1 Value
29772  */
29773 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
29774 /*! @} */
29775 
29776 /*! @name MCCR0 - Master Clock Configuration Register 0 */
29777 /*! @{ */
29778 
29779 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
29780 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
29781 /*! CLKLO - Clock Low Period
29782  */
29783 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
29784 
29785 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
29786 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
29787 /*! CLKHI - Clock High Period
29788  */
29789 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
29790 
29791 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
29792 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
29793 /*! SETHOLD - Setup Hold Delay
29794  */
29795 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
29796 
29797 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
29798 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
29799 /*! DATAVD - Data Valid Delay
29800  */
29801 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
29802 /*! @} */
29803 
29804 /*! @name MCCR1 - Master Clock Configuration Register 1 */
29805 /*! @{ */
29806 
29807 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
29808 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
29809 /*! CLKLO - Clock Low Period
29810  */
29811 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
29812 
29813 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
29814 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
29815 /*! CLKHI - Clock High Period
29816  */
29817 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
29818 
29819 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
29820 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
29821 /*! SETHOLD - Setup Hold Delay
29822  */
29823 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
29824 
29825 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
29826 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
29827 /*! DATAVD - Data Valid Delay
29828  */
29829 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
29830 /*! @} */
29831 
29832 /*! @name MFCR - Master FIFO Control Register */
29833 /*! @{ */
29834 
29835 #define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
29836 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
29837 /*! TXWATER - Transmit FIFO Watermark
29838  */
29839 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
29840 
29841 #define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
29842 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
29843 /*! RXWATER - Receive FIFO Watermark
29844  */
29845 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
29846 /*! @} */
29847 
29848 /*! @name MFSR - Master FIFO Status Register */
29849 /*! @{ */
29850 
29851 #define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
29852 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
29853 /*! TXCOUNT - Transmit FIFO Count
29854  */
29855 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
29856 
29857 #define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
29858 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
29859 /*! RXCOUNT - Receive FIFO Count
29860  */
29861 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
29862 /*! @} */
29863 
29864 /*! @name MTDR - Master Transmit Data Register */
29865 /*! @{ */
29866 
29867 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
29868 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
29869 /*! DATA - Transmit Data
29870  */
29871 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
29872 
29873 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
29874 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
29875 /*! CMD - Command Data
29876  *  0b000..Transmit DATA[7:0]
29877  *  0b001..Receive (DATA[7:0] + 1) bytes
29878  *  0b010..Generate STOP condition
29879  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
29880  *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
29881  *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
29882  *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
29883  *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
29884  */
29885 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
29886 /*! @} */
29887 
29888 /*! @name MRDR - Master Receive Data Register */
29889 /*! @{ */
29890 
29891 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
29892 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
29893 /*! DATA - Receive Data
29894  */
29895 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
29896 
29897 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
29898 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
29899 /*! RXEMPTY - RX Empty
29900  *  0b0..Receive FIFO is not empty
29901  *  0b1..Receive FIFO is empty
29902  */
29903 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
29904 /*! @} */
29905 
29906 /*! @name SCR - Slave Control Register */
29907 /*! @{ */
29908 
29909 #define LPI2C_SCR_SEN_MASK                       (0x1U)
29910 #define LPI2C_SCR_SEN_SHIFT                      (0U)
29911 /*! SEN - Slave Enable
29912  *  0b0..I2C Slave mode is disabled
29913  *  0b1..I2C Slave mode is enabled
29914  */
29915 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
29916 
29917 #define LPI2C_SCR_RST_MASK                       (0x2U)
29918 #define LPI2C_SCR_RST_SHIFT                      (1U)
29919 /*! RST - Software Reset
29920  *  0b0..Slave mode logic is not reset
29921  *  0b1..Slave mode logic is reset
29922  */
29923 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
29924 
29925 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
29926 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
29927 /*! FILTEN - Filter Enable
29928  *  0b0..Disable digital filter and output delay counter for slave mode
29929  *  0b1..Enable digital filter and output delay counter for slave mode
29930  */
29931 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
29932 
29933 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
29934 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
29935 /*! FILTDZ - Filter Doze Enable
29936  *  0b0..Filter remains enabled in Doze mode
29937  *  0b1..Filter is disabled in Doze mode
29938  */
29939 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
29940 
29941 #define LPI2C_SCR_RTF_MASK                       (0x100U)
29942 #define LPI2C_SCR_RTF_SHIFT                      (8U)
29943 /*! RTF - Reset Transmit FIFO
29944  *  0b0..No effect
29945  *  0b1..Transmit Data Register is now empty
29946  */
29947 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
29948 
29949 #define LPI2C_SCR_RRF_MASK                       (0x200U)
29950 #define LPI2C_SCR_RRF_SHIFT                      (9U)
29951 /*! RRF - Reset Receive FIFO
29952  *  0b0..No effect
29953  *  0b1..Receive Data Register is now empty
29954  */
29955 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
29956 /*! @} */
29957 
29958 /*! @name SSR - Slave Status Register */
29959 /*! @{ */
29960 
29961 #define LPI2C_SSR_TDF_MASK                       (0x1U)
29962 #define LPI2C_SSR_TDF_SHIFT                      (0U)
29963 /*! TDF - Transmit Data Flag
29964  *  0b0..Transmit data not requested
29965  *  0b1..Transmit data is requested
29966  */
29967 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
29968 
29969 #define LPI2C_SSR_RDF_MASK                       (0x2U)
29970 #define LPI2C_SSR_RDF_SHIFT                      (1U)
29971 /*! RDF - Receive Data Flag
29972  *  0b0..Receive data is not ready
29973  *  0b1..Receive data is ready
29974  */
29975 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
29976 
29977 #define LPI2C_SSR_AVF_MASK                       (0x4U)
29978 #define LPI2C_SSR_AVF_SHIFT                      (2U)
29979 /*! AVF - Address Valid Flag
29980  *  0b0..Address Status Register is not valid
29981  *  0b1..Address Status Register is valid
29982  */
29983 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
29984 
29985 #define LPI2C_SSR_TAF_MASK                       (0x8U)
29986 #define LPI2C_SSR_TAF_SHIFT                      (3U)
29987 /*! TAF - Transmit ACK Flag
29988  *  0b0..Transmit ACK/NACK is not required
29989  *  0b1..Transmit ACK/NACK is required
29990  */
29991 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
29992 
29993 #define LPI2C_SSR_RSF_MASK                       (0x100U)
29994 #define LPI2C_SSR_RSF_SHIFT                      (8U)
29995 /*! RSF - Repeated Start Flag
29996  *  0b0..Slave has not detected a Repeated START condition
29997  *  0b1..Slave has detected a Repeated START condition
29998  */
29999 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
30000 
30001 #define LPI2C_SSR_SDF_MASK                       (0x200U)
30002 #define LPI2C_SSR_SDF_SHIFT                      (9U)
30003 /*! SDF - STOP Detect Flag
30004  *  0b0..Slave has not detected a STOP condition
30005  *  0b1..Slave has detected a STOP condition
30006  */
30007 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
30008 
30009 #define LPI2C_SSR_BEF_MASK                       (0x400U)
30010 #define LPI2C_SSR_BEF_SHIFT                      (10U)
30011 /*! BEF - Bit Error Flag
30012  *  0b0..Slave has not detected a bit error
30013  *  0b1..Slave has detected a bit error
30014  */
30015 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
30016 
30017 #define LPI2C_SSR_FEF_MASK                       (0x800U)
30018 #define LPI2C_SSR_FEF_SHIFT                      (11U)
30019 /*! FEF - FIFO Error Flag
30020  *  0b0..FIFO underflow or overflow was not detected
30021  *  0b1..FIFO underflow or overflow was detected
30022  */
30023 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
30024 
30025 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
30026 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
30027 /*! AM0F - Address Match 0 Flag
30028  *  0b0..Have not received an ADDR0 matching address
30029  *  0b1..Have received an ADDR0 matching address
30030  */
30031 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
30032 
30033 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
30034 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
30035 /*! AM1F - Address Match 1 Flag
30036  *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
30037  *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
30038  */
30039 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
30040 
30041 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
30042 #define LPI2C_SSR_GCF_SHIFT                      (14U)
30043 /*! GCF - General Call Flag
30044  *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
30045  *  0b1..Slave has detected the General Call Address
30046  */
30047 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
30048 
30049 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
30050 #define LPI2C_SSR_SARF_SHIFT                     (15U)
30051 /*! SARF - SMBus Alert Response Flag
30052  *  0b0..SMBus Alert Response is disabled or not detected
30053  *  0b1..SMBus Alert Response is enabled and detected
30054  */
30055 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
30056 
30057 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
30058 #define LPI2C_SSR_SBF_SHIFT                      (24U)
30059 /*! SBF - Slave Busy Flag
30060  *  0b0..I2C Slave is idle
30061  *  0b1..I2C Slave is busy
30062  */
30063 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
30064 
30065 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
30066 #define LPI2C_SSR_BBF_SHIFT                      (25U)
30067 /*! BBF - Bus Busy Flag
30068  *  0b0..I2C Bus is idle
30069  *  0b1..I2C Bus is busy
30070  */
30071 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
30072 /*! @} */
30073 
30074 /*! @name SIER - Slave Interrupt Enable Register */
30075 /*! @{ */
30076 
30077 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
30078 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
30079 /*! TDIE - Transmit Data Interrupt Enable
30080  *  0b0..Disabled
30081  *  0b1..Enabled
30082  */
30083 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
30084 
30085 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
30086 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
30087 /*! RDIE - Receive Data Interrupt Enable
30088  *  0b0..Disabled
30089  *  0b1..Enabled
30090  */
30091 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
30092 
30093 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
30094 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
30095 /*! AVIE - Address Valid Interrupt Enable
30096  *  0b0..Disabled
30097  *  0b1..Enabled
30098  */
30099 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
30100 
30101 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
30102 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
30103 /*! TAIE - Transmit ACK Interrupt Enable
30104  *  0b0..Disabled
30105  *  0b1..Enabled
30106  */
30107 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
30108 
30109 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
30110 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
30111 /*! RSIE - Repeated Start Interrupt Enable
30112  *  0b0..Disabled
30113  *  0b1..Enabled
30114  */
30115 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
30116 
30117 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
30118 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
30119 /*! SDIE - STOP Detect Interrupt Enable
30120  *  0b0..Disabled
30121  *  0b1..Enabled
30122  */
30123 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
30124 
30125 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
30126 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
30127 /*! BEIE - Bit Error Interrupt Enable
30128  *  0b0..Disabled
30129  *  0b1..Enabled
30130  */
30131 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
30132 
30133 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
30134 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
30135 /*! FEIE - FIFO Error Interrupt Enable
30136  *  0b0..Disabled
30137  *  0b1..Enabled
30138  */
30139 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
30140 
30141 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
30142 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
30143 /*! AM0IE - Address Match 0 Interrupt Enable
30144  *  0b0..Enabled
30145  *  0b1..Disabled
30146  */
30147 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
30148 
30149 #define LPI2C_SIER_AM1F_MASK                     (0x2000U)
30150 #define LPI2C_SIER_AM1F_SHIFT                    (13U)
30151 /*! AM1F - Address Match 1 Interrupt Enable
30152  *  0b0..Disabled
30153  *  0b1..Enabled
30154  */
30155 #define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
30156 
30157 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
30158 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
30159 /*! GCIE - General Call Interrupt Enable
30160  *  0b0..Disabled
30161  *  0b1..Enabled
30162  */
30163 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
30164 
30165 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
30166 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
30167 /*! SARIE - SMBus Alert Response Interrupt Enable
30168  *  0b0..Disabled
30169  *  0b1..Enabled
30170  */
30171 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
30172 /*! @} */
30173 
30174 /*! @name SDER - Slave DMA Enable Register */
30175 /*! @{ */
30176 
30177 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
30178 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
30179 /*! TDDE - Transmit Data DMA Enable
30180  *  0b0..DMA request is disabled
30181  *  0b1..DMA request is enabled
30182  */
30183 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
30184 
30185 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
30186 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
30187 /*! RDDE - Receive Data DMA Enable
30188  *  0b0..DMA request is disabled
30189  *  0b1..DMA request is enabled
30190  */
30191 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
30192 
30193 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
30194 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
30195 /*! AVDE - Address Valid DMA Enable
30196  *  0b0..DMA request is disabled
30197  *  0b1..DMA request is enabled
30198  */
30199 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
30200 /*! @} */
30201 
30202 /*! @name SCFGR1 - Slave Configuration Register 1 */
30203 /*! @{ */
30204 
30205 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
30206 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
30207 /*! ADRSTALL - Address SCL Stall
30208  *  0b0..Clock stretching is disabled
30209  *  0b1..Clock stretching is enabled
30210  */
30211 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
30212 
30213 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
30214 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
30215 /*! RXSTALL - RX SCL Stall
30216  *  0b0..Clock stretching is disabled
30217  *  0b1..Clock stretching is enabled
30218  */
30219 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
30220 
30221 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
30222 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
30223 /*! TXDSTALL - TX Data SCL Stall
30224  *  0b0..Clock stretching is disabled
30225  *  0b1..Clock stretching is enabled
30226  */
30227 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
30228 
30229 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
30230 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
30231 /*! ACKSTALL - ACK SCL Stall
30232  *  0b0..Clock stretching is disabled
30233  *  0b1..Clock stretching is enabled
30234  */
30235 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
30236 
30237 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
30238 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
30239 /*! GCEN - General Call Enable
30240  *  0b0..General Call address is disabled
30241  *  0b1..General Call address is enabled
30242  */
30243 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
30244 
30245 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
30246 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
30247 /*! SAEN - SMBus Alert Enable
30248  *  0b0..Disables match on SMBus Alert
30249  *  0b1..Enables match on SMBus Alert
30250  */
30251 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
30252 
30253 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
30254 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
30255 /*! TXCFG - Transmit Flag Configuration
30256  *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
30257  *  0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
30258  */
30259 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
30260 
30261 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
30262 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
30263 /*! RXCFG - Receive Data Configuration
30264  *  0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
30265  *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address
30266  *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid
30267  *       flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
30268  */
30269 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
30270 
30271 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
30272 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
30273 /*! IGNACK - Ignore NACK
30274  *  0b0..Slave will end transfer when NACK is detected
30275  *  0b1..Slave will not end transfer when NACK detected
30276  */
30277 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
30278 
30279 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
30280 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
30281 /*! HSMEN - High Speed Mode Enable
30282  *  0b0..Disables detection of HS-mode master code
30283  *  0b1..Enables detection of HS-mode master code
30284  */
30285 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
30286 
30287 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
30288 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
30289 /*! ADDRCFG - Address Configuration
30290  *  0b000..Address match 0 (7-bit)
30291  *  0b001..Address match 0 (10-bit)
30292  *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
30293  *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
30294  *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
30295  *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
30296  *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
30297  *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
30298  */
30299 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
30300 /*! @} */
30301 
30302 /*! @name SCFGR2 - Slave Configuration Register 2 */
30303 /*! @{ */
30304 
30305 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
30306 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
30307 /*! CLKHOLD - Clock Hold Time
30308  */
30309 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
30310 
30311 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
30312 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
30313 /*! DATAVD - Data Valid Delay
30314  */
30315 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
30316 
30317 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
30318 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
30319 /*! FILTSCL - Glitch Filter SCL
30320  */
30321 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
30322 
30323 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
30324 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
30325 /*! FILTSDA - Glitch Filter SDA
30326  */
30327 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
30328 /*! @} */
30329 
30330 /*! @name SAMR - Slave Address Match Register */
30331 /*! @{ */
30332 
30333 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
30334 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
30335 /*! ADDR0 - Address 0 Value
30336  */
30337 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
30338 
30339 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
30340 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
30341 /*! ADDR1 - Address 1 Value
30342  */
30343 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
30344 /*! @} */
30345 
30346 /*! @name SASR - Slave Address Status Register */
30347 /*! @{ */
30348 
30349 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
30350 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
30351 /*! RADDR - Received Address
30352  */
30353 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
30354 
30355 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
30356 #define LPI2C_SASR_ANV_SHIFT                     (14U)
30357 /*! ANV - Address Not Valid
30358  *  0b0..Received Address (RADDR) is valid
30359  *  0b1..Received Address (RADDR) is not valid
30360  */
30361 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
30362 /*! @} */
30363 
30364 /*! @name STAR - Slave Transmit ACK Register */
30365 /*! @{ */
30366 
30367 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
30368 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
30369 /*! TXNACK - Transmit NACK
30370  *  0b0..Write a Transmit ACK for each received word
30371  *  0b1..Write a Transmit NACK for each received word
30372  */
30373 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
30374 /*! @} */
30375 
30376 /*! @name STDR - Slave Transmit Data Register */
30377 /*! @{ */
30378 
30379 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
30380 #define LPI2C_STDR_DATA_SHIFT                    (0U)
30381 /*! DATA - Transmit Data
30382  */
30383 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
30384 /*! @} */
30385 
30386 /*! @name SRDR - Slave Receive Data Register */
30387 /*! @{ */
30388 
30389 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
30390 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
30391 /*! DATA - Receive Data
30392  */
30393 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
30394 
30395 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
30396 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
30397 /*! RXEMPTY - RX Empty
30398  *  0b0..The Receive Data Register is not empty
30399  *  0b1..The Receive Data Register is empty
30400  */
30401 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
30402 
30403 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
30404 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
30405 /*! SOF - Start Of Frame
30406  *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
30407  *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
30408  */
30409 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
30410 /*! @} */
30411 
30412 
30413 /*!
30414  * @}
30415  */ /* end of group LPI2C_Register_Masks */
30416 
30417 
30418 /* LPI2C - Peripheral instance base addresses */
30419 /** Peripheral LPI2C1 base address */
30420 #define LPI2C1_BASE                              (0x403F0000u)
30421 /** Peripheral LPI2C1 base pointer */
30422 #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
30423 /** Peripheral LPI2C2 base address */
30424 #define LPI2C2_BASE                              (0x403F4000u)
30425 /** Peripheral LPI2C2 base pointer */
30426 #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
30427 /** Peripheral LPI2C3 base address */
30428 #define LPI2C3_BASE                              (0x403F8000u)
30429 /** Peripheral LPI2C3 base pointer */
30430 #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
30431 /** Peripheral LPI2C4 base address */
30432 #define LPI2C4_BASE                              (0x403FC000u)
30433 /** Peripheral LPI2C4 base pointer */
30434 #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
30435 /** Array initializer of LPI2C peripheral base addresses */
30436 #define LPI2C_BASE_ADDRS                         { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
30437 /** Array initializer of LPI2C peripheral base pointers */
30438 #define LPI2C_BASE_PTRS                          { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
30439 /** Interrupt vectors for the LPI2C peripheral type */
30440 #define LPI2C_IRQS                               { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
30441 
30442 /*!
30443  * @}
30444  */ /* end of group LPI2C_Peripheral_Access_Layer */
30445 
30446 
30447 /* ----------------------------------------------------------------------------
30448    -- LPSPI Peripheral Access Layer
30449    ---------------------------------------------------------------------------- */
30450 
30451 /*!
30452  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
30453  * @{
30454  */
30455 
30456 /** LPSPI - Register Layout Typedef */
30457 typedef struct {
30458   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
30459   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
30460        uint8_t RESERVED_0[8];
30461   __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
30462   __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
30463   __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x18 */
30464   __IO uint32_t DER;                               /**< DMA Enable Register, offset: 0x1C */
30465   __IO uint32_t CFGR0;                             /**< Configuration Register 0, offset: 0x20 */
30466   __IO uint32_t CFGR1;                             /**< Configuration Register 1, offset: 0x24 */
30467        uint8_t RESERVED_1[8];
30468   __IO uint32_t DMR0;                              /**< Data Match Register 0, offset: 0x30 */
30469   __IO uint32_t DMR1;                              /**< Data Match Register 1, offset: 0x34 */
30470        uint8_t RESERVED_2[8];
30471   __IO uint32_t CCR;                               /**< Clock Configuration Register, offset: 0x40 */
30472        uint8_t RESERVED_3[20];
30473   __IO uint32_t FCR;                               /**< The FIFO Control register contains the RXWATER and TXWATER control fields., offset: 0x58 */
30474   __I  uint32_t FSR;                               /**< FIFO Status Register, offset: 0x5C */
30475   __IO uint32_t TCR;                               /**< Transmit Command Register, offset: 0x60 */
30476   __O  uint32_t TDR;                               /**< Transmit Data Register, offset: 0x64 */
30477        uint8_t RESERVED_4[8];
30478   __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x70 */
30479   __I  uint32_t RDR;                               /**< Receive Data Register, offset: 0x74 */
30480 } LPSPI_Type;
30481 
30482 /* ----------------------------------------------------------------------------
30483    -- LPSPI Register Masks
30484    ---------------------------------------------------------------------------- */
30485 
30486 /*!
30487  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
30488  * @{
30489  */
30490 
30491 /*! @name VERID - Version ID Register */
30492 /*! @{ */
30493 
30494 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
30495 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
30496 /*! FEATURE - Module Identification Number
30497  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
30498  */
30499 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
30500 
30501 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
30502 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
30503 /*! MINOR - Minor Version Number
30504  */
30505 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
30506 
30507 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
30508 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
30509 /*! MAJOR - Major Version Number
30510  */
30511 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
30512 /*! @} */
30513 
30514 /*! @name PARAM - Parameter Register */
30515 /*! @{ */
30516 
30517 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
30518 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
30519 /*! TXFIFO - Transmit FIFO Size
30520  */
30521 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
30522 
30523 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
30524 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
30525 /*! RXFIFO - Receive FIFO Size
30526  */
30527 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
30528 /*! @} */
30529 
30530 /*! @name CR - Control Register */
30531 /*! @{ */
30532 
30533 #define LPSPI_CR_MEN_MASK                        (0x1U)
30534 #define LPSPI_CR_MEN_SHIFT                       (0U)
30535 /*! MEN - Module Enable
30536  *  0b0..Module is disabled
30537  *  0b1..Module is enabled
30538  */
30539 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
30540 
30541 #define LPSPI_CR_RST_MASK                        (0x2U)
30542 #define LPSPI_CR_RST_SHIFT                       (1U)
30543 /*! RST - Software Reset
30544  *  0b0..Module is not reset
30545  *  0b1..Module is reset
30546  */
30547 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
30548 
30549 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
30550 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
30551 /*! DOZEN - Doze Mode Enable
30552  *  0b0..LPSPI module is enabled in Doze mode
30553  *  0b1..LPSPI module is disabled in Doze mode
30554  */
30555 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
30556 
30557 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
30558 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
30559 /*! DBGEN - Debug Enable
30560  *  0b0..LPSPI module is disabled in debug mode
30561  *  0b1..LPSPI module is enabled in debug mode
30562  */
30563 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
30564 
30565 #define LPSPI_CR_RTF_MASK                        (0x100U)
30566 #define LPSPI_CR_RTF_SHIFT                       (8U)
30567 /*! RTF - Reset Transmit FIFO
30568  *  0b0..No effect
30569  *  0b1..Transmit FIFO is reset
30570  */
30571 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
30572 
30573 #define LPSPI_CR_RRF_MASK                        (0x200U)
30574 #define LPSPI_CR_RRF_SHIFT                       (9U)
30575 /*! RRF - Reset Receive FIFO
30576  *  0b0..No effect
30577  *  0b1..Receive FIFO is reset
30578  */
30579 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
30580 /*! @} */
30581 
30582 /*! @name SR - Status Register */
30583 /*! @{ */
30584 
30585 #define LPSPI_SR_TDF_MASK                        (0x1U)
30586 #define LPSPI_SR_TDF_SHIFT                       (0U)
30587 /*! TDF - Transmit Data Flag
30588  *  0b0..Transmit data not requested
30589  *  0b1..Transmit data is requested
30590  */
30591 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
30592 
30593 #define LPSPI_SR_RDF_MASK                        (0x2U)
30594 #define LPSPI_SR_RDF_SHIFT                       (1U)
30595 /*! RDF - Receive Data Flag
30596  *  0b0..Receive Data is not ready
30597  *  0b1..Receive data is ready
30598  */
30599 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
30600 
30601 #define LPSPI_SR_WCF_MASK                        (0x100U)
30602 #define LPSPI_SR_WCF_SHIFT                       (8U)
30603 /*! WCF - Word Complete Flag
30604  *  0b0..Transfer of a received word has not yet completed
30605  *  0b1..Transfer of a received word has completed
30606  */
30607 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
30608 
30609 #define LPSPI_SR_FCF_MASK                        (0x200U)
30610 #define LPSPI_SR_FCF_SHIFT                       (9U)
30611 /*! FCF - Frame Complete Flag
30612  *  0b0..Frame transfer has not completed
30613  *  0b1..Frame transfer has completed
30614  */
30615 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
30616 
30617 #define LPSPI_SR_TCF_MASK                        (0x400U)
30618 #define LPSPI_SR_TCF_SHIFT                       (10U)
30619 /*! TCF - Transfer Complete Flag
30620  *  0b0..All transfers have not completed
30621  *  0b1..All transfers have completed
30622  */
30623 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
30624 
30625 #define LPSPI_SR_TEF_MASK                        (0x800U)
30626 #define LPSPI_SR_TEF_SHIFT                       (11U)
30627 /*! TEF - Transmit Error Flag
30628  *  0b0..Transmit FIFO underrun has not occurred
30629  *  0b1..Transmit FIFO underrun has occurred
30630  */
30631 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
30632 
30633 #define LPSPI_SR_REF_MASK                        (0x1000U)
30634 #define LPSPI_SR_REF_SHIFT                       (12U)
30635 /*! REF - Receive Error Flag
30636  *  0b0..Receive FIFO has not overflowed
30637  *  0b1..Receive FIFO has overflowed
30638  */
30639 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
30640 
30641 #define LPSPI_SR_DMF_MASK                        (0x2000U)
30642 #define LPSPI_SR_DMF_SHIFT                       (13U)
30643 /*! DMF - Data Match Flag
30644  *  0b0..Have not received matching data
30645  *  0b1..Have received matching data
30646  */
30647 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
30648 
30649 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
30650 #define LPSPI_SR_MBF_SHIFT                       (24U)
30651 /*! MBF - Module Busy Flag
30652  *  0b0..LPSPI is idle
30653  *  0b1..LPSPI is busy
30654  */
30655 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
30656 /*! @} */
30657 
30658 /*! @name IER - Interrupt Enable Register */
30659 /*! @{ */
30660 
30661 #define LPSPI_IER_TDIE_MASK                      (0x1U)
30662 #define LPSPI_IER_TDIE_SHIFT                     (0U)
30663 /*! TDIE - Transmit Data Interrupt Enable
30664  *  0b0..Disabled
30665  *  0b1..Enabled
30666  */
30667 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
30668 
30669 #define LPSPI_IER_RDIE_MASK                      (0x2U)
30670 #define LPSPI_IER_RDIE_SHIFT                     (1U)
30671 /*! RDIE - Receive Data Interrupt Enable
30672  *  0b0..Disabled
30673  *  0b1..Enabled
30674  */
30675 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
30676 
30677 #define LPSPI_IER_WCIE_MASK                      (0x100U)
30678 #define LPSPI_IER_WCIE_SHIFT                     (8U)
30679 /*! WCIE - Word Complete Interrupt Enable
30680  *  0b0..Disabled
30681  *  0b1..Enabled
30682  */
30683 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
30684 
30685 #define LPSPI_IER_FCIE_MASK                      (0x200U)
30686 #define LPSPI_IER_FCIE_SHIFT                     (9U)
30687 /*! FCIE - Frame Complete Interrupt Enable
30688  *  0b0..Disabled
30689  *  0b1..Enabled
30690  */
30691 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
30692 
30693 #define LPSPI_IER_TCIE_MASK                      (0x400U)
30694 #define LPSPI_IER_TCIE_SHIFT                     (10U)
30695 /*! TCIE - Transfer Complete Interrupt Enable
30696  *  0b0..Disabled
30697  *  0b1..Enabled
30698  */
30699 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
30700 
30701 #define LPSPI_IER_TEIE_MASK                      (0x800U)
30702 #define LPSPI_IER_TEIE_SHIFT                     (11U)
30703 /*! TEIE - Transmit Error Interrupt Enable
30704  *  0b0..Disabled
30705  *  0b1..Enabled
30706  */
30707 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
30708 
30709 #define LPSPI_IER_REIE_MASK                      (0x1000U)
30710 #define LPSPI_IER_REIE_SHIFT                     (12U)
30711 /*! REIE - Receive Error Interrupt Enable
30712  *  0b0..Disabled
30713  *  0b1..Enabled
30714  */
30715 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
30716 
30717 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
30718 #define LPSPI_IER_DMIE_SHIFT                     (13U)
30719 /*! DMIE - Data Match Interrupt Enable
30720  *  0b0..Disabled
30721  *  0b1..Enabled
30722  */
30723 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
30724 /*! @} */
30725 
30726 /*! @name DER - DMA Enable Register */
30727 /*! @{ */
30728 
30729 #define LPSPI_DER_TDDE_MASK                      (0x1U)
30730 #define LPSPI_DER_TDDE_SHIFT                     (0U)
30731 /*! TDDE - Transmit Data DMA Enable
30732  *  0b0..DMA request is disabled
30733  *  0b1..DMA request is enabled
30734  */
30735 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
30736 
30737 #define LPSPI_DER_RDDE_MASK                      (0x2U)
30738 #define LPSPI_DER_RDDE_SHIFT                     (1U)
30739 /*! RDDE - Receive Data DMA Enable
30740  *  0b0..DMA request is disabled
30741  *  0b1..DMA request is enabled
30742  */
30743 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
30744 /*! @} */
30745 
30746 /*! @name CFGR0 - Configuration Register 0 */
30747 /*! @{ */
30748 
30749 #define LPSPI_CFGR0_HREN_MASK                    (0x1U)
30750 #define LPSPI_CFGR0_HREN_SHIFT                   (0U)
30751 /*! HREN - Host Request Enable
30752  *  0b0..Host request is disabled
30753  *  0b1..Host request is enabled
30754  */
30755 #define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
30756 
30757 #define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
30758 #define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
30759 /*! HRPOL - Host Request Polarity
30760  *  0b0..LPSPI_HREQ pin is active low
30761  *  0b1..LPSPI_HREQ pin is active high
30762  */
30763 #define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
30764 
30765 #define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
30766 #define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
30767 /*! HRSEL - Host Request Select
30768  *  0b0..Host request input is the LPSPI_HREQ pin
30769  *  0b1..Host request input is the input trigger
30770  */
30771 #define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
30772 
30773 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
30774 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
30775 /*! CIRFIFO - Circular FIFO Enable
30776  *  0b0..Circular FIFO is disabled
30777  *  0b1..Circular FIFO is enabled
30778  */
30779 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
30780 
30781 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
30782 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
30783 /*! RDMO - Receive Data Match Only
30784  *  0b0..Received data is stored in the receive FIFO as in normal operations
30785  *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
30786  */
30787 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
30788 /*! @} */
30789 
30790 /*! @name CFGR1 - Configuration Register 1 */
30791 /*! @{ */
30792 
30793 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
30794 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
30795 /*! MASTER - Master Mode
30796  *  0b0..Slave mode
30797  *  0b1..Master mode
30798  */
30799 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
30800 
30801 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
30802 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
30803 /*! SAMPLE - Sample Point
30804  *  0b0..Input data is sampled on SCK edge
30805  *  0b1..Input data is sampled on delayed SCK edge
30806  */
30807 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
30808 
30809 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
30810 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
30811 /*! AUTOPCS - Automatic PCS
30812  *  0b0..Automatic PCS generation is disabled
30813  *  0b1..Automatic PCS generation is enabled
30814  */
30815 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
30816 
30817 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
30818 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
30819 /*! NOSTALL - No Stall
30820  *  0b0..Transfers will stall when the transmit FIFO is empty
30821  *  0b1..Transfers will not stall, allowing transmit FIFO underruns to occur
30822  */
30823 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
30824 
30825 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
30826 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
30827 /*! PCSPOL - Peripheral Chip Select Polarity
30828  */
30829 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
30830 
30831 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
30832 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
30833 /*! MATCFG - Match Configuration
30834  *  0b000..Match is disabled
30835  *  0b001..Reserved
30836  *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
30837  *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
30838  *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st
30839  *         data word = MATCH0) * (2nd data word = MATCH1)]
30840  *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e.,
30841  *         [(any data word = MATCH0) * (next data word = MATCH1)]
30842  *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
30843  *  0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
30844  */
30845 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
30846 
30847 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
30848 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
30849 /*! PINCFG - Pin Configuration
30850  *  0b00..SIN is used for input data and SOUT is used for output data
30851  *  0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported
30852  *  0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported
30853  *  0b11..SOUT is used for input data and SIN is used for output data
30854  */
30855 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
30856 
30857 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
30858 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
30859 /*! OUTCFG - Output Configuration
30860  *  0b0..Output data retains last value when chip select is negated
30861  *  0b1..Output data is tristated when chip select is negated
30862  */
30863 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
30864 
30865 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
30866 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
30867 /*! PCSCFG - Peripheral Chip Select Configuration
30868  *  0b0..PCS[3:2] are configured for chip select function
30869  *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
30870  */
30871 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
30872 /*! @} */
30873 
30874 /*! @name DMR0 - Data Match Register 0 */
30875 /*! @{ */
30876 
30877 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
30878 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
30879 /*! MATCH0 - Match 0 Value
30880  */
30881 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
30882 /*! @} */
30883 
30884 /*! @name DMR1 - Data Match Register 1 */
30885 /*! @{ */
30886 
30887 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
30888 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
30889 /*! MATCH1 - Match 1 Value
30890  */
30891 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
30892 /*! @} */
30893 
30894 /*! @name CCR - Clock Configuration Register */
30895 /*! @{ */
30896 
30897 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
30898 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
30899 /*! SCKDIV - SCK Divider
30900  */
30901 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
30902 
30903 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
30904 #define LPSPI_CCR_DBT_SHIFT                      (8U)
30905 /*! DBT - Delay Between Transfers
30906  */
30907 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
30908 
30909 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
30910 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
30911 /*! PCSSCK - PCS-to-SCK Delay
30912  */
30913 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
30914 
30915 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
30916 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
30917 /*! SCKPCS - SCK-to-PCS Delay
30918  */
30919 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
30920 /*! @} */
30921 
30922 /*! @name FCR - The FIFO Control register contains the RXWATER and TXWATER control fields. */
30923 /*! @{ */
30924 
30925 #define LPSPI_FCR_TXWATER_MASK                   (0xFU)
30926 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
30927 /*! TXWATER - Transmit FIFO Watermark
30928  */
30929 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
30930 
30931 #define LPSPI_FCR_RXWATER_MASK                   (0xF0000U)
30932 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
30933 /*! RXWATER - Receive FIFO Watermark
30934  */
30935 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
30936 /*! @} */
30937 
30938 /*! @name FSR - FIFO Status Register */
30939 /*! @{ */
30940 
30941 #define LPSPI_FSR_TXCOUNT_MASK                   (0x1FU)
30942 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
30943 /*! TXCOUNT - Transmit FIFO Count
30944  */
30945 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
30946 
30947 #define LPSPI_FSR_RXCOUNT_MASK                   (0x1F0000U)
30948 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
30949 /*! RXCOUNT - Receive FIFO Count
30950  */
30951 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
30952 /*! @} */
30953 
30954 /*! @name TCR - Transmit Command Register */
30955 /*! @{ */
30956 
30957 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
30958 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
30959 /*! FRAMESZ - Frame Size
30960  */
30961 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
30962 
30963 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
30964 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
30965 /*! WIDTH - Transfer Width
30966  *  0b00..1 bit transfer
30967  *  0b01..2 bit transfer
30968  *  0b10..4 bit transfer
30969  *  0b11..Reserved
30970  */
30971 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
30972 
30973 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
30974 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
30975 /*! TXMSK - Transmit Data Mask
30976  *  0b0..Normal transfer
30977  *  0b1..Mask transmit data
30978  */
30979 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
30980 
30981 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
30982 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
30983 /*! RXMSK - Receive Data Mask
30984  *  0b0..Normal transfer
30985  *  0b1..Receive data is masked
30986  */
30987 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
30988 
30989 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
30990 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
30991 /*! CONTC - Continuing Command
30992  *  0b0..Command word for start of new transfer
30993  *  0b1..Command word for continuing transfer
30994  */
30995 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
30996 
30997 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
30998 #define LPSPI_TCR_CONT_SHIFT                     (21U)
30999 /*! CONT - Continuous Transfer
31000  *  0b0..Continuous transfer is disabled
31001  *  0b1..Continuous transfer is enabled
31002  */
31003 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
31004 
31005 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
31006 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
31007 /*! BYSW - Byte Swap
31008  *  0b0..Byte swap is disabled
31009  *  0b1..Byte swap is enabled
31010  */
31011 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
31012 
31013 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
31014 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
31015 /*! LSBF - LSB First
31016  *  0b0..Data is transferred MSB first
31017  *  0b1..Data is transferred LSB first
31018  */
31019 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
31020 
31021 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
31022 #define LPSPI_TCR_PCS_SHIFT                      (24U)
31023 /*! PCS - Peripheral Chip Select
31024  *  0b00..Transfer using LPSPI_PCS[0]
31025  *  0b01..Transfer using LPSPI_PCS[1]
31026  *  0b10..Transfer using LPSPI_PCS[2]
31027  *  0b11..Transfer using LPSPI_PCS[3]
31028  */
31029 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
31030 
31031 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
31032 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
31033 /*! PRESCALE - Prescaler Value
31034  *  0b000..Divide by 1
31035  *  0b001..Divide by 2
31036  *  0b010..Divide by 4
31037  *  0b011..Divide by 8
31038  *  0b100..Divide by 16
31039  *  0b101..Divide by 32
31040  *  0b110..Divide by 64
31041  *  0b111..Divide by 128
31042  */
31043 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
31044 
31045 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
31046 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
31047 /*! CPHA - Clock Phase
31048  *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
31049  *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
31050  */
31051 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
31052 
31053 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
31054 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
31055 /*! CPOL - Clock Polarity
31056  *  0b0..The inactive state value of SCK is low
31057  *  0b1..The inactive state value of SCK is high
31058  */
31059 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
31060 /*! @} */
31061 
31062 /*! @name TDR - Transmit Data Register */
31063 /*! @{ */
31064 
31065 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
31066 #define LPSPI_TDR_DATA_SHIFT                     (0U)
31067 /*! DATA - Transmit Data
31068  */
31069 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
31070 /*! @} */
31071 
31072 /*! @name RSR - Receive Status Register */
31073 /*! @{ */
31074 
31075 #define LPSPI_RSR_SOF_MASK                       (0x1U)
31076 #define LPSPI_RSR_SOF_SHIFT                      (0U)
31077 /*! SOF - Start Of Frame
31078  *  0b0..Subsequent data word received after LPSPI_PCS assertion
31079  *  0b1..First data word received after LPSPI_PCS assertion
31080  */
31081 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
31082 
31083 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
31084 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
31085 /*! RXEMPTY - RX FIFO Empty
31086  *  0b0..RX FIFO is not empty
31087  *  0b1..RX FIFO is empty
31088  */
31089 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
31090 /*! @} */
31091 
31092 /*! @name RDR - Receive Data Register */
31093 /*! @{ */
31094 
31095 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
31096 #define LPSPI_RDR_DATA_SHIFT                     (0U)
31097 /*! DATA - Receive Data
31098  */
31099 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
31100 /*! @} */
31101 
31102 
31103 /*!
31104  * @}
31105  */ /* end of group LPSPI_Register_Masks */
31106 
31107 
31108 /* LPSPI - Peripheral instance base addresses */
31109 /** Peripheral LPSPI1 base address */
31110 #define LPSPI1_BASE                              (0x40394000u)
31111 /** Peripheral LPSPI1 base pointer */
31112 #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
31113 /** Peripheral LPSPI2 base address */
31114 #define LPSPI2_BASE                              (0x40398000u)
31115 /** Peripheral LPSPI2 base pointer */
31116 #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
31117 /** Peripheral LPSPI3 base address */
31118 #define LPSPI3_BASE                              (0x4039C000u)
31119 /** Peripheral LPSPI3 base pointer */
31120 #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
31121 /** Peripheral LPSPI4 base address */
31122 #define LPSPI4_BASE                              (0x403A0000u)
31123 /** Peripheral LPSPI4 base pointer */
31124 #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
31125 /** Array initializer of LPSPI peripheral base addresses */
31126 #define LPSPI_BASE_ADDRS                         { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
31127 /** Array initializer of LPSPI peripheral base pointers */
31128 #define LPSPI_BASE_PTRS                          { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
31129 /** Interrupt vectors for the LPSPI peripheral type */
31130 #define LPSPI_IRQS                               { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
31131 
31132 /*!
31133  * @}
31134  */ /* end of group LPSPI_Peripheral_Access_Layer */
31135 
31136 
31137 /* ----------------------------------------------------------------------------
31138    -- LPUART Peripheral Access Layer
31139    ---------------------------------------------------------------------------- */
31140 
31141 /*!
31142  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
31143  * @{
31144  */
31145 
31146 /** LPUART - Register Layout Typedef */
31147 typedef struct {
31148   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
31149   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
31150   __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
31151   __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
31152   __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
31153   __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
31154   __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
31155   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
31156   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
31157   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
31158   __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
31159   __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
31160 } LPUART_Type;
31161 
31162 /* ----------------------------------------------------------------------------
31163    -- LPUART Register Masks
31164    ---------------------------------------------------------------------------- */
31165 
31166 /*!
31167  * @addtogroup LPUART_Register_Masks LPUART Register Masks
31168  * @{
31169  */
31170 
31171 /*! @name VERID - Version ID Register */
31172 /*! @{ */
31173 
31174 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
31175 #define LPUART_VERID_FEATURE_SHIFT               (0U)
31176 /*! FEATURE - Feature Identification Number
31177  *  0b0000000000000001..Standard feature set.
31178  *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
31179  */
31180 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
31181 
31182 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
31183 #define LPUART_VERID_MINOR_SHIFT                 (16U)
31184 /*! MINOR - Minor Version Number
31185  */
31186 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
31187 
31188 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
31189 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
31190 /*! MAJOR - Major Version Number
31191  */
31192 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
31193 /*! @} */
31194 
31195 /*! @name PARAM - Parameter Register */
31196 /*! @{ */
31197 
31198 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
31199 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
31200 /*! TXFIFO - Transmit FIFO Size
31201  */
31202 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
31203 
31204 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
31205 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
31206 /*! RXFIFO - Receive FIFO Size
31207  */
31208 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
31209 /*! @} */
31210 
31211 /*! @name GLOBAL - LPUART Global Register */
31212 /*! @{ */
31213 
31214 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
31215 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
31216 /*! RST - Software Reset
31217  *  0b0..Module is not reset.
31218  *  0b1..Module is reset.
31219  */
31220 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
31221 /*! @} */
31222 
31223 /*! @name PINCFG - LPUART Pin Configuration Register */
31224 /*! @{ */
31225 
31226 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
31227 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
31228 /*! TRGSEL - Trigger Select
31229  *  0b00..Input trigger is disabled.
31230  *  0b01..Input trigger is used instead of RXD pin input.
31231  *  0b10..Input trigger is used instead of CTS_B pin input.
31232  *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
31233  */
31234 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
31235 /*! @} */
31236 
31237 /*! @name BAUD - LPUART Baud Rate Register */
31238 /*! @{ */
31239 
31240 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
31241 #define LPUART_BAUD_SBR_SHIFT                    (0U)
31242 /*! SBR - Baud Rate Modulo Divisor.
31243  */
31244 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
31245 
31246 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
31247 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
31248 /*! SBNS - Stop Bit Number Select
31249  *  0b0..One stop bit.
31250  *  0b1..Two stop bits.
31251  */
31252 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
31253 
31254 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
31255 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
31256 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
31257  *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
31258  *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
31259  */
31260 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
31261 
31262 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
31263 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
31264 /*! LBKDIE - LIN Break Detect Interrupt Enable
31265  *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
31266  *  0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.
31267  */
31268 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
31269 
31270 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
31271 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
31272 /*! RESYNCDIS - Resynchronization Disable
31273  *  0b0..Resynchronization during received data word is supported
31274  *  0b1..Resynchronization during received data word is disabled
31275  */
31276 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
31277 
31278 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
31279 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
31280 /*! BOTHEDGE - Both Edge Sampling
31281  *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
31282  *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
31283  */
31284 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
31285 
31286 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
31287 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
31288 /*! MATCFG - Match Configuration
31289  *  0b00..Address Match Wakeup
31290  *  0b01..Idle Match Wakeup
31291  *  0b10..Match On and Match Off
31292  *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
31293  */
31294 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
31295 
31296 #define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
31297 #define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
31298 /*! RIDMAE - Receiver Idle DMA Enable
31299  *  0b0..DMA request disabled.
31300  *  0b1..DMA request enabled.
31301  */
31302 #define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
31303 
31304 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
31305 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
31306 /*! RDMAE - Receiver Full DMA Enable
31307  *  0b0..DMA request disabled.
31308  *  0b1..DMA request enabled.
31309  */
31310 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
31311 
31312 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
31313 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
31314 /*! TDMAE - Transmitter DMA Enable
31315  *  0b0..DMA request disabled.
31316  *  0b1..DMA request enabled.
31317  */
31318 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
31319 
31320 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
31321 #define LPUART_BAUD_OSR_SHIFT                    (24U)
31322 /*! OSR - Oversampling Ratio
31323  *  0b00000..Writing 0 to this field results in an oversampling ratio of 16
31324  *  0b00001..Reserved
31325  *  0b00010..Reserved
31326  *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
31327  *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
31328  *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
31329  *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
31330  *  0b00111..Oversampling ratio of 8.
31331  *  0b01000..Oversampling ratio of 9.
31332  *  0b01001..Oversampling ratio of 10.
31333  *  0b01010..Oversampling ratio of 11.
31334  *  0b01011..Oversampling ratio of 12.
31335  *  0b01100..Oversampling ratio of 13.
31336  *  0b01101..Oversampling ratio of 14.
31337  *  0b01110..Oversampling ratio of 15.
31338  *  0b01111..Oversampling ratio of 16.
31339  *  0b10000..Oversampling ratio of 17.
31340  *  0b10001..Oversampling ratio of 18.
31341  *  0b10010..Oversampling ratio of 19.
31342  *  0b10011..Oversampling ratio of 20.
31343  *  0b10100..Oversampling ratio of 21.
31344  *  0b10101..Oversampling ratio of 22.
31345  *  0b10110..Oversampling ratio of 23.
31346  *  0b10111..Oversampling ratio of 24.
31347  *  0b11000..Oversampling ratio of 25.
31348  *  0b11001..Oversampling ratio of 26.
31349  *  0b11010..Oversampling ratio of 27.
31350  *  0b11011..Oversampling ratio of 28.
31351  *  0b11100..Oversampling ratio of 29.
31352  *  0b11101..Oversampling ratio of 30.
31353  *  0b11110..Oversampling ratio of 31.
31354  *  0b11111..Oversampling ratio of 32.
31355  */
31356 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
31357 
31358 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
31359 #define LPUART_BAUD_M10_SHIFT                    (29U)
31360 /*! M10 - 10-bit Mode select
31361  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
31362  *  0b1..Receiver and transmitter use 10-bit data characters.
31363  */
31364 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
31365 
31366 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
31367 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
31368 /*! MAEN2 - Match Address Mode Enable 2
31369  *  0b0..Normal operation.
31370  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
31371  */
31372 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
31373 
31374 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
31375 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
31376 /*! MAEN1 - Match Address Mode Enable 1
31377  *  0b0..Normal operation.
31378  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
31379  */
31380 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
31381 /*! @} */
31382 
31383 /*! @name STAT - LPUART Status Register */
31384 /*! @{ */
31385 
31386 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
31387 #define LPUART_STAT_MA2F_SHIFT                   (14U)
31388 /*! MA2F - Match 2 Flag
31389  *  0b0..Received data is not equal to MA2
31390  *  0b1..Received data is equal to MA2
31391  */
31392 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
31393 
31394 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
31395 #define LPUART_STAT_MA1F_SHIFT                   (15U)
31396 /*! MA1F - Match 1 Flag
31397  *  0b0..Received data is not equal to MA1
31398  *  0b1..Received data is equal to MA1
31399  */
31400 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
31401 
31402 #define LPUART_STAT_PF_MASK                      (0x10000U)
31403 #define LPUART_STAT_PF_SHIFT                     (16U)
31404 /*! PF - Parity Error Flag
31405  *  0b0..No parity error.
31406  *  0b1..Parity error.
31407  */
31408 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
31409 
31410 #define LPUART_STAT_FE_MASK                      (0x20000U)
31411 #define LPUART_STAT_FE_SHIFT                     (17U)
31412 /*! FE - Framing Error Flag
31413  *  0b0..No framing error detected. This does not guarantee the framing is correct.
31414  *  0b1..Framing error.
31415  */
31416 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
31417 
31418 #define LPUART_STAT_NF_MASK                      (0x40000U)
31419 #define LPUART_STAT_NF_SHIFT                     (18U)
31420 /*! NF - Noise Flag
31421  *  0b0..No noise detected.
31422  *  0b1..Noise detected in the received character in the DATA register.
31423  */
31424 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
31425 
31426 #define LPUART_STAT_OR_MASK                      (0x80000U)
31427 #define LPUART_STAT_OR_SHIFT                     (19U)
31428 /*! OR - Receiver Overrun Flag
31429  *  0b0..No overrun.
31430  *  0b1..Receive overrun (new LPUART data lost).
31431  */
31432 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
31433 
31434 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
31435 #define LPUART_STAT_IDLE_SHIFT                   (20U)
31436 /*! IDLE - Idle Line Flag
31437  *  0b0..No idle line detected.
31438  *  0b1..Idle line was detected.
31439  */
31440 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
31441 
31442 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
31443 #define LPUART_STAT_RDRF_SHIFT                   (21U)
31444 /*! RDRF - Receive Data Register Full Flag
31445  *  0b0..Receive data buffer empty.
31446  *  0b1..Receive data buffer full.
31447  */
31448 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
31449 
31450 #define LPUART_STAT_TC_MASK                      (0x400000U)
31451 #define LPUART_STAT_TC_SHIFT                     (22U)
31452 /*! TC - Transmission Complete Flag
31453  *  0b0..Transmitter active (sending data, a preamble, or a break).
31454  *  0b1..Transmitter idle (transmission activity complete).
31455  */
31456 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
31457 
31458 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
31459 #define LPUART_STAT_TDRE_SHIFT                   (23U)
31460 /*! TDRE - Transmit Data Register Empty Flag
31461  *  0b0..Transmit data buffer full.
31462  *  0b1..Transmit data buffer empty.
31463  */
31464 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
31465 
31466 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
31467 #define LPUART_STAT_RAF_SHIFT                    (24U)
31468 /*! RAF - Receiver Active Flag
31469  *  0b0..LPUART receiver idle waiting for a start bit.
31470  *  0b1..LPUART receiver active (RXD input not idle).
31471  */
31472 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
31473 
31474 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
31475 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
31476 /*! LBKDE - LIN Break Detection Enable
31477  *  0b0..LIN break detect is disabled, normal break character can be detected.
31478  *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
31479  */
31480 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
31481 
31482 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
31483 #define LPUART_STAT_BRK13_SHIFT                  (26U)
31484 /*! BRK13 - Break Character Generation Length
31485  *  0b0..Break character is transmitted with length of 9 to 13 bit times.
31486  *  0b1..Break character is transmitted with length of 12 to 15 bit times.
31487  */
31488 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
31489 
31490 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
31491 #define LPUART_STAT_RWUID_SHIFT                  (27U)
31492 /*! RWUID - Receive Wake Up Idle Detect
31493  *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
31494  *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
31495  *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
31496  *       address match wakeup, the IDLE bit does set when an address does not match.
31497  */
31498 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
31499 
31500 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
31501 #define LPUART_STAT_RXINV_SHIFT                  (28U)
31502 /*! RXINV - Receive Data Inversion
31503  *  0b0..Receive data not inverted.
31504  *  0b1..Receive data inverted.
31505  */
31506 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
31507 
31508 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
31509 #define LPUART_STAT_MSBF_SHIFT                   (29U)
31510 /*! MSBF - MSB First
31511  *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
31512  *       after the start bit is identified as bit0.
31513  *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on
31514  *       the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
31515  *       identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
31516  */
31517 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
31518 
31519 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
31520 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
31521 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
31522  *  0b0..No active edge on the receive pin has occurred.
31523  *  0b1..An active edge on the receive pin has occurred.
31524  */
31525 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
31526 
31527 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
31528 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
31529 /*! LBKDIF - LIN Break Detect Interrupt Flag
31530  *  0b0..No LIN break character has been detected.
31531  *  0b1..LIN break character has been detected.
31532  */
31533 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
31534 /*! @} */
31535 
31536 /*! @name CTRL - LPUART Control Register */
31537 /*! @{ */
31538 
31539 #define LPUART_CTRL_PT_MASK                      (0x1U)
31540 #define LPUART_CTRL_PT_SHIFT                     (0U)
31541 /*! PT - Parity Type
31542  *  0b0..Even parity.
31543  *  0b1..Odd parity.
31544  */
31545 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
31546 
31547 #define LPUART_CTRL_PE_MASK                      (0x2U)
31548 #define LPUART_CTRL_PE_SHIFT                     (1U)
31549 /*! PE - Parity Enable
31550  *  0b0..No hardware parity generation or checking.
31551  *  0b1..Parity enabled.
31552  */
31553 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
31554 
31555 #define LPUART_CTRL_ILT_MASK                     (0x4U)
31556 #define LPUART_CTRL_ILT_SHIFT                    (2U)
31557 /*! ILT - Idle Line Type Select
31558  *  0b0..Idle character bit count starts after start bit.
31559  *  0b1..Idle character bit count starts after stop bit.
31560  */
31561 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
31562 
31563 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
31564 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
31565 /*! WAKE - Receiver Wakeup Method Select
31566  *  0b0..Configures RWU for idle-line wakeup.
31567  *  0b1..Configures RWU with address-mark wakeup.
31568  */
31569 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
31570 
31571 #define LPUART_CTRL_M_MASK                       (0x10U)
31572 #define LPUART_CTRL_M_SHIFT                      (4U)
31573 /*! M - 9-Bit or 8-Bit Mode Select
31574  *  0b0..Receiver and transmitter use 8-bit data characters.
31575  *  0b1..Receiver and transmitter use 9-bit data characters.
31576  */
31577 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
31578 
31579 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
31580 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
31581 /*! RSRC - Receiver Source Select
31582  *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
31583  *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
31584  */
31585 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
31586 
31587 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
31588 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
31589 /*! DOZEEN - Doze Enable
31590  *  0b0..LPUART is enabled in Doze mode.
31591  *  0b1..LPUART is disabled in Doze mode.
31592  */
31593 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
31594 
31595 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
31596 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
31597 /*! LOOPS - Loop Mode Select
31598  *  0b0..Normal operation - RXD and TXD use separate pins.
31599  *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
31600  */
31601 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
31602 
31603 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
31604 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
31605 /*! IDLECFG - Idle Configuration
31606  *  0b000..1 idle character
31607  *  0b001..2 idle characters
31608  *  0b010..4 idle characters
31609  *  0b011..8 idle characters
31610  *  0b100..16 idle characters
31611  *  0b101..32 idle characters
31612  *  0b110..64 idle characters
31613  *  0b111..128 idle characters
31614  */
31615 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
31616 
31617 #define LPUART_CTRL_M7_MASK                      (0x800U)
31618 #define LPUART_CTRL_M7_SHIFT                     (11U)
31619 /*! M7 - 7-Bit Mode Select
31620  *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
31621  *  0b1..Receiver and transmitter use 7-bit data characters.
31622  */
31623 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
31624 
31625 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
31626 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
31627 /*! MA2IE - Match 2 Interrupt Enable
31628  *  0b0..MA2F interrupt disabled
31629  *  0b1..MA2F interrupt enabled
31630  */
31631 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
31632 
31633 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
31634 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
31635 /*! MA1IE - Match 1 Interrupt Enable
31636  *  0b0..MA1F interrupt disabled
31637  *  0b1..MA1F interrupt enabled
31638  */
31639 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
31640 
31641 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
31642 #define LPUART_CTRL_SBK_SHIFT                    (16U)
31643 /*! SBK - Send Break
31644  *  0b0..Normal transmitter operation.
31645  *  0b1..Queue break character(s) to be sent.
31646  */
31647 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
31648 
31649 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
31650 #define LPUART_CTRL_RWU_SHIFT                    (17U)
31651 /*! RWU - Receiver Wakeup Control
31652  *  0b0..Normal receiver operation.
31653  *  0b1..LPUART receiver in standby waiting for wakeup condition.
31654  */
31655 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
31656 
31657 #define LPUART_CTRL_RE_MASK                      (0x40000U)
31658 #define LPUART_CTRL_RE_SHIFT                     (18U)
31659 /*! RE - Receiver Enable
31660  *  0b0..Receiver disabled.
31661  *  0b1..Receiver enabled.
31662  */
31663 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
31664 
31665 #define LPUART_CTRL_TE_MASK                      (0x80000U)
31666 #define LPUART_CTRL_TE_SHIFT                     (19U)
31667 /*! TE - Transmitter Enable
31668  *  0b0..Transmitter disabled.
31669  *  0b1..Transmitter enabled.
31670  */
31671 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
31672 
31673 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
31674 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
31675 /*! ILIE - Idle Line Interrupt Enable
31676  *  0b0..Hardware interrupts from IDLE disabled; use polling.
31677  *  0b1..Hardware interrupt requested when IDLE flag is 1.
31678  */
31679 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
31680 
31681 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
31682 #define LPUART_CTRL_RIE_SHIFT                    (21U)
31683 /*! RIE - Receiver Interrupt Enable
31684  *  0b0..Hardware interrupts from RDRF disabled; use polling.
31685  *  0b1..Hardware interrupt requested when RDRF flag is 1.
31686  */
31687 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
31688 
31689 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
31690 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
31691 /*! TCIE - Transmission Complete Interrupt Enable for
31692  *  0b0..Hardware interrupts from TC disabled; use polling.
31693  *  0b1..Hardware interrupt requested when TC flag is 1.
31694  */
31695 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
31696 
31697 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
31698 #define LPUART_CTRL_TIE_SHIFT                    (23U)
31699 /*! TIE - Transmit Interrupt Enable
31700  *  0b0..Hardware interrupts from TDRE disabled; use polling.
31701  *  0b1..Hardware interrupt requested when TDRE flag is 1.
31702  */
31703 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
31704 
31705 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
31706 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
31707 /*! PEIE - Parity Error Interrupt Enable
31708  *  0b0..PF interrupts disabled; use polling).
31709  *  0b1..Hardware interrupt requested when PF is set.
31710  */
31711 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
31712 
31713 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
31714 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
31715 /*! FEIE - Framing Error Interrupt Enable
31716  *  0b0..FE interrupts disabled; use polling.
31717  *  0b1..Hardware interrupt requested when FE is set.
31718  */
31719 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
31720 
31721 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
31722 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
31723 /*! NEIE - Noise Error Interrupt Enable
31724  *  0b0..NF interrupts disabled; use polling.
31725  *  0b1..Hardware interrupt requested when NF is set.
31726  */
31727 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
31728 
31729 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
31730 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
31731 /*! ORIE - Overrun Interrupt Enable
31732  *  0b0..OR interrupts disabled; use polling.
31733  *  0b1..Hardware interrupt requested when OR is set.
31734  */
31735 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
31736 
31737 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
31738 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
31739 /*! TXINV - Transmit Data Inversion
31740  *  0b0..Transmit data not inverted.
31741  *  0b1..Transmit data inverted.
31742  */
31743 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
31744 
31745 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
31746 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
31747 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
31748  *  0b0..TXD pin is an input in single-wire mode.
31749  *  0b1..TXD pin is an output in single-wire mode.
31750  */
31751 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
31752 
31753 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
31754 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
31755 /*! R9T8 - Receive Bit 9 / Transmit Bit 8
31756  */
31757 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
31758 
31759 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
31760 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
31761 /*! R8T9 - Receive Bit 8 / Transmit Bit 9
31762  */
31763 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
31764 /*! @} */
31765 
31766 /*! @name DATA - LPUART Data Register */
31767 /*! @{ */
31768 
31769 #define LPUART_DATA_R0T0_MASK                    (0x1U)
31770 #define LPUART_DATA_R0T0_SHIFT                   (0U)
31771 /*! R0T0 - R0T0
31772  */
31773 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
31774 
31775 #define LPUART_DATA_R1T1_MASK                    (0x2U)
31776 #define LPUART_DATA_R1T1_SHIFT                   (1U)
31777 /*! R1T1 - R1T1
31778  */
31779 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
31780 
31781 #define LPUART_DATA_R2T2_MASK                    (0x4U)
31782 #define LPUART_DATA_R2T2_SHIFT                   (2U)
31783 /*! R2T2 - R2T2
31784  */
31785 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
31786 
31787 #define LPUART_DATA_R3T3_MASK                    (0x8U)
31788 #define LPUART_DATA_R3T3_SHIFT                   (3U)
31789 /*! R3T3 - R3T3
31790  */
31791 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
31792 
31793 #define LPUART_DATA_R4T4_MASK                    (0x10U)
31794 #define LPUART_DATA_R4T4_SHIFT                   (4U)
31795 /*! R4T4 - R4T4
31796  */
31797 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
31798 
31799 #define LPUART_DATA_R5T5_MASK                    (0x20U)
31800 #define LPUART_DATA_R5T5_SHIFT                   (5U)
31801 /*! R5T5 - R5T5
31802  */
31803 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
31804 
31805 #define LPUART_DATA_R6T6_MASK                    (0x40U)
31806 #define LPUART_DATA_R6T6_SHIFT                   (6U)
31807 /*! R6T6 - R6T6
31808  */
31809 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
31810 
31811 #define LPUART_DATA_R7T7_MASK                    (0x80U)
31812 #define LPUART_DATA_R7T7_SHIFT                   (7U)
31813 /*! R7T7 - R7T7
31814  */
31815 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
31816 
31817 #define LPUART_DATA_R8T8_MASK                    (0x100U)
31818 #define LPUART_DATA_R8T8_SHIFT                   (8U)
31819 /*! R8T8 - R8T8
31820  */
31821 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
31822 
31823 #define LPUART_DATA_R9T9_MASK                    (0x200U)
31824 #define LPUART_DATA_R9T9_SHIFT                   (9U)
31825 /*! R9T9 - R9T9
31826  */
31827 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
31828 
31829 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
31830 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
31831 /*! IDLINE - Idle Line
31832  *  0b0..Receiver was not idle before receiving this character.
31833  *  0b1..Receiver was idle before receiving this character.
31834  */
31835 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
31836 
31837 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
31838 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
31839 /*! RXEMPT - Receive Buffer Empty
31840  *  0b0..Receive buffer contains valid data.
31841  *  0b1..Receive buffer is empty, data returned on read is not valid.
31842  */
31843 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
31844 
31845 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
31846 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
31847 /*! FRETSC - Frame Error / Transmit Special Character
31848  *  0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
31849  *  0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
31850  */
31851 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
31852 
31853 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
31854 #define LPUART_DATA_PARITYE_SHIFT                (14U)
31855 /*! PARITYE - PARITYE
31856  *  0b0..The dataword was received without a parity error.
31857  *  0b1..The dataword was received with a parity error.
31858  */
31859 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
31860 
31861 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
31862 #define LPUART_DATA_NOISY_SHIFT                  (15U)
31863 /*! NOISY - NOISY
31864  *  0b0..The dataword was received without noise.
31865  *  0b1..The data was received with noise.
31866  */
31867 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
31868 /*! @} */
31869 
31870 /*! @name MATCH - LPUART Match Address Register */
31871 /*! @{ */
31872 
31873 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
31874 #define LPUART_MATCH_MA1_SHIFT                   (0U)
31875 /*! MA1 - Match Address 1
31876  */
31877 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
31878 
31879 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
31880 #define LPUART_MATCH_MA2_SHIFT                   (16U)
31881 /*! MA2 - Match Address 2
31882  */
31883 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
31884 /*! @} */
31885 
31886 /*! @name MODIR - LPUART Modem IrDA Register */
31887 /*! @{ */
31888 
31889 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
31890 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
31891 /*! TXCTSE - Transmitter clear-to-send enable
31892  *  0b0..CTS has no effect on the transmitter.
31893  *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
31894  *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
31895  *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
31896  *       do not affect its transmission.
31897  */
31898 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
31899 
31900 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
31901 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
31902 /*! TXRTSE - Transmitter request-to-send enable
31903  *  0b0..The transmitter has no effect on RTS.
31904  *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
31905  *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and
31906  *       shift register are completely sent, including the last stop bit.
31907  */
31908 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
31909 
31910 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
31911 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
31912 /*! TXRTSPOL - Transmitter request-to-send polarity
31913  *  0b0..Transmitter RTS is active low.
31914  *  0b1..Transmitter RTS is active high.
31915  */
31916 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
31917 
31918 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
31919 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
31920 /*! RXRTSE - Receiver request-to-send enable
31921  *  0b0..The receiver has no effect on RTS.
31922  *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
31923  *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
31924  *       has not detected a start bit that would cause the receiver data register to become full.
31925  */
31926 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
31927 
31928 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
31929 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
31930 /*! TXCTSC - Transmit CTS Configuration
31931  *  0b0..CTS input is sampled at the start of each character.
31932  *  0b1..CTS input is sampled when the transmitter is idle.
31933  */
31934 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
31935 
31936 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
31937 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
31938 /*! TXCTSSRC - Transmit CTS Source
31939  *  0b0..CTS input is the CTS_B pin.
31940  *  0b1..CTS input is the inverted Receiver Match result.
31941  */
31942 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
31943 
31944 #define LPUART_MODIR_RTSWATER_MASK               (0x300U)
31945 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
31946 /*! RTSWATER - Receive RTS Configuration
31947  */
31948 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
31949 
31950 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
31951 #define LPUART_MODIR_TNP_SHIFT                   (16U)
31952 /*! TNP - Transmitter narrow pulse
31953  *  0b00..1/OSR.
31954  *  0b01..2/OSR.
31955  *  0b10..3/OSR.
31956  *  0b11..4/OSR.
31957  */
31958 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
31959 
31960 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
31961 #define LPUART_MODIR_IREN_SHIFT                  (18U)
31962 /*! IREN - Infrared enable
31963  *  0b0..IR disabled.
31964  *  0b1..IR enabled.
31965  */
31966 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
31967 /*! @} */
31968 
31969 /*! @name FIFO - LPUART FIFO Register */
31970 /*! @{ */
31971 
31972 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
31973 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
31974 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
31975  *  0b000..Receive FIFO/Buffer depth = 1 dataword.
31976  *  0b001..Receive FIFO/Buffer depth = 4 datawords.
31977  *  0b010..Receive FIFO/Buffer depth = 8 datawords.
31978  *  0b011..Receive FIFO/Buffer depth = 16 datawords.
31979  *  0b100..Receive FIFO/Buffer depth = 32 datawords.
31980  *  0b101..Receive FIFO/Buffer depth = 64 datawords.
31981  *  0b110..Receive FIFO/Buffer depth = 128 datawords.
31982  *  0b111..Receive FIFO/Buffer depth = 256 datawords.
31983  */
31984 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
31985 
31986 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
31987 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
31988 /*! RXFE - Receive FIFO Enable
31989  *  0b0..Receive FIFO is not enabled. Buffer is depth 1.
31990  *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
31991  */
31992 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
31993 
31994 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
31995 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
31996 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
31997  *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
31998  *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
31999  *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
32000  *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
32001  *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
32002  *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
32003  *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
32004  *  0b111..Transmit FIFO/Buffer depth = 256 datawords
32005  */
32006 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
32007 
32008 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
32009 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
32010 /*! TXFE - Transmit FIFO Enable
32011  *  0b0..Transmit FIFO is not enabled. Buffer is depth 1.
32012  *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
32013  */
32014 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
32015 
32016 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
32017 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
32018 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
32019  *  0b0..RXUF flag does not generate an interrupt to the host.
32020  *  0b1..RXUF flag generates an interrupt to the host.
32021  */
32022 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
32023 
32024 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
32025 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
32026 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
32027  *  0b0..TXOF flag does not generate an interrupt to the host.
32028  *  0b1..TXOF flag generates an interrupt to the host.
32029  */
32030 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
32031 
32032 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
32033 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
32034 /*! RXIDEN - Receiver Idle Empty Enable
32035  *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
32036  *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
32037  *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
32038  *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
32039  *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
32040  *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
32041  *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
32042  *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
32043  */
32044 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
32045 
32046 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
32047 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
32048 /*! RXFLUSH - Receive FIFO/Buffer Flush
32049  *  0b0..No flush operation occurs.
32050  *  0b1..All data in the receive FIFO/buffer is cleared out.
32051  */
32052 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
32053 
32054 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
32055 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
32056 /*! TXFLUSH - Transmit FIFO/Buffer Flush
32057  *  0b0..No flush operation occurs.
32058  *  0b1..All data in the transmit FIFO/Buffer is cleared out.
32059  */
32060 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
32061 
32062 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
32063 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
32064 /*! RXUF - Receiver Buffer Underflow Flag
32065  *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
32066  *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
32067  */
32068 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
32069 
32070 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
32071 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
32072 /*! TXOF - Transmitter Buffer Overflow Flag
32073  *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
32074  *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
32075  */
32076 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
32077 
32078 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
32079 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
32080 /*! RXEMPT - Receive Buffer/FIFO Empty
32081  *  0b0..Receive buffer is not empty.
32082  *  0b1..Receive buffer is empty.
32083  */
32084 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
32085 
32086 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
32087 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
32088 /*! TXEMPT - Transmit Buffer/FIFO Empty
32089  *  0b0..Transmit buffer is not empty.
32090  *  0b1..Transmit buffer is empty.
32091  */
32092 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
32093 /*! @} */
32094 
32095 /*! @name WATER - LPUART Watermark Register */
32096 /*! @{ */
32097 
32098 #define LPUART_WATER_TXWATER_MASK                (0x3U)
32099 #define LPUART_WATER_TXWATER_SHIFT               (0U)
32100 /*! TXWATER - Transmit Watermark
32101  */
32102 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
32103 
32104 #define LPUART_WATER_TXCOUNT_MASK                (0x700U)
32105 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
32106 /*! TXCOUNT - Transmit Counter
32107  */
32108 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
32109 
32110 #define LPUART_WATER_RXWATER_MASK                (0x30000U)
32111 #define LPUART_WATER_RXWATER_SHIFT               (16U)
32112 /*! RXWATER - Receive Watermark
32113  */
32114 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
32115 
32116 #define LPUART_WATER_RXCOUNT_MASK                (0x7000000U)
32117 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
32118 /*! RXCOUNT - Receive Counter
32119  */
32120 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
32121 /*! @} */
32122 
32123 
32124 /*!
32125  * @}
32126  */ /* end of group LPUART_Register_Masks */
32127 
32128 
32129 /* LPUART - Peripheral instance base addresses */
32130 /** Peripheral LPUART1 base address */
32131 #define LPUART1_BASE                             (0x40184000u)
32132 /** Peripheral LPUART1 base pointer */
32133 #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
32134 /** Peripheral LPUART2 base address */
32135 #define LPUART2_BASE                             (0x40188000u)
32136 /** Peripheral LPUART2 base pointer */
32137 #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
32138 /** Peripheral LPUART3 base address */
32139 #define LPUART3_BASE                             (0x4018C000u)
32140 /** Peripheral LPUART3 base pointer */
32141 #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
32142 /** Peripheral LPUART4 base address */
32143 #define LPUART4_BASE                             (0x40190000u)
32144 /** Peripheral LPUART4 base pointer */
32145 #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
32146 /** Peripheral LPUART5 base address */
32147 #define LPUART5_BASE                             (0x40194000u)
32148 /** Peripheral LPUART5 base pointer */
32149 #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
32150 /** Peripheral LPUART6 base address */
32151 #define LPUART6_BASE                             (0x40198000u)
32152 /** Peripheral LPUART6 base pointer */
32153 #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
32154 /** Peripheral LPUART7 base address */
32155 #define LPUART7_BASE                             (0x4019C000u)
32156 /** Peripheral LPUART7 base pointer */
32157 #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
32158 /** Peripheral LPUART8 base address */
32159 #define LPUART8_BASE                             (0x401A0000u)
32160 /** Peripheral LPUART8 base pointer */
32161 #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
32162 /** Array initializer of LPUART peripheral base addresses */
32163 #define LPUART_BASE_ADDRS                        { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
32164 /** Array initializer of LPUART peripheral base pointers */
32165 #define LPUART_BASE_PTRS                         { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
32166 /** Interrupt vectors for the LPUART peripheral type */
32167 #define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
32168 
32169 /*!
32170  * @}
32171  */ /* end of group LPUART_Peripheral_Access_Layer */
32172 
32173 
32174 /* ----------------------------------------------------------------------------
32175    -- OCOTP Peripheral Access Layer
32176    ---------------------------------------------------------------------------- */
32177 
32178 /*!
32179  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
32180  * @{
32181  */
32182 
32183 /** OCOTP - Register Layout Typedef */
32184 typedef struct {
32185   __IO uint32_t CTRL;                              /**< OTP Controller Control and Status Register, offset: 0x0 */
32186   __IO uint32_t CTRL_SET;                          /**< OTP Controller Control and Status Register, offset: 0x4 */
32187   __IO uint32_t CTRL_CLR;                          /**< OTP Controller Control and Status Register, offset: 0x8 */
32188   __IO uint32_t CTRL_TOG;                          /**< OTP Controller Control and Status Register, offset: 0xC */
32189   __IO uint32_t TIMING;                            /**< OTP Controller Timing Register, offset: 0x10 */
32190        uint8_t RESERVED_0[12];
32191   __IO uint32_t DATA;                              /**< OTP Controller Write Data Register, offset: 0x20 */
32192        uint8_t RESERVED_1[12];
32193   __IO uint32_t READ_CTRL;                         /**< OTP Controller Write Data Register, offset: 0x30 */
32194        uint8_t RESERVED_2[12];
32195   __IO uint32_t READ_FUSE_DATA;                    /**< OTP Controller Read Data Register, offset: 0x40 */
32196        uint8_t RESERVED_3[12];
32197   __IO uint32_t SW_STICKY;                         /**< Sticky bit Register, offset: 0x50 */
32198        uint8_t RESERVED_4[12];
32199   __IO uint32_t SCS;                               /**< Software Controllable Signals Register, offset: 0x60 */
32200   __IO uint32_t SCS_SET;                           /**< Software Controllable Signals Register, offset: 0x64 */
32201   __IO uint32_t SCS_CLR;                           /**< Software Controllable Signals Register, offset: 0x68 */
32202   __IO uint32_t SCS_TOG;                           /**< Software Controllable Signals Register, offset: 0x6C */
32203        uint8_t RESERVED_5[32];
32204   __I  uint32_t VERSION;                           /**< OTP Controller Version Register, offset: 0x90 */
32205        uint8_t RESERVED_6[108];
32206   __IO uint32_t TIMING2;                           /**< OTP Controller Timing Register 2, offset: 0x100 */
32207        uint8_t RESERVED_7[764];
32208   __IO uint32_t LOCK;                              /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
32209        uint8_t RESERVED_8[12];
32210   __IO uint32_t CFG0;                              /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */
32211        uint8_t RESERVED_9[12];
32212   __IO uint32_t CFG1;                              /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */
32213        uint8_t RESERVED_10[12];
32214   __IO uint32_t CFG2;                              /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */
32215        uint8_t RESERVED_11[12];
32216   __IO uint32_t CFG3;                              /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */
32217        uint8_t RESERVED_12[12];
32218   __IO uint32_t CFG4;                              /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */
32219        uint8_t RESERVED_13[12];
32220   __IO uint32_t CFG5;                              /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */
32221        uint8_t RESERVED_14[12];
32222   __IO uint32_t CFG6;                              /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */
32223        uint8_t RESERVED_15[12];
32224   __IO uint32_t MEM0;                              /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */
32225        uint8_t RESERVED_16[12];
32226   __IO uint32_t MEM1;                              /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */
32227        uint8_t RESERVED_17[12];
32228   __IO uint32_t MEM2;                              /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */
32229        uint8_t RESERVED_18[12];
32230   __IO uint32_t MEM3;                              /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */
32231        uint8_t RESERVED_19[12];
32232   __IO uint32_t MEM4;                              /**< Value of OTP Bank 1 Word 4 (Memory Related Info.), offset: 0x4C0 */
32233        uint8_t RESERVED_20[12];
32234   __IO uint32_t ANA0;                              /**< Value of OTP Bank 1 Word 5 (Analog Info.), offset: 0x4D0 */
32235        uint8_t RESERVED_21[12];
32236   __IO uint32_t ANA1;                              /**< Value of OTP Bank 1 Word 6 (Analog Info.), offset: 0x4E0 */
32237        uint8_t RESERVED_22[12];
32238   __IO uint32_t ANA2;                              /**< Value of OTP Bank 1 Word 7 (Analog Info.), offset: 0x4F0 */
32239        uint8_t RESERVED_23[140];
32240   __IO uint32_t SRK0;                              /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */
32241        uint8_t RESERVED_24[12];
32242   __IO uint32_t SRK1;                              /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */
32243        uint8_t RESERVED_25[12];
32244   __IO uint32_t SRK2;                              /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */
32245        uint8_t RESERVED_26[12];
32246   __IO uint32_t SRK3;                              /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */
32247        uint8_t RESERVED_27[12];
32248   __IO uint32_t SRK4;                              /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */
32249        uint8_t RESERVED_28[12];
32250   __IO uint32_t SRK5;                              /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */
32251        uint8_t RESERVED_29[12];
32252   __IO uint32_t SRK6;                              /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */
32253        uint8_t RESERVED_30[12];
32254   __IO uint32_t SRK7;                              /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */
32255        uint8_t RESERVED_31[12];
32256   __IO uint32_t SJC_RESP0;                         /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */
32257        uint8_t RESERVED_32[12];
32258   __IO uint32_t SJC_RESP1;                         /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */
32259        uint8_t RESERVED_33[12];
32260   __IO uint32_t MAC0;                              /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */
32261        uint8_t RESERVED_34[12];
32262   __IO uint32_t MAC1;                              /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */
32263        uint8_t RESERVED_35[12];
32264   __IO uint32_t GP3;                               /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */
32265        uint8_t RESERVED_36[28];
32266   __IO uint32_t GP1;                               /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */
32267        uint8_t RESERVED_37[12];
32268   __IO uint32_t GP2;                               /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */
32269        uint8_t RESERVED_38[12];
32270   __IO uint32_t SW_GP1;                            /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */
32271        uint8_t RESERVED_39[12];
32272   __IO uint32_t SW_GP20;                           /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */
32273        uint8_t RESERVED_40[12];
32274   __IO uint32_t SW_GP21;                           /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */
32275        uint8_t RESERVED_41[12];
32276   __IO uint32_t SW_GP22;                           /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */
32277        uint8_t RESERVED_42[12];
32278   __IO uint32_t SW_GP23;                           /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */
32279        uint8_t RESERVED_43[12];
32280   __IO uint32_t MISC_CONF0;                        /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */
32281        uint8_t RESERVED_44[12];
32282   __IO uint32_t MISC_CONF1;                        /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */
32283        uint8_t RESERVED_45[12];
32284   __IO uint32_t SRK_REVOKE;                        /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */
32285 } OCOTP_Type;
32286 
32287 /* ----------------------------------------------------------------------------
32288    -- OCOTP Register Masks
32289    ---------------------------------------------------------------------------- */
32290 
32291 /*!
32292  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
32293  * @{
32294  */
32295 
32296 /*! @name CTRL - OTP Controller Control and Status Register */
32297 /*! @{ */
32298 
32299 #define OCOTP_CTRL_ADDR_MASK                     (0x3FU)
32300 #define OCOTP_CTRL_ADDR_SHIFT                    (0U)
32301 /*! ADDR - OTP write and read access address register
32302  */
32303 #define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
32304 
32305 #define OCOTP_CTRL_BUSY_MASK                     (0x100U)
32306 #define OCOTP_CTRL_BUSY_SHIFT                    (8U)
32307 /*! BUSY - OTP controller status bit
32308  *  0b0..No write or read access to OTP started.
32309  *  0b1..Write or read access to OTP started.
32310  */
32311 #define OCOTP_CTRL_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
32312 
32313 #define OCOTP_CTRL_ERROR_MASK                    (0x200U)
32314 #define OCOTP_CTRL_ERROR_SHIFT                   (9U)
32315 /*! ERROR - Locked Region Access Error
32316  *  0b0..No error.
32317  *  0b1..Error - access to a locked region requested.
32318  */
32319 #define OCOTP_CTRL_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
32320 
32321 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK           (0x400U)
32322 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          (10U)
32323 /*! RELOAD_SHADOWS - Reload Shadow Registers
32324  *  0b0..Do not force shadow register re-load.
32325  *  0b1..Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded.
32326  */
32327 #define OCOTP_CTRL_RELOAD_SHADOWS(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
32328 
32329 #define OCOTP_CTRL_WR_UNLOCK_MASK                (0xFFFF0000U)
32330 #define OCOTP_CTRL_WR_UNLOCK_SHIFT               (16U)
32331 /*! WR_UNLOCK - Write Unlock
32332  *  0b0000000000000000..OTP write access is locked.
32333  *  0b0011111001110111..OTP write access is unlocked.
32334  */
32335 #define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
32336 /*! @} */
32337 
32338 /*! @name CTRL_SET - OTP Controller Control and Status Register */
32339 /*! @{ */
32340 
32341 #define OCOTP_CTRL_SET_ADDR_MASK                 (0x3FU)
32342 #define OCOTP_CTRL_SET_ADDR_SHIFT                (0U)
32343 /*! ADDR - OTP write and read access address register
32344  */
32345 #define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
32346 
32347 #define OCOTP_CTRL_SET_BUSY_MASK                 (0x100U)
32348 #define OCOTP_CTRL_SET_BUSY_SHIFT                (8U)
32349 /*! BUSY - OTP controller status bit
32350  */
32351 #define OCOTP_CTRL_SET_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
32352 
32353 #define OCOTP_CTRL_SET_ERROR_MASK                (0x200U)
32354 #define OCOTP_CTRL_SET_ERROR_SHIFT               (9U)
32355 /*! ERROR - Locked Region Access Error
32356  */
32357 #define OCOTP_CTRL_SET_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
32358 
32359 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       (0x400U)
32360 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      (10U)
32361 /*! RELOAD_SHADOWS - Reload Shadow Registers
32362  */
32363 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
32364 
32365 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK            (0xFFFF0000U)
32366 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           (16U)
32367 /*! WR_UNLOCK - Write Unlock
32368  */
32369 #define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
32370 /*! @} */
32371 
32372 /*! @name CTRL_CLR - OTP Controller Control and Status Register */
32373 /*! @{ */
32374 
32375 #define OCOTP_CTRL_CLR_ADDR_MASK                 (0x3FU)
32376 #define OCOTP_CTRL_CLR_ADDR_SHIFT                (0U)
32377 /*! ADDR - OTP write and read access address register
32378  */
32379 #define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
32380 
32381 #define OCOTP_CTRL_CLR_BUSY_MASK                 (0x100U)
32382 #define OCOTP_CTRL_CLR_BUSY_SHIFT                (8U)
32383 /*! BUSY - OTP controller status bit
32384  */
32385 #define OCOTP_CTRL_CLR_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
32386 
32387 #define OCOTP_CTRL_CLR_ERROR_MASK                (0x200U)
32388 #define OCOTP_CTRL_CLR_ERROR_SHIFT               (9U)
32389 /*! ERROR - Locked Region Access Error
32390  */
32391 #define OCOTP_CTRL_CLR_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
32392 
32393 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       (0x400U)
32394 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      (10U)
32395 /*! RELOAD_SHADOWS - Reload Shadow Registers
32396  */
32397 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
32398 
32399 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            (0xFFFF0000U)
32400 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           (16U)
32401 /*! WR_UNLOCK - Write Unlock
32402  */
32403 #define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
32404 /*! @} */
32405 
32406 /*! @name CTRL_TOG - OTP Controller Control and Status Register */
32407 /*! @{ */
32408 
32409 #define OCOTP_CTRL_TOG_ADDR_MASK                 (0x3FU)
32410 #define OCOTP_CTRL_TOG_ADDR_SHIFT                (0U)
32411 /*! ADDR - OTP write and read access address register
32412  */
32413 #define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
32414 
32415 #define OCOTP_CTRL_TOG_BUSY_MASK                 (0x100U)
32416 #define OCOTP_CTRL_TOG_BUSY_SHIFT                (8U)
32417 /*! BUSY - OTP controller status bit
32418  */
32419 #define OCOTP_CTRL_TOG_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
32420 
32421 #define OCOTP_CTRL_TOG_ERROR_MASK                (0x200U)
32422 #define OCOTP_CTRL_TOG_ERROR_SHIFT               (9U)
32423 /*! ERROR - Locked Region Access Error
32424  */
32425 #define OCOTP_CTRL_TOG_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
32426 
32427 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       (0x400U)
32428 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      (10U)
32429 /*! RELOAD_SHADOWS - Reload Shadow Registers
32430  */
32431 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
32432 
32433 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            (0xFFFF0000U)
32434 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           (16U)
32435 /*! WR_UNLOCK - Write Unlock
32436  */
32437 #define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
32438 /*! @} */
32439 
32440 /*! @name TIMING - OTP Controller Timing Register */
32441 /*! @{ */
32442 
32443 #define OCOTP_TIMING_STROBE_PROG_MASK            (0xFFFU)
32444 #define OCOTP_TIMING_STROBE_PROG_SHIFT           (0U)
32445 /*! STROBE_PROG - Write Strobe Period
32446  */
32447 #define OCOTP_TIMING_STROBE_PROG(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
32448 
32449 #define OCOTP_TIMING_RELAX_MASK                  (0xF000U)
32450 #define OCOTP_TIMING_RELAX_SHIFT                 (12U)
32451 /*! RELAX - Relax Count Value
32452  */
32453 #define OCOTP_TIMING_RELAX(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
32454 
32455 #define OCOTP_TIMING_STROBE_READ_MASK            (0x3F0000U)
32456 #define OCOTP_TIMING_STROBE_READ_SHIFT           (16U)
32457 /*! STROBE_READ - Read Strobe Period
32458  */
32459 #define OCOTP_TIMING_STROBE_READ(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
32460 
32461 #define OCOTP_TIMING_WAIT_MASK                   (0xFC00000U)
32462 #define OCOTP_TIMING_WAIT_SHIFT                  (22U)
32463 /*! WAIT - Wait Interval
32464  */
32465 #define OCOTP_TIMING_WAIT(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
32466 /*! @} */
32467 
32468 /*! @name DATA - OTP Controller Write Data Register */
32469 /*! @{ */
32470 
32471 #define OCOTP_DATA_DATA_MASK                     (0xFFFFFFFFU)
32472 #define OCOTP_DATA_DATA_SHIFT                    (0U)
32473 /*! DATA - Data
32474  */
32475 #define OCOTP_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
32476 /*! @} */
32477 
32478 /*! @name READ_CTRL - OTP Controller Write Data Register */
32479 /*! @{ */
32480 
32481 #define OCOTP_READ_CTRL_READ_FUSE_MASK           (0x1U)
32482 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT          (0U)
32483 /*! READ_FUSE - Read Fuse
32484  */
32485 #define OCOTP_READ_CTRL_READ_FUSE(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
32486 /*! @} */
32487 
32488 /*! @name READ_FUSE_DATA - OTP Controller Read Data Register */
32489 /*! @{ */
32490 
32491 #define OCOTP_READ_FUSE_DATA_DATA_MASK           (0xFFFFFFFFU)
32492 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT          (0U)
32493 /*! DATA - Data
32494  */
32495 #define OCOTP_READ_FUSE_DATA_DATA(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
32496 /*! @} */
32497 
32498 /*! @name SW_STICKY - Sticky bit Register */
32499 /*! @{ */
32500 
32501 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK     (0x2U)
32502 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT    (1U)
32503 /*! SRK_REVOKE_LOCK - SRK Revoke Lock
32504  *  0b0..The writing of this region's shadow register and OTP fuse word are not blocked.
32505  *  0b1..The writing of this region's shadow register and OTP fuse word are blocked. Once this bit is set, it is always high unless a POR is issued.
32506  */
32507 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
32508 
32509 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK   (0x4U)
32510 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT  (2U)
32511 /*! FIELD_RETURN_LOCK - Field Return Lock
32512  *  0b0..Writing to this region's shadow register and OTP fuse word are not blocked.
32513  *  0b1..Writing to this region's shadow register and OTP fuse word are blocked. Once this bit is set, it is always high unless a POR is issued.
32514  */
32515 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
32516 /*! @} */
32517 
32518 /*! @name SCS - Software Controllable Signals Register */
32519 /*! @{ */
32520 
32521 #define OCOTP_SCS_HAB_JDE_MASK                   (0x1U)
32522 #define OCOTP_SCS_HAB_JDE_SHIFT                  (0U)
32523 /*! HAB_JDE - HAB JTAG Debug Enable
32524  *  0b0..JTAG debugging is not enabled by the HAB (it may still be enabled by other mechanisms).
32525  *  0b1..JTAG debugging is enabled by the HAB (though this signal may be gated off).
32526  */
32527 #define OCOTP_SCS_HAB_JDE(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
32528 
32529 #define OCOTP_SCS_SPARE_MASK                     (0x7FFFFFFEU)
32530 #define OCOTP_SCS_SPARE_SHIFT                    (1U)
32531 /*! SPARE - Spare
32532  */
32533 #define OCOTP_SCS_SPARE(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
32534 
32535 #define OCOTP_SCS_LOCK_MASK                      (0x80000000U)
32536 #define OCOTP_SCS_LOCK_SHIFT                     (31U)
32537 /*! LOCK - Lock
32538  *  0b0..Bits in this register are unlocked.
32539  *  0b1..Bits in this register are locked. When set, all of the bits in this register are locked and can not be
32540  *       changed through SW programming. After this bit is set, it can only be cleared by a POR.
32541  */
32542 #define OCOTP_SCS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
32543 /*! @} */
32544 
32545 /*! @name SCS_SET - Software Controllable Signals Register */
32546 /*! @{ */
32547 
32548 #define OCOTP_SCS_SET_HAB_JDE_MASK               (0x1U)
32549 #define OCOTP_SCS_SET_HAB_JDE_SHIFT              (0U)
32550 /*! HAB_JDE - HAB JTAG Debug Enable
32551  */
32552 #define OCOTP_SCS_SET_HAB_JDE(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
32553 
32554 #define OCOTP_SCS_SET_SPARE_MASK                 (0x7FFFFFFEU)
32555 #define OCOTP_SCS_SET_SPARE_SHIFT                (1U)
32556 /*! SPARE - Spare
32557  */
32558 #define OCOTP_SCS_SET_SPARE(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
32559 
32560 #define OCOTP_SCS_SET_LOCK_MASK                  (0x80000000U)
32561 #define OCOTP_SCS_SET_LOCK_SHIFT                 (31U)
32562 /*! LOCK - Lock
32563  */
32564 #define OCOTP_SCS_SET_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
32565 /*! @} */
32566 
32567 /*! @name SCS_CLR - Software Controllable Signals Register */
32568 /*! @{ */
32569 
32570 #define OCOTP_SCS_CLR_HAB_JDE_MASK               (0x1U)
32571 #define OCOTP_SCS_CLR_HAB_JDE_SHIFT              (0U)
32572 /*! HAB_JDE - HAB JTAG Debug Enable
32573  */
32574 #define OCOTP_SCS_CLR_HAB_JDE(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
32575 
32576 #define OCOTP_SCS_CLR_SPARE_MASK                 (0x7FFFFFFEU)
32577 #define OCOTP_SCS_CLR_SPARE_SHIFT                (1U)
32578 /*! SPARE - Spare
32579  */
32580 #define OCOTP_SCS_CLR_SPARE(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
32581 
32582 #define OCOTP_SCS_CLR_LOCK_MASK                  (0x80000000U)
32583 #define OCOTP_SCS_CLR_LOCK_SHIFT                 (31U)
32584 /*! LOCK - Lock
32585  */
32586 #define OCOTP_SCS_CLR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
32587 /*! @} */
32588 
32589 /*! @name SCS_TOG - Software Controllable Signals Register */
32590 /*! @{ */
32591 
32592 #define OCOTP_SCS_TOG_HAB_JDE_MASK               (0x1U)
32593 #define OCOTP_SCS_TOG_HAB_JDE_SHIFT              (0U)
32594 /*! HAB_JDE - HAB JTAG Debug Enable
32595  */
32596 #define OCOTP_SCS_TOG_HAB_JDE(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
32597 
32598 #define OCOTP_SCS_TOG_SPARE_MASK                 (0x7FFFFFFEU)
32599 #define OCOTP_SCS_TOG_SPARE_SHIFT                (1U)
32600 /*! SPARE - Spare
32601  */
32602 #define OCOTP_SCS_TOG_SPARE(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
32603 
32604 #define OCOTP_SCS_TOG_LOCK_MASK                  (0x80000000U)
32605 #define OCOTP_SCS_TOG_LOCK_SHIFT                 (31U)
32606 /*! LOCK - Lock
32607  */
32608 #define OCOTP_SCS_TOG_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
32609 /*! @} */
32610 
32611 /*! @name VERSION - OTP Controller Version Register */
32612 /*! @{ */
32613 
32614 #define OCOTP_VERSION_STEP_MASK                  (0xFFFFU)
32615 #define OCOTP_VERSION_STEP_SHIFT                 (0U)
32616 /*! STEP - RTL Version Steping
32617  */
32618 #define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
32619 
32620 #define OCOTP_VERSION_MINOR_MASK                 (0xFF0000U)
32621 #define OCOTP_VERSION_MINOR_SHIFT                (16U)
32622 /*! MINOR - Minor RTL Version
32623  */
32624 #define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
32625 
32626 #define OCOTP_VERSION_MAJOR_MASK                 (0xFF000000U)
32627 #define OCOTP_VERSION_MAJOR_SHIFT                (24U)
32628 /*! MAJOR - Major RTL Version
32629  */
32630 #define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
32631 /*! @} */
32632 
32633 /*! @name TIMING2 - OTP Controller Timing Register 2 */
32634 /*! @{ */
32635 
32636 #define OCOTP_TIMING2_RELAX_PROG_MASK            (0xFFFU)
32637 #define OCOTP_TIMING2_RELAX_PROG_SHIFT           (0U)
32638 /*! RELAX_PROG - Relax Prog. count value
32639  */
32640 #define OCOTP_TIMING2_RELAX_PROG(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
32641 
32642 #define OCOTP_TIMING2_RELAX_READ_MASK            (0x3F0000U)
32643 #define OCOTP_TIMING2_RELAX_READ_SHIFT           (16U)
32644 /*! RELAX_READ - Relax Read count value
32645  */
32646 #define OCOTP_TIMING2_RELAX_READ(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
32647 /*! @} */
32648 
32649 /*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */
32650 /*! @{ */
32651 
32652 #define OCOTP_LOCK_BOOT_CFG_MASK                 (0xCU)
32653 #define OCOTP_LOCK_BOOT_CFG_SHIFT                (2U)
32654 /*! BOOT_CFG - BOOT_CFG Write Lock Status
32655  */
32656 #define OCOTP_LOCK_BOOT_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
32657 
32658 #define OCOTP_LOCK_SJC_RESP_MASK                 (0x40U)
32659 #define OCOTP_LOCK_SJC_RESP_SHIFT                (6U)
32660 /*! SJC_RESP - SJC_RESP Lock Status
32661  *  0b0..The writing or reading of this region's shadow register and OTP fuse word are not blocked.
32662  *  0b1..When set, the writing of this region's shadow register and OTP fuse word are blocked. The read of this
32663  *       region's shadow register and OTP fuse word are also blocked
32664  */
32665 #define OCOTP_LOCK_SJC_RESP(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
32666 
32667 #define OCOTP_LOCK_MAC_ADDR_MASK                 (0x300U)
32668 #define OCOTP_LOCK_MAC_ADDR_SHIFT                (8U)
32669 /*! MAC_ADDR - MAC_ADDR Write Lock Status
32670  */
32671 #define OCOTP_LOCK_MAC_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
32672 
32673 #define OCOTP_LOCK_GP1_MASK                      (0xC00U)
32674 #define OCOTP_LOCK_GP1_SHIFT                     (10U)
32675 /*! GP1 - GP1 Write Lock Status
32676  */
32677 #define OCOTP_LOCK_GP1(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
32678 
32679 #define OCOTP_LOCK_GP2_MASK                      (0x3000U)
32680 #define OCOTP_LOCK_GP2_SHIFT                     (12U)
32681 /*! GP2 - GP2 Write Lock Status
32682  */
32683 #define OCOTP_LOCK_GP2(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
32684 
32685 #define OCOTP_LOCK_SW_GP1_MASK                   (0x10000U)
32686 #define OCOTP_LOCK_SW_GP1_SHIFT                  (16U)
32687 /*! SW_GP1 - SW_GP1 Write Lock Status
32688  *  0b0..Writing of this region's shadow register and OTP fuse word are not blocked.
32689  *  0b1..When set, the writing of this region's shadow register and OTP fuse word are blocked.
32690  */
32691 #define OCOTP_LOCK_SW_GP1(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
32692 
32693 #define OCOTP_LOCK_ANALOG_MASK                   (0xC0000U)
32694 #define OCOTP_LOCK_ANALOG_SHIFT                  (18U)
32695 /*! ANALOG - ANALOG Write Lock Status
32696  */
32697 #define OCOTP_LOCK_ANALOG(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
32698 
32699 #define OCOTP_LOCK_SW_GP2_LOCK_MASK              (0x200000U)
32700 #define OCOTP_LOCK_SW_GP2_LOCK_SHIFT             (21U)
32701 /*! SW_GP2_LOCK - SW_GP2 Write Lock Status
32702  *  0b0..Writing of this region's shadow register and OTP fuse word are not blocked.
32703  *  0b1..When set, the writing of this region's shadow register and OTP fuse word are blocked.
32704  */
32705 #define OCOTP_LOCK_SW_GP2_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
32706 
32707 #define OCOTP_LOCK_MISC_CONF_MASK                (0x400000U)
32708 #define OCOTP_LOCK_MISC_CONF_SHIFT               (22U)
32709 /*! MISC_CONF - MISC_CONF Write Lock Status
32710  *  0b0..Writing of this region's shadow register and OTP fuse word are not blocked.
32711  *  0b1..When set, the writing of this region's shadow register and OTP fuse word are blocked.
32712  */
32713 #define OCOTP_LOCK_MISC_CONF(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
32714 
32715 #define OCOTP_LOCK_SW_GP2_RLOCK_MASK             (0x800000U)
32716 #define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT            (23U)
32717 /*! SW_GP2_RLOCK - SW_GP2 Read Lock Status
32718  *  0b0..The reading of this region's shadow register and OTP fuse word are not blocked.
32719  *  0b1..When set, the reading of this region's shadow register and OTP fuse word are blocked.
32720  */
32721 #define OCOTP_LOCK_SW_GP2_RLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
32722 
32723 #define OCOTP_LOCK_GP3_MASK                      (0xC000000U)
32724 #define OCOTP_LOCK_GP3_SHIFT                     (26U)
32725 /*! GP3 - GP3 Write Lock Status
32726  */
32727 #define OCOTP_LOCK_GP3(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
32728 
32729 #define OCOTP_LOCK_FIELD_RETURN_MASK             (0x80000000U)
32730 #define OCOTP_LOCK_FIELD_RETURN_SHIFT            (31U)
32731 /*! FIELD_RETURN - FIELD RETURN Status
32732  *  0b0..The device is a functional part.
32733  *  0b1..The device is a field returned part.
32734  */
32735 #define OCOTP_LOCK_FIELD_RETURN(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
32736 /*! @} */
32737 
32738 /*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */
32739 /*! @{ */
32740 
32741 #define OCOTP_CFG0_BITS_MASK                     (0xFFFFFFFFU)
32742 #define OCOTP_CFG0_BITS_SHIFT                    (0U)
32743 /*! BITS - BITS
32744  */
32745 #define OCOTP_CFG0_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
32746 /*! @} */
32747 
32748 /*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */
32749 /*! @{ */
32750 
32751 #define OCOTP_CFG1_BITS_MASK                     (0xFFFFFFFFU)
32752 #define OCOTP_CFG1_BITS_SHIFT                    (0U)
32753 /*! BITS - BITS
32754  */
32755 #define OCOTP_CFG1_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
32756 /*! @} */
32757 
32758 /*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */
32759 /*! @{ */
32760 
32761 #define OCOTP_CFG2_BITS_MASK                     (0xFFFFFFFFU)
32762 #define OCOTP_CFG2_BITS_SHIFT                    (0U)
32763 /*! BITS - BITS
32764  */
32765 #define OCOTP_CFG2_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
32766 /*! @} */
32767 
32768 /*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */
32769 /*! @{ */
32770 
32771 #define OCOTP_CFG3_BITS_MASK                     (0xFFFFFFFFU)
32772 #define OCOTP_CFG3_BITS_SHIFT                    (0U)
32773 /*! BITS - BITS
32774  */
32775 #define OCOTP_CFG3_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
32776 /*! @} */
32777 
32778 /*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */
32779 /*! @{ */
32780 
32781 #define OCOTP_CFG4_BITS_MASK                     (0xFFFFFFFFU)
32782 #define OCOTP_CFG4_BITS_SHIFT                    (0U)
32783 /*! BITS - BITS
32784  */
32785 #define OCOTP_CFG4_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
32786 /*! @} */
32787 
32788 /*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */
32789 /*! @{ */
32790 
32791 #define OCOTP_CFG5_BITS_MASK                     (0xFFFFFFFFU)
32792 #define OCOTP_CFG5_BITS_SHIFT                    (0U)
32793 /*! BITS - BITS
32794  */
32795 #define OCOTP_CFG5_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
32796 /*! @} */
32797 
32798 /*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */
32799 /*! @{ */
32800 
32801 #define OCOTP_CFG6_BITS_MASK                     (0xFFFFFFFFU)
32802 #define OCOTP_CFG6_BITS_SHIFT                    (0U)
32803 /*! BITS - BITS
32804  */
32805 #define OCOTP_CFG6_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
32806 /*! @} */
32807 
32808 /*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */
32809 /*! @{ */
32810 
32811 #define OCOTP_MEM0_BITS_MASK                     (0xFFFFFFFFU)
32812 #define OCOTP_MEM0_BITS_SHIFT                    (0U)
32813 /*! BITS - BITS
32814  */
32815 #define OCOTP_MEM0_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
32816 /*! @} */
32817 
32818 /*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */
32819 /*! @{ */
32820 
32821 #define OCOTP_MEM1_BITS_MASK                     (0xFFFFFFFFU)
32822 #define OCOTP_MEM1_BITS_SHIFT                    (0U)
32823 /*! BITS - BITS
32824  */
32825 #define OCOTP_MEM1_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
32826 /*! @} */
32827 
32828 /*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */
32829 /*! @{ */
32830 
32831 #define OCOTP_MEM2_BITS_MASK                     (0xFFFFFFFFU)
32832 #define OCOTP_MEM2_BITS_SHIFT                    (0U)
32833 /*! BITS - BITS
32834  */
32835 #define OCOTP_MEM2_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
32836 /*! @} */
32837 
32838 /*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */
32839 /*! @{ */
32840 
32841 #define OCOTP_MEM3_BITS_MASK                     (0xFFFFFFFFU)
32842 #define OCOTP_MEM3_BITS_SHIFT                    (0U)
32843 /*! BITS - BITS
32844  */
32845 #define OCOTP_MEM3_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
32846 /*! @} */
32847 
32848 /*! @name MEM4 - Value of OTP Bank 1 Word 4 (Memory Related Info.) */
32849 /*! @{ */
32850 
32851 #define OCOTP_MEM4_BITS_MASK                     (0xFFFFFFFFU)
32852 #define OCOTP_MEM4_BITS_SHIFT                    (0U)
32853 /*! BITS - BITS
32854  */
32855 #define OCOTP_MEM4_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
32856 /*! @} */
32857 
32858 /*! @name ANA0 - Value of OTP Bank 1 Word 5 (Analog Info.) */
32859 /*! @{ */
32860 
32861 #define OCOTP_ANA0_BITS_MASK                     (0xFFFFFFFFU)
32862 #define OCOTP_ANA0_BITS_SHIFT                    (0U)
32863 /*! BITS - BITS
32864  */
32865 #define OCOTP_ANA0_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
32866 /*! @} */
32867 
32868 /*! @name ANA1 - Value of OTP Bank 1 Word 6 (Analog Info.) */
32869 /*! @{ */
32870 
32871 #define OCOTP_ANA1_BITS_MASK                     (0xFFFFFFFFU)
32872 #define OCOTP_ANA1_BITS_SHIFT                    (0U)
32873 /*! BITS - BITS
32874  */
32875 #define OCOTP_ANA1_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
32876 /*! @} */
32877 
32878 /*! @name ANA2 - Value of OTP Bank 1 Word 7 (Analog Info.) */
32879 /*! @{ */
32880 
32881 #define OCOTP_ANA2_BITS_MASK                     (0xFFFFFFFFU)
32882 #define OCOTP_ANA2_BITS_SHIFT                    (0U)
32883 /*! BITS - BITS
32884  */
32885 #define OCOTP_ANA2_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
32886 /*! @} */
32887 
32888 /*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */
32889 /*! @{ */
32890 
32891 #define OCOTP_SRK0_BITS_MASK                     (0xFFFFFFFFU)
32892 #define OCOTP_SRK0_BITS_SHIFT                    (0U)
32893 /*! BITS - BITS
32894  */
32895 #define OCOTP_SRK0_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
32896 /*! @} */
32897 
32898 /*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */
32899 /*! @{ */
32900 
32901 #define OCOTP_SRK1_BITS_MASK                     (0xFFFFFFFFU)
32902 #define OCOTP_SRK1_BITS_SHIFT                    (0U)
32903 /*! BITS - BITS
32904  */
32905 #define OCOTP_SRK1_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
32906 /*! @} */
32907 
32908 /*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */
32909 /*! @{ */
32910 
32911 #define OCOTP_SRK2_BITS_MASK                     (0xFFFFFFFFU)
32912 #define OCOTP_SRK2_BITS_SHIFT                    (0U)
32913 /*! BITS - BITS
32914  */
32915 #define OCOTP_SRK2_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
32916 /*! @} */
32917 
32918 /*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */
32919 /*! @{ */
32920 
32921 #define OCOTP_SRK3_BITS_MASK                     (0xFFFFFFFFU)
32922 #define OCOTP_SRK3_BITS_SHIFT                    (0U)
32923 /*! BITS - BITS
32924  */
32925 #define OCOTP_SRK3_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
32926 /*! @} */
32927 
32928 /*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */
32929 /*! @{ */
32930 
32931 #define OCOTP_SRK4_BITS_MASK                     (0xFFFFFFFFU)
32932 #define OCOTP_SRK4_BITS_SHIFT                    (0U)
32933 /*! BITS - BITS
32934  */
32935 #define OCOTP_SRK4_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
32936 /*! @} */
32937 
32938 /*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */
32939 /*! @{ */
32940 
32941 #define OCOTP_SRK5_BITS_MASK                     (0xFFFFFFFFU)
32942 #define OCOTP_SRK5_BITS_SHIFT                    (0U)
32943 /*! BITS - BITS
32944  */
32945 #define OCOTP_SRK5_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
32946 /*! @} */
32947 
32948 /*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */
32949 /*! @{ */
32950 
32951 #define OCOTP_SRK6_BITS_MASK                     (0xFFFFFFFFU)
32952 #define OCOTP_SRK6_BITS_SHIFT                    (0U)
32953 /*! BITS - BITS
32954  */
32955 #define OCOTP_SRK6_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
32956 /*! @} */
32957 
32958 /*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */
32959 /*! @{ */
32960 
32961 #define OCOTP_SRK7_BITS_MASK                     (0xFFFFFFFFU)
32962 #define OCOTP_SRK7_BITS_SHIFT                    (0U)
32963 /*! BITS - BITS
32964  */
32965 #define OCOTP_SRK7_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
32966 /*! @} */
32967 
32968 /*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
32969 /*! @{ */
32970 
32971 #define OCOTP_SJC_RESP0_BITS_MASK                (0xFFFFFFFFU)
32972 #define OCOTP_SJC_RESP0_BITS_SHIFT               (0U)
32973 /*! BITS - BITS
32974  */
32975 #define OCOTP_SJC_RESP0_BITS(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
32976 /*! @} */
32977 
32978 /*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
32979 /*! @{ */
32980 
32981 #define OCOTP_SJC_RESP1_BITS_MASK                (0xFFFFFFFFU)
32982 #define OCOTP_SJC_RESP1_BITS_SHIFT               (0U)
32983 /*! BITS - BITS
32984  */
32985 #define OCOTP_SJC_RESP1_BITS(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
32986 /*! @} */
32987 
32988 /*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */
32989 /*! @{ */
32990 
32991 #define OCOTP_MAC0_BITS_MASK                     (0xFFFFFFFFU)
32992 #define OCOTP_MAC0_BITS_SHIFT                    (0U)
32993 /*! BITS - BITS
32994  */
32995 #define OCOTP_MAC0_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
32996 /*! @} */
32997 
32998 /*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */
32999 /*! @{ */
33000 
33001 #define OCOTP_MAC1_BITS_MASK                     (0xFFFFFFFFU)
33002 #define OCOTP_MAC1_BITS_SHIFT                    (0U)
33003 /*! BITS - BITS
33004  */
33005 #define OCOTP_MAC1_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
33006 /*! @} */
33007 
33008 /*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */
33009 /*! @{ */
33010 
33011 #define OCOTP_GP3_BITS_MASK                      (0xFFFFFFFFU)
33012 #define OCOTP_GP3_BITS_SHIFT                     (0U)
33013 /*! BITS - BITS
33014  */
33015 #define OCOTP_GP3_BITS(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)
33016 /*! @} */
33017 
33018 /*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */
33019 /*! @{ */
33020 
33021 #define OCOTP_GP1_BITS_MASK                      (0xFFFFFFFFU)
33022 #define OCOTP_GP1_BITS_SHIFT                     (0U)
33023 /*! BITS - BITS
33024  */
33025 #define OCOTP_GP1_BITS(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
33026 /*! @} */
33027 
33028 /*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */
33029 /*! @{ */
33030 
33031 #define OCOTP_GP2_BITS_MASK                      (0xFFFFFFFFU)
33032 #define OCOTP_GP2_BITS_SHIFT                     (0U)
33033 /*! BITS - BITS
33034  */
33035 #define OCOTP_GP2_BITS(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
33036 /*! @} */
33037 
33038 /*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */
33039 /*! @{ */
33040 
33041 #define OCOTP_SW_GP1_BITS_MASK                   (0xFFFFFFFFU)
33042 #define OCOTP_SW_GP1_BITS_SHIFT                  (0U)
33043 /*! BITS - BITS
33044  */
33045 #define OCOTP_SW_GP1_BITS(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
33046 /*! @} */
33047 
33048 /*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */
33049 /*! @{ */
33050 
33051 #define OCOTP_SW_GP20_BITS_MASK                  (0xFFFFFFFFU)
33052 #define OCOTP_SW_GP20_BITS_SHIFT                 (0U)
33053 /*! BITS - BITS
33054  */
33055 #define OCOTP_SW_GP20_BITS(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
33056 /*! @} */
33057 
33058 /*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */
33059 /*! @{ */
33060 
33061 #define OCOTP_SW_GP21_BITS_MASK                  (0xFFFFFFFFU)
33062 #define OCOTP_SW_GP21_BITS_SHIFT                 (0U)
33063 /*! BITS - BITS
33064  */
33065 #define OCOTP_SW_GP21_BITS(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
33066 /*! @} */
33067 
33068 /*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */
33069 /*! @{ */
33070 
33071 #define OCOTP_SW_GP22_BITS_MASK                  (0xFFFFFFFFU)
33072 #define OCOTP_SW_GP22_BITS_SHIFT                 (0U)
33073 /*! BITS - BITS
33074  */
33075 #define OCOTP_SW_GP22_BITS(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
33076 /*! @} */
33077 
33078 /*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */
33079 /*! @{ */
33080 
33081 #define OCOTP_SW_GP23_BITS_MASK                  (0xFFFFFFFFU)
33082 #define OCOTP_SW_GP23_BITS_SHIFT                 (0U)
33083 /*! BITS - BITS
33084  */
33085 #define OCOTP_SW_GP23_BITS(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
33086 /*! @} */
33087 
33088 /*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */
33089 /*! @{ */
33090 
33091 #define OCOTP_MISC_CONF0_BITS_MASK               (0xFFFFFFFFU)
33092 #define OCOTP_MISC_CONF0_BITS_SHIFT              (0U)
33093 /*! BITS - BITS
33094  */
33095 #define OCOTP_MISC_CONF0_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
33096 /*! @} */
33097 
33098 /*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */
33099 /*! @{ */
33100 
33101 #define OCOTP_MISC_CONF1_BITS_MASK               (0xFFFFFFFFU)
33102 #define OCOTP_MISC_CONF1_BITS_SHIFT              (0U)
33103 /*! BITS - BITS
33104  */
33105 #define OCOTP_MISC_CONF1_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
33106 /*! @} */
33107 
33108 /*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */
33109 /*! @{ */
33110 
33111 #define OCOTP_SRK_REVOKE_BITS_MASK               (0xFFFFFFFFU)
33112 #define OCOTP_SRK_REVOKE_BITS_SHIFT              (0U)
33113 /*! BITS - BITS
33114  */
33115 #define OCOTP_SRK_REVOKE_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
33116 /*! @} */
33117 
33118 
33119 /*!
33120  * @}
33121  */ /* end of group OCOTP_Register_Masks */
33122 
33123 
33124 /* OCOTP - Peripheral instance base addresses */
33125 /** Peripheral OCOTP base address */
33126 #define OCOTP_BASE                               (0x401F4000u)
33127 /** Peripheral OCOTP base pointer */
33128 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
33129 /** Array initializer of OCOTP peripheral base addresses */
33130 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
33131 /** Array initializer of OCOTP peripheral base pointers */
33132 #define OCOTP_BASE_PTRS                          { OCOTP }
33133 
33134 /*!
33135  * @}
33136  */ /* end of group OCOTP_Peripheral_Access_Layer */
33137 
33138 
33139 /* ----------------------------------------------------------------------------
33140    -- PGC Peripheral Access Layer
33141    ---------------------------------------------------------------------------- */
33142 
33143 /*!
33144  * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer
33145  * @{
33146  */
33147 
33148 /** PGC - Register Layout Typedef */
33149 typedef struct {
33150        uint8_t RESERVED_0[544];
33151   __IO uint32_t MEGA_CTRL;                         /**< PGC Mega Control Register, offset: 0x220 */
33152   __IO uint32_t MEGA_PUPSCR;                       /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */
33153   __IO uint32_t MEGA_PDNSCR;                       /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */
33154   __IO uint32_t MEGA_SR;                           /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */
33155        uint8_t RESERVED_1[112];
33156   __IO uint32_t CPU_CTRL;                          /**< PGC CPU Control Register, offset: 0x2A0 */
33157   __IO uint32_t CPU_PUPSCR;                        /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */
33158   __IO uint32_t CPU_PDNSCR;                        /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */
33159   __IO uint32_t CPU_SR;                            /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */
33160 } PGC_Type;
33161 
33162 /* ----------------------------------------------------------------------------
33163    -- PGC Register Masks
33164    ---------------------------------------------------------------------------- */
33165 
33166 /*!
33167  * @addtogroup PGC_Register_Masks PGC Register Masks
33168  * @{
33169  */
33170 
33171 /*! @name MEGA_CTRL - PGC Mega Control Register */
33172 /*! @{ */
33173 
33174 #define PGC_MEGA_CTRL_PCR_MASK                   (0x1U)
33175 #define PGC_MEGA_CTRL_PCR_SHIFT                  (0U)
33176 /*! PCR
33177  *  0b0..Do not switch off power even if pdn_req is asserted.
33178  *  0b1..Switch off power when pdn_req is asserted.
33179  */
33180 #define PGC_MEGA_CTRL_PCR(x)                     (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
33181 /*! @} */
33182 
33183 /*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */
33184 /*! @{ */
33185 
33186 #define PGC_MEGA_PUPSCR_SW_MASK                  (0x3FU)
33187 #define PGC_MEGA_PUPSCR_SW_SHIFT                 (0U)
33188 #define PGC_MEGA_PUPSCR_SW(x)                    (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
33189 
33190 #define PGC_MEGA_PUPSCR_SW2ISO_MASK              (0x3F00U)
33191 #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT             (8U)
33192 #define PGC_MEGA_PUPSCR_SW2ISO(x)                (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
33193 /*! @} */
33194 
33195 /*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */
33196 /*! @{ */
33197 
33198 #define PGC_MEGA_PDNSCR_ISO_MASK                 (0x3FU)
33199 #define PGC_MEGA_PDNSCR_ISO_SHIFT                (0U)
33200 #define PGC_MEGA_PDNSCR_ISO(x)                   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
33201 
33202 #define PGC_MEGA_PDNSCR_ISO2SW_MASK              (0x3F00U)
33203 #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT             (8U)
33204 #define PGC_MEGA_PDNSCR_ISO2SW(x)                (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
33205 /*! @} */
33206 
33207 /*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */
33208 /*! @{ */
33209 
33210 #define PGC_MEGA_SR_PSR_MASK                     (0x1U)
33211 #define PGC_MEGA_SR_PSR_SHIFT                    (0U)
33212 /*! PSR
33213  *  0b0..The target subsystem was not powered down for the previous power-down request.
33214  *  0b1..The target subsystem was powered down for the previous power-down request.
33215  */
33216 #define PGC_MEGA_SR_PSR(x)                       (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
33217 /*! @} */
33218 
33219 /*! @name CPU_CTRL - PGC CPU Control Register */
33220 /*! @{ */
33221 
33222 #define PGC_CPU_CTRL_PCR_MASK                    (0x1U)
33223 #define PGC_CPU_CTRL_PCR_SHIFT                   (0U)
33224 /*! PCR
33225  *  0b0..Do not switch off power even if pdn_req is asserted.
33226  *  0b1..Switch off power when pdn_req is asserted.
33227  */
33228 #define PGC_CPU_CTRL_PCR(x)                      (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
33229 /*! @} */
33230 
33231 /*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */
33232 /*! @{ */
33233 
33234 #define PGC_CPU_PUPSCR_SW_MASK                   (0x3FU)
33235 #define PGC_CPU_PUPSCR_SW_SHIFT                  (0U)
33236 #define PGC_CPU_PUPSCR_SW(x)                     (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
33237 
33238 #define PGC_CPU_PUPSCR_SW2ISO_MASK               (0x3F00U)
33239 #define PGC_CPU_PUPSCR_SW2ISO_SHIFT              (8U)
33240 #define PGC_CPU_PUPSCR_SW2ISO(x)                 (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
33241 /*! @} */
33242 
33243 /*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */
33244 /*! @{ */
33245 
33246 #define PGC_CPU_PDNSCR_ISO_MASK                  (0x3FU)
33247 #define PGC_CPU_PDNSCR_ISO_SHIFT                 (0U)
33248 #define PGC_CPU_PDNSCR_ISO(x)                    (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
33249 
33250 #define PGC_CPU_PDNSCR_ISO2SW_MASK               (0x3F00U)
33251 #define PGC_CPU_PDNSCR_ISO2SW_SHIFT              (8U)
33252 #define PGC_CPU_PDNSCR_ISO2SW(x)                 (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
33253 /*! @} */
33254 
33255 /*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */
33256 /*! @{ */
33257 
33258 #define PGC_CPU_SR_PSR_MASK                      (0x1U)
33259 #define PGC_CPU_SR_PSR_SHIFT                     (0U)
33260 /*! PSR
33261  *  0b0..The target subsystem was not powered down for the previous power-down request.
33262  *  0b1..The target subsystem was powered down for the previous power-down request.
33263  */
33264 #define PGC_CPU_SR_PSR(x)                        (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
33265 /*! @} */
33266 
33267 
33268 /*!
33269  * @}
33270  */ /* end of group PGC_Register_Masks */
33271 
33272 
33273 /* PGC - Peripheral instance base addresses */
33274 /** Peripheral PGC base address */
33275 #define PGC_BASE                                 (0x400F4000u)
33276 /** Peripheral PGC base pointer */
33277 #define PGC                                      ((PGC_Type *)PGC_BASE)
33278 /** Array initializer of PGC peripheral base addresses */
33279 #define PGC_BASE_ADDRS                           { PGC_BASE }
33280 /** Array initializer of PGC peripheral base pointers */
33281 #define PGC_BASE_PTRS                            { PGC }
33282 
33283 /*!
33284  * @}
33285  */ /* end of group PGC_Peripheral_Access_Layer */
33286 
33287 
33288 /* ----------------------------------------------------------------------------
33289    -- PIT Peripheral Access Layer
33290    ---------------------------------------------------------------------------- */
33291 
33292 /*!
33293  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
33294  * @{
33295  */
33296 
33297 /** PIT - Register Layout Typedef */
33298 typedef struct {
33299   __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
33300        uint8_t RESERVED_0[220];
33301   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
33302   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
33303        uint8_t RESERVED_1[24];
33304   struct {                                         /* offset: 0x100, array step: 0x10 */
33305     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
33306     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
33307     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
33308     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
33309   } CHANNEL[4];
33310 } PIT_Type;
33311 
33312 /* ----------------------------------------------------------------------------
33313    -- PIT Register Masks
33314    ---------------------------------------------------------------------------- */
33315 
33316 /*!
33317  * @addtogroup PIT_Register_Masks PIT Register Masks
33318  * @{
33319  */
33320 
33321 /*! @name MCR - PIT Module Control Register */
33322 /*! @{ */
33323 
33324 #define PIT_MCR_FRZ_MASK                         (0x1U)
33325 #define PIT_MCR_FRZ_SHIFT                        (0U)
33326 /*! FRZ - Freeze
33327  *  0b0..Timers continue to run in Debug mode.
33328  *  0b1..Timers are stopped in Debug mode.
33329  */
33330 #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
33331 
33332 #define PIT_MCR_MDIS_MASK                        (0x2U)
33333 #define PIT_MCR_MDIS_SHIFT                       (1U)
33334 /*! MDIS - Module Disable for PIT
33335  *  0b0..Clock for standard PIT timers is enabled.
33336  *  0b1..Clock for standard PIT timers is disabled.
33337  */
33338 #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
33339 /*! @} */
33340 
33341 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
33342 /*! @{ */
33343 
33344 #define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
33345 #define PIT_LTMR64H_LTH_SHIFT                    (0U)
33346 /*! LTH - Life Timer value
33347  */
33348 #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
33349 /*! @} */
33350 
33351 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
33352 /*! @{ */
33353 
33354 #define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
33355 #define PIT_LTMR64L_LTL_SHIFT                    (0U)
33356 /*! LTL - Life Timer value
33357  */
33358 #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
33359 /*! @} */
33360 
33361 /*! @name LDVAL - Timer Load Value Register */
33362 /*! @{ */
33363 
33364 #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
33365 #define PIT_LDVAL_TSV_SHIFT                      (0U)
33366 /*! TSV - Timer Start Value
33367  */
33368 #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
33369 /*! @} */
33370 
33371 /* The count of PIT_LDVAL */
33372 #define PIT_LDVAL_COUNT                          (4U)
33373 
33374 /*! @name CVAL - Current Timer Value Register */
33375 /*! @{ */
33376 
33377 #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
33378 #define PIT_CVAL_TVL_SHIFT                       (0U)
33379 /*! TVL - Current Timer Value
33380  */
33381 #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
33382 /*! @} */
33383 
33384 /* The count of PIT_CVAL */
33385 #define PIT_CVAL_COUNT                           (4U)
33386 
33387 /*! @name TCTRL - Timer Control Register */
33388 /*! @{ */
33389 
33390 #define PIT_TCTRL_TEN_MASK                       (0x1U)
33391 #define PIT_TCTRL_TEN_SHIFT                      (0U)
33392 /*! TEN - Timer Enable
33393  *  0b0..Timer n is disabled.
33394  *  0b1..Timer n is enabled.
33395  */
33396 #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
33397 
33398 #define PIT_TCTRL_TIE_MASK                       (0x2U)
33399 #define PIT_TCTRL_TIE_SHIFT                      (1U)
33400 /*! TIE - Timer Interrupt Enable
33401  *  0b0..Interrupt requests from Timer n are disabled.
33402  *  0b1..Interrupt is requested whenever TIF is set.
33403  */
33404 #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
33405 
33406 #define PIT_TCTRL_CHN_MASK                       (0x4U)
33407 #define PIT_TCTRL_CHN_SHIFT                      (2U)
33408 /*! CHN - Chain Mode
33409  *  0b0..Timer is not chained.
33410  *  0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.
33411  */
33412 #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
33413 /*! @} */
33414 
33415 /* The count of PIT_TCTRL */
33416 #define PIT_TCTRL_COUNT                          (4U)
33417 
33418 /*! @name TFLG - Timer Flag Register */
33419 /*! @{ */
33420 
33421 #define PIT_TFLG_TIF_MASK                        (0x1U)
33422 #define PIT_TFLG_TIF_SHIFT                       (0U)
33423 /*! TIF - Timer Interrupt Flag
33424  *  0b0..Timeout has not yet occurred.
33425  *  0b1..Timeout has occurred.
33426  */
33427 #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
33428 /*! @} */
33429 
33430 /* The count of PIT_TFLG */
33431 #define PIT_TFLG_COUNT                           (4U)
33432 
33433 
33434 /*!
33435  * @}
33436  */ /* end of group PIT_Register_Masks */
33437 
33438 
33439 /* PIT - Peripheral instance base addresses */
33440 /** Peripheral PIT base address */
33441 #define PIT_BASE                                 (0x40084000u)
33442 /** Peripheral PIT base pointer */
33443 #define PIT                                      ((PIT_Type *)PIT_BASE)
33444 /** Array initializer of PIT peripheral base addresses */
33445 #define PIT_BASE_ADDRS                           { PIT_BASE }
33446 /** Array initializer of PIT peripheral base pointers */
33447 #define PIT_BASE_PTRS                            { PIT }
33448 /** Interrupt vectors for the PIT peripheral type */
33449 #define PIT_IRQS                                 { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
33450 
33451 /*!
33452  * @}
33453  */ /* end of group PIT_Peripheral_Access_Layer */
33454 
33455 
33456 /* ----------------------------------------------------------------------------
33457    -- PMU Peripheral Access Layer
33458    ---------------------------------------------------------------------------- */
33459 
33460 /*!
33461  * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
33462  * @{
33463  */
33464 
33465 /** PMU - Register Layout Typedef */
33466 typedef struct {
33467        uint8_t RESERVED_0[272];
33468   __IO uint32_t REG_1P1;                           /**< Regulator 1P1 Register, offset: 0x110 */
33469   __IO uint32_t REG_1P1_SET;                       /**< Regulator 1P1 Register, offset: 0x114 */
33470   __IO uint32_t REG_1P1_CLR;                       /**< Regulator 1P1 Register, offset: 0x118 */
33471   __IO uint32_t REG_1P1_TOG;                       /**< Regulator 1P1 Register, offset: 0x11C */
33472   __IO uint32_t REG_3P0;                           /**< Regulator 3P0 Register, offset: 0x120 */
33473   __IO uint32_t REG_3P0_SET;                       /**< Regulator 3P0 Register, offset: 0x124 */
33474   __IO uint32_t REG_3P0_CLR;                       /**< Regulator 3P0 Register, offset: 0x128 */
33475   __IO uint32_t REG_3P0_TOG;                       /**< Regulator 3P0 Register, offset: 0x12C */
33476   __IO uint32_t REG_2P5;                           /**< Regulator 2P5 Register, offset: 0x130 */
33477   __IO uint32_t REG_2P5_SET;                       /**< Regulator 2P5 Register, offset: 0x134 */
33478   __IO uint32_t REG_2P5_CLR;                       /**< Regulator 2P5 Register, offset: 0x138 */
33479   __IO uint32_t REG_2P5_TOG;                       /**< Regulator 2P5 Register, offset: 0x13C */
33480   __IO uint32_t REG_CORE;                          /**< Digital Regulator Core Register, offset: 0x140 */
33481   __IO uint32_t REG_CORE_SET;                      /**< Digital Regulator Core Register, offset: 0x144 */
33482   __IO uint32_t REG_CORE_CLR;                      /**< Digital Regulator Core Register, offset: 0x148 */
33483   __IO uint32_t REG_CORE_TOG;                      /**< Digital Regulator Core Register, offset: 0x14C */
33484   __IO uint32_t MISC0;                             /**< Miscellaneous Register 0, offset: 0x150 */
33485   __IO uint32_t MISC0_SET;                         /**< Miscellaneous Register 0, offset: 0x154 */
33486   __IO uint32_t MISC0_CLR;                         /**< Miscellaneous Register 0, offset: 0x158 */
33487   __IO uint32_t MISC0_TOG;                         /**< Miscellaneous Register 0, offset: 0x15C */
33488   __IO uint32_t MISC1;                             /**< Miscellaneous Register 1, offset: 0x160 */
33489   __IO uint32_t MISC1_SET;                         /**< Miscellaneous Register 1, offset: 0x164 */
33490   __IO uint32_t MISC1_CLR;                         /**< Miscellaneous Register 1, offset: 0x168 */
33491   __IO uint32_t MISC1_TOG;                         /**< Miscellaneous Register 1, offset: 0x16C */
33492   __IO uint32_t MISC2;                             /**< Miscellaneous Control Register, offset: 0x170 */
33493   __IO uint32_t MISC2_SET;                         /**< Miscellaneous Control Register, offset: 0x174 */
33494   __IO uint32_t MISC2_CLR;                         /**< Miscellaneous Control Register, offset: 0x178 */
33495   __IO uint32_t MISC2_TOG;                         /**< Miscellaneous Control Register, offset: 0x17C */
33496 } PMU_Type;
33497 
33498 /* ----------------------------------------------------------------------------
33499    -- PMU Register Masks
33500    ---------------------------------------------------------------------------- */
33501 
33502 /*!
33503  * @addtogroup PMU_Register_Masks PMU Register Masks
33504  * @{
33505  */
33506 
33507 /*! @name REG_1P1 - Regulator 1P1 Register */
33508 /*! @{ */
33509 
33510 #define PMU_REG_1P1_ENABLE_LINREG_MASK           (0x1U)
33511 #define PMU_REG_1P1_ENABLE_LINREG_SHIFT          (0U)
33512 #define PMU_REG_1P1_ENABLE_LINREG(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
33513 
33514 #define PMU_REG_1P1_ENABLE_BO_MASK               (0x2U)
33515 #define PMU_REG_1P1_ENABLE_BO_SHIFT              (1U)
33516 #define PMU_REG_1P1_ENABLE_BO(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
33517 
33518 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK           (0x4U)
33519 #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT          (2U)
33520 #define PMU_REG_1P1_ENABLE_ILIMIT(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
33521 
33522 #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK         (0x8U)
33523 #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT        (3U)
33524 #define PMU_REG_1P1_ENABLE_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
33525 
33526 #define PMU_REG_1P1_BO_OFFSET_MASK               (0x70U)
33527 #define PMU_REG_1P1_BO_OFFSET_SHIFT              (4U)
33528 #define PMU_REG_1P1_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
33529 
33530 #define PMU_REG_1P1_OUTPUT_TRG_MASK              (0x1F00U)
33531 #define PMU_REG_1P1_OUTPUT_TRG_SHIFT             (8U)
33532 /*! OUTPUT_TRG
33533  *  0b00100..0.8V
33534  *  0b10000..1.1V
33535  *  0b000x1..1.375V
33536  */
33537 #define PMU_REG_1P1_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
33538 
33539 #define PMU_REG_1P1_BO_VDD1P1_MASK               (0x10000U)
33540 #define PMU_REG_1P1_BO_VDD1P1_SHIFT              (16U)
33541 #define PMU_REG_1P1_BO_VDD1P1(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
33542 
33543 #define PMU_REG_1P1_OK_VDD1P1_MASK               (0x20000U)
33544 #define PMU_REG_1P1_OK_VDD1P1_SHIFT              (17U)
33545 #define PMU_REG_1P1_OK_VDD1P1(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
33546 
33547 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK      (0x40000U)
33548 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT     (18U)
33549 #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
33550 
33551 #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK      (0x80000U)
33552 #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT     (19U)
33553 /*! SELREF_WEAK_LINREG
33554  *  0b0..Weak-linreg output tracks low-power-bandgap voltage
33555  *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
33556  */
33557 #define PMU_REG_1P1_SELREF_WEAK_LINREG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
33558 /*! @} */
33559 
33560 /*! @name REG_1P1_SET - Regulator 1P1 Register */
33561 /*! @{ */
33562 
33563 #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK       (0x1U)
33564 #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT      (0U)
33565 #define PMU_REG_1P1_SET_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
33566 
33567 #define PMU_REG_1P1_SET_ENABLE_BO_MASK           (0x2U)
33568 #define PMU_REG_1P1_SET_ENABLE_BO_SHIFT          (1U)
33569 #define PMU_REG_1P1_SET_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
33570 
33571 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK       (0x4U)
33572 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT      (2U)
33573 #define PMU_REG_1P1_SET_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
33574 
33575 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK     (0x8U)
33576 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT    (3U)
33577 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
33578 
33579 #define PMU_REG_1P1_SET_BO_OFFSET_MASK           (0x70U)
33580 #define PMU_REG_1P1_SET_BO_OFFSET_SHIFT          (4U)
33581 #define PMU_REG_1P1_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
33582 
33583 #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK          (0x1F00U)
33584 #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT         (8U)
33585 /*! OUTPUT_TRG
33586  *  0b00100..0.8V
33587  *  0b10000..1.1V
33588  *  0b000x1..1.375V
33589  */
33590 #define PMU_REG_1P1_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
33591 
33592 #define PMU_REG_1P1_SET_BO_VDD1P1_MASK           (0x10000U)
33593 #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT          (16U)
33594 #define PMU_REG_1P1_SET_BO_VDD1P1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
33595 
33596 #define PMU_REG_1P1_SET_OK_VDD1P1_MASK           (0x20000U)
33597 #define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT          (17U)
33598 #define PMU_REG_1P1_SET_OK_VDD1P1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
33599 
33600 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK  (0x40000U)
33601 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
33602 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
33603 
33604 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK  (0x80000U)
33605 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
33606 /*! SELREF_WEAK_LINREG
33607  *  0b0..Weak-linreg output tracks low-power-bandgap voltage
33608  *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
33609  */
33610 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
33611 /*! @} */
33612 
33613 /*! @name REG_1P1_CLR - Regulator 1P1 Register */
33614 /*! @{ */
33615 
33616 #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK       (0x1U)
33617 #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT      (0U)
33618 #define PMU_REG_1P1_CLR_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
33619 
33620 #define PMU_REG_1P1_CLR_ENABLE_BO_MASK           (0x2U)
33621 #define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT          (1U)
33622 #define PMU_REG_1P1_CLR_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
33623 
33624 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK       (0x4U)
33625 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT      (2U)
33626 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
33627 
33628 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK     (0x8U)
33629 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT    (3U)
33630 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
33631 
33632 #define PMU_REG_1P1_CLR_BO_OFFSET_MASK           (0x70U)
33633 #define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT          (4U)
33634 #define PMU_REG_1P1_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
33635 
33636 #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK          (0x1F00U)
33637 #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT         (8U)
33638 /*! OUTPUT_TRG
33639  *  0b00100..0.8V
33640  *  0b10000..1.1V
33641  *  0b000x1..1.375V
33642  */
33643 #define PMU_REG_1P1_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
33644 
33645 #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK           (0x10000U)
33646 #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT          (16U)
33647 #define PMU_REG_1P1_CLR_BO_VDD1P1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
33648 
33649 #define PMU_REG_1P1_CLR_OK_VDD1P1_MASK           (0x20000U)
33650 #define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT          (17U)
33651 #define PMU_REG_1P1_CLR_OK_VDD1P1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
33652 
33653 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK  (0x40000U)
33654 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
33655 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
33656 
33657 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK  (0x80000U)
33658 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
33659 /*! SELREF_WEAK_LINREG
33660  *  0b0..Weak-linreg output tracks low-power-bandgap voltage
33661  *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
33662  */
33663 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
33664 /*! @} */
33665 
33666 /*! @name REG_1P1_TOG - Regulator 1P1 Register */
33667 /*! @{ */
33668 
33669 #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK       (0x1U)
33670 #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT      (0U)
33671 #define PMU_REG_1P1_TOG_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
33672 
33673 #define PMU_REG_1P1_TOG_ENABLE_BO_MASK           (0x2U)
33674 #define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT          (1U)
33675 #define PMU_REG_1P1_TOG_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
33676 
33677 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK       (0x4U)
33678 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT      (2U)
33679 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
33680 
33681 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK     (0x8U)
33682 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT    (3U)
33683 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
33684 
33685 #define PMU_REG_1P1_TOG_BO_OFFSET_MASK           (0x70U)
33686 #define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT          (4U)
33687 #define PMU_REG_1P1_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
33688 
33689 #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK          (0x1F00U)
33690 #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT         (8U)
33691 /*! OUTPUT_TRG
33692  *  0b00100..0.8V
33693  *  0b10000..1.1V
33694  *  0b000x1..1.375V
33695  */
33696 #define PMU_REG_1P1_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
33697 
33698 #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK           (0x10000U)
33699 #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT          (16U)
33700 #define PMU_REG_1P1_TOG_BO_VDD1P1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
33701 
33702 #define PMU_REG_1P1_TOG_OK_VDD1P1_MASK           (0x20000U)
33703 #define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT          (17U)
33704 #define PMU_REG_1P1_TOG_OK_VDD1P1(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
33705 
33706 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK  (0x40000U)
33707 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
33708 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
33709 
33710 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK  (0x80000U)
33711 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
33712 /*! SELREF_WEAK_LINREG
33713  *  0b0..Weak-linreg output tracks low-power-bandgap voltage
33714  *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
33715  */
33716 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
33717 /*! @} */
33718 
33719 /*! @name REG_3P0 - Regulator 3P0 Register */
33720 /*! @{ */
33721 
33722 #define PMU_REG_3P0_ENABLE_LINREG_MASK           (0x1U)
33723 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT          (0U)
33724 #define PMU_REG_3P0_ENABLE_LINREG(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
33725 
33726 #define PMU_REG_3P0_ENABLE_BO_MASK               (0x2U)
33727 #define PMU_REG_3P0_ENABLE_BO_SHIFT              (1U)
33728 #define PMU_REG_3P0_ENABLE_BO(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
33729 
33730 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK           (0x4U)
33731 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT          (2U)
33732 #define PMU_REG_3P0_ENABLE_ILIMIT(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
33733 
33734 #define PMU_REG_3P0_BO_OFFSET_MASK               (0x70U)
33735 #define PMU_REG_3P0_BO_OFFSET_SHIFT              (4U)
33736 #define PMU_REG_3P0_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
33737 
33738 #define PMU_REG_3P0_VBUS_SEL_MASK                (0x80U)
33739 #define PMU_REG_3P0_VBUS_SEL_SHIFT               (7U)
33740 /*! VBUS_SEL
33741  *  0b1..Utilize VBUS OTG1 power
33742  *  0b0..Utilize VBUS OTG2 power
33743  */
33744 #define PMU_REG_3P0_VBUS_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
33745 
33746 #define PMU_REG_3P0_OUTPUT_TRG_MASK              (0x1F00U)
33747 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT             (8U)
33748 /*! OUTPUT_TRG
33749  *  0b00000..2.625V
33750  *  0b01111..3.000V
33751  *  0b11111..3.400V
33752  */
33753 #define PMU_REG_3P0_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
33754 
33755 #define PMU_REG_3P0_BO_VDD3P0_MASK               (0x10000U)
33756 #define PMU_REG_3P0_BO_VDD3P0_SHIFT              (16U)
33757 #define PMU_REG_3P0_BO_VDD3P0(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
33758 
33759 #define PMU_REG_3P0_OK_VDD3P0_MASK               (0x20000U)
33760 #define PMU_REG_3P0_OK_VDD3P0_SHIFT              (17U)
33761 #define PMU_REG_3P0_OK_VDD3P0(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
33762 /*! @} */
33763 
33764 /*! @name REG_3P0_SET - Regulator 3P0 Register */
33765 /*! @{ */
33766 
33767 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK       (0x1U)
33768 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT      (0U)
33769 #define PMU_REG_3P0_SET_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
33770 
33771 #define PMU_REG_3P0_SET_ENABLE_BO_MASK           (0x2U)
33772 #define PMU_REG_3P0_SET_ENABLE_BO_SHIFT          (1U)
33773 #define PMU_REG_3P0_SET_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
33774 
33775 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK       (0x4U)
33776 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT      (2U)
33777 #define PMU_REG_3P0_SET_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
33778 
33779 #define PMU_REG_3P0_SET_BO_OFFSET_MASK           (0x70U)
33780 #define PMU_REG_3P0_SET_BO_OFFSET_SHIFT          (4U)
33781 #define PMU_REG_3P0_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
33782 
33783 #define PMU_REG_3P0_SET_VBUS_SEL_MASK            (0x80U)
33784 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT           (7U)
33785 /*! VBUS_SEL
33786  *  0b1..Utilize VBUS OTG1 power
33787  *  0b0..Utilize VBUS OTG2 power
33788  */
33789 #define PMU_REG_3P0_SET_VBUS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
33790 
33791 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK          (0x1F00U)
33792 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT         (8U)
33793 /*! OUTPUT_TRG
33794  *  0b00000..2.625V
33795  *  0b01111..3.000V
33796  *  0b11111..3.400V
33797  */
33798 #define PMU_REG_3P0_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
33799 
33800 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK           (0x10000U)
33801 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT          (16U)
33802 #define PMU_REG_3P0_SET_BO_VDD3P0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
33803 
33804 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK           (0x20000U)
33805 #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT          (17U)
33806 #define PMU_REG_3P0_SET_OK_VDD3P0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
33807 /*! @} */
33808 
33809 /*! @name REG_3P0_CLR - Regulator 3P0 Register */
33810 /*! @{ */
33811 
33812 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK       (0x1U)
33813 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT      (0U)
33814 #define PMU_REG_3P0_CLR_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
33815 
33816 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK           (0x2U)
33817 #define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT          (1U)
33818 #define PMU_REG_3P0_CLR_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
33819 
33820 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK       (0x4U)
33821 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT      (2U)
33822 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
33823 
33824 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK           (0x70U)
33825 #define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT          (4U)
33826 #define PMU_REG_3P0_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
33827 
33828 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK            (0x80U)
33829 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT           (7U)
33830 /*! VBUS_SEL
33831  *  0b1..Utilize VBUS OTG1 power
33832  *  0b0..Utilize VBUS OTG2 power
33833  */
33834 #define PMU_REG_3P0_CLR_VBUS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
33835 
33836 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK          (0x1F00U)
33837 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT         (8U)
33838 /*! OUTPUT_TRG
33839  *  0b00000..2.625V
33840  *  0b01111..3.000V
33841  *  0b11111..3.400V
33842  */
33843 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
33844 
33845 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK           (0x10000U)
33846 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT          (16U)
33847 #define PMU_REG_3P0_CLR_BO_VDD3P0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
33848 
33849 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK           (0x20000U)
33850 #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT          (17U)
33851 #define PMU_REG_3P0_CLR_OK_VDD3P0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
33852 /*! @} */
33853 
33854 /*! @name REG_3P0_TOG - Regulator 3P0 Register */
33855 /*! @{ */
33856 
33857 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK       (0x1U)
33858 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT      (0U)
33859 #define PMU_REG_3P0_TOG_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
33860 
33861 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK           (0x2U)
33862 #define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT          (1U)
33863 #define PMU_REG_3P0_TOG_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
33864 
33865 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK       (0x4U)
33866 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT      (2U)
33867 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
33868 
33869 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK           (0x70U)
33870 #define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT          (4U)
33871 #define PMU_REG_3P0_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
33872 
33873 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK            (0x80U)
33874 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT           (7U)
33875 /*! VBUS_SEL
33876  *  0b1..Utilize VBUS OTG1 power
33877  *  0b0..Utilize VBUS OTG2 power
33878  */
33879 #define PMU_REG_3P0_TOG_VBUS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
33880 
33881 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK          (0x1F00U)
33882 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT         (8U)
33883 /*! OUTPUT_TRG
33884  *  0b00000..2.625V
33885  *  0b01111..3.000V
33886  *  0b11111..3.400V
33887  */
33888 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
33889 
33890 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK           (0x10000U)
33891 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT          (16U)
33892 #define PMU_REG_3P0_TOG_BO_VDD3P0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
33893 
33894 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK           (0x20000U)
33895 #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT          (17U)
33896 #define PMU_REG_3P0_TOG_OK_VDD3P0(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
33897 /*! @} */
33898 
33899 /*! @name REG_2P5 - Regulator 2P5 Register */
33900 /*! @{ */
33901 
33902 #define PMU_REG_2P5_ENABLE_LINREG_MASK           (0x1U)
33903 #define PMU_REG_2P5_ENABLE_LINREG_SHIFT          (0U)
33904 #define PMU_REG_2P5_ENABLE_LINREG(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
33905 
33906 #define PMU_REG_2P5_ENABLE_BO_MASK               (0x2U)
33907 #define PMU_REG_2P5_ENABLE_BO_SHIFT              (1U)
33908 #define PMU_REG_2P5_ENABLE_BO(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
33909 
33910 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK           (0x4U)
33911 #define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT          (2U)
33912 #define PMU_REG_2P5_ENABLE_ILIMIT(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
33913 
33914 #define PMU_REG_2P5_ENABLE_PULLDOWN_MASK         (0x8U)
33915 #define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT        (3U)
33916 #define PMU_REG_2P5_ENABLE_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
33917 
33918 #define PMU_REG_2P5_BO_OFFSET_MASK               (0x70U)
33919 #define PMU_REG_2P5_BO_OFFSET_SHIFT              (4U)
33920 #define PMU_REG_2P5_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
33921 
33922 #define PMU_REG_2P5_OUTPUT_TRG_MASK              (0x1F00U)
33923 #define PMU_REG_2P5_OUTPUT_TRG_SHIFT             (8U)
33924 /*! OUTPUT_TRG
33925  *  0b00000..2.10V
33926  *  0b10000..2.50V
33927  *  0b11111..2.875V
33928  */
33929 #define PMU_REG_2P5_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
33930 
33931 #define PMU_REG_2P5_BO_VDD2P5_MASK               (0x10000U)
33932 #define PMU_REG_2P5_BO_VDD2P5_SHIFT              (16U)
33933 #define PMU_REG_2P5_BO_VDD2P5(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
33934 
33935 #define PMU_REG_2P5_OK_VDD2P5_MASK               (0x20000U)
33936 #define PMU_REG_2P5_OK_VDD2P5_SHIFT              (17U)
33937 #define PMU_REG_2P5_OK_VDD2P5(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
33938 
33939 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK      (0x40000U)
33940 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT     (18U)
33941 #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
33942 /*! @} */
33943 
33944 /*! @name REG_2P5_SET - Regulator 2P5 Register */
33945 /*! @{ */
33946 
33947 #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK       (0x1U)
33948 #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT      (0U)
33949 #define PMU_REG_2P5_SET_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
33950 
33951 #define PMU_REG_2P5_SET_ENABLE_BO_MASK           (0x2U)
33952 #define PMU_REG_2P5_SET_ENABLE_BO_SHIFT          (1U)
33953 #define PMU_REG_2P5_SET_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
33954 
33955 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK       (0x4U)
33956 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT      (2U)
33957 #define PMU_REG_2P5_SET_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
33958 
33959 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK     (0x8U)
33960 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT    (3U)
33961 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
33962 
33963 #define PMU_REG_2P5_SET_BO_OFFSET_MASK           (0x70U)
33964 #define PMU_REG_2P5_SET_BO_OFFSET_SHIFT          (4U)
33965 #define PMU_REG_2P5_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
33966 
33967 #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK          (0x1F00U)
33968 #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT         (8U)
33969 /*! OUTPUT_TRG
33970  *  0b00000..2.10V
33971  *  0b10000..2.50V
33972  *  0b11111..2.875V
33973  */
33974 #define PMU_REG_2P5_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
33975 
33976 #define PMU_REG_2P5_SET_BO_VDD2P5_MASK           (0x10000U)
33977 #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT          (16U)
33978 #define PMU_REG_2P5_SET_BO_VDD2P5(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
33979 
33980 #define PMU_REG_2P5_SET_OK_VDD2P5_MASK           (0x20000U)
33981 #define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT          (17U)
33982 #define PMU_REG_2P5_SET_OK_VDD2P5(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
33983 
33984 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK  (0x40000U)
33985 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
33986 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
33987 /*! @} */
33988 
33989 /*! @name REG_2P5_CLR - Regulator 2P5 Register */
33990 /*! @{ */
33991 
33992 #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK       (0x1U)
33993 #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT      (0U)
33994 #define PMU_REG_2P5_CLR_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
33995 
33996 #define PMU_REG_2P5_CLR_ENABLE_BO_MASK           (0x2U)
33997 #define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT          (1U)
33998 #define PMU_REG_2P5_CLR_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
33999 
34000 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK       (0x4U)
34001 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT      (2U)
34002 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
34003 
34004 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK     (0x8U)
34005 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT    (3U)
34006 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
34007 
34008 #define PMU_REG_2P5_CLR_BO_OFFSET_MASK           (0x70U)
34009 #define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT          (4U)
34010 #define PMU_REG_2P5_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
34011 
34012 #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK          (0x1F00U)
34013 #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT         (8U)
34014 /*! OUTPUT_TRG
34015  *  0b00000..2.10V
34016  *  0b10000..2.50V
34017  *  0b11111..2.875V
34018  */
34019 #define PMU_REG_2P5_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
34020 
34021 #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK           (0x10000U)
34022 #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT          (16U)
34023 #define PMU_REG_2P5_CLR_BO_VDD2P5(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
34024 
34025 #define PMU_REG_2P5_CLR_OK_VDD2P5_MASK           (0x20000U)
34026 #define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT          (17U)
34027 #define PMU_REG_2P5_CLR_OK_VDD2P5(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
34028 
34029 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK  (0x40000U)
34030 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
34031 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
34032 /*! @} */
34033 
34034 /*! @name REG_2P5_TOG - Regulator 2P5 Register */
34035 /*! @{ */
34036 
34037 #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK       (0x1U)
34038 #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT      (0U)
34039 #define PMU_REG_2P5_TOG_ENABLE_LINREG(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
34040 
34041 #define PMU_REG_2P5_TOG_ENABLE_BO_MASK           (0x2U)
34042 #define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT          (1U)
34043 #define PMU_REG_2P5_TOG_ENABLE_BO(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
34044 
34045 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK       (0x4U)
34046 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT      (2U)
34047 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x)         (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
34048 
34049 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK     (0x8U)
34050 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT    (3U)
34051 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
34052 
34053 #define PMU_REG_2P5_TOG_BO_OFFSET_MASK           (0x70U)
34054 #define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT          (4U)
34055 #define PMU_REG_2P5_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
34056 
34057 #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK          (0x1F00U)
34058 #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT         (8U)
34059 /*! OUTPUT_TRG
34060  *  0b00000..2.10V
34061  *  0b10000..2.50V
34062  *  0b11111..2.875V
34063  */
34064 #define PMU_REG_2P5_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
34065 
34066 #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK           (0x10000U)
34067 #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT          (16U)
34068 #define PMU_REG_2P5_TOG_BO_VDD2P5(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
34069 
34070 #define PMU_REG_2P5_TOG_OK_VDD2P5_MASK           (0x20000U)
34071 #define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT          (17U)
34072 #define PMU_REG_2P5_TOG_OK_VDD2P5(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
34073 
34074 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK  (0x40000U)
34075 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
34076 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
34077 /*! @} */
34078 
34079 /*! @name REG_CORE - Digital Regulator Core Register */
34080 /*! @{ */
34081 
34082 #define PMU_REG_CORE_REG0_TARG_MASK              (0x1FU)
34083 #define PMU_REG_CORE_REG0_TARG_SHIFT             (0U)
34084 /*! REG0_TARG
34085  *  0b00000..Power gated off
34086  *  0b00001..Target core voltage = 0.725V
34087  *  0b00010..Target core voltage = 0.750V
34088  *  0b00011..Target core voltage = 0.775V
34089  *  0b10000..Target core voltage = 1.100V
34090  *  0b11110..Target core voltage = 1.450V
34091  *  0b11111..Power FET switched full on. No regulation.
34092  */
34093 #define PMU_REG_CORE_REG0_TARG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
34094 
34095 #define PMU_REG_CORE_REG0_ADJ_MASK               (0x1E0U)
34096 #define PMU_REG_CORE_REG0_ADJ_SHIFT              (5U)
34097 /*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
34098  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34099  *    register.
34100  *  0b0000..No adjustment
34101  *  0b0001..+ 0.25%
34102  *  0b0010..+ 0.50%
34103  *  0b0011..+ 0.75%
34104  *  0b0100..+ 1.00%
34105  *  0b0101..+ 1.25%
34106  *  0b0110..+ 1.50%
34107  *  0b0111..+ 1.75%
34108  *  0b1000..- 0.25%
34109  *  0b1001..- 0.50%
34110  *  0b1010..- 0.75%
34111  *  0b1011..- 1.00%
34112  *  0b1100..- 1.25%
34113  *  0b1101..- 1.50%
34114  *  0b1110..- 1.75%
34115  *  0b1111..- 2.00%
34116  */
34117 #define PMU_REG_CORE_REG0_ADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
34118 
34119 #define PMU_REG_CORE_REG1_TARG_MASK              (0x3E00U)
34120 #define PMU_REG_CORE_REG1_TARG_SHIFT             (9U)
34121 /*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
34122  *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
34123  *    of input supply limitations or load operation.
34124  *  0b00000..Power gated off
34125  *  0b00001..Target core voltage = 0.725V
34126  *  0b00010..Target core voltage = 0.750V
34127  *  0b00011..Target core voltage = 0.775V
34128  *  0b10000..Target core voltage = 1.100V
34129  *  0b11110..Target core voltage = 1.450V
34130  *  0b11111..Power FET switched full on. No regulation.
34131  */
34132 #define PMU_REG_CORE_REG1_TARG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
34133 
34134 #define PMU_REG_CORE_REG1_ADJ_MASK               (0x3C000U)
34135 #define PMU_REG_CORE_REG1_ADJ_SHIFT              (14U)
34136 /*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
34137  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34138  *    register.
34139  *  0b0000..No adjustment
34140  *  0b0001..+ 0.25%
34141  *  0b0010..+ 0.50%
34142  *  0b0011..+ 0.75%
34143  *  0b0100..+ 1.00%
34144  *  0b0101..+ 1.25%
34145  *  0b0110..+ 1.50%
34146  *  0b0111..+ 1.75%
34147  *  0b1000..- 0.25%
34148  *  0b1001..- 0.50%
34149  *  0b1010..- 0.75%
34150  *  0b1011..- 1.00%
34151  *  0b1100..- 1.25%
34152  *  0b1101..- 1.50%
34153  *  0b1110..- 1.75%
34154  *  0b1111..- 2.00%
34155  */
34156 #define PMU_REG_CORE_REG1_ADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
34157 
34158 #define PMU_REG_CORE_REG2_TARG_MASK              (0x7C0000U)
34159 #define PMU_REG_CORE_REG2_TARG_SHIFT             (18U)
34160 /*! REG2_TARG
34161  *  0b00000..Power gated off
34162  *  0b00001..Target core voltage = 0.725V
34163  *  0b00010..Target core voltage = 0.750V
34164  *  0b00011..Target core voltage = 0.775V
34165  *  0b10000..Target core voltage = 1.100V
34166  *  0b11110..Target core voltage = 1.450V
34167  *  0b11111..Power FET switched full on. No regulation.
34168  */
34169 #define PMU_REG_CORE_REG2_TARG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
34170 
34171 #define PMU_REG_CORE_REG2_ADJ_MASK               (0x7800000U)
34172 #define PMU_REG_CORE_REG2_ADJ_SHIFT              (23U)
34173 /*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
34174  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34175  *    register.
34176  *  0b0000..No adjustment
34177  *  0b0001..+ 0.25%
34178  *  0b0010..+ 0.50%
34179  *  0b0011..+ 0.75%
34180  *  0b0100..+ 1.00%
34181  *  0b0101..+ 1.25%
34182  *  0b0110..+ 1.50%
34183  *  0b0111..+ 1.75%
34184  *  0b1000..- 0.25%
34185  *  0b1001..- 0.50%
34186  *  0b1010..- 0.75%
34187  *  0b1011..- 1.00%
34188  *  0b1100..- 1.25%
34189  *  0b1101..- 1.50%
34190  *  0b1110..- 1.75%
34191  *  0b1111..- 2.00%
34192  */
34193 #define PMU_REG_CORE_REG2_ADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
34194 
34195 #define PMU_REG_CORE_RAMP_RATE_MASK              (0x18000000U)
34196 #define PMU_REG_CORE_RAMP_RATE_SHIFT             (27U)
34197 /*! RAMP_RATE
34198  *  0b00..Fast
34199  *  0b01..Medium Fast
34200  *  0b10..Medium Slow
34201  *  0b11..Slow
34202  */
34203 #define PMU_REG_CORE_RAMP_RATE(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
34204 
34205 #define PMU_REG_CORE_FET_ODRIVE_MASK             (0x20000000U)
34206 #define PMU_REG_CORE_FET_ODRIVE_SHIFT            (29U)
34207 #define PMU_REG_CORE_FET_ODRIVE(x)               (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
34208 /*! @} */
34209 
34210 /*! @name REG_CORE_SET - Digital Regulator Core Register */
34211 /*! @{ */
34212 
34213 #define PMU_REG_CORE_SET_REG0_TARG_MASK          (0x1FU)
34214 #define PMU_REG_CORE_SET_REG0_TARG_SHIFT         (0U)
34215 /*! REG0_TARG
34216  *  0b00000..Power gated off
34217  *  0b00001..Target core voltage = 0.725V
34218  *  0b00010..Target core voltage = 0.750V
34219  *  0b00011..Target core voltage = 0.775V
34220  *  0b10000..Target core voltage = 1.100V
34221  *  0b11110..Target core voltage = 1.450V
34222  *  0b11111..Power FET switched full on. No regulation.
34223  */
34224 #define PMU_REG_CORE_SET_REG0_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
34225 
34226 #define PMU_REG_CORE_SET_REG0_ADJ_MASK           (0x1E0U)
34227 #define PMU_REG_CORE_SET_REG0_ADJ_SHIFT          (5U)
34228 /*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
34229  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34230  *    register.
34231  *  0b0000..No adjustment
34232  *  0b0001..+ 0.25%
34233  *  0b0010..+ 0.50%
34234  *  0b0011..+ 0.75%
34235  *  0b0100..+ 1.00%
34236  *  0b0101..+ 1.25%
34237  *  0b0110..+ 1.50%
34238  *  0b0111..+ 1.75%
34239  *  0b1000..- 0.25%
34240  *  0b1001..- 0.50%
34241  *  0b1010..- 0.75%
34242  *  0b1011..- 1.00%
34243  *  0b1100..- 1.25%
34244  *  0b1101..- 1.50%
34245  *  0b1110..- 1.75%
34246  *  0b1111..- 2.00%
34247  */
34248 #define PMU_REG_CORE_SET_REG0_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
34249 
34250 #define PMU_REG_CORE_SET_REG1_TARG_MASK          (0x3E00U)
34251 #define PMU_REG_CORE_SET_REG1_TARG_SHIFT         (9U)
34252 /*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
34253  *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
34254  *    of input supply limitations or load operation.
34255  *  0b00000..Power gated off
34256  *  0b00001..Target core voltage = 0.725V
34257  *  0b00010..Target core voltage = 0.750V
34258  *  0b00011..Target core voltage = 0.775V
34259  *  0b10000..Target core voltage = 1.100V
34260  *  0b11110..Target core voltage = 1.450V
34261  *  0b11111..Power FET switched full on. No regulation.
34262  */
34263 #define PMU_REG_CORE_SET_REG1_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
34264 
34265 #define PMU_REG_CORE_SET_REG1_ADJ_MASK           (0x3C000U)
34266 #define PMU_REG_CORE_SET_REG1_ADJ_SHIFT          (14U)
34267 /*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
34268  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34269  *    register.
34270  *  0b0000..No adjustment
34271  *  0b0001..+ 0.25%
34272  *  0b0010..+ 0.50%
34273  *  0b0011..+ 0.75%
34274  *  0b0100..+ 1.00%
34275  *  0b0101..+ 1.25%
34276  *  0b0110..+ 1.50%
34277  *  0b0111..+ 1.75%
34278  *  0b1000..- 0.25%
34279  *  0b1001..- 0.50%
34280  *  0b1010..- 0.75%
34281  *  0b1011..- 1.00%
34282  *  0b1100..- 1.25%
34283  *  0b1101..- 1.50%
34284  *  0b1110..- 1.75%
34285  *  0b1111..- 2.00%
34286  */
34287 #define PMU_REG_CORE_SET_REG1_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
34288 
34289 #define PMU_REG_CORE_SET_REG2_TARG_MASK          (0x7C0000U)
34290 #define PMU_REG_CORE_SET_REG2_TARG_SHIFT         (18U)
34291 /*! REG2_TARG
34292  *  0b00000..Power gated off
34293  *  0b00001..Target core voltage = 0.725V
34294  *  0b00010..Target core voltage = 0.750V
34295  *  0b00011..Target core voltage = 0.775V
34296  *  0b10000..Target core voltage = 1.100V
34297  *  0b11110..Target core voltage = 1.450V
34298  *  0b11111..Power FET switched full on. No regulation.
34299  */
34300 #define PMU_REG_CORE_SET_REG2_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
34301 
34302 #define PMU_REG_CORE_SET_REG2_ADJ_MASK           (0x7800000U)
34303 #define PMU_REG_CORE_SET_REG2_ADJ_SHIFT          (23U)
34304 /*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
34305  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34306  *    register.
34307  *  0b0000..No adjustment
34308  *  0b0001..+ 0.25%
34309  *  0b0010..+ 0.50%
34310  *  0b0011..+ 0.75%
34311  *  0b0100..+ 1.00%
34312  *  0b0101..+ 1.25%
34313  *  0b0110..+ 1.50%
34314  *  0b0111..+ 1.75%
34315  *  0b1000..- 0.25%
34316  *  0b1001..- 0.50%
34317  *  0b1010..- 0.75%
34318  *  0b1011..- 1.00%
34319  *  0b1100..- 1.25%
34320  *  0b1101..- 1.50%
34321  *  0b1110..- 1.75%
34322  *  0b1111..- 2.00%
34323  */
34324 #define PMU_REG_CORE_SET_REG2_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
34325 
34326 #define PMU_REG_CORE_SET_RAMP_RATE_MASK          (0x18000000U)
34327 #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT         (27U)
34328 /*! RAMP_RATE
34329  *  0b00..Fast
34330  *  0b01..Medium Fast
34331  *  0b10..Medium Slow
34332  *  0b11..Slow
34333  */
34334 #define PMU_REG_CORE_SET_RAMP_RATE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
34335 
34336 #define PMU_REG_CORE_SET_FET_ODRIVE_MASK         (0x20000000U)
34337 #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT        (29U)
34338 #define PMU_REG_CORE_SET_FET_ODRIVE(x)           (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
34339 /*! @} */
34340 
34341 /*! @name REG_CORE_CLR - Digital Regulator Core Register */
34342 /*! @{ */
34343 
34344 #define PMU_REG_CORE_CLR_REG0_TARG_MASK          (0x1FU)
34345 #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT         (0U)
34346 /*! REG0_TARG
34347  *  0b00000..Power gated off
34348  *  0b00001..Target core voltage = 0.725V
34349  *  0b00010..Target core voltage = 0.750V
34350  *  0b00011..Target core voltage = 0.775V
34351  *  0b10000..Target core voltage = 1.100V
34352  *  0b11110..Target core voltage = 1.450V
34353  *  0b11111..Power FET switched full on. No regulation.
34354  */
34355 #define PMU_REG_CORE_CLR_REG0_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
34356 
34357 #define PMU_REG_CORE_CLR_REG0_ADJ_MASK           (0x1E0U)
34358 #define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT          (5U)
34359 /*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
34360  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34361  *    register.
34362  *  0b0000..No adjustment
34363  *  0b0001..+ 0.25%
34364  *  0b0010..+ 0.50%
34365  *  0b0011..+ 0.75%
34366  *  0b0100..+ 1.00%
34367  *  0b0101..+ 1.25%
34368  *  0b0110..+ 1.50%
34369  *  0b0111..+ 1.75%
34370  *  0b1000..- 0.25%
34371  *  0b1001..- 0.50%
34372  *  0b1010..- 0.75%
34373  *  0b1011..- 1.00%
34374  *  0b1100..- 1.25%
34375  *  0b1101..- 1.50%
34376  *  0b1110..- 1.75%
34377  *  0b1111..- 2.00%
34378  */
34379 #define PMU_REG_CORE_CLR_REG0_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
34380 
34381 #define PMU_REG_CORE_CLR_REG1_TARG_MASK          (0x3E00U)
34382 #define PMU_REG_CORE_CLR_REG1_TARG_SHIFT         (9U)
34383 /*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
34384  *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
34385  *    of input supply limitations or load operation.
34386  *  0b00000..Power gated off
34387  *  0b00001..Target core voltage = 0.725V
34388  *  0b00010..Target core voltage = 0.750V
34389  *  0b00011..Target core voltage = 0.775V
34390  *  0b10000..Target core voltage = 1.100V
34391  *  0b11110..Target core voltage = 1.450V
34392  *  0b11111..Power FET switched full on. No regulation.
34393  */
34394 #define PMU_REG_CORE_CLR_REG1_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
34395 
34396 #define PMU_REG_CORE_CLR_REG1_ADJ_MASK           (0x3C000U)
34397 #define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT          (14U)
34398 /*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
34399  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34400  *    register.
34401  *  0b0000..No adjustment
34402  *  0b0001..+ 0.25%
34403  *  0b0010..+ 0.50%
34404  *  0b0011..+ 0.75%
34405  *  0b0100..+ 1.00%
34406  *  0b0101..+ 1.25%
34407  *  0b0110..+ 1.50%
34408  *  0b0111..+ 1.75%
34409  *  0b1000..- 0.25%
34410  *  0b1001..- 0.50%
34411  *  0b1010..- 0.75%
34412  *  0b1011..- 1.00%
34413  *  0b1100..- 1.25%
34414  *  0b1101..- 1.50%
34415  *  0b1110..- 1.75%
34416  *  0b1111..- 2.00%
34417  */
34418 #define PMU_REG_CORE_CLR_REG1_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
34419 
34420 #define PMU_REG_CORE_CLR_REG2_TARG_MASK          (0x7C0000U)
34421 #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT         (18U)
34422 /*! REG2_TARG
34423  *  0b00000..Power gated off
34424  *  0b00001..Target core voltage = 0.725V
34425  *  0b00010..Target core voltage = 0.750V
34426  *  0b00011..Target core voltage = 0.775V
34427  *  0b10000..Target core voltage = 1.100V
34428  *  0b11110..Target core voltage = 1.450V
34429  *  0b11111..Power FET switched full on. No regulation.
34430  */
34431 #define PMU_REG_CORE_CLR_REG2_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
34432 
34433 #define PMU_REG_CORE_CLR_REG2_ADJ_MASK           (0x7800000U)
34434 #define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT          (23U)
34435 /*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
34436  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34437  *    register.
34438  *  0b0000..No adjustment
34439  *  0b0001..+ 0.25%
34440  *  0b0010..+ 0.50%
34441  *  0b0011..+ 0.75%
34442  *  0b0100..+ 1.00%
34443  *  0b0101..+ 1.25%
34444  *  0b0110..+ 1.50%
34445  *  0b0111..+ 1.75%
34446  *  0b1000..- 0.25%
34447  *  0b1001..- 0.50%
34448  *  0b1010..- 0.75%
34449  *  0b1011..- 1.00%
34450  *  0b1100..- 1.25%
34451  *  0b1101..- 1.50%
34452  *  0b1110..- 1.75%
34453  *  0b1111..- 2.00%
34454  */
34455 #define PMU_REG_CORE_CLR_REG2_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
34456 
34457 #define PMU_REG_CORE_CLR_RAMP_RATE_MASK          (0x18000000U)
34458 #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT         (27U)
34459 /*! RAMP_RATE
34460  *  0b00..Fast
34461  *  0b01..Medium Fast
34462  *  0b10..Medium Slow
34463  *  0b11..Slow
34464  */
34465 #define PMU_REG_CORE_CLR_RAMP_RATE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
34466 
34467 #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK         (0x20000000U)
34468 #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT        (29U)
34469 #define PMU_REG_CORE_CLR_FET_ODRIVE(x)           (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
34470 /*! @} */
34471 
34472 /*! @name REG_CORE_TOG - Digital Regulator Core Register */
34473 /*! @{ */
34474 
34475 #define PMU_REG_CORE_TOG_REG0_TARG_MASK          (0x1FU)
34476 #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT         (0U)
34477 /*! REG0_TARG
34478  *  0b00000..Power gated off
34479  *  0b00001..Target core voltage = 0.725V
34480  *  0b00010..Target core voltage = 0.750V
34481  *  0b00011..Target core voltage = 0.775V
34482  *  0b10000..Target core voltage = 1.100V
34483  *  0b11110..Target core voltage = 1.450V
34484  *  0b11111..Power FET switched full on. No regulation.
34485  */
34486 #define PMU_REG_CORE_TOG_REG0_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
34487 
34488 #define PMU_REG_CORE_TOG_REG0_ADJ_MASK           (0x1E0U)
34489 #define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT          (5U)
34490 /*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
34491  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34492  *    register.
34493  *  0b0000..No adjustment
34494  *  0b0001..+ 0.25%
34495  *  0b0010..+ 0.50%
34496  *  0b0011..+ 0.75%
34497  *  0b0100..+ 1.00%
34498  *  0b0101..+ 1.25%
34499  *  0b0110..+ 1.50%
34500  *  0b0111..+ 1.75%
34501  *  0b1000..- 0.25%
34502  *  0b1001..- 0.50%
34503  *  0b1010..- 0.75%
34504  *  0b1011..- 1.00%
34505  *  0b1100..- 1.25%
34506  *  0b1101..- 1.50%
34507  *  0b1110..- 1.75%
34508  *  0b1111..- 2.00%
34509  */
34510 #define PMU_REG_CORE_TOG_REG0_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
34511 
34512 #define PMU_REG_CORE_TOG_REG1_TARG_MASK          (0x3E00U)
34513 #define PMU_REG_CORE_TOG_REG1_TARG_SHIFT         (9U)
34514 /*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
34515  *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
34516  *    of input supply limitations or load operation.
34517  *  0b00000..Power gated off
34518  *  0b00001..Target core voltage = 0.725V
34519  *  0b00010..Target core voltage = 0.750V
34520  *  0b00011..Target core voltage = 0.775V
34521  *  0b10000..Target core voltage = 1.100V
34522  *  0b11110..Target core voltage = 1.450V
34523  *  0b11111..Power FET switched full on. No regulation.
34524  */
34525 #define PMU_REG_CORE_TOG_REG1_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
34526 
34527 #define PMU_REG_CORE_TOG_REG1_ADJ_MASK           (0x3C000U)
34528 #define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT          (14U)
34529 /*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
34530  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34531  *    register.
34532  *  0b0000..No adjustment
34533  *  0b0001..+ 0.25%
34534  *  0b0010..+ 0.50%
34535  *  0b0011..+ 0.75%
34536  *  0b0100..+ 1.00%
34537  *  0b0101..+ 1.25%
34538  *  0b0110..+ 1.50%
34539  *  0b0111..+ 1.75%
34540  *  0b1000..- 0.25%
34541  *  0b1001..- 0.50%
34542  *  0b1010..- 0.75%
34543  *  0b1011..- 1.00%
34544  *  0b1100..- 1.25%
34545  *  0b1101..- 1.50%
34546  *  0b1110..- 1.75%
34547  *  0b1111..- 2.00%
34548  */
34549 #define PMU_REG_CORE_TOG_REG1_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
34550 
34551 #define PMU_REG_CORE_TOG_REG2_TARG_MASK          (0x7C0000U)
34552 #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT         (18U)
34553 /*! REG2_TARG
34554  *  0b00000..Power gated off
34555  *  0b00001..Target core voltage = 0.725V
34556  *  0b00010..Target core voltage = 0.750V
34557  *  0b00011..Target core voltage = 0.775V
34558  *  0b10000..Target core voltage = 1.100V
34559  *  0b11110..Target core voltage = 1.450V
34560  *  0b11111..Power FET switched full on. No regulation.
34561  */
34562 #define PMU_REG_CORE_TOG_REG2_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
34563 
34564 #define PMU_REG_CORE_TOG_REG2_ADJ_MASK           (0x7800000U)
34565 #define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT          (23U)
34566 /*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
34567  *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
34568  *    register.
34569  *  0b0000..No adjustment
34570  *  0b0001..+ 0.25%
34571  *  0b0010..+ 0.50%
34572  *  0b0011..+ 0.75%
34573  *  0b0100..+ 1.00%
34574  *  0b0101..+ 1.25%
34575  *  0b0110..+ 1.50%
34576  *  0b0111..+ 1.75%
34577  *  0b1000..- 0.25%
34578  *  0b1001..- 0.50%
34579  *  0b1010..- 0.75%
34580  *  0b1011..- 1.00%
34581  *  0b1100..- 1.25%
34582  *  0b1101..- 1.50%
34583  *  0b1110..- 1.75%
34584  *  0b1111..- 2.00%
34585  */
34586 #define PMU_REG_CORE_TOG_REG2_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
34587 
34588 #define PMU_REG_CORE_TOG_RAMP_RATE_MASK          (0x18000000U)
34589 #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT         (27U)
34590 /*! RAMP_RATE
34591  *  0b00..Fast
34592  *  0b01..Medium Fast
34593  *  0b10..Medium Slow
34594  *  0b11..Slow
34595  */
34596 #define PMU_REG_CORE_TOG_RAMP_RATE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
34597 
34598 #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK         (0x20000000U)
34599 #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT        (29U)
34600 #define PMU_REG_CORE_TOG_FET_ODRIVE(x)           (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
34601 /*! @} */
34602 
34603 /*! @name MISC0 - Miscellaneous Register 0 */
34604 /*! @{ */
34605 
34606 #define PMU_MISC0_REFTOP_PWD_MASK                (0x1U)
34607 #define PMU_MISC0_REFTOP_PWD_SHIFT               (0U)
34608 #define PMU_MISC0_REFTOP_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
34609 
34610 #define PMU_MISC0_REFTOP_PWDVBGUP_MASK           (0x2U)
34611 #define PMU_MISC0_REFTOP_PWDVBGUP_SHIFT          (1U)
34612 #define PMU_MISC0_REFTOP_PWDVBGUP(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_REFTOP_PWDVBGUP_MASK)
34613 
34614 #define PMU_MISC0_REFTOP_LOWPOWER_MASK           (0x4U)
34615 #define PMU_MISC0_REFTOP_LOWPOWER_SHIFT          (2U)
34616 #define PMU_MISC0_REFTOP_LOWPOWER(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_REFTOP_LOWPOWER_MASK)
34617 
34618 #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK        (0x8U)
34619 #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT       (3U)
34620 /*! REFTOP_SELFBIASOFF
34621  *  0b0..Uses coarse bias currents for startup
34622  *  0b1..Uses bandgap-based bias currents for best performance.
34623  */
34624 #define PMU_MISC0_REFTOP_SELFBIASOFF(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
34625 
34626 #define PMU_MISC0_REFTOP_VBGADJ_MASK             (0x70U)
34627 #define PMU_MISC0_REFTOP_VBGADJ_SHIFT            (4U)
34628 /*! REFTOP_VBGADJ
34629  *  0b000..Nominal VBG
34630  *  0b001..VBG+0.78%
34631  *  0b010..VBG+1.56%
34632  *  0b011..VBG+2.34%
34633  *  0b100..VBG-0.78%
34634  *  0b101..VBG-1.56%
34635  *  0b110..VBG-2.34%
34636  *  0b111..VBG-3.12%
34637  */
34638 #define PMU_MISC0_REFTOP_VBGADJ(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
34639 
34640 #define PMU_MISC0_REFTOP_VBGUP_MASK              (0x80U)
34641 #define PMU_MISC0_REFTOP_VBGUP_SHIFT             (7U)
34642 #define PMU_MISC0_REFTOP_VBGUP(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
34643 
34644 #define PMU_MISC0_STOP_MODE_CONFIG_MASK          (0xC00U)
34645 #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT         (10U)
34646 /*! STOP_MODE_CONFIG
34647  *  0b00..SUSPEND (DSM)
34648  *  0b01..Analog regulators are ON.
34649  *  0b10..STOP (lower power)
34650  *  0b11..STOP (very lower power)
34651  */
34652 #define PMU_MISC0_STOP_MODE_CONFIG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
34653 
34654 #define PMU_MISC0_DISCON_HIGH_SNVS_MASK          (0x1000U)
34655 #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT         (12U)
34656 /*! DISCON_HIGH_SNVS
34657  *  0b0..Turn on the switch
34658  *  0b1..Turn off the switch
34659  */
34660 #define PMU_MISC0_DISCON_HIGH_SNVS(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
34661 
34662 #define PMU_MISC0_OSC_I_MASK                     (0x6000U)
34663 #define PMU_MISC0_OSC_I_SHIFT                    (13U)
34664 /*! OSC_I
34665  *  0b00..Nominal
34666  *  0b01..Decrease current by 12.5%
34667  *  0b10..Decrease current by 25.0%
34668  *  0b11..Decrease current by 37.5%
34669  */
34670 #define PMU_MISC0_OSC_I(x)                       (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
34671 
34672 #define PMU_MISC0_OSC_XTALOK_MASK                (0x8000U)
34673 #define PMU_MISC0_OSC_XTALOK_SHIFT               (15U)
34674 #define PMU_MISC0_OSC_XTALOK(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
34675 
34676 #define PMU_MISC0_OSC_XTALOK_EN_MASK             (0x10000U)
34677 #define PMU_MISC0_OSC_XTALOK_EN_SHIFT            (16U)
34678 #define PMU_MISC0_OSC_XTALOK_EN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
34679 
34680 #define PMU_MISC0_CLKGATE_CTRL_MASK              (0x2000000U)
34681 #define PMU_MISC0_CLKGATE_CTRL_SHIFT             (25U)
34682 /*! CLKGATE_CTRL
34683  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
34684  *  0b1..Prevent the logic from ever gating off the clock.
34685  */
34686 #define PMU_MISC0_CLKGATE_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
34687 
34688 #define PMU_MISC0_CLKGATE_DELAY_MASK             (0x1C000000U)
34689 #define PMU_MISC0_CLKGATE_DELAY_SHIFT            (26U)
34690 /*! CLKGATE_DELAY
34691  *  0b000..0.5ms
34692  *  0b001..1.0ms
34693  *  0b010..2.0ms
34694  *  0b011..3.0ms
34695  *  0b100..4.0ms
34696  *  0b101..5.0ms
34697  *  0b110..6.0ms
34698  *  0b111..7.0ms
34699  */
34700 #define PMU_MISC0_CLKGATE_DELAY(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
34701 
34702 #define PMU_MISC0_RTC_XTAL_SOURCE_MASK           (0x20000000U)
34703 #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT          (29U)
34704 /*! RTC_XTAL_SOURCE
34705  *  0b0..Internal ring oscillator
34706  *  0b1..RTC_XTAL
34707  */
34708 #define PMU_MISC0_RTC_XTAL_SOURCE(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
34709 
34710 #define PMU_MISC0_XTAL_24M_PWD_MASK              (0x40000000U)
34711 #define PMU_MISC0_XTAL_24M_PWD_SHIFT             (30U)
34712 #define PMU_MISC0_XTAL_24M_PWD(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
34713 
34714 #define PMU_MISC0_VID_PLL_PREDIV_MASK            (0x80000000U)
34715 #define PMU_MISC0_VID_PLL_PREDIV_SHIFT           (31U)
34716 /*! VID_PLL_PREDIV
34717  *  0b0..Divide by 1
34718  *  0b1..Divide by 2
34719  */
34720 #define PMU_MISC0_VID_PLL_PREDIV(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
34721 /*! @} */
34722 
34723 /*! @name MISC0_SET - Miscellaneous Register 0 */
34724 /*! @{ */
34725 
34726 #define PMU_MISC0_SET_REFTOP_PWD_MASK            (0x1U)
34727 #define PMU_MISC0_SET_REFTOP_PWD_SHIFT           (0U)
34728 #define PMU_MISC0_SET_REFTOP_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
34729 
34730 #define PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK       (0x2U)
34731 #define PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT      (1U)
34732 #define PMU_MISC0_SET_REFTOP_PWDVBGUP(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK)
34733 
34734 #define PMU_MISC0_SET_REFTOP_LOWPOWER_MASK       (0x4U)
34735 #define PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT      (2U)
34736 #define PMU_MISC0_SET_REFTOP_LOWPOWER(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_SET_REFTOP_LOWPOWER_MASK)
34737 
34738 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK    (0x8U)
34739 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT   (3U)
34740 /*! REFTOP_SELFBIASOFF
34741  *  0b0..Uses coarse bias currents for startup
34742  *  0b1..Uses bandgap-based bias currents for best performance.
34743  */
34744 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x)      (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
34745 
34746 #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK         (0x70U)
34747 #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT        (4U)
34748 /*! REFTOP_VBGADJ
34749  *  0b000..Nominal VBG
34750  *  0b001..VBG+0.78%
34751  *  0b010..VBG+1.56%
34752  *  0b011..VBG+2.34%
34753  *  0b100..VBG-0.78%
34754  *  0b101..VBG-1.56%
34755  *  0b110..VBG-2.34%
34756  *  0b111..VBG-3.12%
34757  */
34758 #define PMU_MISC0_SET_REFTOP_VBGADJ(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
34759 
34760 #define PMU_MISC0_SET_REFTOP_VBGUP_MASK          (0x80U)
34761 #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT         (7U)
34762 #define PMU_MISC0_SET_REFTOP_VBGUP(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
34763 
34764 #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK      (0xC00U)
34765 #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT     (10U)
34766 /*! STOP_MODE_CONFIG
34767  *  0b00..SUSPEND (DSM)
34768  *  0b01..Analog regulators are ON.
34769  *  0b10..STOP (lower power)
34770  *  0b11..STOP (very lower power)
34771  */
34772 #define PMU_MISC0_SET_STOP_MODE_CONFIG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
34773 
34774 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK      (0x1000U)
34775 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT     (12U)
34776 /*! DISCON_HIGH_SNVS
34777  *  0b0..Turn on the switch
34778  *  0b1..Turn off the switch
34779  */
34780 #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
34781 
34782 #define PMU_MISC0_SET_OSC_I_MASK                 (0x6000U)
34783 #define PMU_MISC0_SET_OSC_I_SHIFT                (13U)
34784 /*! OSC_I
34785  *  0b00..Nominal
34786  *  0b01..Decrease current by 12.5%
34787  *  0b10..Decrease current by 25.0%
34788  *  0b11..Decrease current by 37.5%
34789  */
34790 #define PMU_MISC0_SET_OSC_I(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
34791 
34792 #define PMU_MISC0_SET_OSC_XTALOK_MASK            (0x8000U)
34793 #define PMU_MISC0_SET_OSC_XTALOK_SHIFT           (15U)
34794 #define PMU_MISC0_SET_OSC_XTALOK(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
34795 
34796 #define PMU_MISC0_SET_OSC_XTALOK_EN_MASK         (0x10000U)
34797 #define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT        (16U)
34798 #define PMU_MISC0_SET_OSC_XTALOK_EN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
34799 
34800 #define PMU_MISC0_SET_CLKGATE_CTRL_MASK          (0x2000000U)
34801 #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT         (25U)
34802 /*! CLKGATE_CTRL
34803  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
34804  *  0b1..Prevent the logic from ever gating off the clock.
34805  */
34806 #define PMU_MISC0_SET_CLKGATE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
34807 
34808 #define PMU_MISC0_SET_CLKGATE_DELAY_MASK         (0x1C000000U)
34809 #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT        (26U)
34810 /*! CLKGATE_DELAY
34811  *  0b000..0.5ms
34812  *  0b001..1.0ms
34813  *  0b010..2.0ms
34814  *  0b011..3.0ms
34815  *  0b100..4.0ms
34816  *  0b101..5.0ms
34817  *  0b110..6.0ms
34818  *  0b111..7.0ms
34819  */
34820 #define PMU_MISC0_SET_CLKGATE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
34821 
34822 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK       (0x20000000U)
34823 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT      (29U)
34824 /*! RTC_XTAL_SOURCE
34825  *  0b0..Internal ring oscillator
34826  *  0b1..RTC_XTAL
34827  */
34828 #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
34829 
34830 #define PMU_MISC0_SET_XTAL_24M_PWD_MASK          (0x40000000U)
34831 #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT         (30U)
34832 #define PMU_MISC0_SET_XTAL_24M_PWD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
34833 
34834 #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK        (0x80000000U)
34835 #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT       (31U)
34836 /*! VID_PLL_PREDIV
34837  *  0b0..Divide by 1
34838  *  0b1..Divide by 2
34839  */
34840 #define PMU_MISC0_SET_VID_PLL_PREDIV(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
34841 /*! @} */
34842 
34843 /*! @name MISC0_CLR - Miscellaneous Register 0 */
34844 /*! @{ */
34845 
34846 #define PMU_MISC0_CLR_REFTOP_PWD_MASK            (0x1U)
34847 #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT           (0U)
34848 #define PMU_MISC0_CLR_REFTOP_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
34849 
34850 #define PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK       (0x2U)
34851 #define PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT      (1U)
34852 #define PMU_MISC0_CLR_REFTOP_PWDVBGUP(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK)
34853 
34854 #define PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK       (0x4U)
34855 #define PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT      (2U)
34856 #define PMU_MISC0_CLR_REFTOP_LOWPOWER(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK)
34857 
34858 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK    (0x8U)
34859 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT   (3U)
34860 /*! REFTOP_SELFBIASOFF
34861  *  0b0..Uses coarse bias currents for startup
34862  *  0b1..Uses bandgap-based bias currents for best performance.
34863  */
34864 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x)      (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
34865 
34866 #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK         (0x70U)
34867 #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT        (4U)
34868 /*! REFTOP_VBGADJ
34869  *  0b000..Nominal VBG
34870  *  0b001..VBG+0.78%
34871  *  0b010..VBG+1.56%
34872  *  0b011..VBG+2.34%
34873  *  0b100..VBG-0.78%
34874  *  0b101..VBG-1.56%
34875  *  0b110..VBG-2.34%
34876  *  0b111..VBG-3.12%
34877  */
34878 #define PMU_MISC0_CLR_REFTOP_VBGADJ(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
34879 
34880 #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK          (0x80U)
34881 #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT         (7U)
34882 #define PMU_MISC0_CLR_REFTOP_VBGUP(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
34883 
34884 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK      (0xC00U)
34885 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT     (10U)
34886 /*! STOP_MODE_CONFIG
34887  *  0b00..SUSPEND (DSM)
34888  *  0b01..Analog regulators are ON.
34889  *  0b10..STOP (lower power)
34890  *  0b11..STOP (very lower power)
34891  */
34892 #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
34893 
34894 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK      (0x1000U)
34895 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT     (12U)
34896 /*! DISCON_HIGH_SNVS
34897  *  0b0..Turn on the switch
34898  *  0b1..Turn off the switch
34899  */
34900 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
34901 
34902 #define PMU_MISC0_CLR_OSC_I_MASK                 (0x6000U)
34903 #define PMU_MISC0_CLR_OSC_I_SHIFT                (13U)
34904 /*! OSC_I
34905  *  0b00..Nominal
34906  *  0b01..Decrease current by 12.5%
34907  *  0b10..Decrease current by 25.0%
34908  *  0b11..Decrease current by 37.5%
34909  */
34910 #define PMU_MISC0_CLR_OSC_I(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
34911 
34912 #define PMU_MISC0_CLR_OSC_XTALOK_MASK            (0x8000U)
34913 #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT           (15U)
34914 #define PMU_MISC0_CLR_OSC_XTALOK(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
34915 
34916 #define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK         (0x10000U)
34917 #define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT        (16U)
34918 #define PMU_MISC0_CLR_OSC_XTALOK_EN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
34919 
34920 #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK          (0x2000000U)
34921 #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT         (25U)
34922 /*! CLKGATE_CTRL
34923  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
34924  *  0b1..Prevent the logic from ever gating off the clock.
34925  */
34926 #define PMU_MISC0_CLR_CLKGATE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
34927 
34928 #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK         (0x1C000000U)
34929 #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT        (26U)
34930 /*! CLKGATE_DELAY
34931  *  0b000..0.5ms
34932  *  0b001..1.0ms
34933  *  0b010..2.0ms
34934  *  0b011..3.0ms
34935  *  0b100..4.0ms
34936  *  0b101..5.0ms
34937  *  0b110..6.0ms
34938  *  0b111..7.0ms
34939  */
34940 #define PMU_MISC0_CLR_CLKGATE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
34941 
34942 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK       (0x20000000U)
34943 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT      (29U)
34944 /*! RTC_XTAL_SOURCE
34945  *  0b0..Internal ring oscillator
34946  *  0b1..RTC_XTAL
34947  */
34948 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
34949 
34950 #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK          (0x40000000U)
34951 #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT         (30U)
34952 #define PMU_MISC0_CLR_XTAL_24M_PWD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
34953 
34954 #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK        (0x80000000U)
34955 #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT       (31U)
34956 /*! VID_PLL_PREDIV
34957  *  0b0..Divide by 1
34958  *  0b1..Divide by 2
34959  */
34960 #define PMU_MISC0_CLR_VID_PLL_PREDIV(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
34961 /*! @} */
34962 
34963 /*! @name MISC0_TOG - Miscellaneous Register 0 */
34964 /*! @{ */
34965 
34966 #define PMU_MISC0_TOG_REFTOP_PWD_MASK            (0x1U)
34967 #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT           (0U)
34968 #define PMU_MISC0_TOG_REFTOP_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
34969 
34970 #define PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK       (0x2U)
34971 #define PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT      (1U)
34972 #define PMU_MISC0_TOG_REFTOP_PWDVBGUP(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK)
34973 
34974 #define PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK       (0x4U)
34975 #define PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT      (2U)
34976 #define PMU_MISC0_TOG_REFTOP_LOWPOWER(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK)
34977 
34978 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK    (0x8U)
34979 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT   (3U)
34980 /*! REFTOP_SELFBIASOFF
34981  *  0b0..Uses coarse bias currents for startup
34982  *  0b1..Uses bandgap-based bias currents for best performance.
34983  */
34984 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x)      (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
34985 
34986 #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK         (0x70U)
34987 #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT        (4U)
34988 /*! REFTOP_VBGADJ
34989  *  0b000..Nominal VBG
34990  *  0b001..VBG+0.78%
34991  *  0b010..VBG+1.56%
34992  *  0b011..VBG+2.34%
34993  *  0b100..VBG-0.78%
34994  *  0b101..VBG-1.56%
34995  *  0b110..VBG-2.34%
34996  *  0b111..VBG-3.12%
34997  */
34998 #define PMU_MISC0_TOG_REFTOP_VBGADJ(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
34999 
35000 #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK          (0x80U)
35001 #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT         (7U)
35002 #define PMU_MISC0_TOG_REFTOP_VBGUP(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
35003 
35004 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK      (0xC00U)
35005 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT     (10U)
35006 /*! STOP_MODE_CONFIG
35007  *  0b00..SUSPEND (DSM)
35008  *  0b01..Analog regulators are ON.
35009  *  0b10..STOP (lower power)
35010  *  0b11..STOP (very lower power)
35011  */
35012 #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
35013 
35014 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK      (0x1000U)
35015 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT     (12U)
35016 /*! DISCON_HIGH_SNVS
35017  *  0b0..Turn on the switch
35018  *  0b1..Turn off the switch
35019  */
35020 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
35021 
35022 #define PMU_MISC0_TOG_OSC_I_MASK                 (0x6000U)
35023 #define PMU_MISC0_TOG_OSC_I_SHIFT                (13U)
35024 /*! OSC_I
35025  *  0b00..Nominal
35026  *  0b01..Decrease current by 12.5%
35027  *  0b10..Decrease current by 25.0%
35028  *  0b11..Decrease current by 37.5%
35029  */
35030 #define PMU_MISC0_TOG_OSC_I(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
35031 
35032 #define PMU_MISC0_TOG_OSC_XTALOK_MASK            (0x8000U)
35033 #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT           (15U)
35034 #define PMU_MISC0_TOG_OSC_XTALOK(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
35035 
35036 #define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK         (0x10000U)
35037 #define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT        (16U)
35038 #define PMU_MISC0_TOG_OSC_XTALOK_EN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
35039 
35040 #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK          (0x2000000U)
35041 #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT         (25U)
35042 /*! CLKGATE_CTRL
35043  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
35044  *  0b1..Prevent the logic from ever gating off the clock.
35045  */
35046 #define PMU_MISC0_TOG_CLKGATE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
35047 
35048 #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK         (0x1C000000U)
35049 #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT        (26U)
35050 /*! CLKGATE_DELAY
35051  *  0b000..0.5ms
35052  *  0b001..1.0ms
35053  *  0b010..2.0ms
35054  *  0b011..3.0ms
35055  *  0b100..4.0ms
35056  *  0b101..5.0ms
35057  *  0b110..6.0ms
35058  *  0b111..7.0ms
35059  */
35060 #define PMU_MISC0_TOG_CLKGATE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
35061 
35062 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK       (0x20000000U)
35063 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT      (29U)
35064 /*! RTC_XTAL_SOURCE
35065  *  0b0..Internal ring oscillator
35066  *  0b1..RTC_XTAL
35067  */
35068 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
35069 
35070 #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK          (0x40000000U)
35071 #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT         (30U)
35072 #define PMU_MISC0_TOG_XTAL_24M_PWD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
35073 
35074 #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK        (0x80000000U)
35075 #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT       (31U)
35076 /*! VID_PLL_PREDIV
35077  *  0b0..Divide by 1
35078  *  0b1..Divide by 2
35079  */
35080 #define PMU_MISC0_TOG_VID_PLL_PREDIV(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
35081 /*! @} */
35082 
35083 /*! @name MISC1 - Miscellaneous Register 1 */
35084 /*! @{ */
35085 
35086 #define PMU_MISC1_LVDS1_CLK_SEL_MASK             (0x1FU)
35087 #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT            (0U)
35088 /*! LVDS1_CLK_SEL
35089  *  0b00000..ARM PLL
35090  *  0b00001..System PLL
35091  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35092  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35093  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35094  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35095  *  0b00110..Audio PLL
35096  *  0b00111..Video PLL
35097  *  0b01001..ethernet ref clock (ENET_PLL)
35098  *  0b01100..USB1 PLL clock
35099  *  0b01101..USB2 PLL clock
35100  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35101  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35102  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35103  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35104  *  0b10010..xtal (24M)
35105  */
35106 #define PMU_MISC1_LVDS1_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
35107 
35108 #define PMU_MISC1_LVDS2_CLK_SEL_MASK             (0x3E0U)
35109 #define PMU_MISC1_LVDS2_CLK_SEL_SHIFT            (5U)
35110 /*! LVDS2_CLK_SEL
35111  *  0b00000..ARM PLL
35112  *  0b00001..System PLL
35113  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35114  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35115  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35116  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35117  *  0b00110..Audio PLL
35118  *  0b00111..Video PLL
35119  *  0b01000..MLB PLL
35120  *  0b01001..ethernet ref clock (ENET_PLL)
35121  *  0b01010..PCIe ref clock (125M)
35122  *  0b01011..SATA ref clock (100M)
35123  *  0b01100..USB1 PLL clock
35124  *  0b01101..USB2 PLL clock
35125  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35126  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35127  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35128  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35129  *  0b10010..xtal (24M)
35130  *  0b10011..LVDS1 (loopback)
35131  *  0b10100..LVDS2 (not useful)
35132  */
35133 #define PMU_MISC1_LVDS2_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
35134 
35135 #define PMU_MISC1_LVDSCLK1_OBEN_MASK             (0x400U)
35136 #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT            (10U)
35137 #define PMU_MISC1_LVDSCLK1_OBEN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
35138 
35139 #define PMU_MISC1_LVDSCLK2_OBEN_MASK             (0x800U)
35140 #define PMU_MISC1_LVDSCLK2_OBEN_SHIFT            (11U)
35141 #define PMU_MISC1_LVDSCLK2_OBEN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
35142 
35143 #define PMU_MISC1_LVDSCLK1_IBEN_MASK             (0x1000U)
35144 #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT            (12U)
35145 #define PMU_MISC1_LVDSCLK1_IBEN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
35146 
35147 #define PMU_MISC1_LVDSCLK2_IBEN_MASK             (0x2000U)
35148 #define PMU_MISC1_LVDSCLK2_IBEN_SHIFT            (13U)
35149 #define PMU_MISC1_LVDSCLK2_IBEN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
35150 
35151 #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK       (0x10000U)
35152 #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT      (16U)
35153 #define PMU_MISC1_PFD_480_AUTOGATE_EN(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
35154 
35155 #define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK       (0x20000U)
35156 #define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT      (17U)
35157 #define PMU_MISC1_PFD_528_AUTOGATE_EN(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
35158 
35159 #define PMU_MISC1_IRQ_TEMPPANIC_MASK             (0x8000000U)
35160 #define PMU_MISC1_IRQ_TEMPPANIC_SHIFT            (27U)
35161 #define PMU_MISC1_IRQ_TEMPPANIC(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
35162 
35163 #define PMU_MISC1_IRQ_TEMPLOW_MASK               (0x10000000U)
35164 #define PMU_MISC1_IRQ_TEMPLOW_SHIFT              (28U)
35165 #define PMU_MISC1_IRQ_TEMPLOW(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
35166 
35167 #define PMU_MISC1_IRQ_TEMPHIGH_MASK              (0x20000000U)
35168 #define PMU_MISC1_IRQ_TEMPHIGH_SHIFT             (29U)
35169 #define PMU_MISC1_IRQ_TEMPHIGH(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
35170 
35171 #define PMU_MISC1_IRQ_ANA_BO_MASK                (0x40000000U)
35172 #define PMU_MISC1_IRQ_ANA_BO_SHIFT               (30U)
35173 #define PMU_MISC1_IRQ_ANA_BO(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
35174 
35175 #define PMU_MISC1_IRQ_DIG_BO_MASK                (0x80000000U)
35176 #define PMU_MISC1_IRQ_DIG_BO_SHIFT               (31U)
35177 #define PMU_MISC1_IRQ_DIG_BO(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
35178 /*! @} */
35179 
35180 /*! @name MISC1_SET - Miscellaneous Register 1 */
35181 /*! @{ */
35182 
35183 #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK         (0x1FU)
35184 #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT        (0U)
35185 /*! LVDS1_CLK_SEL
35186  *  0b00000..ARM PLL
35187  *  0b00001..System PLL
35188  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35189  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35190  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35191  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35192  *  0b00110..Audio PLL
35193  *  0b00111..Video PLL
35194  *  0b01001..ethernet ref clock (ENET_PLL)
35195  *  0b01100..USB1 PLL clock
35196  *  0b01101..USB2 PLL clock
35197  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35198  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35199  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35200  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35201  *  0b10010..xtal (24M)
35202  */
35203 #define PMU_MISC1_SET_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
35204 
35205 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK         (0x3E0U)
35206 #define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT        (5U)
35207 /*! LVDS2_CLK_SEL
35208  *  0b00000..ARM PLL
35209  *  0b00001..System PLL
35210  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35211  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35212  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35213  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35214  *  0b00110..Audio PLL
35215  *  0b00111..Video PLL
35216  *  0b01000..MLB PLL
35217  *  0b01001..ethernet ref clock (ENET_PLL)
35218  *  0b01010..PCIe ref clock (125M)
35219  *  0b01011..SATA ref clock (100M)
35220  *  0b01100..USB1 PLL clock
35221  *  0b01101..USB2 PLL clock
35222  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35223  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35224  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35225  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35226  *  0b10010..xtal (24M)
35227  *  0b10011..LVDS1 (loopback)
35228  *  0b10100..LVDS2 (not useful)
35229  */
35230 #define PMU_MISC1_SET_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
35231 
35232 #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK         (0x400U)
35233 #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT        (10U)
35234 #define PMU_MISC1_SET_LVDSCLK1_OBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
35235 
35236 #define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK         (0x800U)
35237 #define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT        (11U)
35238 #define PMU_MISC1_SET_LVDSCLK2_OBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
35239 
35240 #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK         (0x1000U)
35241 #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT        (12U)
35242 #define PMU_MISC1_SET_LVDSCLK1_IBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
35243 
35244 #define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK         (0x2000U)
35245 #define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT        (13U)
35246 #define PMU_MISC1_SET_LVDSCLK2_IBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
35247 
35248 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK   (0x10000U)
35249 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT  (16U)
35250 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x)     (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
35251 
35252 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK   (0x20000U)
35253 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT  (17U)
35254 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x)     (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
35255 
35256 #define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK         (0x8000000U)
35257 #define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT        (27U)
35258 #define PMU_MISC1_SET_IRQ_TEMPPANIC(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
35259 
35260 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK           (0x10000000U)
35261 #define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT          (28U)
35262 #define PMU_MISC1_SET_IRQ_TEMPLOW(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
35263 
35264 #define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK          (0x20000000U)
35265 #define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT         (29U)
35266 #define PMU_MISC1_SET_IRQ_TEMPHIGH(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
35267 
35268 #define PMU_MISC1_SET_IRQ_ANA_BO_MASK            (0x40000000U)
35269 #define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT           (30U)
35270 #define PMU_MISC1_SET_IRQ_ANA_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
35271 
35272 #define PMU_MISC1_SET_IRQ_DIG_BO_MASK            (0x80000000U)
35273 #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT           (31U)
35274 #define PMU_MISC1_SET_IRQ_DIG_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
35275 /*! @} */
35276 
35277 /*! @name MISC1_CLR - Miscellaneous Register 1 */
35278 /*! @{ */
35279 
35280 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK         (0x1FU)
35281 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT        (0U)
35282 /*! LVDS1_CLK_SEL
35283  *  0b00000..ARM PLL
35284  *  0b00001..System PLL
35285  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35286  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35287  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35288  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35289  *  0b00110..Audio PLL
35290  *  0b00111..Video PLL
35291  *  0b01001..ethernet ref clock (ENET_PLL)
35292  *  0b01100..USB1 PLL clock
35293  *  0b01101..USB2 PLL clock
35294  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35295  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35296  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35297  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35298  *  0b10010..xtal (24M)
35299  */
35300 #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
35301 
35302 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK         (0x3E0U)
35303 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT        (5U)
35304 /*! LVDS2_CLK_SEL
35305  *  0b00000..ARM PLL
35306  *  0b00001..System PLL
35307  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35308  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35309  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35310  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35311  *  0b00110..Audio PLL
35312  *  0b00111..Video PLL
35313  *  0b01000..MLB PLL
35314  *  0b01001..ethernet ref clock (ENET_PLL)
35315  *  0b01010..PCIe ref clock (125M)
35316  *  0b01011..SATA ref clock (100M)
35317  *  0b01100..USB1 PLL clock
35318  *  0b01101..USB2 PLL clock
35319  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35320  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35321  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35322  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35323  *  0b10010..xtal (24M)
35324  *  0b10011..LVDS1 (loopback)
35325  *  0b10100..LVDS2 (not useful)
35326  */
35327 #define PMU_MISC1_CLR_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
35328 
35329 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK         (0x400U)
35330 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT        (10U)
35331 #define PMU_MISC1_CLR_LVDSCLK1_OBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
35332 
35333 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK         (0x800U)
35334 #define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT        (11U)
35335 #define PMU_MISC1_CLR_LVDSCLK2_OBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
35336 
35337 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK         (0x1000U)
35338 #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT        (12U)
35339 #define PMU_MISC1_CLR_LVDSCLK1_IBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
35340 
35341 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK         (0x2000U)
35342 #define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT        (13U)
35343 #define PMU_MISC1_CLR_LVDSCLK2_IBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
35344 
35345 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK   (0x10000U)
35346 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT  (16U)
35347 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x)     (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
35348 
35349 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK   (0x20000U)
35350 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT  (17U)
35351 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x)     (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
35352 
35353 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK         (0x8000000U)
35354 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT        (27U)
35355 #define PMU_MISC1_CLR_IRQ_TEMPPANIC(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
35356 
35357 #define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK           (0x10000000U)
35358 #define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT          (28U)
35359 #define PMU_MISC1_CLR_IRQ_TEMPLOW(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
35360 
35361 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK          (0x20000000U)
35362 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT         (29U)
35363 #define PMU_MISC1_CLR_IRQ_TEMPHIGH(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
35364 
35365 #define PMU_MISC1_CLR_IRQ_ANA_BO_MASK            (0x40000000U)
35366 #define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT           (30U)
35367 #define PMU_MISC1_CLR_IRQ_ANA_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
35368 
35369 #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK            (0x80000000U)
35370 #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT           (31U)
35371 #define PMU_MISC1_CLR_IRQ_DIG_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
35372 /*! @} */
35373 
35374 /*! @name MISC1_TOG - Miscellaneous Register 1 */
35375 /*! @{ */
35376 
35377 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK         (0x1FU)
35378 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT        (0U)
35379 /*! LVDS1_CLK_SEL
35380  *  0b00000..ARM PLL
35381  *  0b00001..System PLL
35382  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35383  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35384  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35385  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35386  *  0b00110..Audio PLL
35387  *  0b00111..Video PLL
35388  *  0b01001..ethernet ref clock (ENET_PLL)
35389  *  0b01100..USB1 PLL clock
35390  *  0b01101..USB2 PLL clock
35391  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35392  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35393  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35394  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35395  *  0b10010..xtal (24M)
35396  */
35397 #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
35398 
35399 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK         (0x3E0U)
35400 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT        (5U)
35401 /*! LVDS2_CLK_SEL
35402  *  0b00000..ARM PLL
35403  *  0b00001..System PLL
35404  *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
35405  *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
35406  *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
35407  *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
35408  *  0b00110..Audio PLL
35409  *  0b00111..Video PLL
35410  *  0b01000..MLB PLL
35411  *  0b01001..ethernet ref clock (ENET_PLL)
35412  *  0b01010..PCIe ref clock (125M)
35413  *  0b01011..SATA ref clock (100M)
35414  *  0b01100..USB1 PLL clock
35415  *  0b01101..USB2 PLL clock
35416  *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
35417  *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
35418  *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
35419  *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
35420  *  0b10010..xtal (24M)
35421  *  0b10011..LVDS1 (loopback)
35422  *  0b10100..LVDS2 (not useful)
35423  */
35424 #define PMU_MISC1_TOG_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
35425 
35426 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK         (0x400U)
35427 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT        (10U)
35428 #define PMU_MISC1_TOG_LVDSCLK1_OBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
35429 
35430 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK         (0x800U)
35431 #define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT        (11U)
35432 #define PMU_MISC1_TOG_LVDSCLK2_OBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
35433 
35434 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK         (0x1000U)
35435 #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT        (12U)
35436 #define PMU_MISC1_TOG_LVDSCLK1_IBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
35437 
35438 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK         (0x2000U)
35439 #define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT        (13U)
35440 #define PMU_MISC1_TOG_LVDSCLK2_IBEN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
35441 
35442 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK   (0x10000U)
35443 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT  (16U)
35444 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x)     (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
35445 
35446 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK   (0x20000U)
35447 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT  (17U)
35448 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x)     (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
35449 
35450 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK         (0x8000000U)
35451 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT        (27U)
35452 #define PMU_MISC1_TOG_IRQ_TEMPPANIC(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
35453 
35454 #define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK           (0x10000000U)
35455 #define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT          (28U)
35456 #define PMU_MISC1_TOG_IRQ_TEMPLOW(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
35457 
35458 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK          (0x20000000U)
35459 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT         (29U)
35460 #define PMU_MISC1_TOG_IRQ_TEMPHIGH(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
35461 
35462 #define PMU_MISC1_TOG_IRQ_ANA_BO_MASK            (0x40000000U)
35463 #define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT           (30U)
35464 #define PMU_MISC1_TOG_IRQ_ANA_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
35465 
35466 #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK            (0x80000000U)
35467 #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT           (31U)
35468 #define PMU_MISC1_TOG_IRQ_DIG_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
35469 /*! @} */
35470 
35471 /*! @name MISC2 - Miscellaneous Control Register */
35472 /*! @{ */
35473 
35474 #define PMU_MISC2_REG0_BO_OFFSET_MASK            (0x7U)
35475 #define PMU_MISC2_REG0_BO_OFFSET_SHIFT           (0U)
35476 /*! REG0_BO_OFFSET
35477  *  0b100..Brownout offset = 0.100V
35478  *  0b111..Brownout offset = 0.175V
35479  */
35480 #define PMU_MISC2_REG0_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
35481 
35482 #define PMU_MISC2_REG0_BO_STATUS_MASK            (0x8U)
35483 #define PMU_MISC2_REG0_BO_STATUS_SHIFT           (3U)
35484 /*! REG0_BO_STATUS
35485  *  0b1..Brownout, supply is below target minus brownout offset.
35486  */
35487 #define PMU_MISC2_REG0_BO_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
35488 
35489 #define PMU_MISC2_REG0_ENABLE_BO_MASK            (0x20U)
35490 #define PMU_MISC2_REG0_ENABLE_BO_SHIFT           (5U)
35491 #define PMU_MISC2_REG0_ENABLE_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
35492 
35493 #define PMU_MISC2_PLL3_disable_MASK              (0x80U)
35494 #define PMU_MISC2_PLL3_disable_SHIFT             (7U)
35495 #define PMU_MISC2_PLL3_disable(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
35496 
35497 #define PMU_MISC2_REG1_BO_OFFSET_MASK            (0x700U)
35498 #define PMU_MISC2_REG1_BO_OFFSET_SHIFT           (8U)
35499 /*! REG1_BO_OFFSET
35500  *  0b100..Brownout offset = 0.100V
35501  *  0b111..Brownout offset = 0.175V
35502  */
35503 #define PMU_MISC2_REG1_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
35504 
35505 #define PMU_MISC2_REG1_BO_STATUS_MASK            (0x800U)
35506 #define PMU_MISC2_REG1_BO_STATUS_SHIFT           (11U)
35507 /*! REG1_BO_STATUS
35508  *  0b1..Brownout, supply is below target minus brownout offset.
35509  */
35510 #define PMU_MISC2_REG1_BO_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
35511 
35512 #define PMU_MISC2_REG1_ENABLE_BO_MASK            (0x2000U)
35513 #define PMU_MISC2_REG1_ENABLE_BO_SHIFT           (13U)
35514 #define PMU_MISC2_REG1_ENABLE_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
35515 
35516 #define PMU_MISC2_AUDIO_DIV_LSB_MASK             (0x8000U)
35517 #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT            (15U)
35518 /*! AUDIO_DIV_LSB
35519  *  0b0..divide by 1 (Default)
35520  *  0b1..divide by 2
35521  */
35522 #define PMU_MISC2_AUDIO_DIV_LSB(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
35523 
35524 #define PMU_MISC2_REG2_BO_OFFSET_MASK            (0x70000U)
35525 #define PMU_MISC2_REG2_BO_OFFSET_SHIFT           (16U)
35526 /*! REG2_BO_OFFSET
35527  *  0b100..Brownout offset = 0.100V
35528  *  0b111..Brownout offset = 0.175V
35529  */
35530 #define PMU_MISC2_REG2_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
35531 
35532 #define PMU_MISC2_REG2_BO_STATUS_MASK            (0x80000U)
35533 #define PMU_MISC2_REG2_BO_STATUS_SHIFT           (19U)
35534 #define PMU_MISC2_REG2_BO_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
35535 
35536 #define PMU_MISC2_REG2_ENABLE_BO_MASK            (0x200000U)
35537 #define PMU_MISC2_REG2_ENABLE_BO_SHIFT           (21U)
35538 #define PMU_MISC2_REG2_ENABLE_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
35539 
35540 #define PMU_MISC2_REG2_OK_MASK                   (0x400000U)
35541 #define PMU_MISC2_REG2_OK_SHIFT                  (22U)
35542 #define PMU_MISC2_REG2_OK(x)                     (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
35543 
35544 #define PMU_MISC2_AUDIO_DIV_MSB_MASK             (0x800000U)
35545 #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT            (23U)
35546 /*! AUDIO_DIV_MSB
35547  *  0b0..divide by 1 (Default)
35548  *  0b1..divide by 2
35549  */
35550 #define PMU_MISC2_AUDIO_DIV_MSB(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
35551 
35552 #define PMU_MISC2_REG0_STEP_TIME_MASK            (0x3000000U)
35553 #define PMU_MISC2_REG0_STEP_TIME_SHIFT           (24U)
35554 /*! REG0_STEP_TIME
35555  *  0b00..64
35556  *  0b01..128
35557  *  0b10..256
35558  *  0b11..512
35559  */
35560 #define PMU_MISC2_REG0_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
35561 
35562 #define PMU_MISC2_REG1_STEP_TIME_MASK            (0xC000000U)
35563 #define PMU_MISC2_REG1_STEP_TIME_SHIFT           (26U)
35564 /*! REG1_STEP_TIME
35565  *  0b00..64
35566  *  0b01..128
35567  *  0b10..256
35568  *  0b11..512
35569  */
35570 #define PMU_MISC2_REG1_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
35571 
35572 #define PMU_MISC2_REG2_STEP_TIME_MASK            (0x30000000U)
35573 #define PMU_MISC2_REG2_STEP_TIME_SHIFT           (28U)
35574 /*! REG2_STEP_TIME
35575  *  0b00..64
35576  *  0b01..128
35577  *  0b10..256
35578  *  0b11..512
35579  */
35580 #define PMU_MISC2_REG2_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
35581 
35582 #define PMU_MISC2_VIDEO_DIV_MASK                 (0xC0000000U)
35583 #define PMU_MISC2_VIDEO_DIV_SHIFT                (30U)
35584 /*! VIDEO_DIV
35585  *  0b00..divide by 1 (Default)
35586  *  0b01..divide by 2
35587  *  0b10..divide by 1
35588  *  0b11..divide by 4
35589  */
35590 #define PMU_MISC2_VIDEO_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
35591 /*! @} */
35592 
35593 /*! @name MISC2_SET - Miscellaneous Control Register */
35594 /*! @{ */
35595 
35596 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK        (0x7U)
35597 #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT       (0U)
35598 /*! REG0_BO_OFFSET
35599  *  0b100..Brownout offset = 0.100V
35600  *  0b111..Brownout offset = 0.175V
35601  */
35602 #define PMU_MISC2_SET_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
35603 
35604 #define PMU_MISC2_SET_REG0_BO_STATUS_MASK        (0x8U)
35605 #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT       (3U)
35606 /*! REG0_BO_STATUS
35607  *  0b1..Brownout, supply is below target minus brownout offset.
35608  */
35609 #define PMU_MISC2_SET_REG0_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
35610 
35611 #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK        (0x20U)
35612 #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT       (5U)
35613 #define PMU_MISC2_SET_REG0_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
35614 
35615 #define PMU_MISC2_SET_PLL3_disable_MASK          (0x80U)
35616 #define PMU_MISC2_SET_PLL3_disable_SHIFT         (7U)
35617 #define PMU_MISC2_SET_PLL3_disable(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
35618 
35619 #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK        (0x700U)
35620 #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT       (8U)
35621 /*! REG1_BO_OFFSET
35622  *  0b100..Brownout offset = 0.100V
35623  *  0b111..Brownout offset = 0.175V
35624  */
35625 #define PMU_MISC2_SET_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
35626 
35627 #define PMU_MISC2_SET_REG1_BO_STATUS_MASK        (0x800U)
35628 #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT       (11U)
35629 /*! REG1_BO_STATUS
35630  *  0b1..Brownout, supply is below target minus brownout offset.
35631  */
35632 #define PMU_MISC2_SET_REG1_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
35633 
35634 #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK        (0x2000U)
35635 #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT       (13U)
35636 #define PMU_MISC2_SET_REG1_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
35637 
35638 #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK         (0x8000U)
35639 #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT        (15U)
35640 /*! AUDIO_DIV_LSB
35641  *  0b0..divide by 1 (Default)
35642  *  0b1..divide by 2
35643  */
35644 #define PMU_MISC2_SET_AUDIO_DIV_LSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
35645 
35646 #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK        (0x70000U)
35647 #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT       (16U)
35648 /*! REG2_BO_OFFSET
35649  *  0b100..Brownout offset = 0.100V
35650  *  0b111..Brownout offset = 0.175V
35651  */
35652 #define PMU_MISC2_SET_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
35653 
35654 #define PMU_MISC2_SET_REG2_BO_STATUS_MASK        (0x80000U)
35655 #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT       (19U)
35656 #define PMU_MISC2_SET_REG2_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
35657 
35658 #define PMU_MISC2_SET_REG2_ENABLE_BO_MASK        (0x200000U)
35659 #define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT       (21U)
35660 #define PMU_MISC2_SET_REG2_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
35661 
35662 #define PMU_MISC2_SET_REG2_OK_MASK               (0x400000U)
35663 #define PMU_MISC2_SET_REG2_OK_SHIFT              (22U)
35664 #define PMU_MISC2_SET_REG2_OK(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
35665 
35666 #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK         (0x800000U)
35667 #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT        (23U)
35668 /*! AUDIO_DIV_MSB
35669  *  0b0..divide by 1 (Default)
35670  *  0b1..divide by 2
35671  */
35672 #define PMU_MISC2_SET_AUDIO_DIV_MSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
35673 
35674 #define PMU_MISC2_SET_REG0_STEP_TIME_MASK        (0x3000000U)
35675 #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT       (24U)
35676 /*! REG0_STEP_TIME
35677  *  0b00..64
35678  *  0b01..128
35679  *  0b10..256
35680  *  0b11..512
35681  */
35682 #define PMU_MISC2_SET_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
35683 
35684 #define PMU_MISC2_SET_REG1_STEP_TIME_MASK        (0xC000000U)
35685 #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT       (26U)
35686 /*! REG1_STEP_TIME
35687  *  0b00..64
35688  *  0b01..128
35689  *  0b10..256
35690  *  0b11..512
35691  */
35692 #define PMU_MISC2_SET_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
35693 
35694 #define PMU_MISC2_SET_REG2_STEP_TIME_MASK        (0x30000000U)
35695 #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT       (28U)
35696 /*! REG2_STEP_TIME
35697  *  0b00..64
35698  *  0b01..128
35699  *  0b10..256
35700  *  0b11..512
35701  */
35702 #define PMU_MISC2_SET_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
35703 
35704 #define PMU_MISC2_SET_VIDEO_DIV_MASK             (0xC0000000U)
35705 #define PMU_MISC2_SET_VIDEO_DIV_SHIFT            (30U)
35706 /*! VIDEO_DIV
35707  *  0b00..divide by 1 (Default)
35708  *  0b01..divide by 2
35709  *  0b10..divide by 1
35710  *  0b11..divide by 4
35711  */
35712 #define PMU_MISC2_SET_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
35713 /*! @} */
35714 
35715 /*! @name MISC2_CLR - Miscellaneous Control Register */
35716 /*! @{ */
35717 
35718 #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK        (0x7U)
35719 #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT       (0U)
35720 /*! REG0_BO_OFFSET
35721  *  0b100..Brownout offset = 0.100V
35722  *  0b111..Brownout offset = 0.175V
35723  */
35724 #define PMU_MISC2_CLR_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
35725 
35726 #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK        (0x8U)
35727 #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT       (3U)
35728 /*! REG0_BO_STATUS
35729  *  0b1..Brownout, supply is below target minus brownout offset.
35730  */
35731 #define PMU_MISC2_CLR_REG0_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
35732 
35733 #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK        (0x20U)
35734 #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT       (5U)
35735 #define PMU_MISC2_CLR_REG0_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
35736 
35737 #define PMU_MISC2_CLR_PLL3_disable_MASK          (0x80U)
35738 #define PMU_MISC2_CLR_PLL3_disable_SHIFT         (7U)
35739 #define PMU_MISC2_CLR_PLL3_disable(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
35740 
35741 #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK        (0x700U)
35742 #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT       (8U)
35743 /*! REG1_BO_OFFSET
35744  *  0b100..Brownout offset = 0.100V
35745  *  0b111..Brownout offset = 0.175V
35746  */
35747 #define PMU_MISC2_CLR_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
35748 
35749 #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK        (0x800U)
35750 #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT       (11U)
35751 /*! REG1_BO_STATUS
35752  *  0b1..Brownout, supply is below target minus brownout offset.
35753  */
35754 #define PMU_MISC2_CLR_REG1_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
35755 
35756 #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK        (0x2000U)
35757 #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT       (13U)
35758 #define PMU_MISC2_CLR_REG1_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
35759 
35760 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK         (0x8000U)
35761 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT        (15U)
35762 /*! AUDIO_DIV_LSB
35763  *  0b0..divide by 1 (Default)
35764  *  0b1..divide by 2
35765  */
35766 #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
35767 
35768 #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK        (0x70000U)
35769 #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT       (16U)
35770 /*! REG2_BO_OFFSET
35771  *  0b100..Brownout offset = 0.100V
35772  *  0b111..Brownout offset = 0.175V
35773  */
35774 #define PMU_MISC2_CLR_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
35775 
35776 #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK        (0x80000U)
35777 #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT       (19U)
35778 #define PMU_MISC2_CLR_REG2_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
35779 
35780 #define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK        (0x200000U)
35781 #define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT       (21U)
35782 #define PMU_MISC2_CLR_REG2_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
35783 
35784 #define PMU_MISC2_CLR_REG2_OK_MASK               (0x400000U)
35785 #define PMU_MISC2_CLR_REG2_OK_SHIFT              (22U)
35786 #define PMU_MISC2_CLR_REG2_OK(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
35787 
35788 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK         (0x800000U)
35789 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT        (23U)
35790 /*! AUDIO_DIV_MSB
35791  *  0b0..divide by 1 (Default)
35792  *  0b1..divide by 2
35793  */
35794 #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
35795 
35796 #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK        (0x3000000U)
35797 #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT       (24U)
35798 /*! REG0_STEP_TIME
35799  *  0b00..64
35800  *  0b01..128
35801  *  0b10..256
35802  *  0b11..512
35803  */
35804 #define PMU_MISC2_CLR_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
35805 
35806 #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK        (0xC000000U)
35807 #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT       (26U)
35808 /*! REG1_STEP_TIME
35809  *  0b00..64
35810  *  0b01..128
35811  *  0b10..256
35812  *  0b11..512
35813  */
35814 #define PMU_MISC2_CLR_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
35815 
35816 #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK        (0x30000000U)
35817 #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT       (28U)
35818 /*! REG2_STEP_TIME
35819  *  0b00..64
35820  *  0b01..128
35821  *  0b10..256
35822  *  0b11..512
35823  */
35824 #define PMU_MISC2_CLR_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
35825 
35826 #define PMU_MISC2_CLR_VIDEO_DIV_MASK             (0xC0000000U)
35827 #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT            (30U)
35828 /*! VIDEO_DIV
35829  *  0b00..divide by 1 (Default)
35830  *  0b01..divide by 2
35831  *  0b10..divide by 1
35832  *  0b11..divide by 4
35833  */
35834 #define PMU_MISC2_CLR_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
35835 /*! @} */
35836 
35837 /*! @name MISC2_TOG - Miscellaneous Control Register */
35838 /*! @{ */
35839 
35840 #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK        (0x7U)
35841 #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT       (0U)
35842 /*! REG0_BO_OFFSET
35843  *  0b100..Brownout offset = 0.100V
35844  *  0b111..Brownout offset = 0.175V
35845  */
35846 #define PMU_MISC2_TOG_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
35847 
35848 #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK        (0x8U)
35849 #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT       (3U)
35850 /*! REG0_BO_STATUS
35851  *  0b1..Brownout, supply is below target minus brownout offset.
35852  */
35853 #define PMU_MISC2_TOG_REG0_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
35854 
35855 #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK        (0x20U)
35856 #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT       (5U)
35857 #define PMU_MISC2_TOG_REG0_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
35858 
35859 #define PMU_MISC2_TOG_PLL3_disable_MASK          (0x80U)
35860 #define PMU_MISC2_TOG_PLL3_disable_SHIFT         (7U)
35861 #define PMU_MISC2_TOG_PLL3_disable(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
35862 
35863 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK        (0x700U)
35864 #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT       (8U)
35865 /*! REG1_BO_OFFSET
35866  *  0b100..Brownout offset = 0.100V
35867  *  0b111..Brownout offset = 0.175V
35868  */
35869 #define PMU_MISC2_TOG_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
35870 
35871 #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK        (0x800U)
35872 #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT       (11U)
35873 /*! REG1_BO_STATUS
35874  *  0b1..Brownout, supply is below target minus brownout offset.
35875  */
35876 #define PMU_MISC2_TOG_REG1_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
35877 
35878 #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK        (0x2000U)
35879 #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT       (13U)
35880 #define PMU_MISC2_TOG_REG1_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
35881 
35882 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK         (0x8000U)
35883 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT        (15U)
35884 /*! AUDIO_DIV_LSB
35885  *  0b0..divide by 1 (Default)
35886  *  0b1..divide by 2
35887  */
35888 #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
35889 
35890 #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK        (0x70000U)
35891 #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT       (16U)
35892 /*! REG2_BO_OFFSET
35893  *  0b100..Brownout offset = 0.100V
35894  *  0b111..Brownout offset = 0.175V
35895  */
35896 #define PMU_MISC2_TOG_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
35897 
35898 #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK        (0x80000U)
35899 #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT       (19U)
35900 #define PMU_MISC2_TOG_REG2_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
35901 
35902 #define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK        (0x200000U)
35903 #define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT       (21U)
35904 #define PMU_MISC2_TOG_REG2_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
35905 
35906 #define PMU_MISC2_TOG_REG2_OK_MASK               (0x400000U)
35907 #define PMU_MISC2_TOG_REG2_OK_SHIFT              (22U)
35908 #define PMU_MISC2_TOG_REG2_OK(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
35909 
35910 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK         (0x800000U)
35911 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT        (23U)
35912 /*! AUDIO_DIV_MSB
35913  *  0b0..divide by 1 (Default)
35914  *  0b1..divide by 2
35915  */
35916 #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
35917 
35918 #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK        (0x3000000U)
35919 #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT       (24U)
35920 /*! REG0_STEP_TIME
35921  *  0b00..64
35922  *  0b01..128
35923  *  0b10..256
35924  *  0b11..512
35925  */
35926 #define PMU_MISC2_TOG_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
35927 
35928 #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK        (0xC000000U)
35929 #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT       (26U)
35930 /*! REG1_STEP_TIME
35931  *  0b00..64
35932  *  0b01..128
35933  *  0b10..256
35934  *  0b11..512
35935  */
35936 #define PMU_MISC2_TOG_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
35937 
35938 #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK        (0x30000000U)
35939 #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT       (28U)
35940 /*! REG2_STEP_TIME
35941  *  0b00..64
35942  *  0b01..128
35943  *  0b10..256
35944  *  0b11..512
35945  */
35946 #define PMU_MISC2_TOG_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
35947 
35948 #define PMU_MISC2_TOG_VIDEO_DIV_MASK             (0xC0000000U)
35949 #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT            (30U)
35950 /*! VIDEO_DIV
35951  *  0b00..divide by 1 (Default)
35952  *  0b01..divide by 2
35953  *  0b10..divide by 1
35954  *  0b11..divide by 4
35955  */
35956 #define PMU_MISC2_TOG_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
35957 /*! @} */
35958 
35959 
35960 /*!
35961  * @}
35962  */ /* end of group PMU_Register_Masks */
35963 
35964 
35965 /* PMU - Peripheral instance base addresses */
35966 /** Peripheral PMU base address */
35967 #define PMU_BASE                                 (0x400D8000u)
35968 /** Peripheral PMU base pointer */
35969 #define PMU                                      ((PMU_Type *)PMU_BASE)
35970 /** Array initializer of PMU peripheral base addresses */
35971 #define PMU_BASE_ADDRS                           { PMU_BASE }
35972 /** Array initializer of PMU peripheral base pointers */
35973 #define PMU_BASE_PTRS                            { PMU }
35974 
35975 /*!
35976  * @}
35977  */ /* end of group PMU_Peripheral_Access_Layer */
35978 
35979 
35980 /* ----------------------------------------------------------------------------
35981    -- PWM Peripheral Access Layer
35982    ---------------------------------------------------------------------------- */
35983 
35984 /*!
35985  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
35986  * @{
35987  */
35988 
35989 /** PWM - Register Layout Typedef */
35990 typedef struct {
35991   struct {                                         /* offset: 0x0, array step: 0x60 */
35992     __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
35993     __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
35994     __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
35995     __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
35996          uint8_t RESERVED_0[2];
35997     __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
35998     __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
35999     __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
36000     __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
36001     __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
36002     __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
36003     __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
36004     __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
36005     __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
36006     __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
36007     __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
36008     __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
36009     __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
36010     __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
36011     __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
36012     __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
36013     __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
36014     __IO uint16_t DISMAP[2];                         /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */
36015     __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
36016     __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
36017     __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
36018     __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
36019     __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
36020     __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
36021     __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
36022     __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
36023     __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
36024     __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
36025     __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
36026     __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
36027     __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
36028     __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
36029     __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
36030     __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
36031     __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
36032     __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
36033     __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
36034     __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
36035          uint8_t RESERVED_1[8];
36036   } SM[4];
36037   __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
36038   __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
36039   __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
36040   __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
36041   __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
36042   __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
36043   __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
36044   __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
36045   __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
36046   __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
36047   __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
36048 } PWM_Type;
36049 
36050 /* ----------------------------------------------------------------------------
36051    -- PWM Register Masks
36052    ---------------------------------------------------------------------------- */
36053 
36054 /*!
36055  * @addtogroup PWM_Register_Masks PWM Register Masks
36056  * @{
36057  */
36058 
36059 /*! @name CNT - Counter Register */
36060 /*! @{ */
36061 
36062 #define PWM_CNT_CNT_MASK                         (0xFFFFU)
36063 #define PWM_CNT_CNT_SHIFT                        (0U)
36064 /*! CNT - Counter Register Bits
36065  */
36066 #define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
36067 /*! @} */
36068 
36069 /* The count of PWM_CNT */
36070 #define PWM_CNT_COUNT                            (4U)
36071 
36072 /*! @name INIT - Initial Count Register */
36073 /*! @{ */
36074 
36075 #define PWM_INIT_INIT_MASK                       (0xFFFFU)
36076 #define PWM_INIT_INIT_SHIFT                      (0U)
36077 /*! INIT - Initial Count Register Bits
36078  */
36079 #define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
36080 /*! @} */
36081 
36082 /* The count of PWM_INIT */
36083 #define PWM_INIT_COUNT                           (4U)
36084 
36085 /*! @name CTRL2 - Control 2 Register */
36086 /*! @{ */
36087 
36088 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
36089 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
36090 /*! CLK_SEL - Clock Source Select
36091  *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
36092  *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
36093  *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
36094  *        setting should not be used in submodule 0 as it will force the clock to logic 0.
36095  *  0b11..reserved
36096  */
36097 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
36098 
36099 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
36100 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
36101 /*! RELOAD_SEL - Reload Source Select
36102  *  0b0..The local RELOAD signal is used to reload registers.
36103  *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
36104  *       in submodule 0 as it will force the RELOAD signal to logic 0.
36105  */
36106 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
36107 
36108 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
36109 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
36110 /*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
36111  *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
36112  *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
36113  *         submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
36114  *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
36115  *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
36116  *         not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
36117  *  0b100..The local sync signal from this submodule is used to force updates.
36118  *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
36119  *         submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
36120  *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
36121  *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
36122  */
36123 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
36124 
36125 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
36126 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
36127 /*! FORCE - Force Initialization
36128  */
36129 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
36130 
36131 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
36132 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
36133 /*! FRCEN - FRCEN
36134  *  0b0..Initialization from a FORCE_OUT is disabled.
36135  *  0b1..Initialization from a FORCE_OUT is enabled.
36136  */
36137 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
36138 
36139 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
36140 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
36141 /*! INIT_SEL - Initialization Control Select
36142  *  0b00..Local sync (PWM_X) causes initialization.
36143  *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
36144  *        it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
36145  *        reload occurs.
36146  *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
36147  *        will force the INIT signal to logic 0.
36148  *  0b11..EXT_SYNC causes initialization.
36149  */
36150 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
36151 
36152 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
36153 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
36154 /*! PWMX_INIT - PWM_X Initial Value
36155  */
36156 #define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
36157 
36158 #define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
36159 #define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
36160 /*! PWM45_INIT - PWM45 Initial Value
36161  */
36162 #define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
36163 
36164 #define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
36165 #define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
36166 /*! PWM23_INIT - PWM23 Initial Value
36167  */
36168 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
36169 
36170 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
36171 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
36172 /*! INDEP - Independent or Complementary Pair Operation
36173  *  0b0..PWM_A and PWM_B form a complementary PWM pair.
36174  *  0b1..PWM_A and PWM_B outputs are independent PWMs.
36175  */
36176 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
36177 
36178 #define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
36179 #define PWM_CTRL2_WAITEN_SHIFT                   (14U)
36180 /*! WAITEN - WAIT Enable
36181  */
36182 #define PWM_CTRL2_WAITEN(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
36183 
36184 #define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
36185 #define PWM_CTRL2_DBGEN_SHIFT                    (15U)
36186 /*! DBGEN - Debug Enable
36187  */
36188 #define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
36189 /*! @} */
36190 
36191 /* The count of PWM_CTRL2 */
36192 #define PWM_CTRL2_COUNT                          (4U)
36193 
36194 /*! @name CTRL - Control Register */
36195 /*! @{ */
36196 
36197 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
36198 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
36199 /*! DBLEN - Double Switching Enable
36200  *  0b0..Double switching disabled.
36201  *  0b1..Double switching enabled.
36202  */
36203 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
36204 
36205 #define PWM_CTRL_DBLX_MASK                       (0x2U)
36206 #define PWM_CTRL_DBLX_SHIFT                      (1U)
36207 /*! DBLX - PWMX Double Switching Enable
36208  *  0b0..PWMX double pulse disabled.
36209  *  0b1..PWMX double pulse enabled.
36210  */
36211 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
36212 
36213 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
36214 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
36215 /*! LDMOD - Load Mode Select
36216  *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
36217  *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
36218  *       In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
36219  */
36220 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
36221 
36222 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
36223 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
36224 /*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
36225  *  0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
36226  *  0b1..DBLPWM is split to PWMA and PWMB.
36227  */
36228 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
36229 
36230 #define PWM_CTRL_PRSC_MASK                       (0x70U)
36231 #define PWM_CTRL_PRSC_SHIFT                      (4U)
36232 /*! PRSC - Prescaler
36233  *  0b000..PWM clock frequency = fclk
36234  *  0b001..PWM clock frequency = fclk/2
36235  *  0b010..PWM clock frequency = fclk/4
36236  *  0b011..PWM clock frequency = fclk/8
36237  *  0b100..PWM clock frequency = fclk/16
36238  *  0b101..PWM clock frequency = fclk/32
36239  *  0b110..PWM clock frequency = fclk/64
36240  *  0b111..PWM clock frequency = fclk/128
36241  */
36242 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
36243 
36244 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
36245 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
36246 /*! COMPMODE - Compare Mode
36247  *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
36248  *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
36249  *       output that is high at the end of a period will maintain this state until a match with VAL3 clears the
36250  *       output in the following period.
36251  *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
36252  *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
36253  *       values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
36254  *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
36255  */
36256 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
36257 
36258 #define PWM_CTRL_DT_MASK                         (0x300U)
36259 #define PWM_CTRL_DT_SHIFT                        (8U)
36260 /*! DT - Deadtime
36261  */
36262 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
36263 
36264 #define PWM_CTRL_FULL_MASK                       (0x400U)
36265 #define PWM_CTRL_FULL_SHIFT                      (10U)
36266 /*! FULL - Full Cycle Reload
36267  *  0b0..Full-cycle reloads disabled.
36268  *  0b1..Full-cycle reloads enabled.
36269  */
36270 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
36271 
36272 #define PWM_CTRL_HALF_MASK                       (0x800U)
36273 #define PWM_CTRL_HALF_SHIFT                      (11U)
36274 /*! HALF - Half Cycle Reload
36275  *  0b0..Half-cycle reloads disabled.
36276  *  0b1..Half-cycle reloads enabled.
36277  */
36278 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
36279 
36280 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
36281 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
36282 /*! LDFQ - Load Frequency
36283  *  0b0000..Every PWM opportunity
36284  *  0b0001..Every 2 PWM opportunities
36285  *  0b0010..Every 3 PWM opportunities
36286  *  0b0011..Every 4 PWM opportunities
36287  *  0b0100..Every 5 PWM opportunities
36288  *  0b0101..Every 6 PWM opportunities
36289  *  0b0110..Every 7 PWM opportunities
36290  *  0b0111..Every 8 PWM opportunities
36291  *  0b1000..Every 9 PWM opportunities
36292  *  0b1001..Every 10 PWM opportunities
36293  *  0b1010..Every 11 PWM opportunities
36294  *  0b1011..Every 12 PWM opportunities
36295  *  0b1100..Every 13 PWM opportunities
36296  *  0b1101..Every 14 PWM opportunities
36297  *  0b1110..Every 15 PWM opportunities
36298  *  0b1111..Every 16 PWM opportunities
36299  */
36300 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
36301 /*! @} */
36302 
36303 /* The count of PWM_CTRL */
36304 #define PWM_CTRL_COUNT                           (4U)
36305 
36306 /*! @name VAL0 - Value Register 0 */
36307 /*! @{ */
36308 
36309 #define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
36310 #define PWM_VAL0_VAL0_SHIFT                      (0U)
36311 /*! VAL0 - Value Register 0
36312  */
36313 #define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
36314 /*! @} */
36315 
36316 /* The count of PWM_VAL0 */
36317 #define PWM_VAL0_COUNT                           (4U)
36318 
36319 /*! @name FRACVAL1 - Fractional Value Register 1 */
36320 /*! @{ */
36321 
36322 #define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
36323 #define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
36324 /*! FRACVAL1 - Fractional Value 1 Register
36325  */
36326 #define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
36327 /*! @} */
36328 
36329 /* The count of PWM_FRACVAL1 */
36330 #define PWM_FRACVAL1_COUNT                       (4U)
36331 
36332 /*! @name VAL1 - Value Register 1 */
36333 /*! @{ */
36334 
36335 #define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
36336 #define PWM_VAL1_VAL1_SHIFT                      (0U)
36337 /*! VAL1 - Value Register 1
36338  */
36339 #define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
36340 /*! @} */
36341 
36342 /* The count of PWM_VAL1 */
36343 #define PWM_VAL1_COUNT                           (4U)
36344 
36345 /*! @name FRACVAL2 - Fractional Value Register 2 */
36346 /*! @{ */
36347 
36348 #define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
36349 #define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
36350 /*! FRACVAL2 - Fractional Value 2
36351  */
36352 #define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
36353 /*! @} */
36354 
36355 /* The count of PWM_FRACVAL2 */
36356 #define PWM_FRACVAL2_COUNT                       (4U)
36357 
36358 /*! @name VAL2 - Value Register 2 */
36359 /*! @{ */
36360 
36361 #define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
36362 #define PWM_VAL2_VAL2_SHIFT                      (0U)
36363 /*! VAL2 - Value Register 2
36364  */
36365 #define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
36366 /*! @} */
36367 
36368 /* The count of PWM_VAL2 */
36369 #define PWM_VAL2_COUNT                           (4U)
36370 
36371 /*! @name FRACVAL3 - Fractional Value Register 3 */
36372 /*! @{ */
36373 
36374 #define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
36375 #define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
36376 /*! FRACVAL3 - Fractional Value 3
36377  */
36378 #define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
36379 /*! @} */
36380 
36381 /* The count of PWM_FRACVAL3 */
36382 #define PWM_FRACVAL3_COUNT                       (4U)
36383 
36384 /*! @name VAL3 - Value Register 3 */
36385 /*! @{ */
36386 
36387 #define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
36388 #define PWM_VAL3_VAL3_SHIFT                      (0U)
36389 /*! VAL3 - Value Register 3
36390  */
36391 #define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
36392 /*! @} */
36393 
36394 /* The count of PWM_VAL3 */
36395 #define PWM_VAL3_COUNT                           (4U)
36396 
36397 /*! @name FRACVAL4 - Fractional Value Register 4 */
36398 /*! @{ */
36399 
36400 #define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
36401 #define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
36402 /*! FRACVAL4 - Fractional Value 4
36403  */
36404 #define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
36405 /*! @} */
36406 
36407 /* The count of PWM_FRACVAL4 */
36408 #define PWM_FRACVAL4_COUNT                       (4U)
36409 
36410 /*! @name VAL4 - Value Register 4 */
36411 /*! @{ */
36412 
36413 #define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
36414 #define PWM_VAL4_VAL4_SHIFT                      (0U)
36415 /*! VAL4 - Value Register 4
36416  */
36417 #define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
36418 /*! @} */
36419 
36420 /* The count of PWM_VAL4 */
36421 #define PWM_VAL4_COUNT                           (4U)
36422 
36423 /*! @name FRACVAL5 - Fractional Value Register 5 */
36424 /*! @{ */
36425 
36426 #define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
36427 #define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
36428 /*! FRACVAL5 - Fractional Value 5
36429  */
36430 #define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
36431 /*! @} */
36432 
36433 /* The count of PWM_FRACVAL5 */
36434 #define PWM_FRACVAL5_COUNT                       (4U)
36435 
36436 /*! @name VAL5 - Value Register 5 */
36437 /*! @{ */
36438 
36439 #define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
36440 #define PWM_VAL5_VAL5_SHIFT                      (0U)
36441 /*! VAL5 - Value Register 5
36442  */
36443 #define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
36444 /*! @} */
36445 
36446 /* The count of PWM_VAL5 */
36447 #define PWM_VAL5_COUNT                           (4U)
36448 
36449 /*! @name FRCTRL - Fractional Control Register */
36450 /*! @{ */
36451 
36452 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
36453 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
36454 /*! FRAC1_EN - Fractional Cycle PWM Period Enable
36455  *  0b0..Disable fractional cycle length for the PWM period.
36456  *  0b1..Enable fractional cycle length for the PWM period.
36457  */
36458 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
36459 
36460 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
36461 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
36462 /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
36463  *  0b0..Disable fractional cycle placement for PWM_A.
36464  *  0b1..Enable fractional cycle placement for PWM_A.
36465  */
36466 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
36467 
36468 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
36469 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
36470 /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
36471  *  0b0..Disable fractional cycle placement for PWM_B.
36472  *  0b1..Enable fractional cycle placement for PWM_B.
36473  */
36474 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
36475 
36476 #define PWM_FRCTRL_FRAC_PU_MASK                  (0x100U)
36477 #define PWM_FRCTRL_FRAC_PU_SHIFT                 (8U)
36478 /*! FRAC_PU - Fractional Delay Circuit Power Up
36479  *  0b0..Turn off fractional delay logic.
36480  *  0b1..Power up fractional delay logic.
36481  */
36482 #define PWM_FRCTRL_FRAC_PU(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
36483 
36484 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
36485 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
36486 /*! TEST - Test Status Bit
36487  */
36488 #define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
36489 /*! @} */
36490 
36491 /* The count of PWM_FRCTRL */
36492 #define PWM_FRCTRL_COUNT                         (4U)
36493 
36494 /*! @name OCTRL - Output Control Register */
36495 /*! @{ */
36496 
36497 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
36498 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
36499 /*! PWMXFS - PWM_X Fault State
36500  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
36501  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
36502  *  0b10..Output is tristated.
36503  *  0b11..Output is tristated.
36504  */
36505 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
36506 
36507 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
36508 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
36509 /*! PWMBFS - PWM_B Fault State
36510  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
36511  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
36512  *  0b10..Output is tristated.
36513  *  0b11..Output is tristated.
36514  */
36515 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
36516 
36517 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
36518 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
36519 /*! PWMAFS - PWM_A Fault State
36520  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
36521  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
36522  *  0b10..Output is tristated.
36523  *  0b11..Output is tristated.
36524  */
36525 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
36526 
36527 #define PWM_OCTRL_POLX_MASK                      (0x100U)
36528 #define PWM_OCTRL_POLX_SHIFT                     (8U)
36529 /*! POLX - PWM_X Output Polarity
36530  *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
36531  *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
36532  */
36533 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
36534 
36535 #define PWM_OCTRL_POLB_MASK                      (0x200U)
36536 #define PWM_OCTRL_POLB_SHIFT                     (9U)
36537 /*! POLB - PWM_B Output Polarity
36538  *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
36539  *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
36540  */
36541 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
36542 
36543 #define PWM_OCTRL_POLA_MASK                      (0x400U)
36544 #define PWM_OCTRL_POLA_SHIFT                     (10U)
36545 /*! POLA - PWM_A Output Polarity
36546  *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
36547  *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
36548  */
36549 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
36550 
36551 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
36552 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
36553 /*! PWMX_IN - PWM_X Input
36554  */
36555 #define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
36556 
36557 #define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
36558 #define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
36559 /*! PWMB_IN - PWM_B Input
36560  */
36561 #define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
36562 
36563 #define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
36564 #define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
36565 /*! PWMA_IN - PWM_A Input
36566  */
36567 #define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
36568 /*! @} */
36569 
36570 /* The count of PWM_OCTRL */
36571 #define PWM_OCTRL_COUNT                          (4U)
36572 
36573 /*! @name STS - Status Register */
36574 /*! @{ */
36575 
36576 #define PWM_STS_CMPF_MASK                        (0x3FU)
36577 #define PWM_STS_CMPF_SHIFT                       (0U)
36578 /*! CMPF - Compare Flags
36579  *  0b000000..No compare event has occurred for a particular VALx value.
36580  *  0b000001..A compare event has occurred for a particular VALx value.
36581  */
36582 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
36583 
36584 #define PWM_STS_CFX0_MASK                        (0x40U)
36585 #define PWM_STS_CFX0_SHIFT                       (6U)
36586 /*! CFX0 - Capture Flag X0
36587  */
36588 #define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
36589 
36590 #define PWM_STS_CFX1_MASK                        (0x80U)
36591 #define PWM_STS_CFX1_SHIFT                       (7U)
36592 /*! CFX1 - Capture Flag X1
36593  */
36594 #define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
36595 
36596 #define PWM_STS_CFB0_MASK                        (0x100U)
36597 #define PWM_STS_CFB0_SHIFT                       (8U)
36598 /*! CFB0 - Capture Flag B0
36599  */
36600 #define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
36601 
36602 #define PWM_STS_CFB1_MASK                        (0x200U)
36603 #define PWM_STS_CFB1_SHIFT                       (9U)
36604 /*! CFB1 - Capture Flag B1
36605  */
36606 #define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
36607 
36608 #define PWM_STS_CFA0_MASK                        (0x400U)
36609 #define PWM_STS_CFA0_SHIFT                       (10U)
36610 /*! CFA0 - Capture Flag A0
36611  */
36612 #define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
36613 
36614 #define PWM_STS_CFA1_MASK                        (0x800U)
36615 #define PWM_STS_CFA1_SHIFT                       (11U)
36616 /*! CFA1 - Capture Flag A1
36617  */
36618 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
36619 
36620 #define PWM_STS_RF_MASK                          (0x1000U)
36621 #define PWM_STS_RF_SHIFT                         (12U)
36622 /*! RF - Reload Flag
36623  *  0b0..No new reload cycle since last STS[RF] clearing
36624  *  0b1..New reload cycle since last STS[RF] clearing
36625  */
36626 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
36627 
36628 #define PWM_STS_REF_MASK                         (0x2000U)
36629 #define PWM_STS_REF_SHIFT                        (13U)
36630 /*! REF - Reload Error Flag
36631  *  0b0..No reload error occurred.
36632  *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
36633  */
36634 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
36635 
36636 #define PWM_STS_RUF_MASK                         (0x4000U)
36637 #define PWM_STS_RUF_SHIFT                        (14U)
36638 /*! RUF - Registers Updated Flag
36639  *  0b0..No register update has occurred since last reload.
36640  *  0b1..At least one of the double buffered registers has been updated since the last reload.
36641  */
36642 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
36643 /*! @} */
36644 
36645 /* The count of PWM_STS */
36646 #define PWM_STS_COUNT                            (4U)
36647 
36648 /*! @name INTEN - Interrupt Enable Register */
36649 /*! @{ */
36650 
36651 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
36652 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
36653 /*! CMPIE - Compare Interrupt Enables
36654  *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
36655  *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
36656  */
36657 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
36658 
36659 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
36660 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
36661 /*! CX0IE - Capture X 0 Interrupt Enable
36662  *  0b0..Interrupt request disabled for STS[CFX0].
36663  *  0b1..Interrupt request enabled for STS[CFX0].
36664  */
36665 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
36666 
36667 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
36668 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
36669 /*! CX1IE - Capture X 1 Interrupt Enable
36670  *  0b0..Interrupt request disabled for STS[CFX1].
36671  *  0b1..Interrupt request enabled for STS[CFX1].
36672  */
36673 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
36674 
36675 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
36676 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
36677 /*! CB0IE - Capture B 0 Interrupt Enable
36678  *  0b0..Interrupt request disabled for STS[CFB0].
36679  *  0b1..Interrupt request enabled for STS[CFB0].
36680  */
36681 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
36682 
36683 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
36684 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
36685 /*! CB1IE - Capture B 1 Interrupt Enable
36686  *  0b0..Interrupt request disabled for STS[CFB1].
36687  *  0b1..Interrupt request enabled for STS[CFB1].
36688  */
36689 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
36690 
36691 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
36692 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
36693 /*! CA0IE - Capture A 0 Interrupt Enable
36694  *  0b0..Interrupt request disabled for STS[CFA0].
36695  *  0b1..Interrupt request enabled for STS[CFA0].
36696  */
36697 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
36698 
36699 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
36700 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
36701 /*! CA1IE - Capture A 1 Interrupt Enable
36702  *  0b0..Interrupt request disabled for STS[CFA1].
36703  *  0b1..Interrupt request enabled for STS[CFA1].
36704  */
36705 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
36706 
36707 #define PWM_INTEN_RIE_MASK                       (0x1000U)
36708 #define PWM_INTEN_RIE_SHIFT                      (12U)
36709 /*! RIE - Reload Interrupt Enable
36710  *  0b0..STS[RF] CPU interrupt requests disabled
36711  *  0b1..STS[RF] CPU interrupt requests enabled
36712  */
36713 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
36714 
36715 #define PWM_INTEN_REIE_MASK                      (0x2000U)
36716 #define PWM_INTEN_REIE_SHIFT                     (13U)
36717 /*! REIE - Reload Error Interrupt Enable
36718  *  0b0..STS[REF] CPU interrupt requests disabled
36719  *  0b1..STS[REF] CPU interrupt requests enabled
36720  */
36721 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
36722 /*! @} */
36723 
36724 /* The count of PWM_INTEN */
36725 #define PWM_INTEN_COUNT                          (4U)
36726 
36727 /*! @name DMAEN - DMA Enable Register */
36728 /*! @{ */
36729 
36730 #define PWM_DMAEN_CX0DE_MASK                     (0x1U)
36731 #define PWM_DMAEN_CX0DE_SHIFT                    (0U)
36732 /*! CX0DE - Capture X0 FIFO DMA Enable
36733  */
36734 #define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
36735 
36736 #define PWM_DMAEN_CX1DE_MASK                     (0x2U)
36737 #define PWM_DMAEN_CX1DE_SHIFT                    (1U)
36738 /*! CX1DE - Capture X1 FIFO DMA Enable
36739  */
36740 #define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
36741 
36742 #define PWM_DMAEN_CB0DE_MASK                     (0x4U)
36743 #define PWM_DMAEN_CB0DE_SHIFT                    (2U)
36744 /*! CB0DE - Capture B0 FIFO DMA Enable
36745  */
36746 #define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
36747 
36748 #define PWM_DMAEN_CB1DE_MASK                     (0x8U)
36749 #define PWM_DMAEN_CB1DE_SHIFT                    (3U)
36750 /*! CB1DE - Capture B1 FIFO DMA Enable
36751  */
36752 #define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
36753 
36754 #define PWM_DMAEN_CA0DE_MASK                     (0x10U)
36755 #define PWM_DMAEN_CA0DE_SHIFT                    (4U)
36756 /*! CA0DE - Capture A0 FIFO DMA Enable
36757  */
36758 #define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
36759 
36760 #define PWM_DMAEN_CA1DE_MASK                     (0x20U)
36761 #define PWM_DMAEN_CA1DE_SHIFT                    (5U)
36762 /*! CA1DE - Capture A1 FIFO DMA Enable
36763  */
36764 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
36765 
36766 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
36767 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
36768 /*! CAPTDE - Capture DMA Enable Source Select
36769  *  0b00..Read DMA requests disabled.
36770  *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
36771  *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
36772  *        which watermark(s) the DMA request is sensitive.
36773  *  0b10..A local sync (VAL1 matches counter) sets the read DMA request.
36774  *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
36775  */
36776 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
36777 
36778 #define PWM_DMAEN_FAND_MASK                      (0x100U)
36779 #define PWM_DMAEN_FAND_SHIFT                     (8U)
36780 /*! FAND - FIFO Watermark AND Control
36781  *  0b0..Selected FIFO watermarks are OR'ed together.
36782  *  0b1..Selected FIFO watermarks are AND'ed together.
36783  */
36784 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
36785 
36786 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
36787 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
36788 /*! VALDE - Value Registers DMA Enable
36789  *  0b0..DMA write requests disabled
36790  *  0b1..DMA write requests for the VALx and FRACVALx registers enabled
36791  */
36792 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
36793 /*! @} */
36794 
36795 /* The count of PWM_DMAEN */
36796 #define PWM_DMAEN_COUNT                          (4U)
36797 
36798 /*! @name TCTRL - Output Trigger Control Register */
36799 /*! @{ */
36800 
36801 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
36802 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
36803 /*! OUT_TRIG_EN - Output Trigger Enables
36804  *  0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
36805  *  0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value.
36806  */
36807 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
36808 
36809 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
36810 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
36811 /*! TRGFRQ - Trigger frequency
36812  *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
36813  *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
36814  *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
36815  */
36816 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
36817 
36818 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
36819 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
36820 /*! PWBOT1 - Output Trigger 1 Source Select
36821  *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
36822  *  0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
36823  */
36824 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
36825 
36826 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
36827 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
36828 /*! PWAOT0 - Output Trigger 0 Source Select
36829  *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
36830  *  0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
36831  */
36832 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
36833 /*! @} */
36834 
36835 /* The count of PWM_TCTRL */
36836 #define PWM_TCTRL_COUNT                          (4U)
36837 
36838 /*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */
36839 /*! @{ */
36840 
36841 #define PWM_DISMAP_DIS0A_MASK                    (0xFU)
36842 #define PWM_DISMAP_DIS0A_SHIFT                   (0U)
36843 /*! DIS0A - PWM_A Fault Disable Mask 0
36844  */
36845 #define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
36846 
36847 #define PWM_DISMAP_DIS1A_MASK                    (0xFU)
36848 #define PWM_DISMAP_DIS1A_SHIFT                   (0U)
36849 /*! DIS1A - PWM_A Fault Disable Mask 1
36850  */
36851 #define PWM_DISMAP_DIS1A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
36852 
36853 #define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
36854 #define PWM_DISMAP_DIS0B_SHIFT                   (4U)
36855 /*! DIS0B - PWM_B Fault Disable Mask 0
36856  */
36857 #define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
36858 
36859 #define PWM_DISMAP_DIS1B_MASK                    (0xF0U)
36860 #define PWM_DISMAP_DIS1B_SHIFT                   (4U)
36861 /*! DIS1B - PWM_B Fault Disable Mask 1
36862  */
36863 #define PWM_DISMAP_DIS1B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
36864 
36865 #define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
36866 #define PWM_DISMAP_DIS0X_SHIFT                   (8U)
36867 /*! DIS0X - PWM_X Fault Disable Mask 0
36868  */
36869 #define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
36870 
36871 #define PWM_DISMAP_DIS1X_MASK                    (0xF00U)
36872 #define PWM_DISMAP_DIS1X_SHIFT                   (8U)
36873 /*! DIS1X - PWM_X Fault Disable Mask 1
36874  */
36875 #define PWM_DISMAP_DIS1X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
36876 /*! @} */
36877 
36878 /* The count of PWM_DISMAP */
36879 #define PWM_DISMAP_COUNT                         (4U)
36880 
36881 /* The count of PWM_DISMAP */
36882 #define PWM_DISMAP_COUNT2                        (2U)
36883 
36884 /*! @name DTCNT0 - Deadtime Count Register 0 */
36885 /*! @{ */
36886 
36887 #define PWM_DTCNT0_DTCNT0_MASK                   (0xFFFFU)
36888 #define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
36889 /*! DTCNT0 - DTCNT0
36890  */
36891 #define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
36892 /*! @} */
36893 
36894 /* The count of PWM_DTCNT0 */
36895 #define PWM_DTCNT0_COUNT                         (4U)
36896 
36897 /*! @name DTCNT1 - Deadtime Count Register 1 */
36898 /*! @{ */
36899 
36900 #define PWM_DTCNT1_DTCNT1_MASK                   (0xFFFFU)
36901 #define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
36902 /*! DTCNT1 - DTCNT1
36903  */
36904 #define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
36905 /*! @} */
36906 
36907 /* The count of PWM_DTCNT1 */
36908 #define PWM_DTCNT1_COUNT                         (4U)
36909 
36910 /*! @name CAPTCTRLA - Capture Control A Register */
36911 /*! @{ */
36912 
36913 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
36914 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
36915 /*! ARMA - Arm A
36916  *  0b0..Input capture operation is disabled.
36917  *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
36918  */
36919 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
36920 
36921 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
36922 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
36923 /*! ONESHOTA - One Shot Mode A
36924  *  0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
36925  *       first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1
36926  *       is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed.
36927  *       The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
36928  *       indefinitely on the enabled capture circuit.
36929  *  0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
36930  *       after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
36931  *       armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No
36932  *       further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is
36933  *       enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
36934  */
36935 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
36936 
36937 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
36938 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
36939 /*! EDGA0 - Edge A 0
36940  *  0b00..Disabled
36941  *  0b01..Capture falling edges
36942  *  0b10..Capture rising edges
36943  *  0b11..Capture any edge
36944  */
36945 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
36946 
36947 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
36948 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
36949 /*! EDGA1 - Edge A 1
36950  *  0b00..Disabled
36951  *  0b01..Capture falling edges
36952  *  0b10..Capture rising edges
36953  *  0b11..Capture any edge
36954  */
36955 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
36956 
36957 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
36958 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
36959 /*! INP_SELA - Input Select A
36960  *  0b0..Raw PWM_A input signal selected as source.
36961  *  0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
36962  *       edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and
36963  *       CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the
36964  *       CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
36965  */
36966 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
36967 
36968 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
36969 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
36970 /*! EDGCNTA_EN - Edge Counter A Enable
36971  *  0b0..Edge counter disabled and held in reset
36972  *  0b1..Edge counter enabled
36973  */
36974 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
36975 
36976 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
36977 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
36978 /*! CFAWM - Capture A FIFOs Water Mark
36979  */
36980 #define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
36981 
36982 #define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
36983 #define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
36984 /*! CA0CNT - Capture A0 FIFO Word Count
36985  */
36986 #define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
36987 
36988 #define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
36989 #define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
36990 /*! CA1CNT - Capture A1 FIFO Word Count
36991  */
36992 #define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
36993 /*! @} */
36994 
36995 /* The count of PWM_CAPTCTRLA */
36996 #define PWM_CAPTCTRLA_COUNT                      (4U)
36997 
36998 /*! @name CAPTCOMPA - Capture Compare A Register */
36999 /*! @{ */
37000 
37001 #define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
37002 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
37003 /*! EDGCMPA - Edge Compare A
37004  */
37005 #define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
37006 
37007 #define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
37008 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
37009 /*! EDGCNTA - Edge Counter A
37010  */
37011 #define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
37012 /*! @} */
37013 
37014 /* The count of PWM_CAPTCOMPA */
37015 #define PWM_CAPTCOMPA_COUNT                      (4U)
37016 
37017 /*! @name CAPTCTRLB - Capture Control B Register */
37018 /*! @{ */
37019 
37020 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
37021 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
37022 /*! ARMB - Arm B
37023  *  0b0..Input capture operation is disabled.
37024  *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
37025  */
37026 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
37027 
37028 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
37029 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
37030 /*! ONESHOTB - One Shot Mode B
37031  *  0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
37032  *       first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1
37033  *       is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed.
37034  *       The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
37035  *       indefinitely on the enabled capture circuit.
37036  *  0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
37037  *       after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
37038  *       armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No
37039  *       further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is
37040  *       enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
37041  */
37042 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
37043 
37044 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
37045 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
37046 /*! EDGB0 - Edge B 0
37047  *  0b00..Disabled
37048  *  0b01..Capture falling edges
37049  *  0b10..Capture rising edges
37050  *  0b11..Capture any edge
37051  */
37052 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
37053 
37054 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
37055 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
37056 /*! EDGB1 - Edge B 1
37057  *  0b00..Disabled
37058  *  0b01..Capture falling edges
37059  *  0b10..Capture rising edges
37060  *  0b11..Capture any edge
37061  */
37062 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
37063 
37064 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
37065 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
37066 /*! INP_SELB - Input Select B
37067  *  0b0..Raw PWM_B input signal selected as source.
37068  *  0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
37069  *       edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and
37070  *       CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the
37071  *       CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
37072  */
37073 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
37074 
37075 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
37076 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
37077 /*! EDGCNTB_EN - Edge Counter B Enable
37078  *  0b0..Edge counter disabled and held in reset
37079  *  0b1..Edge counter enabled
37080  */
37081 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
37082 
37083 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
37084 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
37085 /*! CFBWM - Capture B FIFOs Water Mark
37086  */
37087 #define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
37088 
37089 #define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
37090 #define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
37091 /*! CB0CNT - Capture B0 FIFO Word Count
37092  */
37093 #define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
37094 
37095 #define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
37096 #define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
37097 /*! CB1CNT - Capture B1 FIFO Word Count
37098  */
37099 #define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
37100 /*! @} */
37101 
37102 /* The count of PWM_CAPTCTRLB */
37103 #define PWM_CAPTCTRLB_COUNT                      (4U)
37104 
37105 /*! @name CAPTCOMPB - Capture Compare B Register */
37106 /*! @{ */
37107 
37108 #define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
37109 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
37110 /*! EDGCMPB - Edge Compare B
37111  */
37112 #define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
37113 
37114 #define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
37115 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
37116 /*! EDGCNTB - Edge Counter B
37117  */
37118 #define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
37119 /*! @} */
37120 
37121 /* The count of PWM_CAPTCOMPB */
37122 #define PWM_CAPTCOMPB_COUNT                      (4U)
37123 
37124 /*! @name CAPTCTRLX - Capture Control X Register */
37125 /*! @{ */
37126 
37127 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
37128 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
37129 /*! ARMX - Arm X
37130  *  0b0..Input capture operation is disabled.
37131  *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
37132  */
37133 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
37134 
37135 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
37136 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
37137 /*! ONESHOTX - One Shot Mode Aux
37138  *  0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
37139  *       first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
37140  *       armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The
37141  *       process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
37142  *       indefinitely on the enabled capture circuit.
37143  *  0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
37144  *       after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
37145  *       armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further
37146  *       captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled,
37147  *       then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
37148  */
37149 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
37150 
37151 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
37152 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
37153 /*! EDGX0 - Edge X 0
37154  *  0b00..Disabled
37155  *  0b01..Capture falling edges
37156  *  0b10..Capture rising edges
37157  *  0b11..Capture any edge
37158  */
37159 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
37160 
37161 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
37162 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
37163 /*! EDGX1 - Edge X 1
37164  *  0b00..Disabled
37165  *  0b01..Capture falling edges
37166  *  0b10..Capture rising edges
37167  *  0b11..Capture any edge
37168  */
37169 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
37170 
37171 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
37172 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
37173 /*! INP_SELX - Input Select X
37174  *  0b0..Raw PWM_X input signal selected as source.
37175  *  0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
37176  *       edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and
37177  *       CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the
37178  *       CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
37179  */
37180 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
37181 
37182 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
37183 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
37184 /*! EDGCNTX_EN - Edge Counter X Enable
37185  *  0b0..Edge counter disabled and held in reset
37186  *  0b1..Edge counter enabled
37187  */
37188 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
37189 
37190 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
37191 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
37192 /*! CFXWM - Capture X FIFOs Water Mark
37193  */
37194 #define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
37195 
37196 #define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
37197 #define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
37198 /*! CX0CNT - Capture X0 FIFO Word Count
37199  */
37200 #define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
37201 
37202 #define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
37203 #define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
37204 /*! CX1CNT - Capture X1 FIFO Word Count
37205  */
37206 #define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
37207 /*! @} */
37208 
37209 /* The count of PWM_CAPTCTRLX */
37210 #define PWM_CAPTCTRLX_COUNT                      (4U)
37211 
37212 /*! @name CAPTCOMPX - Capture Compare X Register */
37213 /*! @{ */
37214 
37215 #define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
37216 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
37217 /*! EDGCMPX - Edge Compare X
37218  */
37219 #define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
37220 
37221 #define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
37222 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
37223 /*! EDGCNTX - Edge Counter X
37224  */
37225 #define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
37226 /*! @} */
37227 
37228 /* The count of PWM_CAPTCOMPX */
37229 #define PWM_CAPTCOMPX_COUNT                      (4U)
37230 
37231 /*! @name CVAL0 - Capture Value 0 Register */
37232 /*! @{ */
37233 
37234 #define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
37235 #define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
37236 /*! CAPTVAL0 - CAPTVAL0
37237  */
37238 #define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
37239 /*! @} */
37240 
37241 /* The count of PWM_CVAL0 */
37242 #define PWM_CVAL0_COUNT                          (4U)
37243 
37244 /*! @name CVAL0CYC - Capture Value 0 Cycle Register */
37245 /*! @{ */
37246 
37247 #define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
37248 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
37249 /*! CVAL0CYC - CVAL0CYC
37250  */
37251 #define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
37252 /*! @} */
37253 
37254 /* The count of PWM_CVAL0CYC */
37255 #define PWM_CVAL0CYC_COUNT                       (4U)
37256 
37257 /*! @name CVAL1 - Capture Value 1 Register */
37258 /*! @{ */
37259 
37260 #define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
37261 #define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
37262 /*! CAPTVAL1 - CAPTVAL1
37263  */
37264 #define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
37265 /*! @} */
37266 
37267 /* The count of PWM_CVAL1 */
37268 #define PWM_CVAL1_COUNT                          (4U)
37269 
37270 /*! @name CVAL1CYC - Capture Value 1 Cycle Register */
37271 /*! @{ */
37272 
37273 #define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
37274 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
37275 /*! CVAL1CYC - CVAL1CYC
37276  */
37277 #define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
37278 /*! @} */
37279 
37280 /* The count of PWM_CVAL1CYC */
37281 #define PWM_CVAL1CYC_COUNT                       (4U)
37282 
37283 /*! @name CVAL2 - Capture Value 2 Register */
37284 /*! @{ */
37285 
37286 #define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
37287 #define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
37288 /*! CAPTVAL2 - CAPTVAL2
37289  */
37290 #define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
37291 /*! @} */
37292 
37293 /* The count of PWM_CVAL2 */
37294 #define PWM_CVAL2_COUNT                          (4U)
37295 
37296 /*! @name CVAL2CYC - Capture Value 2 Cycle Register */
37297 /*! @{ */
37298 
37299 #define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
37300 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
37301 /*! CVAL2CYC - CVAL2CYC
37302  */
37303 #define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
37304 /*! @} */
37305 
37306 /* The count of PWM_CVAL2CYC */
37307 #define PWM_CVAL2CYC_COUNT                       (4U)
37308 
37309 /*! @name CVAL3 - Capture Value 3 Register */
37310 /*! @{ */
37311 
37312 #define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
37313 #define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
37314 /*! CAPTVAL3 - CAPTVAL3
37315  */
37316 #define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
37317 /*! @} */
37318 
37319 /* The count of PWM_CVAL3 */
37320 #define PWM_CVAL3_COUNT                          (4U)
37321 
37322 /*! @name CVAL3CYC - Capture Value 3 Cycle Register */
37323 /*! @{ */
37324 
37325 #define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
37326 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
37327 /*! CVAL3CYC - CVAL3CYC
37328  */
37329 #define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
37330 /*! @} */
37331 
37332 /* The count of PWM_CVAL3CYC */
37333 #define PWM_CVAL3CYC_COUNT                       (4U)
37334 
37335 /*! @name CVAL4 - Capture Value 4 Register */
37336 /*! @{ */
37337 
37338 #define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
37339 #define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
37340 /*! CAPTVAL4 - CAPTVAL4
37341  */
37342 #define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
37343 /*! @} */
37344 
37345 /* The count of PWM_CVAL4 */
37346 #define PWM_CVAL4_COUNT                          (4U)
37347 
37348 /*! @name CVAL4CYC - Capture Value 4 Cycle Register */
37349 /*! @{ */
37350 
37351 #define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
37352 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
37353 /*! CVAL4CYC - CVAL4CYC
37354  */
37355 #define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
37356 /*! @} */
37357 
37358 /* The count of PWM_CVAL4CYC */
37359 #define PWM_CVAL4CYC_COUNT                       (4U)
37360 
37361 /*! @name CVAL5 - Capture Value 5 Register */
37362 /*! @{ */
37363 
37364 #define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
37365 #define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
37366 /*! CAPTVAL5 - CAPTVAL5
37367  */
37368 #define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
37369 /*! @} */
37370 
37371 /* The count of PWM_CVAL5 */
37372 #define PWM_CVAL5_COUNT                          (4U)
37373 
37374 /*! @name CVAL5CYC - Capture Value 5 Cycle Register */
37375 /*! @{ */
37376 
37377 #define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
37378 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
37379 /*! CVAL5CYC - CVAL5CYC
37380  */
37381 #define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
37382 /*! @} */
37383 
37384 /* The count of PWM_CVAL5CYC */
37385 #define PWM_CVAL5CYC_COUNT                       (4U)
37386 
37387 /*! @name OUTEN - Output Enable Register */
37388 /*! @{ */
37389 
37390 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
37391 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
37392 /*! PWMX_EN - PWM_X Output Enables
37393  *  0b0000..PWM_X output disabled.
37394  *  0b0001..PWM_X output enabled.
37395  */
37396 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
37397 
37398 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
37399 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
37400 /*! PWMB_EN - PWM_B Output Enables
37401  *  0b0000..PWM_B output disabled.
37402  *  0b0001..PWM_B output enabled.
37403  */
37404 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
37405 
37406 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
37407 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
37408 /*! PWMA_EN - PWM_A Output Enables
37409  *  0b0000..PWM_A output disabled.
37410  *  0b0001..PWM_A output enabled.
37411  */
37412 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
37413 /*! @} */
37414 
37415 /*! @name MASK - Mask Register */
37416 /*! @{ */
37417 
37418 #define PWM_MASK_MASKX_MASK                      (0xFU)
37419 #define PWM_MASK_MASKX_SHIFT                     (0U)
37420 /*! MASKX - PWM_X Masks
37421  *  0b0000..PWM_X output normal.
37422  *  0b0001..PWM_X output masked.
37423  */
37424 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
37425 
37426 #define PWM_MASK_MASKB_MASK                      (0xF0U)
37427 #define PWM_MASK_MASKB_SHIFT                     (4U)
37428 /*! MASKB - PWM_B Masks
37429  *  0b0000..PWM_B output normal.
37430  *  0b0001..PWM_B output masked.
37431  */
37432 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
37433 
37434 #define PWM_MASK_MASKA_MASK                      (0xF00U)
37435 #define PWM_MASK_MASKA_SHIFT                     (8U)
37436 /*! MASKA - PWM_A Masks
37437  *  0b0000..PWM_A output normal.
37438  *  0b0001..PWM_A output masked.
37439  */
37440 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
37441 /*! @} */
37442 
37443 /*! @name SWCOUT - Software Controlled Output Register */
37444 /*! @{ */
37445 
37446 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
37447 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
37448 /*! SM0OUT45 - Submodule 0 Software Controlled Output 45
37449  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
37450  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
37451  */
37452 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
37453 
37454 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
37455 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
37456 /*! SM0OUT23 - Submodule 0 Software Controlled Output 23
37457  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
37458  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
37459  */
37460 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
37461 
37462 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
37463 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
37464 /*! SM1OUT45 - Submodule 1 Software Controlled Output 45
37465  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
37466  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
37467  */
37468 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
37469 
37470 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
37471 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
37472 /*! SM1OUT23 - Submodule 1 Software Controlled Output 23
37473  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
37474  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
37475  */
37476 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
37477 
37478 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
37479 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
37480 /*! SM2OUT45 - Submodule 2 Software Controlled Output 45
37481  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
37482  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
37483  */
37484 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
37485 
37486 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
37487 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
37488 /*! SM2OUT23 - Submodule 2 Software Controlled Output 23
37489  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
37490  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
37491  */
37492 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
37493 
37494 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
37495 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
37496 /*! SM3OUT45 - Submodule 3 Software Controlled Output 45
37497  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
37498  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
37499  */
37500 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
37501 
37502 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
37503 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
37504 /*! SM3OUT23 - Submodule 3 Software Controlled Output 23
37505  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
37506  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
37507  */
37508 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
37509 /*! @} */
37510 
37511 /*! @name DTSRCSEL - PWM Source Select Register */
37512 /*! @{ */
37513 
37514 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
37515 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
37516 /*! SM0SEL45 - Submodule 0 PWM45 Control Select
37517  *  0b00..Generated SM0PWM45 signal is used by the deadtime logic.
37518  *  0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
37519  *  0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
37520  *  0b11..PWM0_EXTB signal is used by the deadtime logic.
37521  */
37522 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
37523 
37524 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
37525 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
37526 /*! SM0SEL23 - Submodule 0 PWM23 Control Select
37527  *  0b00..Generated SM0PWM23 signal is used by the deadtime logic.
37528  *  0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
37529  *  0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
37530  *  0b11..PWM0_EXTA signal is used by the deadtime logic.
37531  */
37532 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
37533 
37534 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
37535 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
37536 /*! SM1SEL45 - Submodule 1 PWM45 Control Select
37537  *  0b00..Generated SM1PWM45 signal is used by the deadtime logic.
37538  *  0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
37539  *  0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
37540  *  0b11..PWM1_EXTB signal is used by the deadtime logic.
37541  */
37542 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
37543 
37544 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
37545 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
37546 /*! SM1SEL23 - Submodule 1 PWM23 Control Select
37547  *  0b00..Generated SM1PWM23 signal is used by the deadtime logic.
37548  *  0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
37549  *  0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
37550  *  0b11..PWM1_EXTA signal is used by the deadtime logic.
37551  */
37552 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
37553 
37554 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
37555 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
37556 /*! SM2SEL45 - Submodule 2 PWM45 Control Select
37557  *  0b00..Generated SM2PWM45 signal is used by the deadtime logic.
37558  *  0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
37559  *  0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
37560  *  0b11..PWM2_EXTB signal is used by the deadtime logic.
37561  */
37562 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
37563 
37564 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
37565 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
37566 /*! SM2SEL23 - Submodule 2 PWM23 Control Select
37567  *  0b00..Generated SM2PWM23 signal is used by the deadtime logic.
37568  *  0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
37569  *  0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
37570  *  0b11..PWM2_EXTA signal is used by the deadtime logic.
37571  */
37572 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
37573 
37574 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
37575 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
37576 /*! SM3SEL45 - Submodule 3 PWM45 Control Select
37577  *  0b00..Generated SM3PWM45 signal is used by the deadtime logic.
37578  *  0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
37579  *  0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
37580  *  0b11..PWM3_EXTB signal is used by the deadtime logic.
37581  */
37582 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
37583 
37584 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
37585 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
37586 /*! SM3SEL23 - Submodule 3 PWM23 Control Select
37587  *  0b00..Generated SM3PWM23 signal is used by the deadtime logic.
37588  *  0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
37589  *  0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
37590  *  0b11..PWM3_EXTA signal is used by the deadtime logic.
37591  */
37592 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
37593 /*! @} */
37594 
37595 /*! @name MCTRL - Master Control Register */
37596 /*! @{ */
37597 
37598 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
37599 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
37600 /*! LDOK - Load Okay
37601  *  0b0000..Do not load new values.
37602  *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
37603  */
37604 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
37605 
37606 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
37607 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
37608 /*! CLDOK - Clear Load Okay
37609  */
37610 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
37611 
37612 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
37613 #define PWM_MCTRL_RUN_SHIFT                      (8U)
37614 /*! RUN - Run
37615  *  0b0000..PWM generator is disabled in the corresponding submodule.
37616  *  0b0001..PWM generator is enabled in the corresponding submodule.
37617  */
37618 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
37619 
37620 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
37621 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
37622 /*! IPOL - Current Polarity
37623  *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
37624  *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
37625  */
37626 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
37627 /*! @} */
37628 
37629 /*! @name MCTRL2 - Master Control 2 Register */
37630 /*! @{ */
37631 
37632 #define PWM_MCTRL2_MONPLL_MASK                   (0x3U)
37633 #define PWM_MCTRL2_MONPLL_SHIFT                  (0U)
37634 /*! MONPLL - Monitor PLL State
37635  *  0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
37636  *  0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
37637  *  0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
37638  *        will be controlled by software. These bits are write protected until the next reset.
37639  *  0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
37640  *        encounters problems. These bits are write protected until the next reset.
37641  */
37642 #define PWM_MCTRL2_MONPLL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
37643 /*! @} */
37644 
37645 /*! @name FCTRL - Fault Control Register */
37646 /*! @{ */
37647 
37648 #define PWM_FCTRL_FIE_MASK                       (0xFU)
37649 #define PWM_FCTRL_FIE_SHIFT                      (0U)
37650 /*! FIE - Fault Interrupt Enables
37651  *  0b0000..FAULTx CPU interrupt requests disabled.
37652  *  0b0001..FAULTx CPU interrupt requests enabled.
37653  */
37654 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
37655 
37656 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
37657 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
37658 /*! FSAFE - Fault Safety Mode
37659  *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
37660  *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
37661  *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is setm then the fault condition cannot be
37662  *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
37663  *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
37664  *          DISMAPn).
37665  *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
37666  *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
37667  *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
37668  */
37669 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
37670 
37671 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
37672 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
37673 /*! FAUTO - Automatic Fault Clearing
37674  *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
37675  *          at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If
37676  *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by
37677  *          FCTRL[FSAFE].
37678  *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
37679  *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
37680  *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
37681  *          cannot be cleared.
37682  */
37683 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
37684 
37685 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
37686 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
37687 /*! FLVL - Fault Level
37688  *  0b0000..A logic 0 on the fault input indicates a fault condition.
37689  *  0b0001..A logic 1 on the fault input indicates a fault condition.
37690  */
37691 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
37692 /*! @} */
37693 
37694 /*! @name FSTS - Fault Status Register */
37695 /*! @{ */
37696 
37697 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
37698 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
37699 /*! FFLAG - Fault Flags
37700  *  0b0000..No fault on the FAULTx pin.
37701  *  0b0001..Fault on the FAULTx pin.
37702  */
37703 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
37704 
37705 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
37706 #define PWM_FSTS_FFULL_SHIFT                     (4U)
37707 /*! FFULL - Full Cycle
37708  *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
37709  *  0b0001..PWM outputs are re-enabled at the start of a full cycle
37710  */
37711 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
37712 
37713 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
37714 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
37715 /*! FFPIN - Filtered Fault Pins
37716  */
37717 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
37718 
37719 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
37720 #define PWM_FSTS_FHALF_SHIFT                     (12U)
37721 /*! FHALF - Half Cycle Fault Recovery
37722  *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
37723  *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
37724  */
37725 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
37726 /*! @} */
37727 
37728 /*! @name FFILT - Fault Filter Register */
37729 /*! @{ */
37730 
37731 #define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
37732 #define PWM_FFILT_FILT_PER_SHIFT                 (0U)
37733 /*! FILT_PER - Fault Filter Period
37734  */
37735 #define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
37736 
37737 #define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
37738 #define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
37739 /*! FILT_CNT - Fault Filter Count
37740  */
37741 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
37742 
37743 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
37744 #define PWM_FFILT_GSTR_SHIFT                     (15U)
37745 /*! GSTR - Fault Glitch Stretch Enable
37746  *  0b0..Fault input glitch stretching is disabled.
37747  *  0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
37748  */
37749 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
37750 /*! @} */
37751 
37752 /*! @name FTST - Fault Test Register */
37753 /*! @{ */
37754 
37755 #define PWM_FTST_FTEST_MASK                      (0x1U)
37756 #define PWM_FTST_FTEST_SHIFT                     (0U)
37757 /*! FTEST - Fault Test
37758  *  0b0..No fault
37759  *  0b1..Cause a simulated fault
37760  */
37761 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
37762 /*! @} */
37763 
37764 /*! @name FCTRL2 - Fault Control 2 Register */
37765 /*! @{ */
37766 
37767 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
37768 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
37769 /*! NOCOMB - No Combinational Path From Fault Input To PWM Output
37770  *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
37771  *          with the filtered and latched fault signals to disable the PWM outputs.
37772  *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
37773  *          and latched fault signals are used to disable the PWM outputs.
37774  */
37775 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
37776 /*! @} */
37777 
37778 
37779 /*!
37780  * @}
37781  */ /* end of group PWM_Register_Masks */
37782 
37783 
37784 /* PWM - Peripheral instance base addresses */
37785 /** Peripheral PWM1 base address */
37786 #define PWM1_BASE                                (0x403DC000u)
37787 /** Peripheral PWM1 base pointer */
37788 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
37789 /** Peripheral PWM2 base address */
37790 #define PWM2_BASE                                (0x403E0000u)
37791 /** Peripheral PWM2 base pointer */
37792 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
37793 /** Peripheral PWM3 base address */
37794 #define PWM3_BASE                                (0x403E4000u)
37795 /** Peripheral PWM3 base pointer */
37796 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
37797 /** Peripheral PWM4 base address */
37798 #define PWM4_BASE                                (0x403E8000u)
37799 /** Peripheral PWM4 base pointer */
37800 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
37801 /** Array initializer of PWM peripheral base addresses */
37802 #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
37803 /** Array initializer of PWM peripheral base pointers */
37804 #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
37805 /** Interrupt vectors for the PWM peripheral type */
37806 #define PWM_CMP_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
37807 #define PWM_RELOAD_IRQS                          { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
37808 #define PWM_CAPTURE_IRQS                         { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
37809 #define PWM_FAULT_IRQS                           { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
37810 #define PWM_RELOAD_ERROR_IRQS                    { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
37811 
37812 /*!
37813  * @}
37814  */ /* end of group PWM_Peripheral_Access_Layer */
37815 
37816 
37817 /* ----------------------------------------------------------------------------
37818    -- PXP Peripheral Access Layer
37819    ---------------------------------------------------------------------------- */
37820 
37821 /*!
37822  * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
37823  * @{
37824  */
37825 
37826 /** PXP - Register Layout Typedef */
37827 typedef struct {
37828   __IO uint32_t CTRL;                              /**< Control Register 0, offset: 0x0 */
37829   __IO uint32_t CTRL_SET;                          /**< Control Register 0, offset: 0x4 */
37830   __IO uint32_t CTRL_CLR;                          /**< Control Register 0, offset: 0x8 */
37831   __IO uint32_t CTRL_TOG;                          /**< Control Register 0, offset: 0xC */
37832   __IO uint32_t STAT;                              /**< Status Register, offset: 0x10 */
37833   __IO uint32_t STAT_SET;                          /**< Status Register, offset: 0x14 */
37834   __IO uint32_t STAT_CLR;                          /**< Status Register, offset: 0x18 */
37835   __IO uint32_t STAT_TOG;                          /**< Status Register, offset: 0x1C */
37836   __IO uint32_t OUT_CTRL;                          /**< Output Buffer Control Register, offset: 0x20 */
37837   __IO uint32_t OUT_CTRL_SET;                      /**< Output Buffer Control Register, offset: 0x24 */
37838   __IO uint32_t OUT_CTRL_CLR;                      /**< Output Buffer Control Register, offset: 0x28 */
37839   __IO uint32_t OUT_CTRL_TOG;                      /**< Output Buffer Control Register, offset: 0x2C */
37840   __IO uint32_t OUT_BUF;                           /**< Output Frame Buffer Pointer, offset: 0x30 */
37841        uint8_t RESERVED_0[12];
37842   __IO uint32_t OUT_BUF2;                          /**< Output Frame Buffer Pointer #2, offset: 0x40 */
37843        uint8_t RESERVED_1[12];
37844   __IO uint32_t OUT_PITCH;                         /**< Output Buffer Pitch, offset: 0x50 */
37845        uint8_t RESERVED_2[12];
37846   __IO uint32_t OUT_LRC;                           /**< Output Surface Lower Right Coordinate, offset: 0x60 */
37847        uint8_t RESERVED_3[12];
37848   __IO uint32_t OUT_PS_ULC;                        /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
37849        uint8_t RESERVED_4[12];
37850   __IO uint32_t OUT_PS_LRC;                        /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
37851        uint8_t RESERVED_5[12];
37852   __IO uint32_t OUT_AS_ULC;                        /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
37853        uint8_t RESERVED_6[12];
37854   __IO uint32_t OUT_AS_LRC;                        /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
37855        uint8_t RESERVED_7[12];
37856   __IO uint32_t PS_CTRL;                           /**< Processed Surface (PS) Control Register, offset: 0xB0 */
37857   __IO uint32_t PS_CTRL_SET;                       /**< Processed Surface (PS) Control Register, offset: 0xB4 */
37858   __IO uint32_t PS_CTRL_CLR;                       /**< Processed Surface (PS) Control Register, offset: 0xB8 */
37859   __IO uint32_t PS_CTRL_TOG;                       /**< Processed Surface (PS) Control Register, offset: 0xBC */
37860   __IO uint32_t PS_BUF;                            /**< PS Input Buffer Address, offset: 0xC0 */
37861        uint8_t RESERVED_8[12];
37862   __IO uint32_t PS_UBUF;                           /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
37863        uint8_t RESERVED_9[12];
37864   __IO uint32_t PS_VBUF;                           /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
37865        uint8_t RESERVED_10[12];
37866   __IO uint32_t PS_PITCH;                          /**< Processed Surface Pitch, offset: 0xF0 */
37867        uint8_t RESERVED_11[12];
37868   __IO uint32_t PS_BACKGROUND;                     /**< PS Background Color, offset: 0x100 */
37869        uint8_t RESERVED_12[12];
37870   __IO uint32_t PS_SCALE;                          /**< PS Scale Factor Register, offset: 0x110 */
37871        uint8_t RESERVED_13[12];
37872   __IO uint32_t PS_OFFSET;                         /**< PS Scale Offset Register, offset: 0x120 */
37873        uint8_t RESERVED_14[12];
37874   __IO uint32_t PS_CLRKEYLOW;                      /**< PS Color Key Low, offset: 0x130 */
37875        uint8_t RESERVED_15[12];
37876   __IO uint32_t PS_CLRKEYHIGH;                     /**< PS Color Key High, offset: 0x140 */
37877        uint8_t RESERVED_16[12];
37878   __IO uint32_t AS_CTRL;                           /**< Alpha Surface Control, offset: 0x150 */
37879        uint8_t RESERVED_17[12];
37880   __IO uint32_t AS_BUF;                            /**< Alpha Surface Buffer Pointer, offset: 0x160 */
37881        uint8_t RESERVED_18[12];
37882   __IO uint32_t AS_PITCH;                          /**< Alpha Surface Pitch, offset: 0x170 */
37883        uint8_t RESERVED_19[12];
37884   __IO uint32_t AS_CLRKEYLOW;                      /**< Overlay Color Key Low, offset: 0x180 */
37885        uint8_t RESERVED_20[12];
37886   __IO uint32_t AS_CLRKEYHIGH;                     /**< Overlay Color Key High, offset: 0x190 */
37887        uint8_t RESERVED_21[12];
37888   __IO uint32_t CSC1_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
37889        uint8_t RESERVED_22[12];
37890   __IO uint32_t CSC1_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
37891        uint8_t RESERVED_23[12];
37892   __IO uint32_t CSC1_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
37893        uint8_t RESERVED_24[348];
37894   __IO uint32_t POWER;                             /**< PXP Power Control Register, offset: 0x320 */
37895        uint8_t RESERVED_25[220];
37896   __IO uint32_t NEXT;                              /**< Next Frame Pointer, offset: 0x400 */
37897        uint8_t RESERVED_26[60];
37898   __IO uint32_t PORTER_DUFF_CTRL;                  /**< PXP Alpha Engine A Control Register., offset: 0x440 */
37899 } PXP_Type;
37900 
37901 /* ----------------------------------------------------------------------------
37902    -- PXP Register Masks
37903    ---------------------------------------------------------------------------- */
37904 
37905 /*!
37906  * @addtogroup PXP_Register_Masks PXP Register Masks
37907  * @{
37908  */
37909 
37910 /*! @name CTRL - Control Register 0 */
37911 /*! @{ */
37912 
37913 #define PXP_CTRL_ENABLE_MASK                     (0x1U)
37914 #define PXP_CTRL_ENABLE_SHIFT                    (0U)
37915 /*! ENABLE
37916  *  0b1..PXP is enabled
37917  *  0b0..PXP is disabled
37918  */
37919 #define PXP_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
37920 
37921 #define PXP_CTRL_IRQ_ENABLE_MASK                 (0x2U)
37922 #define PXP_CTRL_IRQ_ENABLE_SHIFT                (1U)
37923 /*! IRQ_ENABLE
37924  *  0b1..PXP interrupt is enabled
37925  *  0b0..PXP interrupt is disabled
37926  */
37927 #define PXP_CTRL_IRQ_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
37928 
37929 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK            (0x4U)
37930 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT           (2U)
37931 /*! NEXT_IRQ_ENABLE
37932  *  0b0..Disabled
37933  *  0b1..Enabled
37934  */
37935 #define PXP_CTRL_NEXT_IRQ_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
37936 
37937 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK       (0x10U)
37938 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT      (4U)
37939 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
37940 
37941 #define PXP_CTRL_ROTATE_MASK                     (0x300U)
37942 #define PXP_CTRL_ROTATE_SHIFT                    (8U)
37943 /*! ROTATE
37944  *  0b00..ROT_0
37945  *  0b01..ROT_90
37946  *  0b10..ROT_180
37947  *  0b11..ROT_270
37948  */
37949 #define PXP_CTRL_ROTATE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
37950 
37951 #define PXP_CTRL_HFLIP_MASK                      (0x400U)
37952 #define PXP_CTRL_HFLIP_SHIFT                     (10U)
37953 /*! HFLIP
37954  *  0b0..Horizontal Flip is disabled
37955  *  0b1..Horizontal Flip is enabled
37956  */
37957 #define PXP_CTRL_HFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
37958 
37959 #define PXP_CTRL_VFLIP_MASK                      (0x800U)
37960 #define PXP_CTRL_VFLIP_SHIFT                     (11U)
37961 /*! VFLIP
37962  *  0b0..Vertical Flip is disabled
37963  *  0b1..Vertical Flip is enabled
37964  */
37965 #define PXP_CTRL_VFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
37966 
37967 #define PXP_CTRL_ROT_POS_MASK                    (0x400000U)
37968 #define PXP_CTRL_ROT_POS_SHIFT                   (22U)
37969 #define PXP_CTRL_ROT_POS(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
37970 
37971 #define PXP_CTRL_BLOCK_SIZE_MASK                 (0x800000U)
37972 #define PXP_CTRL_BLOCK_SIZE_SHIFT                (23U)
37973 /*! BLOCK_SIZE
37974  *  0b0..Process 8x8 pixel blocks.
37975  *  0b1..Process 16x16 pixel blocks.
37976  */
37977 #define PXP_CTRL_BLOCK_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
37978 
37979 #define PXP_CTRL_EN_REPEAT_MASK                  (0x10000000U)
37980 #define PXP_CTRL_EN_REPEAT_SHIFT                 (28U)
37981 /*! EN_REPEAT
37982  *  0b1..PXP will repeat based on the current configuration register settings
37983  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
37984  */
37985 #define PXP_CTRL_EN_REPEAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
37986 
37987 #define PXP_CTRL_CLKGATE_MASK                    (0x40000000U)
37988 #define PXP_CTRL_CLKGATE_SHIFT                   (30U)
37989 /*! CLKGATE
37990  *  0b0..Normal operation
37991  *  0b1..All clocks to PXP is gated-off
37992  */
37993 #define PXP_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
37994 
37995 #define PXP_CTRL_SFTRST_MASK                     (0x80000000U)
37996 #define PXP_CTRL_SFTRST_SHIFT                    (31U)
37997 /*! SFTRST
37998  *  0b0..Normal PXP operation is enabled
37999  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
38000  */
38001 #define PXP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
38002 /*! @} */
38003 
38004 /*! @name CTRL_SET - Control Register 0 */
38005 /*! @{ */
38006 
38007 #define PXP_CTRL_SET_ENABLE_MASK                 (0x1U)
38008 #define PXP_CTRL_SET_ENABLE_SHIFT                (0U)
38009 /*! ENABLE
38010  *  0b1..PXP is enabled
38011  *  0b0..PXP is disabled
38012  */
38013 #define PXP_CTRL_SET_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
38014 
38015 #define PXP_CTRL_SET_IRQ_ENABLE_MASK             (0x2U)
38016 #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT            (1U)
38017 /*! IRQ_ENABLE
38018  *  0b1..PXP interrupt is enabled
38019  *  0b0..PXP interrupt is disabled
38020  */
38021 #define PXP_CTRL_SET_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
38022 
38023 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK        (0x4U)
38024 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT       (2U)
38025 /*! NEXT_IRQ_ENABLE
38026  *  0b0..Disabled
38027  *  0b1..Enabled
38028  */
38029 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
38030 
38031 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
38032 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
38033 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
38034 
38035 #define PXP_CTRL_SET_ROTATE_MASK                 (0x300U)
38036 #define PXP_CTRL_SET_ROTATE_SHIFT                (8U)
38037 /*! ROTATE
38038  *  0b00..ROT_0
38039  *  0b01..ROT_90
38040  *  0b10..ROT_180
38041  *  0b11..ROT_270
38042  */
38043 #define PXP_CTRL_SET_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
38044 
38045 #define PXP_CTRL_SET_HFLIP_MASK                  (0x400U)
38046 #define PXP_CTRL_SET_HFLIP_SHIFT                 (10U)
38047 /*! HFLIP
38048  *  0b0..Horizontal Flip is disabled
38049  *  0b1..Horizontal Flip is enabled
38050  */
38051 #define PXP_CTRL_SET_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
38052 
38053 #define PXP_CTRL_SET_VFLIP_MASK                  (0x800U)
38054 #define PXP_CTRL_SET_VFLIP_SHIFT                 (11U)
38055 /*! VFLIP
38056  *  0b0..Vertical Flip is disabled
38057  *  0b1..Vertical Flip is enabled
38058  */
38059 #define PXP_CTRL_SET_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
38060 
38061 #define PXP_CTRL_SET_ROT_POS_MASK                (0x400000U)
38062 #define PXP_CTRL_SET_ROT_POS_SHIFT               (22U)
38063 #define PXP_CTRL_SET_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
38064 
38065 #define PXP_CTRL_SET_BLOCK_SIZE_MASK             (0x800000U)
38066 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT            (23U)
38067 /*! BLOCK_SIZE
38068  *  0b0..Process 8x8 pixel blocks.
38069  *  0b1..Process 16x16 pixel blocks.
38070  */
38071 #define PXP_CTRL_SET_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
38072 
38073 #define PXP_CTRL_SET_EN_REPEAT_MASK              (0x10000000U)
38074 #define PXP_CTRL_SET_EN_REPEAT_SHIFT             (28U)
38075 /*! EN_REPEAT
38076  *  0b1..PXP will repeat based on the current configuration register settings
38077  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
38078  */
38079 #define PXP_CTRL_SET_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
38080 
38081 #define PXP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
38082 #define PXP_CTRL_SET_CLKGATE_SHIFT               (30U)
38083 /*! CLKGATE
38084  *  0b0..Normal operation
38085  *  0b1..All clocks to PXP is gated-off
38086  */
38087 #define PXP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
38088 
38089 #define PXP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
38090 #define PXP_CTRL_SET_SFTRST_SHIFT                (31U)
38091 /*! SFTRST
38092  *  0b0..Normal PXP operation is enabled
38093  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
38094  */
38095 #define PXP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
38096 /*! @} */
38097 
38098 /*! @name CTRL_CLR - Control Register 0 */
38099 /*! @{ */
38100 
38101 #define PXP_CTRL_CLR_ENABLE_MASK                 (0x1U)
38102 #define PXP_CTRL_CLR_ENABLE_SHIFT                (0U)
38103 /*! ENABLE
38104  *  0b1..PXP is enabled
38105  *  0b0..PXP is disabled
38106  */
38107 #define PXP_CTRL_CLR_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
38108 
38109 #define PXP_CTRL_CLR_IRQ_ENABLE_MASK             (0x2U)
38110 #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT            (1U)
38111 /*! IRQ_ENABLE
38112  *  0b1..PXP interrupt is enabled
38113  *  0b0..PXP interrupt is disabled
38114  */
38115 #define PXP_CTRL_CLR_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
38116 
38117 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK        (0x4U)
38118 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT       (2U)
38119 /*! NEXT_IRQ_ENABLE
38120  *  0b0..Disabled
38121  *  0b1..Enabled
38122  */
38123 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
38124 
38125 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
38126 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
38127 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
38128 
38129 #define PXP_CTRL_CLR_ROTATE_MASK                 (0x300U)
38130 #define PXP_CTRL_CLR_ROTATE_SHIFT                (8U)
38131 /*! ROTATE
38132  *  0b00..ROT_0
38133  *  0b01..ROT_90
38134  *  0b10..ROT_180
38135  *  0b11..ROT_270
38136  */
38137 #define PXP_CTRL_CLR_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
38138 
38139 #define PXP_CTRL_CLR_HFLIP_MASK                  (0x400U)
38140 #define PXP_CTRL_CLR_HFLIP_SHIFT                 (10U)
38141 /*! HFLIP
38142  *  0b0..Horizontal Flip is disabled
38143  *  0b1..Horizontal Flip is enabled
38144  */
38145 #define PXP_CTRL_CLR_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
38146 
38147 #define PXP_CTRL_CLR_VFLIP_MASK                  (0x800U)
38148 #define PXP_CTRL_CLR_VFLIP_SHIFT                 (11U)
38149 /*! VFLIP
38150  *  0b0..Vertical Flip is disabled
38151  *  0b1..Vertical Flip is enabled
38152  */
38153 #define PXP_CTRL_CLR_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
38154 
38155 #define PXP_CTRL_CLR_ROT_POS_MASK                (0x400000U)
38156 #define PXP_CTRL_CLR_ROT_POS_SHIFT               (22U)
38157 #define PXP_CTRL_CLR_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
38158 
38159 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK             (0x800000U)
38160 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT            (23U)
38161 /*! BLOCK_SIZE
38162  *  0b0..Process 8x8 pixel blocks.
38163  *  0b1..Process 16x16 pixel blocks.
38164  */
38165 #define PXP_CTRL_CLR_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
38166 
38167 #define PXP_CTRL_CLR_EN_REPEAT_MASK              (0x10000000U)
38168 #define PXP_CTRL_CLR_EN_REPEAT_SHIFT             (28U)
38169 /*! EN_REPEAT
38170  *  0b1..PXP will repeat based on the current configuration register settings
38171  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
38172  */
38173 #define PXP_CTRL_CLR_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
38174 
38175 #define PXP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
38176 #define PXP_CTRL_CLR_CLKGATE_SHIFT               (30U)
38177 /*! CLKGATE
38178  *  0b0..Normal operation
38179  *  0b1..All clocks to PXP is gated-off
38180  */
38181 #define PXP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
38182 
38183 #define PXP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
38184 #define PXP_CTRL_CLR_SFTRST_SHIFT                (31U)
38185 /*! SFTRST
38186  *  0b0..Normal PXP operation is enabled
38187  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
38188  */
38189 #define PXP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
38190 /*! @} */
38191 
38192 /*! @name CTRL_TOG - Control Register 0 */
38193 /*! @{ */
38194 
38195 #define PXP_CTRL_TOG_ENABLE_MASK                 (0x1U)
38196 #define PXP_CTRL_TOG_ENABLE_SHIFT                (0U)
38197 /*! ENABLE
38198  *  0b1..PXP is enabled
38199  *  0b0..PXP is disabled
38200  */
38201 #define PXP_CTRL_TOG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
38202 
38203 #define PXP_CTRL_TOG_IRQ_ENABLE_MASK             (0x2U)
38204 #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT            (1U)
38205 /*! IRQ_ENABLE
38206  *  0b1..PXP interrupt is enabled
38207  *  0b0..PXP interrupt is disabled
38208  */
38209 #define PXP_CTRL_TOG_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
38210 
38211 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK        (0x4U)
38212 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT       (2U)
38213 /*! NEXT_IRQ_ENABLE
38214  *  0b0..Disabled
38215  *  0b1..Enabled
38216  */
38217 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
38218 
38219 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
38220 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
38221 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
38222 
38223 #define PXP_CTRL_TOG_ROTATE_MASK                 (0x300U)
38224 #define PXP_CTRL_TOG_ROTATE_SHIFT                (8U)
38225 /*! ROTATE
38226  *  0b00..ROT_0
38227  *  0b01..ROT_90
38228  *  0b10..ROT_180
38229  *  0b11..ROT_270
38230  */
38231 #define PXP_CTRL_TOG_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
38232 
38233 #define PXP_CTRL_TOG_HFLIP_MASK                  (0x400U)
38234 #define PXP_CTRL_TOG_HFLIP_SHIFT                 (10U)
38235 /*! HFLIP
38236  *  0b0..Horizontal Flip is disabled
38237  *  0b1..Horizontal Flip is enabled
38238  */
38239 #define PXP_CTRL_TOG_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
38240 
38241 #define PXP_CTRL_TOG_VFLIP_MASK                  (0x800U)
38242 #define PXP_CTRL_TOG_VFLIP_SHIFT                 (11U)
38243 /*! VFLIP
38244  *  0b0..Vertical Flip is disabled
38245  *  0b1..Vertical Flip is enabled
38246  */
38247 #define PXP_CTRL_TOG_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
38248 
38249 #define PXP_CTRL_TOG_ROT_POS_MASK                (0x400000U)
38250 #define PXP_CTRL_TOG_ROT_POS_SHIFT               (22U)
38251 #define PXP_CTRL_TOG_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
38252 
38253 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK             (0x800000U)
38254 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT            (23U)
38255 /*! BLOCK_SIZE
38256  *  0b0..Process 8x8 pixel blocks.
38257  *  0b1..Process 16x16 pixel blocks.
38258  */
38259 #define PXP_CTRL_TOG_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
38260 
38261 #define PXP_CTRL_TOG_EN_REPEAT_MASK              (0x10000000U)
38262 #define PXP_CTRL_TOG_EN_REPEAT_SHIFT             (28U)
38263 /*! EN_REPEAT
38264  *  0b1..PXP will repeat based on the current configuration register settings
38265  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
38266  */
38267 #define PXP_CTRL_TOG_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
38268 
38269 #define PXP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
38270 #define PXP_CTRL_TOG_CLKGATE_SHIFT               (30U)
38271 /*! CLKGATE
38272  *  0b0..Normal operation
38273  *  0b1..All clocks to PXP is gated-off
38274  */
38275 #define PXP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
38276 
38277 #define PXP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
38278 #define PXP_CTRL_TOG_SFTRST_SHIFT                (31U)
38279 /*! SFTRST
38280  *  0b0..Normal PXP operation is enabled
38281  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
38282  */
38283 #define PXP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
38284 /*! @} */
38285 
38286 /*! @name STAT - Status Register */
38287 /*! @{ */
38288 
38289 #define PXP_STAT_IRQ_MASK                        (0x1U)
38290 #define PXP_STAT_IRQ_SHIFT                       (0U)
38291 /*! IRQ
38292  *  0b0..No interrupt
38293  *  0b1..Interrupt generated
38294  */
38295 #define PXP_STAT_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
38296 
38297 #define PXP_STAT_AXI_WRITE_ERROR_MASK            (0x2U)
38298 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT           (1U)
38299 /*! AXI_WRITE_ERROR
38300  *  0b0..AXI write is normal
38301  *  0b1..AXI write error has occurred
38302  */
38303 #define PXP_STAT_AXI_WRITE_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
38304 
38305 #define PXP_STAT_AXI_READ_ERROR_MASK             (0x4U)
38306 #define PXP_STAT_AXI_READ_ERROR_SHIFT            (2U)
38307 /*! AXI_READ_ERROR
38308  *  0b0..AXI read is normal
38309  *  0b1..AXI read error has occurred
38310  */
38311 #define PXP_STAT_AXI_READ_ERROR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
38312 
38313 #define PXP_STAT_NEXT_IRQ_MASK                   (0x8U)
38314 #define PXP_STAT_NEXT_IRQ_SHIFT                  (3U)
38315 #define PXP_STAT_NEXT_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
38316 
38317 #define PXP_STAT_AXI_ERROR_ID_MASK               (0xF0U)
38318 #define PXP_STAT_AXI_ERROR_ID_SHIFT              (4U)
38319 #define PXP_STAT_AXI_ERROR_ID(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
38320 
38321 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK      (0x100U)
38322 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT     (8U)
38323 /*! LUT_DMA_LOAD_DONE_IRQ
38324  *  0b0..LUT DMA LOAD transfer is active
38325  *  0b1..LUT DMA LOAD transfer is complete
38326  */
38327 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
38328 
38329 #define PXP_STAT_BLOCKY_MASK                     (0xFF0000U)
38330 #define PXP_STAT_BLOCKY_SHIFT                    (16U)
38331 #define PXP_STAT_BLOCKY(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
38332 
38333 #define PXP_STAT_BLOCKX_MASK                     (0xFF000000U)
38334 #define PXP_STAT_BLOCKX_SHIFT                    (24U)
38335 #define PXP_STAT_BLOCKX(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
38336 /*! @} */
38337 
38338 /*! @name STAT_SET - Status Register */
38339 /*! @{ */
38340 
38341 #define PXP_STAT_SET_IRQ_MASK                    (0x1U)
38342 #define PXP_STAT_SET_IRQ_SHIFT                   (0U)
38343 /*! IRQ
38344  *  0b0..No interrupt
38345  *  0b1..Interrupt generated
38346  */
38347 #define PXP_STAT_SET_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
38348 
38349 #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK        (0x2U)
38350 #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT       (1U)
38351 /*! AXI_WRITE_ERROR
38352  *  0b0..AXI write is normal
38353  *  0b1..AXI write error has occurred
38354  */
38355 #define PXP_STAT_SET_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
38356 
38357 #define PXP_STAT_SET_AXI_READ_ERROR_MASK         (0x4U)
38358 #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT        (2U)
38359 /*! AXI_READ_ERROR
38360  *  0b0..AXI read is normal
38361  *  0b1..AXI read error has occurred
38362  */
38363 #define PXP_STAT_SET_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
38364 
38365 #define PXP_STAT_SET_NEXT_IRQ_MASK               (0x8U)
38366 #define PXP_STAT_SET_NEXT_IRQ_SHIFT              (3U)
38367 #define PXP_STAT_SET_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
38368 
38369 #define PXP_STAT_SET_AXI_ERROR_ID_MASK           (0xF0U)
38370 #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT          (4U)
38371 #define PXP_STAT_SET_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
38372 
38373 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
38374 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38375 /*! LUT_DMA_LOAD_DONE_IRQ
38376  *  0b0..LUT DMA LOAD transfer is active
38377  *  0b1..LUT DMA LOAD transfer is complete
38378  */
38379 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
38380 
38381 #define PXP_STAT_SET_BLOCKY_MASK                 (0xFF0000U)
38382 #define PXP_STAT_SET_BLOCKY_SHIFT                (16U)
38383 #define PXP_STAT_SET_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
38384 
38385 #define PXP_STAT_SET_BLOCKX_MASK                 (0xFF000000U)
38386 #define PXP_STAT_SET_BLOCKX_SHIFT                (24U)
38387 #define PXP_STAT_SET_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
38388 /*! @} */
38389 
38390 /*! @name STAT_CLR - Status Register */
38391 /*! @{ */
38392 
38393 #define PXP_STAT_CLR_IRQ_MASK                    (0x1U)
38394 #define PXP_STAT_CLR_IRQ_SHIFT                   (0U)
38395 /*! IRQ
38396  *  0b0..No interrupt
38397  *  0b1..Interrupt generated
38398  */
38399 #define PXP_STAT_CLR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
38400 
38401 #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK        (0x2U)
38402 #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT       (1U)
38403 /*! AXI_WRITE_ERROR
38404  *  0b0..AXI write is normal
38405  *  0b1..AXI write error has occurred
38406  */
38407 #define PXP_STAT_CLR_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
38408 
38409 #define PXP_STAT_CLR_AXI_READ_ERROR_MASK         (0x4U)
38410 #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT        (2U)
38411 /*! AXI_READ_ERROR
38412  *  0b0..AXI read is normal
38413  *  0b1..AXI read error has occurred
38414  */
38415 #define PXP_STAT_CLR_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
38416 
38417 #define PXP_STAT_CLR_NEXT_IRQ_MASK               (0x8U)
38418 #define PXP_STAT_CLR_NEXT_IRQ_SHIFT              (3U)
38419 #define PXP_STAT_CLR_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
38420 
38421 #define PXP_STAT_CLR_AXI_ERROR_ID_MASK           (0xF0U)
38422 #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT          (4U)
38423 #define PXP_STAT_CLR_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
38424 
38425 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
38426 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38427 /*! LUT_DMA_LOAD_DONE_IRQ
38428  *  0b0..LUT DMA LOAD transfer is active
38429  *  0b1..LUT DMA LOAD transfer is complete
38430  */
38431 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
38432 
38433 #define PXP_STAT_CLR_BLOCKY_MASK                 (0xFF0000U)
38434 #define PXP_STAT_CLR_BLOCKY_SHIFT                (16U)
38435 #define PXP_STAT_CLR_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
38436 
38437 #define PXP_STAT_CLR_BLOCKX_MASK                 (0xFF000000U)
38438 #define PXP_STAT_CLR_BLOCKX_SHIFT                (24U)
38439 #define PXP_STAT_CLR_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
38440 /*! @} */
38441 
38442 /*! @name STAT_TOG - Status Register */
38443 /*! @{ */
38444 
38445 #define PXP_STAT_TOG_IRQ_MASK                    (0x1U)
38446 #define PXP_STAT_TOG_IRQ_SHIFT                   (0U)
38447 /*! IRQ
38448  *  0b0..No interrupt
38449  *  0b1..Interrupt generated
38450  */
38451 #define PXP_STAT_TOG_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
38452 
38453 #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK        (0x2U)
38454 #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT       (1U)
38455 /*! AXI_WRITE_ERROR
38456  *  0b0..AXI write is normal
38457  *  0b1..AXI write error has occurred
38458  */
38459 #define PXP_STAT_TOG_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
38460 
38461 #define PXP_STAT_TOG_AXI_READ_ERROR_MASK         (0x4U)
38462 #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT        (2U)
38463 /*! AXI_READ_ERROR
38464  *  0b0..AXI read is normal
38465  *  0b1..AXI read error has occurred
38466  */
38467 #define PXP_STAT_TOG_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
38468 
38469 #define PXP_STAT_TOG_NEXT_IRQ_MASK               (0x8U)
38470 #define PXP_STAT_TOG_NEXT_IRQ_SHIFT              (3U)
38471 #define PXP_STAT_TOG_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
38472 
38473 #define PXP_STAT_TOG_AXI_ERROR_ID_MASK           (0xF0U)
38474 #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT          (4U)
38475 #define PXP_STAT_TOG_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
38476 
38477 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
38478 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38479 /*! LUT_DMA_LOAD_DONE_IRQ
38480  *  0b0..LUT DMA LOAD transfer is active
38481  *  0b1..LUT DMA LOAD transfer is complete
38482  */
38483 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
38484 
38485 #define PXP_STAT_TOG_BLOCKY_MASK                 (0xFF0000U)
38486 #define PXP_STAT_TOG_BLOCKY_SHIFT                (16U)
38487 #define PXP_STAT_TOG_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
38488 
38489 #define PXP_STAT_TOG_BLOCKX_MASK                 (0xFF000000U)
38490 #define PXP_STAT_TOG_BLOCKX_SHIFT                (24U)
38491 #define PXP_STAT_TOG_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
38492 /*! @} */
38493 
38494 /*! @name OUT_CTRL - Output Buffer Control Register */
38495 /*! @{ */
38496 
38497 #define PXP_OUT_CTRL_FORMAT_MASK                 (0x1FU)
38498 #define PXP_OUT_CTRL_FORMAT_SHIFT                (0U)
38499 /*! FORMAT
38500  *  0b00000..32-bit pixels
38501  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
38502  *  0b00101..24-bit pixels (packed 24-bit format)
38503  *  0b01000..16-bit pixels
38504  *  0b01001..16-bit pixels
38505  *  0b01100..16-bit pixels
38506  *  0b01101..16-bit pixels
38507  *  0b01110..16-bit pixels
38508  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
38509  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38510  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38511  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
38512  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38513  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
38514  *  0b11001..16-bit pixels (2-plane UV)
38515  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
38516  *  0b11011..16-bit pixels (2-plane VU)
38517  */
38518 #define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
38519 
38520 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      (0x300U)
38521 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     (8U)
38522 /*! INTERLACED_OUTPUT
38523  *  0b00..All data written in progressive format to the OUTBUF Pointer.
38524  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
38525  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
38526  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
38527  */
38528 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
38529 
38530 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK           (0x800000U)
38531 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT          (23U)
38532 /*! ALPHA_OUTPUT
38533  *  0b0..Retain
38534  *  0b1..Overwritten
38535  */
38536 #define PXP_OUT_CTRL_ALPHA_OUTPUT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
38537 
38538 #define PXP_OUT_CTRL_ALPHA_MASK                  (0xFF000000U)
38539 #define PXP_OUT_CTRL_ALPHA_SHIFT                 (24U)
38540 #define PXP_OUT_CTRL_ALPHA(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
38541 /*! @} */
38542 
38543 /*! @name OUT_CTRL_SET - Output Buffer Control Register */
38544 /*! @{ */
38545 
38546 #define PXP_OUT_CTRL_SET_FORMAT_MASK             (0x1FU)
38547 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT            (0U)
38548 /*! FORMAT
38549  *  0b00000..32-bit pixels
38550  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
38551  *  0b00101..24-bit pixels (packed 24-bit format)
38552  *  0b01000..16-bit pixels
38553  *  0b01001..16-bit pixels
38554  *  0b01100..16-bit pixels
38555  *  0b01101..16-bit pixels
38556  *  0b01110..16-bit pixels
38557  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
38558  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38559  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38560  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
38561  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38562  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
38563  *  0b11001..16-bit pixels (2-plane UV)
38564  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
38565  *  0b11011..16-bit pixels (2-plane VU)
38566  */
38567 #define PXP_OUT_CTRL_SET_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
38568 
38569 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK  (0x300U)
38570 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
38571 /*! INTERLACED_OUTPUT
38572  *  0b00..All data written in progressive format to the OUTBUF Pointer.
38573  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
38574  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
38575  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
38576  */
38577 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
38578 
38579 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK       (0x800000U)
38580 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT      (23U)
38581 /*! ALPHA_OUTPUT
38582  *  0b0..Retain
38583  *  0b1..Overwritten
38584  */
38585 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
38586 
38587 #define PXP_OUT_CTRL_SET_ALPHA_MASK              (0xFF000000U)
38588 #define PXP_OUT_CTRL_SET_ALPHA_SHIFT             (24U)
38589 #define PXP_OUT_CTRL_SET_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
38590 /*! @} */
38591 
38592 /*! @name OUT_CTRL_CLR - Output Buffer Control Register */
38593 /*! @{ */
38594 
38595 #define PXP_OUT_CTRL_CLR_FORMAT_MASK             (0x1FU)
38596 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT            (0U)
38597 /*! FORMAT
38598  *  0b00000..32-bit pixels
38599  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
38600  *  0b00101..24-bit pixels (packed 24-bit format)
38601  *  0b01000..16-bit pixels
38602  *  0b01001..16-bit pixels
38603  *  0b01100..16-bit pixels
38604  *  0b01101..16-bit pixels
38605  *  0b01110..16-bit pixels
38606  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
38607  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38608  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38609  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
38610  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38611  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
38612  *  0b11001..16-bit pixels (2-plane UV)
38613  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
38614  *  0b11011..16-bit pixels (2-plane VU)
38615  */
38616 #define PXP_OUT_CTRL_CLR_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
38617 
38618 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK  (0x300U)
38619 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
38620 /*! INTERLACED_OUTPUT
38621  *  0b00..All data written in progressive format to the OUTBUF Pointer.
38622  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
38623  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
38624  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
38625  */
38626 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
38627 
38628 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK       (0x800000U)
38629 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT      (23U)
38630 /*! ALPHA_OUTPUT
38631  *  0b0..Retain
38632  *  0b1..Overwritten
38633  */
38634 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
38635 
38636 #define PXP_OUT_CTRL_CLR_ALPHA_MASK              (0xFF000000U)
38637 #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT             (24U)
38638 #define PXP_OUT_CTRL_CLR_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
38639 /*! @} */
38640 
38641 /*! @name OUT_CTRL_TOG - Output Buffer Control Register */
38642 /*! @{ */
38643 
38644 #define PXP_OUT_CTRL_TOG_FORMAT_MASK             (0x1FU)
38645 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT            (0U)
38646 /*! FORMAT
38647  *  0b00000..32-bit pixels
38648  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
38649  *  0b00101..24-bit pixels (packed 24-bit format)
38650  *  0b01000..16-bit pixels
38651  *  0b01001..16-bit pixels
38652  *  0b01100..16-bit pixels
38653  *  0b01101..16-bit pixels
38654  *  0b01110..16-bit pixels
38655  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
38656  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38657  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38658  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
38659  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38660  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
38661  *  0b11001..16-bit pixels (2-plane UV)
38662  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
38663  *  0b11011..16-bit pixels (2-plane VU)
38664  */
38665 #define PXP_OUT_CTRL_TOG_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
38666 
38667 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK  (0x300U)
38668 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
38669 /*! INTERLACED_OUTPUT
38670  *  0b00..All data written in progressive format to the OUTBUF Pointer.
38671  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
38672  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
38673  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
38674  */
38675 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
38676 
38677 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK       (0x800000U)
38678 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT      (23U)
38679 /*! ALPHA_OUTPUT
38680  *  0b0..Retain
38681  *  0b1..Overwritten
38682  */
38683 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
38684 
38685 #define PXP_OUT_CTRL_TOG_ALPHA_MASK              (0xFF000000U)
38686 #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT             (24U)
38687 #define PXP_OUT_CTRL_TOG_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
38688 /*! @} */
38689 
38690 /*! @name OUT_BUF - Output Frame Buffer Pointer */
38691 /*! @{ */
38692 
38693 #define PXP_OUT_BUF_ADDR_MASK                    (0xFFFFFFFFU)
38694 #define PXP_OUT_BUF_ADDR_SHIFT                   (0U)
38695 #define PXP_OUT_BUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
38696 /*! @} */
38697 
38698 /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
38699 /*! @{ */
38700 
38701 #define PXP_OUT_BUF2_ADDR_MASK                   (0xFFFFFFFFU)
38702 #define PXP_OUT_BUF2_ADDR_SHIFT                  (0U)
38703 #define PXP_OUT_BUF2_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
38704 /*! @} */
38705 
38706 /*! @name OUT_PITCH - Output Buffer Pitch */
38707 /*! @{ */
38708 
38709 #define PXP_OUT_PITCH_PITCH_MASK                 (0xFFFFU)
38710 #define PXP_OUT_PITCH_PITCH_SHIFT                (0U)
38711 #define PXP_OUT_PITCH_PITCH(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
38712 /*! @} */
38713 
38714 /*! @name OUT_LRC - Output Surface Lower Right Coordinate */
38715 /*! @{ */
38716 
38717 #define PXP_OUT_LRC_Y_MASK                       (0x3FFFU)
38718 #define PXP_OUT_LRC_Y_SHIFT                      (0U)
38719 #define PXP_OUT_LRC_Y(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
38720 
38721 #define PXP_OUT_LRC_X_MASK                       (0x3FFF0000U)
38722 #define PXP_OUT_LRC_X_SHIFT                      (16U)
38723 #define PXP_OUT_LRC_X(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
38724 /*! @} */
38725 
38726 /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
38727 /*! @{ */
38728 
38729 #define PXP_OUT_PS_ULC_Y_MASK                    (0x3FFFU)
38730 #define PXP_OUT_PS_ULC_Y_SHIFT                   (0U)
38731 #define PXP_OUT_PS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
38732 
38733 #define PXP_OUT_PS_ULC_X_MASK                    (0x3FFF0000U)
38734 #define PXP_OUT_PS_ULC_X_SHIFT                   (16U)
38735 #define PXP_OUT_PS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
38736 /*! @} */
38737 
38738 /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
38739 /*! @{ */
38740 
38741 #define PXP_OUT_PS_LRC_Y_MASK                    (0x3FFFU)
38742 #define PXP_OUT_PS_LRC_Y_SHIFT                   (0U)
38743 #define PXP_OUT_PS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
38744 
38745 #define PXP_OUT_PS_LRC_X_MASK                    (0x3FFF0000U)
38746 #define PXP_OUT_PS_LRC_X_SHIFT                   (16U)
38747 #define PXP_OUT_PS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
38748 /*! @} */
38749 
38750 /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
38751 /*! @{ */
38752 
38753 #define PXP_OUT_AS_ULC_Y_MASK                    (0x3FFFU)
38754 #define PXP_OUT_AS_ULC_Y_SHIFT                   (0U)
38755 #define PXP_OUT_AS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
38756 
38757 #define PXP_OUT_AS_ULC_X_MASK                    (0x3FFF0000U)
38758 #define PXP_OUT_AS_ULC_X_SHIFT                   (16U)
38759 #define PXP_OUT_AS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
38760 /*! @} */
38761 
38762 /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
38763 /*! @{ */
38764 
38765 #define PXP_OUT_AS_LRC_Y_MASK                    (0x3FFFU)
38766 #define PXP_OUT_AS_LRC_Y_SHIFT                   (0U)
38767 #define PXP_OUT_AS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
38768 
38769 #define PXP_OUT_AS_LRC_X_MASK                    (0x3FFF0000U)
38770 #define PXP_OUT_AS_LRC_X_SHIFT                   (16U)
38771 #define PXP_OUT_AS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
38772 /*! @} */
38773 
38774 /*! @name PS_CTRL - Processed Surface (PS) Control Register */
38775 /*! @{ */
38776 
38777 #define PXP_PS_CTRL_FORMAT_MASK                  (0x3FU)
38778 #define PXP_PS_CTRL_FORMAT_SHIFT                 (0U)
38779 /*! FORMAT
38780  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
38781  *  0b001100..16-bit pixels with/without alpha at high 1bit
38782  *  0b001101..16-bit pixels with/without alpha at high 4 bits
38783  *  0b001110..16-bit pixels
38784  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
38785  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38786  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38787  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
38788  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38789  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
38790  *  0b011001..16-bit pixels (2-plane UV)
38791  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
38792  *  0b011011..16-bit pixels (2-plane VU)
38793  *  0b011110..16-bit pixels (3-plane format)
38794  *  0b011111..16-bit pixels (3-plane format)
38795  *  0b100100..2-bit pixels with alpha at the low 8 bits
38796  *  0b101100..16-bit pixels with alpha at the low 1bits
38797  *  0b101101..16-bit pixels with alpha at the low 4 bits
38798  */
38799 #define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
38800 
38801 #define PXP_PS_CTRL_WB_SWAP_MASK                 (0x40U)
38802 #define PXP_PS_CTRL_WB_SWAP_SHIFT                (6U)
38803 /*! WB_SWAP
38804  *  0b0..Byte swap is disabled
38805  *  0b1..Byte swap is enabled
38806  */
38807 #define PXP_PS_CTRL_WB_SWAP(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
38808 
38809 #define PXP_PS_CTRL_DECY_MASK                    (0x300U)
38810 #define PXP_PS_CTRL_DECY_SHIFT                   (8U)
38811 /*! DECY
38812  *  0b00..Disable pre-decimation filter.
38813  *  0b01..Decimate PS by 2.
38814  *  0b10..Decimate PS by 4.
38815  *  0b11..Decimate PS by 8.
38816  */
38817 #define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
38818 
38819 #define PXP_PS_CTRL_DECX_MASK                    (0xC00U)
38820 #define PXP_PS_CTRL_DECX_SHIFT                   (10U)
38821 /*! DECX
38822  *  0b00..Disable pre-decimation filter.
38823  *  0b01..Decimate PS by 2.
38824  *  0b10..Decimate PS by 4.
38825  *  0b11..Decimate PS by 8.
38826  */
38827 #define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
38828 /*! @} */
38829 
38830 /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
38831 /*! @{ */
38832 
38833 #define PXP_PS_CTRL_SET_FORMAT_MASK              (0x3FU)
38834 #define PXP_PS_CTRL_SET_FORMAT_SHIFT             (0U)
38835 /*! FORMAT
38836  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
38837  *  0b001100..16-bit pixels with/without alpha at high 1bit
38838  *  0b001101..16-bit pixels with/without alpha at high 4 bits
38839  *  0b001110..16-bit pixels
38840  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
38841  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38842  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38843  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
38844  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38845  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
38846  *  0b011001..16-bit pixels (2-plane UV)
38847  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
38848  *  0b011011..16-bit pixels (2-plane VU)
38849  *  0b011110..16-bit pixels (3-plane format)
38850  *  0b011111..16-bit pixels (3-plane format)
38851  *  0b100100..2-bit pixels with alpha at the low 8 bits
38852  *  0b101100..16-bit pixels with alpha at the low 1bits
38853  *  0b101101..16-bit pixels with alpha at the low 4 bits
38854  */
38855 #define PXP_PS_CTRL_SET_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
38856 
38857 #define PXP_PS_CTRL_SET_WB_SWAP_MASK             (0x40U)
38858 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT            (6U)
38859 /*! WB_SWAP
38860  *  0b0..Byte swap is disabled
38861  *  0b1..Byte swap is enabled
38862  */
38863 #define PXP_PS_CTRL_SET_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
38864 
38865 #define PXP_PS_CTRL_SET_DECY_MASK                (0x300U)
38866 #define PXP_PS_CTRL_SET_DECY_SHIFT               (8U)
38867 /*! DECY
38868  *  0b00..Disable pre-decimation filter.
38869  *  0b01..Decimate PS by 2.
38870  *  0b10..Decimate PS by 4.
38871  *  0b11..Decimate PS by 8.
38872  */
38873 #define PXP_PS_CTRL_SET_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
38874 
38875 #define PXP_PS_CTRL_SET_DECX_MASK                (0xC00U)
38876 #define PXP_PS_CTRL_SET_DECX_SHIFT               (10U)
38877 /*! DECX
38878  *  0b00..Disable pre-decimation filter.
38879  *  0b01..Decimate PS by 2.
38880  *  0b10..Decimate PS by 4.
38881  *  0b11..Decimate PS by 8.
38882  */
38883 #define PXP_PS_CTRL_SET_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
38884 /*! @} */
38885 
38886 /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
38887 /*! @{ */
38888 
38889 #define PXP_PS_CTRL_CLR_FORMAT_MASK              (0x3FU)
38890 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT             (0U)
38891 /*! FORMAT
38892  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
38893  *  0b001100..16-bit pixels with/without alpha at high 1bit
38894  *  0b001101..16-bit pixels with/without alpha at high 4 bits
38895  *  0b001110..16-bit pixels
38896  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
38897  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38898  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38899  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
38900  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38901  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
38902  *  0b011001..16-bit pixels (2-plane UV)
38903  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
38904  *  0b011011..16-bit pixels (2-plane VU)
38905  *  0b011110..16-bit pixels (3-plane format)
38906  *  0b011111..16-bit pixels (3-plane format)
38907  *  0b100100..2-bit pixels with alpha at the low 8 bits
38908  *  0b101100..16-bit pixels with alpha at the low 1bits
38909  *  0b101101..16-bit pixels with alpha at the low 4 bits
38910  */
38911 #define PXP_PS_CTRL_CLR_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
38912 
38913 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK             (0x40U)
38914 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT            (6U)
38915 /*! WB_SWAP
38916  *  0b0..Byte swap is disabled
38917  *  0b1..Byte swap is enabled
38918  */
38919 #define PXP_PS_CTRL_CLR_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
38920 
38921 #define PXP_PS_CTRL_CLR_DECY_MASK                (0x300U)
38922 #define PXP_PS_CTRL_CLR_DECY_SHIFT               (8U)
38923 /*! DECY
38924  *  0b00..Disable pre-decimation filter.
38925  *  0b01..Decimate PS by 2.
38926  *  0b10..Decimate PS by 4.
38927  *  0b11..Decimate PS by 8.
38928  */
38929 #define PXP_PS_CTRL_CLR_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
38930 
38931 #define PXP_PS_CTRL_CLR_DECX_MASK                (0xC00U)
38932 #define PXP_PS_CTRL_CLR_DECX_SHIFT               (10U)
38933 /*! DECX
38934  *  0b00..Disable pre-decimation filter.
38935  *  0b01..Decimate PS by 2.
38936  *  0b10..Decimate PS by 4.
38937  *  0b11..Decimate PS by 8.
38938  */
38939 #define PXP_PS_CTRL_CLR_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
38940 /*! @} */
38941 
38942 /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
38943 /*! @{ */
38944 
38945 #define PXP_PS_CTRL_TOG_FORMAT_MASK              (0x3FU)
38946 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT             (0U)
38947 /*! FORMAT
38948  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
38949  *  0b001100..16-bit pixels with/without alpha at high 1bit
38950  *  0b001101..16-bit pixels with/without alpha at high 4 bits
38951  *  0b001110..16-bit pixels
38952  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
38953  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
38954  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
38955  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
38956  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
38957  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
38958  *  0b011001..16-bit pixels (2-plane UV)
38959  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
38960  *  0b011011..16-bit pixels (2-plane VU)
38961  *  0b011110..16-bit pixels (3-plane format)
38962  *  0b011111..16-bit pixels (3-plane format)
38963  *  0b100100..2-bit pixels with alpha at the low 8 bits
38964  *  0b101100..16-bit pixels with alpha at the low 1bits
38965  *  0b101101..16-bit pixels with alpha at the low 4 bits
38966  */
38967 #define PXP_PS_CTRL_TOG_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
38968 
38969 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK             (0x40U)
38970 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT            (6U)
38971 /*! WB_SWAP
38972  *  0b0..Byte swap is disabled
38973  *  0b1..Byte swap is enabled
38974  */
38975 #define PXP_PS_CTRL_TOG_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
38976 
38977 #define PXP_PS_CTRL_TOG_DECY_MASK                (0x300U)
38978 #define PXP_PS_CTRL_TOG_DECY_SHIFT               (8U)
38979 /*! DECY
38980  *  0b00..Disable pre-decimation filter.
38981  *  0b01..Decimate PS by 2.
38982  *  0b10..Decimate PS by 4.
38983  *  0b11..Decimate PS by 8.
38984  */
38985 #define PXP_PS_CTRL_TOG_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
38986 
38987 #define PXP_PS_CTRL_TOG_DECX_MASK                (0xC00U)
38988 #define PXP_PS_CTRL_TOG_DECX_SHIFT               (10U)
38989 /*! DECX
38990  *  0b00..Disable pre-decimation filter.
38991  *  0b01..Decimate PS by 2.
38992  *  0b10..Decimate PS by 4.
38993  *  0b11..Decimate PS by 8.
38994  */
38995 #define PXP_PS_CTRL_TOG_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
38996 /*! @} */
38997 
38998 /*! @name PS_BUF - PS Input Buffer Address */
38999 /*! @{ */
39000 
39001 #define PXP_PS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
39002 #define PXP_PS_BUF_ADDR_SHIFT                    (0U)
39003 #define PXP_PS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
39004 /*! @} */
39005 
39006 /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
39007 /*! @{ */
39008 
39009 #define PXP_PS_UBUF_ADDR_MASK                    (0xFFFFFFFFU)
39010 #define PXP_PS_UBUF_ADDR_SHIFT                   (0U)
39011 #define PXP_PS_UBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
39012 /*! @} */
39013 
39014 /*! @name PS_VBUF - PS V/Cr Input Buffer Address */
39015 /*! @{ */
39016 
39017 #define PXP_PS_VBUF_ADDR_MASK                    (0xFFFFFFFFU)
39018 #define PXP_PS_VBUF_ADDR_SHIFT                   (0U)
39019 #define PXP_PS_VBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
39020 /*! @} */
39021 
39022 /*! @name PS_PITCH - Processed Surface Pitch */
39023 /*! @{ */
39024 
39025 #define PXP_PS_PITCH_PITCH_MASK                  (0xFFFFU)
39026 #define PXP_PS_PITCH_PITCH_SHIFT                 (0U)
39027 #define PXP_PS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
39028 /*! @} */
39029 
39030 /*! @name PS_BACKGROUND - PS Background Color */
39031 /*! @{ */
39032 
39033 #define PXP_PS_BACKGROUND_COLOR_MASK             (0xFFFFFFU)
39034 #define PXP_PS_BACKGROUND_COLOR_SHIFT            (0U)
39035 #define PXP_PS_BACKGROUND_COLOR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
39036 /*! @} */
39037 
39038 /*! @name PS_SCALE - PS Scale Factor Register */
39039 /*! @{ */
39040 
39041 #define PXP_PS_SCALE_XSCALE_MASK                 (0x7FFFU)
39042 #define PXP_PS_SCALE_XSCALE_SHIFT                (0U)
39043 #define PXP_PS_SCALE_XSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
39044 
39045 #define PXP_PS_SCALE_YSCALE_MASK                 (0x7FFF0000U)
39046 #define PXP_PS_SCALE_YSCALE_SHIFT                (16U)
39047 #define PXP_PS_SCALE_YSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
39048 /*! @} */
39049 
39050 /*! @name PS_OFFSET - PS Scale Offset Register */
39051 /*! @{ */
39052 
39053 #define PXP_PS_OFFSET_XOFFSET_MASK               (0xFFFU)
39054 #define PXP_PS_OFFSET_XOFFSET_SHIFT              (0U)
39055 #define PXP_PS_OFFSET_XOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
39056 
39057 #define PXP_PS_OFFSET_YOFFSET_MASK               (0xFFF0000U)
39058 #define PXP_PS_OFFSET_YOFFSET_SHIFT              (16U)
39059 #define PXP_PS_OFFSET_YOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
39060 /*! @} */
39061 
39062 /*! @name PS_CLRKEYLOW - PS Color Key Low */
39063 /*! @{ */
39064 
39065 #define PXP_PS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
39066 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT             (0U)
39067 #define PXP_PS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
39068 /*! @} */
39069 
39070 /*! @name PS_CLRKEYHIGH - PS Color Key High */
39071 /*! @{ */
39072 
39073 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
39074 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
39075 #define PXP_PS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
39076 /*! @} */
39077 
39078 /*! @name AS_CTRL - Alpha Surface Control */
39079 /*! @{ */
39080 
39081 #define PXP_AS_CTRL_ALPHA_CTRL_MASK              (0x6U)
39082 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             (1U)
39083 /*! ALPHA_CTRL
39084  *  0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
39085  *  0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
39086  *  0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel
39087  *        alpha is multiplied by the value in the ALPHA field.
39088  *  0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
39089  */
39090 #define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
39091 
39092 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         (0x8U)
39093 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        (3U)
39094 /*! ENABLE_COLORKEY
39095  *  0b0..Disabled
39096  *  0b1..Enabled
39097  */
39098 #define PXP_AS_CTRL_ENABLE_COLORKEY(x)           (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
39099 
39100 #define PXP_AS_CTRL_FORMAT_MASK                  (0xF0U)
39101 #define PXP_AS_CTRL_FORMAT_SHIFT                 (4U)
39102 /*! FORMAT
39103  *  0b0000..32-bit pixels with alpha
39104  *  0b0001..2-bit pixel with alpha at low 8 bits
39105  *  0b0100..32-bit pixels without alpha (unpacked 24-bit format)
39106  *  0b1000..16-bit pixels with alpha
39107  *  0b1001..16-bit pixels with alpha
39108  *  0b1010..16-bit pixel with alpha at low 1 bit
39109  *  0b1011..16-bit pixel with alpha at low 4 bits
39110  *  0b1100..16-bit pixels without alpha
39111  *  0b1101..16-bit pixels without alpha
39112  *  0b1110..16-bit pixels without alpha
39113  */
39114 #define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
39115 
39116 #define PXP_AS_CTRL_ALPHA_MASK                   (0xFF00U)
39117 #define PXP_AS_CTRL_ALPHA_SHIFT                  (8U)
39118 #define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
39119 
39120 #define PXP_AS_CTRL_ROP_MASK                     (0xF0000U)
39121 #define PXP_AS_CTRL_ROP_SHIFT                    (16U)
39122 /*! ROP
39123  *  0b0000..AS AND PS
39124  *  0b0001..nAS AND PS
39125  *  0b0010..AS AND nPS
39126  *  0b0011..AS OR PS
39127  *  0b0100..nAS OR PS
39128  *  0b0101..AS OR nPS
39129  *  0b0110..nAS
39130  *  0b0111..nPS
39131  *  0b1000..AS NAND PS
39132  *  0b1001..AS NOR PS
39133  *  0b1010..AS XOR PS
39134  *  0b1011..AS XNOR PS
39135  */
39136 #define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
39137 
39138 #define PXP_AS_CTRL_ALPHA_INVERT_MASK            (0x100000U)
39139 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT           (20U)
39140 /*! ALPHA_INVERT
39141  *  0b0..Not inverted
39142  *  0b1..Inverted
39143  */
39144 #define PXP_AS_CTRL_ALPHA_INVERT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
39145 /*! @} */
39146 
39147 /*! @name AS_BUF - Alpha Surface Buffer Pointer */
39148 /*! @{ */
39149 
39150 #define PXP_AS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
39151 #define PXP_AS_BUF_ADDR_SHIFT                    (0U)
39152 #define PXP_AS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
39153 /*! @} */
39154 
39155 /*! @name AS_PITCH - Alpha Surface Pitch */
39156 /*! @{ */
39157 
39158 #define PXP_AS_PITCH_PITCH_MASK                  (0xFFFFU)
39159 #define PXP_AS_PITCH_PITCH_SHIFT                 (0U)
39160 #define PXP_AS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
39161 /*! @} */
39162 
39163 /*! @name AS_CLRKEYLOW - Overlay Color Key Low */
39164 /*! @{ */
39165 
39166 #define PXP_AS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
39167 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT             (0U)
39168 #define PXP_AS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
39169 /*! @} */
39170 
39171 /*! @name AS_CLRKEYHIGH - Overlay Color Key High */
39172 /*! @{ */
39173 
39174 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
39175 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
39176 #define PXP_AS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
39177 /*! @} */
39178 
39179 /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
39180 /*! @{ */
39181 
39182 #define PXP_CSC1_COEF0_Y_OFFSET_MASK             (0x1FFU)
39183 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT            (0U)
39184 #define PXP_CSC1_COEF0_Y_OFFSET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
39185 
39186 #define PXP_CSC1_COEF0_UV_OFFSET_MASK            (0x3FE00U)
39187 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT           (9U)
39188 #define PXP_CSC1_COEF0_UV_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
39189 
39190 #define PXP_CSC1_COEF0_C0_MASK                   (0x1FFC0000U)
39191 #define PXP_CSC1_COEF0_C0_SHIFT                  (18U)
39192 #define PXP_CSC1_COEF0_C0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
39193 
39194 #define PXP_CSC1_COEF0_BYPASS_MASK               (0x40000000U)
39195 #define PXP_CSC1_COEF0_BYPASS_SHIFT              (30U)
39196 #define PXP_CSC1_COEF0_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
39197 
39198 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK           (0x80000000U)
39199 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT          (31U)
39200 /*! YCBCR_MODE
39201  *  0b0..YUV to RGB
39202  *  0b1..YCbCr to RGB
39203  */
39204 #define PXP_CSC1_COEF0_YCBCR_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
39205 /*! @} */
39206 
39207 /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
39208 /*! @{ */
39209 
39210 #define PXP_CSC1_COEF1_C4_MASK                   (0x7FFU)
39211 #define PXP_CSC1_COEF1_C4_SHIFT                  (0U)
39212 #define PXP_CSC1_COEF1_C4(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
39213 
39214 #define PXP_CSC1_COEF1_C1_MASK                   (0x7FF0000U)
39215 #define PXP_CSC1_COEF1_C1_SHIFT                  (16U)
39216 #define PXP_CSC1_COEF1_C1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
39217 /*! @} */
39218 
39219 /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
39220 /*! @{ */
39221 
39222 #define PXP_CSC1_COEF2_C3_MASK                   (0x7FFU)
39223 #define PXP_CSC1_COEF2_C3_SHIFT                  (0U)
39224 #define PXP_CSC1_COEF2_C3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
39225 
39226 #define PXP_CSC1_COEF2_C2_MASK                   (0x7FF0000U)
39227 #define PXP_CSC1_COEF2_C2_SHIFT                  (16U)
39228 #define PXP_CSC1_COEF2_C2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
39229 /*! @} */
39230 
39231 /*! @name POWER - PXP Power Control Register */
39232 /*! @{ */
39233 
39234 #define PXP_POWER_ROT_MEM_LP_STATE_MASK          (0xE00U)
39235 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT         (9U)
39236 /*! ROT_MEM_LP_STATE
39237  *  0b000..Memory is not in low power state.
39238  *  0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
39239  *  0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
39240  *  0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
39241  */
39242 #define PXP_POWER_ROT_MEM_LP_STATE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
39243 
39244 #define PXP_POWER_CTRL_MASK                      (0xFFFFF000U)
39245 #define PXP_POWER_CTRL_SHIFT                     (12U)
39246 #define PXP_POWER_CTRL(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
39247 /*! @} */
39248 
39249 /*! @name NEXT - Next Frame Pointer */
39250 /*! @{ */
39251 
39252 #define PXP_NEXT_ENABLED_MASK                    (0x1U)
39253 #define PXP_NEXT_ENABLED_SHIFT                   (0U)
39254 #define PXP_NEXT_ENABLED(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
39255 
39256 #define PXP_NEXT_POINTER_MASK                    (0xFFFFFFFCU)
39257 #define PXP_NEXT_POINTER_SHIFT                   (2U)
39258 #define PXP_NEXT_POINTER(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
39259 /*! @} */
39260 
39261 /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
39262 /*! @{ */
39263 
39264 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
39265 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
39266 /*! PORTER_DUFF_ENABLE
39267  *  0b0..Disabled
39268  *  0b1..Enabled
39269  */
39270 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
39271 
39272 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
39273 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
39274 /*! S0_S1_FACTOR_MODE
39275  *  0b00..1
39276  *  0b01..0
39277  *  0b10..Straight alpha
39278  *  0b11..Inverse alpha
39279  */
39280 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
39281 
39282 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
39283 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
39284 /*! S0_GLOBAL_ALPHA_MODE
39285  *  0b00..Global alpha
39286  *  0b01..Local alpha
39287  *  0b10..Scaled alpha
39288  *  0b11..Scaled alpha
39289  */
39290 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
39291 
39292 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK  (0x20U)
39293 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
39294 /*! S0_ALPHA_MODE
39295  *  0b0..Straight mode
39296  *  0b1..Inverted mode
39297  */
39298 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
39299 
39300 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK  (0x40U)
39301 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
39302 /*! S0_COLOR_MODE
39303  *  0b0..Original pixel
39304  *  0b1..Scaled pixel
39305  */
39306 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
39307 
39308 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
39309 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
39310 /*! S1_S0_FACTOR_MODE
39311  *  0b00..1
39312  *  0b01..0
39313  *  0b10..Straight alpha
39314  *  0b11..Inverse alpha
39315  */
39316 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
39317 
39318 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
39319 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
39320 /*! S1_GLOBAL_ALPHA_MODE
39321  *  0b00..Global alpha
39322  *  0b01..Local alpha
39323  *  0b10..Scaled alpha
39324  *  0b11..Scaled alpha
39325  */
39326 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
39327 
39328 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK  (0x1000U)
39329 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
39330 /*! S1_ALPHA_MODE
39331  *  0b0..Straight mode
39332  *  0b1..Inverted mode
39333  */
39334 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
39335 
39336 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK  (0x2000U)
39337 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
39338 /*! S1_COLOR_MODE
39339  *  0b0..Original pixel
39340  *  0b1..Scaled pixel
39341  */
39342 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
39343 
39344 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
39345 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
39346 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
39347 
39348 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
39349 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
39350 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
39351 /*! @} */
39352 
39353 
39354 /*!
39355  * @}
39356  */ /* end of group PXP_Register_Masks */
39357 
39358 
39359 /* PXP - Peripheral instance base addresses */
39360 /** Peripheral PXP base address */
39361 #define PXP_BASE                                 (0x402B4000u)
39362 /** Peripheral PXP base pointer */
39363 #define PXP                                      ((PXP_Type *)PXP_BASE)
39364 /** Array initializer of PXP peripheral base addresses */
39365 #define PXP_BASE_ADDRS                           { PXP_BASE }
39366 /** Array initializer of PXP peripheral base pointers */
39367 #define PXP_BASE_PTRS                            { PXP }
39368 /** Interrupt vectors for the PXP peripheral type */
39369 #define PXP_IRQ0_IRQS                            { PXP_IRQn }
39370 
39371 /*!
39372  * @}
39373  */ /* end of group PXP_Peripheral_Access_Layer */
39374 
39375 
39376 /* ----------------------------------------------------------------------------
39377    -- ROMC Peripheral Access Layer
39378    ---------------------------------------------------------------------------- */
39379 
39380 /*!
39381  * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
39382  * @{
39383  */
39384 
39385 /** ROMC - Register Layout Typedef */
39386 typedef struct {
39387        uint8_t RESERVED_0[212];
39388   __IO uint32_t ROMPATCHD[8];                      /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
39389   __IO uint32_t ROMPATCHCNTL;                      /**< ROMC Control Register, offset: 0xF4 */
39390        uint32_t ROMPATCHENH;                       /**< ROMC Enable Register High, offset: 0xF8 */
39391   __IO uint32_t ROMPATCHENL;                       /**< ROMC Enable Register Low, offset: 0xFC */
39392   __IO uint32_t ROMPATCHA[16];                     /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
39393        uint8_t RESERVED_1[200];
39394   __IO uint32_t ROMPATCHSR;                        /**< ROMC Status Register, offset: 0x208 */
39395 } ROMC_Type;
39396 
39397 /* ----------------------------------------------------------------------------
39398    -- ROMC Register Masks
39399    ---------------------------------------------------------------------------- */
39400 
39401 /*!
39402  * @addtogroup ROMC_Register_Masks ROMC Register Masks
39403  * @{
39404  */
39405 
39406 /*! @name ROMPATCHD - ROMC Data Registers */
39407 /*! @{ */
39408 
39409 #define ROMC_ROMPATCHD_DATAX_MASK                (0xFFFFFFFFU)
39410 #define ROMC_ROMPATCHD_DATAX_SHIFT               (0U)
39411 #define ROMC_ROMPATCHD_DATAX(x)                  (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
39412 /*! @} */
39413 
39414 /* The count of ROMC_ROMPATCHD */
39415 #define ROMC_ROMPATCHD_COUNT                     (8U)
39416 
39417 /*! @name ROMPATCHCNTL - ROMC Control Register */
39418 /*! @{ */
39419 
39420 #define ROMC_ROMPATCHCNTL_DATAFIX_MASK           (0xFFU)
39421 #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT          (0U)
39422 /*! DATAFIX
39423  *  0b00000000..Address comparator triggers a opcode patch
39424  *  0b00000001..Address comparator triggers a data fix
39425  */
39426 #define ROMC_ROMPATCHCNTL_DATAFIX(x)             (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
39427 
39428 #define ROMC_ROMPATCHCNTL_DIS_MASK               (0x20000000U)
39429 #define ROMC_ROMPATCHCNTL_DIS_SHIFT              (29U)
39430 /*! DIS
39431  *  0b0..Does not affect any ROMC functions (default)
39432  *  0b1..Disable all ROMC functions: data fixing, and opcode patching
39433  */
39434 #define ROMC_ROMPATCHCNTL_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
39435 /*! @} */
39436 
39437 /*! @name ROMPATCHENL - ROMC Enable Register Low */
39438 /*! @{ */
39439 
39440 #define ROMC_ROMPATCHENL_ENABLE_MASK             (0xFFFFU)
39441 #define ROMC_ROMPATCHENL_ENABLE_SHIFT            (0U)
39442 /*! ENABLE
39443  *  0b0000000000000000..Address comparator disabled
39444  *  0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
39445  */
39446 #define ROMC_ROMPATCHENL_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
39447 /*! @} */
39448 
39449 /*! @name ROMPATCHA - ROMC Address Registers */
39450 /*! @{ */
39451 
39452 #define ROMC_ROMPATCHA_THUMBX_MASK               (0x1U)
39453 #define ROMC_ROMPATCHA_THUMBX_SHIFT              (0U)
39454 /*! THUMBX
39455  *  0b0..Arm patch
39456  *  0b1..THUMB patch (ignore if data fix)
39457  */
39458 #define ROMC_ROMPATCHA_THUMBX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
39459 
39460 #define ROMC_ROMPATCHA_ADDRX_MASK                (0x7FFFFEU)
39461 #define ROMC_ROMPATCHA_ADDRX_SHIFT               (1U)
39462 #define ROMC_ROMPATCHA_ADDRX(x)                  (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
39463 /*! @} */
39464 
39465 /* The count of ROMC_ROMPATCHA */
39466 #define ROMC_ROMPATCHA_COUNT                     (16U)
39467 
39468 /*! @name ROMPATCHSR - ROMC Status Register */
39469 /*! @{ */
39470 
39471 #define ROMC_ROMPATCHSR_SOURCE_MASK              (0x3FU)
39472 #define ROMC_ROMPATCHSR_SOURCE_SHIFT             (0U)
39473 /*! SOURCE
39474  *  0b000000..Address Comparator 0 matched
39475  *  0b000001..Address Comparator 1 matched
39476  *  0b001111..Address Comparator 15 matched
39477  */
39478 #define ROMC_ROMPATCHSR_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
39479 
39480 #define ROMC_ROMPATCHSR_SW_MASK                  (0x20000U)
39481 #define ROMC_ROMPATCHSR_SW_SHIFT                 (17U)
39482 /*! SW
39483  *  0b0..no event or comparator collisions
39484  *  0b1..a collision has occurred
39485  */
39486 #define ROMC_ROMPATCHSR_SW(x)                    (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
39487 /*! @} */
39488 
39489 
39490 /*!
39491  * @}
39492  */ /* end of group ROMC_Register_Masks */
39493 
39494 
39495 /* ROMC - Peripheral instance base addresses */
39496 /** Peripheral ROMC base address */
39497 #define ROMC_BASE                                (0x40180000u)
39498 /** Peripheral ROMC base pointer */
39499 #define ROMC                                     ((ROMC_Type *)ROMC_BASE)
39500 /** Array initializer of ROMC peripheral base addresses */
39501 #define ROMC_BASE_ADDRS                          { ROMC_BASE }
39502 /** Array initializer of ROMC peripheral base pointers */
39503 #define ROMC_BASE_PTRS                           { ROMC }
39504 
39505 /*!
39506  * @}
39507  */ /* end of group ROMC_Peripheral_Access_Layer */
39508 
39509 
39510 /* ----------------------------------------------------------------------------
39511    -- RTWDOG Peripheral Access Layer
39512    ---------------------------------------------------------------------------- */
39513 
39514 /*!
39515  * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
39516  * @{
39517  */
39518 
39519 /** RTWDOG - Register Layout Typedef */
39520 typedef struct {
39521   __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
39522   __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
39523   __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
39524   __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
39525 } RTWDOG_Type;
39526 
39527 /* ----------------------------------------------------------------------------
39528    -- RTWDOG Register Masks
39529    ---------------------------------------------------------------------------- */
39530 
39531 /*!
39532  * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
39533  * @{
39534  */
39535 
39536 /*! @name CS - Watchdog Control and Status Register */
39537 /*! @{ */
39538 
39539 #define RTWDOG_CS_STOP_MASK                      (0x1U)
39540 #define RTWDOG_CS_STOP_SHIFT                     (0U)
39541 /*! STOP - Stop Enable
39542  *  0b0..Watchdog disabled in chip stop mode.
39543  *  0b1..Watchdog enabled in chip stop mode.
39544  */
39545 #define RTWDOG_CS_STOP(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
39546 
39547 #define RTWDOG_CS_WAIT_MASK                      (0x2U)
39548 #define RTWDOG_CS_WAIT_SHIFT                     (1U)
39549 /*! WAIT - Wait Enable
39550  *  0b0..Watchdog disabled in chip wait mode.
39551  *  0b1..Watchdog enabled in chip wait mode.
39552  */
39553 #define RTWDOG_CS_WAIT(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
39554 
39555 #define RTWDOG_CS_DBG_MASK                       (0x4U)
39556 #define RTWDOG_CS_DBG_SHIFT                      (2U)
39557 /*! DBG - Debug Enable
39558  *  0b0..Watchdog disabled in chip debug mode.
39559  *  0b1..Watchdog enabled in chip debug mode.
39560  */
39561 #define RTWDOG_CS_DBG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
39562 
39563 #define RTWDOG_CS_TST_MASK                       (0x18U)
39564 #define RTWDOG_CS_TST_SHIFT                      (3U)
39565 /*! TST - Watchdog Test
39566  *  0b00..Watchdog test mode disabled.
39567  *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
39568  *        use this setting to indicate that the watchdog is functioning normally in user mode.
39569  *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
39570  *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
39571  */
39572 #define RTWDOG_CS_TST(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
39573 
39574 #define RTWDOG_CS_UPDATE_MASK                    (0x20U)
39575 #define RTWDOG_CS_UPDATE_SHIFT                   (5U)
39576 /*! UPDATE - Allow updates
39577  *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
39578  *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
39579  */
39580 #define RTWDOG_CS_UPDATE(x)                      (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
39581 
39582 #define RTWDOG_CS_INT_MASK                       (0x40U)
39583 #define RTWDOG_CS_INT_SHIFT                      (6U)
39584 /*! INT - Watchdog Interrupt
39585  *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
39586  *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
39587  */
39588 #define RTWDOG_CS_INT(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
39589 
39590 #define RTWDOG_CS_EN_MASK                        (0x80U)
39591 #define RTWDOG_CS_EN_SHIFT                       (7U)
39592 /*! EN - Watchdog Enable
39593  *  0b0..Watchdog disabled.
39594  *  0b1..Watchdog enabled.
39595  */
39596 #define RTWDOG_CS_EN(x)                          (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
39597 
39598 #define RTWDOG_CS_CLK_MASK                       (0x300U)
39599 #define RTWDOG_CS_CLK_SHIFT                      (8U)
39600 /*! CLK - Watchdog Clock
39601  */
39602 #define RTWDOG_CS_CLK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
39603 
39604 #define RTWDOG_CS_RCS_MASK                       (0x400U)
39605 #define RTWDOG_CS_RCS_SHIFT                      (10U)
39606 /*! RCS - Reconfiguration Success
39607  *  0b0..Reconfiguring WDOG.
39608  *  0b1..Reconfiguration is successful.
39609  */
39610 #define RTWDOG_CS_RCS(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
39611 
39612 #define RTWDOG_CS_ULK_MASK                       (0x800U)
39613 #define RTWDOG_CS_ULK_SHIFT                      (11U)
39614 /*! ULK - Unlock status
39615  *  0b0..WDOG is locked.
39616  *  0b1..WDOG is unlocked.
39617  */
39618 #define RTWDOG_CS_ULK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
39619 
39620 #define RTWDOG_CS_PRES_MASK                      (0x1000U)
39621 #define RTWDOG_CS_PRES_SHIFT                     (12U)
39622 /*! PRES - Watchdog prescaler
39623  *  0b0..256 prescaler disabled.
39624  *  0b1..256 prescaler enabled.
39625  */
39626 #define RTWDOG_CS_PRES(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
39627 
39628 #define RTWDOG_CS_CMD32EN_MASK                   (0x2000U)
39629 #define RTWDOG_CS_CMD32EN_SHIFT                  (13U)
39630 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
39631  *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
39632  *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
39633  */
39634 #define RTWDOG_CS_CMD32EN(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
39635 
39636 #define RTWDOG_CS_FLG_MASK                       (0x4000U)
39637 #define RTWDOG_CS_FLG_SHIFT                      (14U)
39638 /*! FLG - Watchdog Interrupt Flag
39639  *  0b0..No interrupt occurred.
39640  *  0b1..An interrupt occurred.
39641  */
39642 #define RTWDOG_CS_FLG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
39643 
39644 #define RTWDOG_CS_WIN_MASK                       (0x8000U)
39645 #define RTWDOG_CS_WIN_SHIFT                      (15U)
39646 /*! WIN - Watchdog Window
39647  *  0b0..Window mode disabled.
39648  *  0b1..Window mode enabled.
39649  */
39650 #define RTWDOG_CS_WIN(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
39651 /*! @} */
39652 
39653 /*! @name CNT - Watchdog Counter Register */
39654 /*! @{ */
39655 
39656 #define RTWDOG_CNT_CNTLOW_MASK                   (0xFFU)
39657 #define RTWDOG_CNT_CNTLOW_SHIFT                  (0U)
39658 /*! CNTLOW - Low byte of the Watchdog Counter
39659  */
39660 #define RTWDOG_CNT_CNTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
39661 
39662 #define RTWDOG_CNT_CNTHIGH_MASK                  (0xFF00U)
39663 #define RTWDOG_CNT_CNTHIGH_SHIFT                 (8U)
39664 /*! CNTHIGH - High byte of the Watchdog Counter
39665  */
39666 #define RTWDOG_CNT_CNTHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
39667 /*! @} */
39668 
39669 /*! @name TOVAL - Watchdog Timeout Value Register */
39670 /*! @{ */
39671 
39672 #define RTWDOG_TOVAL_TOVALLOW_MASK               (0xFFU)
39673 #define RTWDOG_TOVAL_TOVALLOW_SHIFT              (0U)
39674 /*! TOVALLOW - Low byte of the timeout value
39675  */
39676 #define RTWDOG_TOVAL_TOVALLOW(x)                 (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
39677 
39678 #define RTWDOG_TOVAL_TOVALHIGH_MASK              (0xFF00U)
39679 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT             (8U)
39680 /*! TOVALHIGH - High byte of the timeout value
39681  */
39682 #define RTWDOG_TOVAL_TOVALHIGH(x)                (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
39683 /*! @} */
39684 
39685 /*! @name WIN - Watchdog Window Register */
39686 /*! @{ */
39687 
39688 #define RTWDOG_WIN_WINLOW_MASK                   (0xFFU)
39689 #define RTWDOG_WIN_WINLOW_SHIFT                  (0U)
39690 /*! WINLOW - Low byte of Watchdog Window
39691  */
39692 #define RTWDOG_WIN_WINLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
39693 
39694 #define RTWDOG_WIN_WINHIGH_MASK                  (0xFF00U)
39695 #define RTWDOG_WIN_WINHIGH_SHIFT                 (8U)
39696 /*! WINHIGH - High byte of Watchdog Window
39697  */
39698 #define RTWDOG_WIN_WINHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
39699 /*! @} */
39700 
39701 
39702 /*!
39703  * @}
39704  */ /* end of group RTWDOG_Register_Masks */
39705 
39706 
39707 /* RTWDOG - Peripheral instance base addresses */
39708 /** Peripheral RTWDOG base address */
39709 #define RTWDOG_BASE                              (0x400BC000u)
39710 /** Peripheral RTWDOG base pointer */
39711 #define RTWDOG                                   ((RTWDOG_Type *)RTWDOG_BASE)
39712 /** Array initializer of RTWDOG peripheral base addresses */
39713 #define RTWDOG_BASE_ADDRS                        { RTWDOG_BASE }
39714 /** Array initializer of RTWDOG peripheral base pointers */
39715 #define RTWDOG_BASE_PTRS                         { RTWDOG }
39716 /** Interrupt vectors for the RTWDOG peripheral type */
39717 #define RTWDOG_IRQS                              { RTWDOG_IRQn }
39718 /* Extra definition */
39719 #define RTWDOG_UPDATE_KEY                        (0xD928C520U)
39720 #define RTWDOG_REFRESH_KEY                       (0xB480A602U)
39721 
39722 
39723 /*!
39724  * @}
39725  */ /* end of group RTWDOG_Peripheral_Access_Layer */
39726 
39727 
39728 /* ----------------------------------------------------------------------------
39729    -- SEMC Peripheral Access Layer
39730    ---------------------------------------------------------------------------- */
39731 
39732 /*!
39733  * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
39734  * @{
39735  */
39736 
39737 /** SEMC - Register Layout Typedef */
39738 typedef struct {
39739   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
39740   __IO uint32_t IOCR;                              /**< IO Mux Control Register, offset: 0x4 */
39741   __IO uint32_t BMCR0;                             /**< Bus (AXI) Master Control Register 0, offset: 0x8 */
39742   __IO uint32_t BMCR1;                             /**< Bus (AXI) Master Control Register 1, offset: 0xC */
39743   __IO uint32_t BR[9];                             /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */
39744        uint8_t RESERVED_0[4];
39745   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x38 */
39746   __IO uint32_t INTR;                              /**< Interrupt Enable Register, offset: 0x3C */
39747   __IO uint32_t SDRAMCR0;                          /**< SDRAM control register 0, offset: 0x40 */
39748   __IO uint32_t SDRAMCR1;                          /**< SDRAM control register 1, offset: 0x44 */
39749   __IO uint32_t SDRAMCR2;                          /**< SDRAM control register 2, offset: 0x48 */
39750   __IO uint32_t SDRAMCR3;                          /**< SDRAM control register 3, offset: 0x4C */
39751   __IO uint32_t NANDCR0;                           /**< NAND control register 0, offset: 0x50 */
39752   __IO uint32_t NANDCR1;                           /**< NAND control register 1, offset: 0x54 */
39753   __IO uint32_t NANDCR2;                           /**< NAND control register 2, offset: 0x58 */
39754   __IO uint32_t NANDCR3;                           /**< NAND control register 3, offset: 0x5C */
39755   __IO uint32_t NORCR0;                            /**< NOR control register 0, offset: 0x60 */
39756   __IO uint32_t NORCR1;                            /**< NOR control register 1, offset: 0x64 */
39757   __IO uint32_t NORCR2;                            /**< NOR control register 2, offset: 0x68 */
39758        uint32_t NORCR3;                            /**< NOR control register 3, offset: 0x6C */
39759   __IO uint32_t SRAMCR0;                           /**< SRAM control register 0, offset: 0x70 */
39760   __IO uint32_t SRAMCR1;                           /**< SRAM control register 1, offset: 0x74 */
39761   __IO uint32_t SRAMCR2;                           /**< SRAM control register 2, offset: 0x78 */
39762        uint32_t SRAMCR3;                           /**< SRAM control register 3, offset: 0x7C */
39763   __IO uint32_t DBICR0;                            /**< DBI-B control register 0, offset: 0x80 */
39764   __IO uint32_t DBICR1;                            /**< DBI-B control register 1, offset: 0x84 */
39765        uint8_t RESERVED_1[8];
39766   __IO uint32_t IPCR0;                             /**< IP Command control register 0, offset: 0x90 */
39767   __IO uint32_t IPCR1;                             /**< IP Command control register 1, offset: 0x94 */
39768   __IO uint32_t IPCR2;                             /**< IP Command control register 2, offset: 0x98 */
39769   __IO uint32_t IPCMD;                             /**< IP Command register, offset: 0x9C */
39770   __IO uint32_t IPTXDAT;                           /**< TX DATA register (for IP Command), offset: 0xA0 */
39771        uint8_t RESERVED_2[12];
39772   __I  uint32_t IPRXDAT;                           /**< RX DATA register (for IP Command), offset: 0xB0 */
39773        uint8_t RESERVED_3[12];
39774   __I  uint32_t STS0;                              /**< Status register 0, offset: 0xC0 */
39775        uint32_t STS1;                              /**< Status register 1, offset: 0xC4 */
39776   __I  uint32_t STS2;                              /**< Status register 2, offset: 0xC8 */
39777        uint32_t STS3;                              /**< Status register 3, offset: 0xCC */
39778        uint32_t STS4;                              /**< Status register 4, offset: 0xD0 */
39779        uint32_t STS5;                              /**< Status register 5, offset: 0xD4 */
39780        uint32_t STS6;                              /**< Status register 6, offset: 0xD8 */
39781        uint32_t STS7;                              /**< Status register 7, offset: 0xDC */
39782        uint32_t STS8;                              /**< Status register 8, offset: 0xE0 */
39783        uint32_t STS9;                              /**< Status register 9, offset: 0xE4 */
39784        uint32_t STS10;                             /**< Status register 10, offset: 0xE8 */
39785        uint32_t STS11;                             /**< Status register 11, offset: 0xEC */
39786   __I  uint32_t STS12;                             /**< Status register 12, offset: 0xF0 */
39787        uint32_t STS13;                             /**< Status register 13, offset: 0xF4 */
39788        uint32_t STS14;                             /**< Status register 14, offset: 0xF8 */
39789        uint32_t STS15;                             /**< Status register 15, offset: 0xFC */
39790 } SEMC_Type;
39791 
39792 /* ----------------------------------------------------------------------------
39793    -- SEMC Register Masks
39794    ---------------------------------------------------------------------------- */
39795 
39796 /*!
39797  * @addtogroup SEMC_Register_Masks SEMC Register Masks
39798  * @{
39799  */
39800 
39801 /*! @name MCR - Module Control Register */
39802 /*! @{ */
39803 
39804 #define SEMC_MCR_SWRST_MASK                      (0x1U)
39805 #define SEMC_MCR_SWRST_SHIFT                     (0U)
39806 /*! SWRST - Software Reset
39807  */
39808 #define SEMC_MCR_SWRST(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
39809 
39810 #define SEMC_MCR_MDIS_MASK                       (0x2U)
39811 #define SEMC_MCR_MDIS_SHIFT                      (1U)
39812 /*! MDIS - Module Disable
39813  *  0b0..Module enabled
39814  *  0b1..Module disabled
39815  */
39816 #define SEMC_MCR_MDIS(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
39817 
39818 #define SEMC_MCR_DQSMD_MASK                      (0x4U)
39819 #define SEMC_MCR_DQSMD_SHIFT                     (2U)
39820 /*! DQSMD - DQS (read strobe) mode
39821  *  0b0..Dummy read strobe loopbacked internally
39822  *  0b1..Dummy read strobe loopbacked from DQS pad
39823  */
39824 #define SEMC_MCR_DQSMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
39825 
39826 #define SEMC_MCR_WPOL0_MASK                      (0x40U)
39827 #define SEMC_MCR_WPOL0_SHIFT                     (6U)
39828 /*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM
39829  *  0b0..Active low
39830  *  0b1..Active high
39831  */
39832 #define SEMC_MCR_WPOL0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
39833 
39834 #define SEMC_MCR_WPOL1_MASK                      (0x80U)
39835 #define SEMC_MCR_WPOL1_SHIFT                     (7U)
39836 /*! WPOL1 - WAIT/RDY# polarity for NAND
39837  *  0b0..Active low
39838  *  0b1..Active high
39839  */
39840 #define SEMC_MCR_WPOL1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
39841 
39842 #define SEMC_MCR_CTO_MASK                        (0xFF0000U)
39843 #define SEMC_MCR_CTO_SHIFT                       (16U)
39844 /*! CTO - Command Execution timeout cycles
39845  */
39846 #define SEMC_MCR_CTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
39847 
39848 #define SEMC_MCR_BTO_MASK                        (0x1F000000U)
39849 #define SEMC_MCR_BTO_SHIFT                       (24U)
39850 /*! BTO - Bus timeout cycles
39851  *  0b00000..255*1
39852  *  0b00001-0b11110..255*2 - 255*2^30
39853  *  0b11111..255*2^31
39854  */
39855 #define SEMC_MCR_BTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
39856 /*! @} */
39857 
39858 /*! @name IOCR - IO Mux Control Register */
39859 /*! @{ */
39860 
39861 #define SEMC_IOCR_MUX_A8_MASK                    (0x7U)
39862 #define SEMC_IOCR_MUX_A8_SHIFT                   (0U)
39863 /*! MUX_A8 - SEMC_A8 output selection
39864  *  0b000..SDRAM Address bit (A8)
39865  *  0b001..NAND CE#
39866  *  0b010..NOR CE#
39867  *  0b011..PSRAM CE#
39868  *  0b100..DBI CSX
39869  *  0b101..SDRAM Address bit (A8)
39870  *  0b110..SDRAM Address bit (A8)
39871  *  0b111..SDRAM Address bit (A8)
39872  */
39873 #define SEMC_IOCR_MUX_A8(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
39874 
39875 #define SEMC_IOCR_MUX_CSX0_MASK                  (0x38U)
39876 #define SEMC_IOCR_MUX_CSX0_SHIFT                 (3U)
39877 /*! MUX_CSX0 - SEMC_CSX0 output selection
39878  *  0b000..NOR/PSRAM Address bit 24 (A24)
39879  *  0b001..SDRAM CS1
39880  *  0b010..SDRAM CS2
39881  *  0b011..SDRAM CS3
39882  *  0b100..NAND CE#
39883  *  0b101..NOR CE#
39884  *  0b110..PSRAM CE#
39885  *  0b111..DBI CSX
39886  */
39887 #define SEMC_IOCR_MUX_CSX0(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
39888 
39889 #define SEMC_IOCR_MUX_CSX1_MASK                  (0x1C0U)
39890 #define SEMC_IOCR_MUX_CSX1_SHIFT                 (6U)
39891 /*! MUX_CSX1 - SEMC_CSX1 output selection
39892  *  0b000..NOR/PSRAM Address bit 25 (A25)
39893  *  0b001..SDRAM CS1
39894  *  0b010..SDRAM CS2
39895  *  0b011..SDRAM CS3
39896  *  0b100..NAND CE#
39897  *  0b101..NOR CE#
39898  *  0b110..PSRAM CE#
39899  *  0b111..DBI CSX
39900  */
39901 #define SEMC_IOCR_MUX_CSX1(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
39902 
39903 #define SEMC_IOCR_MUX_CSX2_MASK                  (0xE00U)
39904 #define SEMC_IOCR_MUX_CSX2_SHIFT                 (9U)
39905 /*! MUX_CSX2 - SEMC_CSX2 output selection
39906  *  0b000..NOR/PSRAM Address bit 26 (A26)
39907  *  0b001..SDRAM CS1
39908  *  0b010..SDRAM CS2
39909  *  0b011..SDRAM CS3
39910  *  0b100..NAND CE#
39911  *  0b101..NOR CE#
39912  *  0b110..PSRAM CE#
39913  *  0b111..DBI CSX
39914  */
39915 #define SEMC_IOCR_MUX_CSX2(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
39916 
39917 #define SEMC_IOCR_MUX_CSX3_MASK                  (0x7000U)
39918 #define SEMC_IOCR_MUX_CSX3_SHIFT                 (12U)
39919 /*! MUX_CSX3 - SEMC_CSX3 output selection
39920  *  0b000..NOR/PSRAM Address bit 27 (A27)
39921  *  0b001..SDRAM CS1
39922  *  0b010..SDRAM CS2
39923  *  0b011..SDRAM CS3
39924  *  0b100..NAND CE#
39925  *  0b101..NOR CE#
39926  *  0b110..PSRAM CE#
39927  *  0b111..DBI CSX
39928  */
39929 #define SEMC_IOCR_MUX_CSX3(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
39930 
39931 #define SEMC_IOCR_MUX_RDY_MASK                   (0x38000U)
39932 #define SEMC_IOCR_MUX_RDY_SHIFT                  (15U)
39933 /*! MUX_RDY - SEMC_RDY function selection
39934  *  0b000..NAND Ready/Wait# input
39935  *  0b001..SDRAM CS1
39936  *  0b010..SDRAM CS2
39937  *  0b011..SDRAM CS3
39938  *  0b100..NOR CE#
39939  *  0b101..PSRAM CE#
39940  *  0b110..DBI CSX
39941  *  0b111..NOR/PSRAM Address bit 27
39942  */
39943 #define SEMC_IOCR_MUX_RDY(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
39944 /*! @} */
39945 
39946 /*! @name BMCR0 - Bus (AXI) Master Control Register 0 */
39947 /*! @{ */
39948 
39949 #define SEMC_BMCR0_WQOS_MASK                     (0xFU)
39950 #define SEMC_BMCR0_WQOS_SHIFT                    (0U)
39951 /*! WQOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a
39952  *    priority indicator for the associated write or read transaction. A higher value indicates a higher
39953  *    priority transaction. AxQOS is multiplied by WQOS to get weight score.
39954  */
39955 #define SEMC_BMCR0_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
39956 
39957 #define SEMC_BMCR0_WAGE_MASK                     (0xF0U)
39958 #define SEMC_BMCR0_WAGE_SHIFT                    (4U)
39959 /*! WAGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait
39960  *    period. It is multiplied by WAGE to get weight score.
39961  */
39962 #define SEMC_BMCR0_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
39963 
39964 #define SEMC_BMCR0_WSH_MASK                      (0xFF00U)
39965 #define SEMC_BMCR0_WSH_SHIFT                     (8U)
39966 /*! WSH - Weight of Slave Hit without read/write switch. This weight score is valid when queue
39967  *    command's slave is same as current executing command without read/write operation switch.
39968  */
39969 #define SEMC_BMCR0_WSH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
39970 
39971 #define SEMC_BMCR0_WRWS_MASK                     (0xFF0000U)
39972 #define SEMC_BMCR0_WRWS_SHIFT                    (16U)
39973 /*! WRWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue
39974  *    command's slave is same as current executing command with read/write operation switch.
39975  */
39976 #define SEMC_BMCR0_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
39977 /*! @} */
39978 
39979 /*! @name BMCR1 - Bus (AXI) Master Control Register 1 */
39980 /*! @{ */
39981 
39982 #define SEMC_BMCR1_WQOS_MASK                     (0xFU)
39983 #define SEMC_BMCR1_WQOS_SHIFT                    (0U)
39984 /*! WQOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a
39985  *    priority indicator for the associated write or read transaction. A higher value indicates a higher
39986  *    priority transaction. AxQOS is multiplied by WQOS to get weight score.
39987  */
39988 #define SEMC_BMCR1_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
39989 
39990 #define SEMC_BMCR1_WAGE_MASK                     (0xF0U)
39991 #define SEMC_BMCR1_WAGE_SHIFT                    (4U)
39992 /*! WAGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait
39993  *    period. It is multiplied by WAGE to get weight score.
39994  */
39995 #define SEMC_BMCR1_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
39996 
39997 #define SEMC_BMCR1_WPH_MASK                      (0xFF00U)
39998 #define SEMC_BMCR1_WPH_SHIFT                     (8U)
39999 /*! WPH - Weight of Page Hit. This weight score is valid when queue command's page hits current executing command.
40000  */
40001 #define SEMC_BMCR1_WPH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
40002 
40003 #define SEMC_BMCR1_WRWS_MASK                     (0xFF0000U)
40004 #define SEMC_BMCR1_WRWS_SHIFT                    (16U)
40005 /*! WRWS - Weight of slave hit without Read/Write Switch. This weight score is valid when queue
40006  *    command's read/write operation is same as current executing command.
40007  */
40008 #define SEMC_BMCR1_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
40009 
40010 #define SEMC_BMCR1_WBR_MASK                      (0xFF000000U)
40011 #define SEMC_BMCR1_WBR_SHIFT                     (24U)
40012 /*! WBR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current executing command.
40013  */
40014 #define SEMC_BMCR1_WBR(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
40015 /*! @} */
40016 
40017 /*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */
40018 /*! @{ */
40019 
40020 #define SEMC_BR_VLD_MASK                         (0x1U)
40021 #define SEMC_BR_VLD_SHIFT                        (0U)
40022 /*! VLD - Valid
40023  */
40024 #define SEMC_BR_VLD(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
40025 
40026 #define SEMC_BR_MS_MASK                          (0x3EU)
40027 #define SEMC_BR_MS_SHIFT                         (1U)
40028 /*! MS - Memory size
40029  *  0b00000..4KB
40030  *  0b00001..8KB
40031  *  0b00010..16KB
40032  *  0b00011..32KB
40033  *  0b00100..64KB
40034  *  0b00101..128KB
40035  *  0b00110..256KB
40036  *  0b00111..512KB
40037  *  0b01000..1MB
40038  *  0b01001..2MB
40039  *  0b01010..4MB
40040  *  0b01011..8MB
40041  *  0b01100..16MB
40042  *  0b01101..32MB
40043  *  0b01110..64MB
40044  *  0b01111..128MB
40045  *  0b10000..256MB
40046  *  0b10001..512MB
40047  *  0b10010..1GB
40048  *  0b10011..2GB
40049  *  0b10100-0b11111..4GB
40050  */
40051 #define SEMC_BR_MS(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
40052 
40053 #define SEMC_BR_BA_MASK                          (0xFFFFF000U)
40054 #define SEMC_BR_BA_SHIFT                         (12U)
40055 /*! BA - Base Address
40056  */
40057 #define SEMC_BR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
40058 /*! @} */
40059 
40060 /* The count of SEMC_BR */
40061 #define SEMC_BR_COUNT                            (9U)
40062 
40063 /*! @name INTEN - Interrupt Enable Register */
40064 /*! @{ */
40065 
40066 #define SEMC_INTEN_IPCMDDONEEN_MASK              (0x1U)
40067 #define SEMC_INTEN_IPCMDDONEEN_SHIFT             (0U)
40068 /*! IPCMDDONEEN - IP command done interrupt enable
40069  *  0b0..Interrupt is disabled
40070  *  0b1..Interrupt is enabled
40071  */
40072 #define SEMC_INTEN_IPCMDDONEEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
40073 
40074 #define SEMC_INTEN_IPCMDERREN_MASK               (0x2U)
40075 #define SEMC_INTEN_IPCMDERREN_SHIFT              (1U)
40076 /*! IPCMDERREN - IP command error interrupt enable
40077  *  0b0..Interrupt is disabled
40078  *  0b1..Interrupt is enabled
40079  */
40080 #define SEMC_INTEN_IPCMDERREN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
40081 
40082 #define SEMC_INTEN_AXICMDERREN_MASK              (0x4U)
40083 #define SEMC_INTEN_AXICMDERREN_SHIFT             (2U)
40084 /*! AXICMDERREN - AXI command error interrupt enable
40085  *  0b0..Interrupt is disabled
40086  *  0b1..Interrupt is enabled
40087  */
40088 #define SEMC_INTEN_AXICMDERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
40089 
40090 #define SEMC_INTEN_AXIBUSERREN_MASK              (0x8U)
40091 #define SEMC_INTEN_AXIBUSERREN_SHIFT             (3U)
40092 /*! AXIBUSERREN - AXI bus error interrupt enable
40093  *  0b0..Interrupt is disabled
40094  *  0b1..Interrupt is enabled
40095  */
40096 #define SEMC_INTEN_AXIBUSERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
40097 
40098 #define SEMC_INTEN_NDPAGEENDEN_MASK              (0x10U)
40099 #define SEMC_INTEN_NDPAGEENDEN_SHIFT             (4U)
40100 /*! NDPAGEENDEN - NAND page end interrupt enable
40101  *  0b0..Interrupt is disabled
40102  *  0b1..Interrupt is enabled
40103  */
40104 #define SEMC_INTEN_NDPAGEENDEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
40105 
40106 #define SEMC_INTEN_NDNOPENDEN_MASK               (0x20U)
40107 #define SEMC_INTEN_NDNOPENDEN_SHIFT              (5U)
40108 /*! NDNOPENDEN - NAND no pending AXI access interrupt enable
40109  *  0b0..Interrupt is disabled
40110  *  0b1..Interrupt is enabled
40111  */
40112 #define SEMC_INTEN_NDNOPENDEN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
40113 /*! @} */
40114 
40115 /*! @name INTR - Interrupt Enable Register */
40116 /*! @{ */
40117 
40118 #define SEMC_INTR_IPCMDDONE_MASK                 (0x1U)
40119 #define SEMC_INTR_IPCMDDONE_SHIFT                (0U)
40120 /*! IPCMDDONE - IP command normal done interrupt
40121  */
40122 #define SEMC_INTR_IPCMDDONE(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
40123 
40124 #define SEMC_INTR_IPCMDERR_MASK                  (0x2U)
40125 #define SEMC_INTR_IPCMDERR_SHIFT                 (1U)
40126 /*! IPCMDERR - IP command error done interrupt
40127  */
40128 #define SEMC_INTR_IPCMDERR(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
40129 
40130 #define SEMC_INTR_AXICMDERR_MASK                 (0x4U)
40131 #define SEMC_INTR_AXICMDERR_SHIFT                (2U)
40132 /*! AXICMDERR - AXI command error interrupt
40133  */
40134 #define SEMC_INTR_AXICMDERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
40135 
40136 #define SEMC_INTR_AXIBUSERR_MASK                 (0x8U)
40137 #define SEMC_INTR_AXIBUSERR_SHIFT                (3U)
40138 /*! AXIBUSERR - AXI bus error interrupt
40139  */
40140 #define SEMC_INTR_AXIBUSERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
40141 
40142 #define SEMC_INTR_NDPAGEEND_MASK                 (0x10U)
40143 #define SEMC_INTR_NDPAGEEND_SHIFT                (4U)
40144 /*! NDPAGEEND - NAND page end interrupt
40145  */
40146 #define SEMC_INTR_NDPAGEEND(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
40147 
40148 #define SEMC_INTR_NDNOPEND_MASK                  (0x20U)
40149 #define SEMC_INTR_NDNOPEND_SHIFT                 (5U)
40150 /*! NDNOPEND - NAND no pending AXI access interrupt
40151  */
40152 #define SEMC_INTR_NDNOPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
40153 /*! @} */
40154 
40155 /*! @name SDRAMCR0 - SDRAM control register 0 */
40156 /*! @{ */
40157 
40158 #define SEMC_SDRAMCR0_PS_MASK                    (0x1U)
40159 #define SEMC_SDRAMCR0_PS_SHIFT                   (0U)
40160 /*! PS - Port Size
40161  *  0b0..8bit
40162  *  0b1..16bit
40163  */
40164 #define SEMC_SDRAMCR0_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
40165 
40166 #define SEMC_SDRAMCR0_BL_MASK                    (0x70U)
40167 #define SEMC_SDRAMCR0_BL_SHIFT                   (4U)
40168 /*! BL - Burst Length
40169  *  0b000..1
40170  *  0b001..2
40171  *  0b010..4
40172  *  0b011..8
40173  *  0b100..8
40174  *  0b101..8
40175  *  0b110..8
40176  *  0b111..8
40177  */
40178 #define SEMC_SDRAMCR0_BL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
40179 
40180 #define SEMC_SDRAMCR0_COL_MASK                   (0x300U)
40181 #define SEMC_SDRAMCR0_COL_SHIFT                  (8U)
40182 /*! COL - Column address bit number
40183  *  0b00..12 bit
40184  *  0b01..11 bit
40185  *  0b10..10 bit
40186  *  0b11..9 bit
40187  */
40188 #define SEMC_SDRAMCR0_COL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
40189 
40190 #define SEMC_SDRAMCR0_CL_MASK                    (0xC00U)
40191 #define SEMC_SDRAMCR0_CL_SHIFT                   (10U)
40192 /*! CL - CAS Latency
40193  *  0b00..1
40194  *  0b01..1
40195  *  0b10..2
40196  *  0b11..3
40197  */
40198 #define SEMC_SDRAMCR0_CL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
40199 /*! @} */
40200 
40201 /*! @name SDRAMCR1 - SDRAM control register 1 */
40202 /*! @{ */
40203 
40204 #define SEMC_SDRAMCR1_PRE2ACT_MASK               (0xFU)
40205 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT              (0U)
40206 /*! PRE2ACT - PRECHARGE to ACT/Refresh wait time
40207  */
40208 #define SEMC_SDRAMCR1_PRE2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
40209 
40210 #define SEMC_SDRAMCR1_ACT2RW_MASK                (0xF0U)
40211 #define SEMC_SDRAMCR1_ACT2RW_SHIFT               (4U)
40212 /*! ACT2RW - ACT to Read/Write wait time
40213  */
40214 #define SEMC_SDRAMCR1_ACT2RW(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
40215 
40216 #define SEMC_SDRAMCR1_RFRC_MASK                  (0x1F00U)
40217 #define SEMC_SDRAMCR1_RFRC_SHIFT                 (8U)
40218 /*! RFRC - Refresh recovery time
40219  */
40220 #define SEMC_SDRAMCR1_RFRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
40221 
40222 #define SEMC_SDRAMCR1_WRC_MASK                   (0xE000U)
40223 #define SEMC_SDRAMCR1_WRC_SHIFT                  (13U)
40224 /*! WRC - Write recovery time
40225  */
40226 #define SEMC_SDRAMCR1_WRC(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
40227 
40228 #define SEMC_SDRAMCR1_CKEOFF_MASK                (0xF0000U)
40229 #define SEMC_SDRAMCR1_CKEOFF_SHIFT               (16U)
40230 /*! CKEOFF - CKE OFF minimum time
40231  */
40232 #define SEMC_SDRAMCR1_CKEOFF(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
40233 
40234 #define SEMC_SDRAMCR1_ACT2PRE_MASK               (0xF00000U)
40235 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT              (20U)
40236 /*! ACT2PRE - ACT to Precharge minimum time
40237  */
40238 #define SEMC_SDRAMCR1_ACT2PRE(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
40239 /*! @} */
40240 
40241 /*! @name SDRAMCR2 - SDRAM control register 2 */
40242 /*! @{ */
40243 
40244 #define SEMC_SDRAMCR2_SRRC_MASK                  (0xFFU)
40245 #define SEMC_SDRAMCR2_SRRC_SHIFT                 (0U)
40246 /*! SRRC - Self Refresh Recovery time
40247  */
40248 #define SEMC_SDRAMCR2_SRRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
40249 
40250 #define SEMC_SDRAMCR2_REF2REF_MASK               (0xFF00U)
40251 #define SEMC_SDRAMCR2_REF2REF_SHIFT              (8U)
40252 /*! REF2REF - Refresh to Refresh wait time
40253  */
40254 #define SEMC_SDRAMCR2_REF2REF(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
40255 
40256 #define SEMC_SDRAMCR2_ACT2ACT_MASK               (0xFF0000U)
40257 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT              (16U)
40258 /*! ACT2ACT - ACT to ACT wait time
40259  */
40260 #define SEMC_SDRAMCR2_ACT2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
40261 
40262 #define SEMC_SDRAMCR2_ITO_MASK                   (0xFF000000U)
40263 #define SEMC_SDRAMCR2_ITO_SHIFT                  (24U)
40264 /*! ITO - SDRAM Idle timeout
40265  *  0b00000000..IDLE timeout period is 256*Prescale period.
40266  *  0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
40267  */
40268 #define SEMC_SDRAMCR2_ITO(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
40269 /*! @} */
40270 
40271 /*! @name SDRAMCR3 - SDRAM control register 3 */
40272 /*! @{ */
40273 
40274 #define SEMC_SDRAMCR3_REN_MASK                   (0x1U)
40275 #define SEMC_SDRAMCR3_REN_SHIFT                  (0U)
40276 /*! REN - Refresh enable
40277  */
40278 #define SEMC_SDRAMCR3_REN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
40279 
40280 #define SEMC_SDRAMCR3_REBL_MASK                  (0xEU)
40281 #define SEMC_SDRAMCR3_REBL_SHIFT                 (1U)
40282 /*! REBL - Refresh burst length
40283  *  0b000..1
40284  *  0b001..2
40285  *  0b010..3
40286  *  0b011..4
40287  *  0b100..5
40288  *  0b101..6
40289  *  0b110..7
40290  *  0b111..8
40291  */
40292 #define SEMC_SDRAMCR3_REBL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
40293 
40294 #define SEMC_SDRAMCR3_PRESCALE_MASK              (0xFF00U)
40295 #define SEMC_SDRAMCR3_PRESCALE_SHIFT             (8U)
40296 /*! PRESCALE - Prescaler timer period
40297  *  0b00000000..256*16 clock cycles
40298  *  0b00000001-0b11111111..PRESCALE*16 clock cycles
40299  */
40300 #define SEMC_SDRAMCR3_PRESCALE(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
40301 
40302 #define SEMC_SDRAMCR3_RT_MASK                    (0xFF0000U)
40303 #define SEMC_SDRAMCR3_RT_SHIFT                   (16U)
40304 /*! RT - Refresh timer period
40305  *  0b00000000..256*Prescaler period
40306  *  0b00000001-0b11111111..RT*Prescaler period
40307  */
40308 #define SEMC_SDRAMCR3_RT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
40309 
40310 #define SEMC_SDRAMCR3_UT_MASK                    (0xFF000000U)
40311 #define SEMC_SDRAMCR3_UT_SHIFT                   (24U)
40312 /*! UT - Refresh urgent threshold
40313  *  0b00000000..256*Prescaler period
40314  *  0b00000001-0b11111111..UT*Prescaler period
40315  */
40316 #define SEMC_SDRAMCR3_UT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
40317 /*! @} */
40318 
40319 /*! @name NANDCR0 - NAND control register 0 */
40320 /*! @{ */
40321 
40322 #define SEMC_NANDCR0_PS_MASK                     (0x1U)
40323 #define SEMC_NANDCR0_PS_SHIFT                    (0U)
40324 /*! PS - Port Size
40325  *  0b0..8bit
40326  *  0b1..16bit
40327  */
40328 #define SEMC_NANDCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
40329 
40330 #define SEMC_NANDCR0_BL_MASK                     (0x70U)
40331 #define SEMC_NANDCR0_BL_SHIFT                    (4U)
40332 /*! BL - Burst Length
40333  *  0b000..1
40334  *  0b001..2
40335  *  0b010..4
40336  *  0b011..8
40337  *  0b100..16
40338  *  0b101..32
40339  *  0b110..64
40340  *  0b111..64
40341  */
40342 #define SEMC_NANDCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
40343 
40344 #define SEMC_NANDCR0_EDO_MASK                    (0x80U)
40345 #define SEMC_NANDCR0_EDO_SHIFT                   (7U)
40346 /*! EDO - EDO mode enabled
40347  *  0b0..EDO mode disabled
40348  *  0b1..EDO mode enabled
40349  */
40350 #define SEMC_NANDCR0_EDO(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
40351 
40352 #define SEMC_NANDCR0_COL_MASK                    (0x700U)
40353 #define SEMC_NANDCR0_COL_SHIFT                   (8U)
40354 /*! COL - Column address bit number
40355  *  0b000..16
40356  *  0b001..15
40357  *  0b010..14
40358  *  0b011..13
40359  *  0b100..12
40360  *  0b101..11
40361  *  0b110..10
40362  *  0b111..9
40363  */
40364 #define SEMC_NANDCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
40365 /*! @} */
40366 
40367 /*! @name NANDCR1 - NAND control register 1 */
40368 /*! @{ */
40369 
40370 #define SEMC_NANDCR1_CES_MASK                    (0xFU)
40371 #define SEMC_NANDCR1_CES_SHIFT                   (0U)
40372 /*! CES - CE setup time
40373  */
40374 #define SEMC_NANDCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
40375 
40376 #define SEMC_NANDCR1_CEH_MASK                    (0xF0U)
40377 #define SEMC_NANDCR1_CEH_SHIFT                   (4U)
40378 /*! CEH - CE hold time
40379  */
40380 #define SEMC_NANDCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
40381 
40382 #define SEMC_NANDCR1_WEL_MASK                    (0xF00U)
40383 #define SEMC_NANDCR1_WEL_SHIFT                   (8U)
40384 /*! WEL - WE# low time
40385  */
40386 #define SEMC_NANDCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
40387 
40388 #define SEMC_NANDCR1_WEH_MASK                    (0xF000U)
40389 #define SEMC_NANDCR1_WEH_SHIFT                   (12U)
40390 /*! WEH - WE# high time
40391  */
40392 #define SEMC_NANDCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
40393 
40394 #define SEMC_NANDCR1_REL_MASK                    (0xF0000U)
40395 #define SEMC_NANDCR1_REL_SHIFT                   (16U)
40396 /*! REL - RE# low time
40397  */
40398 #define SEMC_NANDCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
40399 
40400 #define SEMC_NANDCR1_REH_MASK                    (0xF00000U)
40401 #define SEMC_NANDCR1_REH_SHIFT                   (20U)
40402 /*! REH - RE# high time
40403  */
40404 #define SEMC_NANDCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
40405 
40406 #define SEMC_NANDCR1_TA_MASK                     (0xF000000U)
40407 #define SEMC_NANDCR1_TA_SHIFT                    (24U)
40408 /*! TA - Turnaround time
40409  */
40410 #define SEMC_NANDCR1_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
40411 
40412 #define SEMC_NANDCR1_CEITV_MASK                  (0xF0000000U)
40413 #define SEMC_NANDCR1_CEITV_SHIFT                 (28U)
40414 /*! CEITV - CE# interval time
40415  */
40416 #define SEMC_NANDCR1_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
40417 /*! @} */
40418 
40419 /*! @name NANDCR2 - NAND control register 2 */
40420 /*! @{ */
40421 
40422 #define SEMC_NANDCR2_TWHR_MASK                   (0x3FU)
40423 #define SEMC_NANDCR2_TWHR_SHIFT                  (0U)
40424 /*! TWHR - WE# high to RE# low wait time
40425  */
40426 #define SEMC_NANDCR2_TWHR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
40427 
40428 #define SEMC_NANDCR2_TRHW_MASK                   (0xFC0U)
40429 #define SEMC_NANDCR2_TRHW_SHIFT                  (6U)
40430 /*! TRHW - RE# high to WE# low wait time
40431  */
40432 #define SEMC_NANDCR2_TRHW(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
40433 
40434 #define SEMC_NANDCR2_TADL_MASK                   (0x3F000U)
40435 #define SEMC_NANDCR2_TADL_SHIFT                  (12U)
40436 /*! TADL - ALE to write data start wait time
40437  */
40438 #define SEMC_NANDCR2_TADL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
40439 
40440 #define SEMC_NANDCR2_TRR_MASK                    (0xFC0000U)
40441 #define SEMC_NANDCR2_TRR_SHIFT                   (18U)
40442 /*! TRR - Ready to RE# low wait time
40443  */
40444 #define SEMC_NANDCR2_TRR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
40445 
40446 #define SEMC_NANDCR2_TWB_MASK                    (0x3F000000U)
40447 #define SEMC_NANDCR2_TWB_SHIFT                   (24U)
40448 /*! TWB - WE# high to busy wait time
40449  */
40450 #define SEMC_NANDCR2_TWB(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
40451 /*! @} */
40452 
40453 /*! @name NANDCR3 - NAND control register 3 */
40454 /*! @{ */
40455 
40456 #define SEMC_NANDCR3_NDOPT1_MASK                 (0x1U)
40457 #define SEMC_NANDCR3_NDOPT1_SHIFT                (0U)
40458 /*! NDOPT1 - NAND option bit 1
40459  */
40460 #define SEMC_NANDCR3_NDOPT1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
40461 
40462 #define SEMC_NANDCR3_NDOPT2_MASK                 (0x2U)
40463 #define SEMC_NANDCR3_NDOPT2_SHIFT                (1U)
40464 /*! NDOPT2 - NAND option bit 2
40465  */
40466 #define SEMC_NANDCR3_NDOPT2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
40467 
40468 #define SEMC_NANDCR3_NDOPT3_MASK                 (0x4U)
40469 #define SEMC_NANDCR3_NDOPT3_SHIFT                (2U)
40470 /*! NDOPT3 - NAND option bit 3
40471  */
40472 #define SEMC_NANDCR3_NDOPT3(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
40473 /*! @} */
40474 
40475 /*! @name NORCR0 - NOR control register 0 */
40476 /*! @{ */
40477 
40478 #define SEMC_NORCR0_PS_MASK                      (0x1U)
40479 #define SEMC_NORCR0_PS_SHIFT                     (0U)
40480 /*! PS - Port Size
40481  *  0b0..8bit
40482  *  0b1..16bit
40483  */
40484 #define SEMC_NORCR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
40485 
40486 #define SEMC_NORCR0_BL_MASK                      (0x70U)
40487 #define SEMC_NORCR0_BL_SHIFT                     (4U)
40488 /*! BL - Burst Length
40489  *  0b000..1
40490  *  0b001..2
40491  *  0b010..4
40492  *  0b011..8
40493  *  0b100..16
40494  *  0b101..32
40495  *  0b110..64
40496  *  0b111..64
40497  */
40498 #define SEMC_NORCR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
40499 
40500 #define SEMC_NORCR0_AM_MASK                      (0x300U)
40501 #define SEMC_NORCR0_AM_SHIFT                     (8U)
40502 /*! AM - Address Mode
40503  *  0b00..Address/Data MUX mode (ADMUX)
40504  *  0b01..Advanced Address/Data MUX mode (AADM)
40505  *  0b10..Reserved
40506  *  0b11..Reserved
40507  */
40508 #define SEMC_NORCR0_AM(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
40509 
40510 #define SEMC_NORCR0_ADVP_MASK                    (0x400U)
40511 #define SEMC_NORCR0_ADVP_SHIFT                   (10U)
40512 /*! ADVP - ADV# polarity
40513  *  0b0..ADV# is active low.
40514  *  0b1..ADV# is active high.
40515  */
40516 #define SEMC_NORCR0_ADVP(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
40517 
40518 #define SEMC_NORCR0_COL_MASK                     (0xF000U)
40519 #define SEMC_NORCR0_COL_SHIFT                    (12U)
40520 /*! COL - Column Address bit width
40521  *  0b0000..12 Bits
40522  *  0b0001..11 Bits
40523  *  0b0010..10 Bits
40524  *  0b0011..9 Bits
40525  *  0b0100..8 Bits
40526  *  0b0101..7 Bits
40527  *  0b0110..6 Bits
40528  *  0b0111..5 Bits
40529  *  0b1000..4 Bits
40530  *  0b1001..3 Bits
40531  *  0b1010..2 Bits
40532  *  0b1011..12 Bits
40533  *  0b1100..12 Bits
40534  *  0b1101..12 Bits
40535  *  0b1110..12 Bits
40536  *  0b1111..12 Bits
40537  */
40538 #define SEMC_NORCR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
40539 /*! @} */
40540 
40541 /*! @name NORCR1 - NOR control register 1 */
40542 /*! @{ */
40543 
40544 #define SEMC_NORCR1_CES_MASK                     (0xFU)
40545 #define SEMC_NORCR1_CES_SHIFT                    (0U)
40546 /*! CES - CE setup time
40547  */
40548 #define SEMC_NORCR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
40549 
40550 #define SEMC_NORCR1_CEH_MASK                     (0xF0U)
40551 #define SEMC_NORCR1_CEH_SHIFT                    (4U)
40552 /*! CEH - CE hold time
40553  */
40554 #define SEMC_NORCR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
40555 
40556 #define SEMC_NORCR1_AS_MASK                      (0xF00U)
40557 #define SEMC_NORCR1_AS_SHIFT                     (8U)
40558 /*! AS - Address setup time
40559  */
40560 #define SEMC_NORCR1_AS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
40561 
40562 #define SEMC_NORCR1_AH_MASK                      (0xF000U)
40563 #define SEMC_NORCR1_AH_SHIFT                     (12U)
40564 /*! AH - Address hold time
40565  */
40566 #define SEMC_NORCR1_AH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
40567 
40568 #define SEMC_NORCR1_WEL_MASK                     (0xF0000U)
40569 #define SEMC_NORCR1_WEL_SHIFT                    (16U)
40570 /*! WEL - WE low time
40571  */
40572 #define SEMC_NORCR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
40573 
40574 #define SEMC_NORCR1_WEH_MASK                     (0xF00000U)
40575 #define SEMC_NORCR1_WEH_SHIFT                    (20U)
40576 /*! WEH - WE high time
40577  */
40578 #define SEMC_NORCR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
40579 
40580 #define SEMC_NORCR1_REL_MASK                     (0xF000000U)
40581 #define SEMC_NORCR1_REL_SHIFT                    (24U)
40582 /*! REL - RE low time
40583  */
40584 #define SEMC_NORCR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
40585 
40586 #define SEMC_NORCR1_REH_MASK                     (0xF0000000U)
40587 #define SEMC_NORCR1_REH_SHIFT                    (28U)
40588 /*! REH - RE high time
40589  */
40590 #define SEMC_NORCR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
40591 /*! @} */
40592 
40593 /*! @name NORCR2 - NOR control register 2 */
40594 /*! @{ */
40595 
40596 #define SEMC_NORCR2_TA_MASK                      (0xF00U)
40597 #define SEMC_NORCR2_TA_SHIFT                     (8U)
40598 /*! TA - Turnaround time
40599  */
40600 #define SEMC_NORCR2_TA(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
40601 
40602 #define SEMC_NORCR2_AWDH_MASK                    (0xF000U)
40603 #define SEMC_NORCR2_AWDH_SHIFT                   (12U)
40604 /*! AWDH - Address to write data hold time
40605  */
40606 #define SEMC_NORCR2_AWDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
40607 
40608 #define SEMC_NORCR2_CEITV_MASK                   (0xF000000U)
40609 #define SEMC_NORCR2_CEITV_SHIFT                  (24U)
40610 /*! CEITV - CE# interval time
40611  */
40612 #define SEMC_NORCR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
40613 /*! @} */
40614 
40615 /*! @name SRAMCR0 - SRAM control register 0 */
40616 /*! @{ */
40617 
40618 #define SEMC_SRAMCR0_PS_MASK                     (0x1U)
40619 #define SEMC_SRAMCR0_PS_SHIFT                    (0U)
40620 /*! PS - Port Size
40621  *  0b0..8bit
40622  *  0b1..16bit
40623  */
40624 #define SEMC_SRAMCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
40625 
40626 #define SEMC_SRAMCR0_BL_MASK                     (0x70U)
40627 #define SEMC_SRAMCR0_BL_SHIFT                    (4U)
40628 /*! BL - Burst Length
40629  *  0b000..1
40630  *  0b001..2
40631  *  0b010..4
40632  *  0b011..8
40633  *  0b100..16
40634  *  0b101..32
40635  *  0b110..64
40636  *  0b111..64
40637  */
40638 #define SEMC_SRAMCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
40639 
40640 #define SEMC_SRAMCR0_AM_MASK                     (0x300U)
40641 #define SEMC_SRAMCR0_AM_SHIFT                    (8U)
40642 /*! AM - Address Mode
40643  *  0b00..Address/Data MUX mode (ADMUX)
40644  *  0b01..Advanced Address/Data MUX mode (AADM)
40645  *  0b10..Reserved
40646  *  0b11..Reserved
40647  */
40648 #define SEMC_SRAMCR0_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
40649 
40650 #define SEMC_SRAMCR0_ADVP_MASK                   (0x400U)
40651 #define SEMC_SRAMCR0_ADVP_SHIFT                  (10U)
40652 /*! ADVP - ADV# polarity
40653  *  0b0..ADV# is active low.
40654  *  0b1..ADV# is active high.
40655  */
40656 #define SEMC_SRAMCR0_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
40657 
40658 #define SEMC_SRAMCR0_COL_MASK                    (0xF000U)
40659 #define SEMC_SRAMCR0_COL_SHIFT                   (12U)
40660 /*! COL - Column Address bit width
40661  *  0b0000..12 Bits
40662  *  0b0001..11 Bits
40663  *  0b0010..10 Bits
40664  *  0b0011..9 Bits
40665  *  0b0100..8 Bits
40666  *  0b0101..7 Bits
40667  *  0b0110..6 Bits
40668  *  0b0111..5 Bits
40669  *  0b1000..4 Bits
40670  *  0b1001..3 Bits
40671  *  0b1010..2 Bits
40672  *  0b1011..12 Bits
40673  *  0b1100..12 Bits
40674  *  0b1101..12 Bits
40675  *  0b1110..12 Bits
40676  *  0b1111..12 Bits
40677  */
40678 #define SEMC_SRAMCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
40679 /*! @} */
40680 
40681 /*! @name SRAMCR1 - SRAM control register 1 */
40682 /*! @{ */
40683 
40684 #define SEMC_SRAMCR1_CES_MASK                    (0xFU)
40685 #define SEMC_SRAMCR1_CES_SHIFT                   (0U)
40686 /*! CES - CE setup time
40687  */
40688 #define SEMC_SRAMCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
40689 
40690 #define SEMC_SRAMCR1_CEH_MASK                    (0xF0U)
40691 #define SEMC_SRAMCR1_CEH_SHIFT                   (4U)
40692 /*! CEH - CE hold time
40693  */
40694 #define SEMC_SRAMCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
40695 
40696 #define SEMC_SRAMCR1_AS_MASK                     (0xF00U)
40697 #define SEMC_SRAMCR1_AS_SHIFT                    (8U)
40698 /*! AS - Address setup time
40699  */
40700 #define SEMC_SRAMCR1_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
40701 
40702 #define SEMC_SRAMCR1_AH_MASK                     (0xF000U)
40703 #define SEMC_SRAMCR1_AH_SHIFT                    (12U)
40704 /*! AH - Address hold time
40705  */
40706 #define SEMC_SRAMCR1_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
40707 
40708 #define SEMC_SRAMCR1_WEL_MASK                    (0xF0000U)
40709 #define SEMC_SRAMCR1_WEL_SHIFT                   (16U)
40710 /*! WEL - WE low time
40711  */
40712 #define SEMC_SRAMCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
40713 
40714 #define SEMC_SRAMCR1_WEH_MASK                    (0xF00000U)
40715 #define SEMC_SRAMCR1_WEH_SHIFT                   (20U)
40716 /*! WEH - WE high time
40717  */
40718 #define SEMC_SRAMCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
40719 
40720 #define SEMC_SRAMCR1_REL_MASK                    (0xF000000U)
40721 #define SEMC_SRAMCR1_REL_SHIFT                   (24U)
40722 /*! REL - RE low time
40723  */
40724 #define SEMC_SRAMCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
40725 
40726 #define SEMC_SRAMCR1_REH_MASK                    (0xF0000000U)
40727 #define SEMC_SRAMCR1_REH_SHIFT                   (28U)
40728 /*! REH - RE high time
40729  */
40730 #define SEMC_SRAMCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
40731 /*! @} */
40732 
40733 /*! @name SRAMCR2 - SRAM control register 2 */
40734 /*! @{ */
40735 
40736 #define SEMC_SRAMCR2_TA_MASK                     (0xF00U)
40737 #define SEMC_SRAMCR2_TA_SHIFT                    (8U)
40738 /*! TA - Turnaround time
40739  */
40740 #define SEMC_SRAMCR2_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
40741 
40742 #define SEMC_SRAMCR2_AWDH_MASK                   (0xF000U)
40743 #define SEMC_SRAMCR2_AWDH_SHIFT                  (12U)
40744 /*! AWDH - Address to write data hold time
40745  */
40746 #define SEMC_SRAMCR2_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
40747 
40748 #define SEMC_SRAMCR2_CEITV_MASK                  (0xF000000U)
40749 #define SEMC_SRAMCR2_CEITV_SHIFT                 (24U)
40750 /*! CEITV - CE# interval time
40751  */
40752 #define SEMC_SRAMCR2_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
40753 /*! @} */
40754 
40755 /*! @name DBICR0 - DBI-B control register 0 */
40756 /*! @{ */
40757 
40758 #define SEMC_DBICR0_PS_MASK                      (0x1U)
40759 #define SEMC_DBICR0_PS_SHIFT                     (0U)
40760 /*! PS - Port Size
40761  *  0b0..8bit
40762  *  0b1..16bit
40763  */
40764 #define SEMC_DBICR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
40765 
40766 #define SEMC_DBICR0_BL_MASK                      (0x70U)
40767 #define SEMC_DBICR0_BL_SHIFT                     (4U)
40768 /*! BL - Burst Length
40769  *  0b000..1
40770  *  0b001..2
40771  *  0b010..4
40772  *  0b011..8
40773  *  0b100..16
40774  *  0b101..32
40775  *  0b110..64
40776  *  0b111..64
40777  */
40778 #define SEMC_DBICR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
40779 
40780 #define SEMC_DBICR0_COL_MASK                     (0xF000U)
40781 #define SEMC_DBICR0_COL_SHIFT                    (12U)
40782 /*! COL - Column Address bit width
40783  *  0b0000..12 Bits
40784  *  0b0001..11 Bits
40785  *  0b0010..10 Bits
40786  *  0b0011..9 Bits
40787  *  0b0100..8 Bits
40788  *  0b0101..7 Bits
40789  *  0b0110..6 Bits
40790  *  0b0111..5 Bits
40791  *  0b1000..4 Bits
40792  *  0b1001..3 Bits
40793  *  0b1010..2 Bits
40794  *  0b1011..12 Bits
40795  *  0b1100..12 Bits
40796  *  0b1101..12 Bits
40797  *  0b1110..12 Bits
40798  *  0b1111..12 Bits
40799  */
40800 #define SEMC_DBICR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
40801 /*! @} */
40802 
40803 /*! @name DBICR1 - DBI-B control register 1 */
40804 /*! @{ */
40805 
40806 #define SEMC_DBICR1_CES_MASK                     (0xFU)
40807 #define SEMC_DBICR1_CES_SHIFT                    (0U)
40808 /*! CES - CSX Setup Time
40809  */
40810 #define SEMC_DBICR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
40811 
40812 #define SEMC_DBICR1_CEH_MASK                     (0xF0U)
40813 #define SEMC_DBICR1_CEH_SHIFT                    (4U)
40814 /*! CEH - CSX Hold Time
40815  */
40816 #define SEMC_DBICR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
40817 
40818 #define SEMC_DBICR1_WEL_MASK                     (0xF00U)
40819 #define SEMC_DBICR1_WEL_SHIFT                    (8U)
40820 /*! WEL - WRX Low Time
40821  */
40822 #define SEMC_DBICR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
40823 
40824 #define SEMC_DBICR1_WEH_MASK                     (0xF000U)
40825 #define SEMC_DBICR1_WEH_SHIFT                    (12U)
40826 /*! WEH - WRX High Time
40827  */
40828 #define SEMC_DBICR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
40829 
40830 #define SEMC_DBICR1_REL_MASK                     (0xF0000U)
40831 #define SEMC_DBICR1_REL_SHIFT                    (16U)
40832 /*! REL - RDX Low Time bit [3:0]
40833  */
40834 #define SEMC_DBICR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
40835 
40836 #define SEMC_DBICR1_REH_MASK                     (0xF00000U)
40837 #define SEMC_DBICR1_REH_SHIFT                    (20U)
40838 /*! REH - RDX High Time bit [3:0]
40839  */
40840 #define SEMC_DBICR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
40841 
40842 #define SEMC_DBICR1_CEITV_MASK                   (0xF000000U)
40843 #define SEMC_DBICR1_CEITV_SHIFT                  (24U)
40844 /*! CEITV - CSX interval time
40845  */
40846 #define SEMC_DBICR1_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
40847 
40848 #define SEMC_DBICR1_REL2_MASK                    (0x30000000U)
40849 #define SEMC_DBICR1_REL2_SHIFT                   (28U)
40850 /*! REL2 - RDX Low Time bit [5:4]
40851  */
40852 #define SEMC_DBICR1_REL2(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)
40853 
40854 #define SEMC_DBICR1_REH2_MASK                    (0xC0000000U)
40855 #define SEMC_DBICR1_REH2_SHIFT                   (30U)
40856 /*! REH2 - RDX High Time bit [5:4]
40857  */
40858 #define SEMC_DBICR1_REH2(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)
40859 /*! @} */
40860 
40861 /*! @name IPCR0 - IP Command control register 0 */
40862 /*! @{ */
40863 
40864 #define SEMC_IPCR0_SA_MASK                       (0xFFFFFFFFU)
40865 #define SEMC_IPCR0_SA_SHIFT                      (0U)
40866 /*! SA - Slave address
40867  */
40868 #define SEMC_IPCR0_SA(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
40869 /*! @} */
40870 
40871 /*! @name IPCR1 - IP Command control register 1 */
40872 /*! @{ */
40873 
40874 #define SEMC_IPCR1_DATSZ_MASK                    (0x7U)
40875 #define SEMC_IPCR1_DATSZ_SHIFT                   (0U)
40876 /*! DATSZ - Data Size in Byte
40877  *  0b000..4
40878  *  0b001..1
40879  *  0b010..2
40880  *  0b011..3
40881  *  0b100..4
40882  *  0b101..4
40883  *  0b110..4
40884  *  0b111..4
40885  */
40886 #define SEMC_IPCR1_DATSZ(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
40887 /*! @} */
40888 
40889 /*! @name IPCR2 - IP Command control register 2 */
40890 /*! @{ */
40891 
40892 #define SEMC_IPCR2_BM0_MASK                      (0x1U)
40893 #define SEMC_IPCR2_BM0_SHIFT                     (0U)
40894 /*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0)
40895  *  0b0..Byte Unmasked
40896  *  0b1..Byte Masked
40897  */
40898 #define SEMC_IPCR2_BM0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
40899 
40900 #define SEMC_IPCR2_BM1_MASK                      (0x2U)
40901 #define SEMC_IPCR2_BM1_SHIFT                     (1U)
40902 /*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8)
40903  *  0b0..Byte Unmasked
40904  *  0b1..Byte Masked
40905  */
40906 #define SEMC_IPCR2_BM1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
40907 
40908 #define SEMC_IPCR2_BM2_MASK                      (0x4U)
40909 #define SEMC_IPCR2_BM2_SHIFT                     (2U)
40910 /*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16)
40911  *  0b0..Byte Unmasked
40912  *  0b1..Byte Masked
40913  */
40914 #define SEMC_IPCR2_BM2(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
40915 
40916 #define SEMC_IPCR2_BM3_MASK                      (0x8U)
40917 #define SEMC_IPCR2_BM3_SHIFT                     (3U)
40918 /*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24)
40919  *  0b0..Byte Unmasked
40920  *  0b1..Byte Masked
40921  */
40922 #define SEMC_IPCR2_BM3(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
40923 /*! @} */
40924 
40925 /*! @name IPCMD - IP Command register */
40926 /*! @{ */
40927 
40928 #define SEMC_IPCMD_CMD_MASK                      (0xFFFFU)
40929 #define SEMC_IPCMD_CMD_SHIFT                     (0U)
40930 #define SEMC_IPCMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
40931 
40932 #define SEMC_IPCMD_KEY_MASK                      (0xFFFF0000U)
40933 #define SEMC_IPCMD_KEY_SHIFT                     (16U)
40934 /*! KEY - This field should be written with 0xA55A when trigging an IP command.
40935  */
40936 #define SEMC_IPCMD_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
40937 /*! @} */
40938 
40939 /*! @name IPTXDAT - TX DATA register (for IP Command) */
40940 /*! @{ */
40941 
40942 #define SEMC_IPTXDAT_DAT_MASK                    (0xFFFFFFFFU)
40943 #define SEMC_IPTXDAT_DAT_SHIFT                   (0U)
40944 /*! DAT - data
40945  */
40946 #define SEMC_IPTXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
40947 /*! @} */
40948 
40949 /*! @name IPRXDAT - RX DATA register (for IP Command) */
40950 /*! @{ */
40951 
40952 #define SEMC_IPRXDAT_DAT_MASK                    (0xFFFFFFFFU)
40953 #define SEMC_IPRXDAT_DAT_SHIFT                   (0U)
40954 /*! DAT - data
40955  */
40956 #define SEMC_IPRXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
40957 /*! @} */
40958 
40959 /*! @name STS0 - Status register 0 */
40960 /*! @{ */
40961 
40962 #define SEMC_STS0_IDLE_MASK                      (0x1U)
40963 #define SEMC_STS0_IDLE_SHIFT                     (0U)
40964 /*! IDLE - Indicating whether SEMC is in IDLE state.
40965  */
40966 #define SEMC_STS0_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
40967 
40968 #define SEMC_STS0_NARDY_MASK                     (0x2U)
40969 #define SEMC_STS0_NARDY_SHIFT                    (1U)
40970 /*! NARDY - Indicating NAND device Ready/WAIT# pin level.
40971  *  0b0..NAND device is not ready
40972  *  0b1..NAND device is ready
40973  */
40974 #define SEMC_STS0_NARDY(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
40975 /*! @} */
40976 
40977 /*! @name STS2 - Status register 2 */
40978 /*! @{ */
40979 
40980 #define SEMC_STS2_NDWRPEND_MASK                  (0x8U)
40981 #define SEMC_STS2_NDWRPEND_SHIFT                 (3U)
40982 /*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
40983  *  0b0..No pending
40984  *  0b1..Pending
40985  */
40986 #define SEMC_STS2_NDWRPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
40987 /*! @} */
40988 
40989 /*! @name STS12 - Status register 12 */
40990 /*! @{ */
40991 
40992 #define SEMC_STS12_NDADDR_MASK                   (0xFFFFFFFFU)
40993 #define SEMC_STS12_NDADDR_SHIFT                  (0U)
40994 /*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
40995  */
40996 #define SEMC_STS12_NDADDR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
40997 /*! @} */
40998 
40999 
41000 /*!
41001  * @}
41002  */ /* end of group SEMC_Register_Masks */
41003 
41004 
41005 /* SEMC - Peripheral instance base addresses */
41006 /** Peripheral SEMC base address */
41007 #define SEMC_BASE                                (0x402F0000u)
41008 /** Peripheral SEMC base pointer */
41009 #define SEMC                                     ((SEMC_Type *)SEMC_BASE)
41010 /** Array initializer of SEMC peripheral base addresses */
41011 #define SEMC_BASE_ADDRS                          { SEMC_BASE }
41012 /** Array initializer of SEMC peripheral base pointers */
41013 #define SEMC_BASE_PTRS                           { SEMC }
41014 /** Interrupt vectors for the SEMC peripheral type */
41015 #define SEMC_IRQS                                { SEMC_IRQn }
41016 
41017 /*!
41018  * @}
41019  */ /* end of group SEMC_Peripheral_Access_Layer */
41020 
41021 
41022 /* ----------------------------------------------------------------------------
41023    -- SNVS Peripheral Access Layer
41024    ---------------------------------------------------------------------------- */
41025 
41026 /*!
41027  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
41028  * @{
41029  */
41030 
41031 /** SNVS - Register Layout Typedef */
41032 typedef struct {
41033   __IO uint32_t HPLR;                              /**< SNVS_HP Lock Register, offset: 0x0 */
41034   __IO uint32_t HPCOMR;                            /**< SNVS_HP Command Register, offset: 0x4 */
41035   __IO uint32_t HPCR;                              /**< SNVS_HP Control Register, offset: 0x8 */
41036   __IO uint32_t HPSICR;                            /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
41037   __IO uint32_t HPSVCR;                            /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
41038   __IO uint32_t HPSR;                              /**< SNVS_HP Status Register, offset: 0x14 */
41039   __IO uint32_t HPSVSR;                            /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
41040   __IO uint32_t HPHACIVR;                          /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
41041   __I  uint32_t HPHACR;                            /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
41042   __IO uint32_t HPRTCMR;                           /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
41043   __IO uint32_t HPRTCLR;                           /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
41044   __IO uint32_t HPTAMR;                            /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
41045   __IO uint32_t HPTALR;                            /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
41046   __IO uint32_t LPLR;                              /**< SNVS_LP Lock Register, offset: 0x34 */
41047   __IO uint32_t LPCR;                              /**< SNVS_LP Control Register, offset: 0x38 */
41048   __IO uint32_t LPMKCR;                            /**< SNVS_LP Master Key Control Register, offset: 0x3C */
41049   __IO uint32_t LPSVCR;                            /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
41050        uint8_t RESERVED_0[4];
41051   __IO uint32_t LPSECR;                            /**< SNVS_LP Security Events Configuration Register, offset: 0x48 */
41052   __IO uint32_t LPSR;                              /**< SNVS_LP Status Register, offset: 0x4C */
41053   __IO uint32_t LPSRTCMR;                          /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
41054   __IO uint32_t LPSRTCLR;                          /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
41055   __IO uint32_t LPTAR;                             /**< SNVS_LP Time Alarm Register, offset: 0x58 */
41056   __IO uint32_t LPSMCMR;                           /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
41057   __IO uint32_t LPSMCLR;                           /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
41058   __IO uint32_t LPLVDR;                            /**< SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64 */
41059   __IO uint32_t LPGPR0_LEGACY_ALIAS;               /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
41060   __IO uint32_t LPZMKR[8];                         /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
41061        uint8_t RESERVED_1[4];
41062   __IO uint32_t LPGPR_ALIAS[4];                    /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
41063        uint8_t RESERVED_2[96];
41064   __IO uint32_t LPGPR[8];                          /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */
41065        uint8_t RESERVED_3[2776];
41066   __I  uint32_t HPVIDR1;                           /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
41067   __I  uint32_t HPVIDR2;                           /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
41068 } SNVS_Type;
41069 
41070 /* ----------------------------------------------------------------------------
41071    -- SNVS Register Masks
41072    ---------------------------------------------------------------------------- */
41073 
41074 /*!
41075  * @addtogroup SNVS_Register_Masks SNVS Register Masks
41076  * @{
41077  */
41078 
41079 /*! @name HPLR - SNVS_HP Lock Register */
41080 /*! @{ */
41081 
41082 #define SNVS_HPLR_ZMK_WSL_MASK                   (0x1U)
41083 #define SNVS_HPLR_ZMK_WSL_SHIFT                  (0U)
41084 /*! ZMK_WSL
41085  *  0b0..Write access is allowed
41086  *  0b1..Write access is not allowed
41087  */
41088 #define SNVS_HPLR_ZMK_WSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
41089 
41090 #define SNVS_HPLR_ZMK_RSL_MASK                   (0x2U)
41091 #define SNVS_HPLR_ZMK_RSL_SHIFT                  (1U)
41092 /*! ZMK_RSL
41093  *  0b0..Read access is allowed (only in software Programming mode)
41094  *  0b1..Read access is not allowed
41095  */
41096 #define SNVS_HPLR_ZMK_RSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
41097 
41098 #define SNVS_HPLR_SRTC_SL_MASK                   (0x4U)
41099 #define SNVS_HPLR_SRTC_SL_SHIFT                  (2U)
41100 /*! SRTC_SL
41101  *  0b0..Write access is allowed
41102  *  0b1..Write access is not allowed
41103  */
41104 #define SNVS_HPLR_SRTC_SL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
41105 
41106 #define SNVS_HPLR_LPCALB_SL_MASK                 (0x8U)
41107 #define SNVS_HPLR_LPCALB_SL_SHIFT                (3U)
41108 /*! LPCALB_SL
41109  *  0b0..Write access is allowed
41110  *  0b1..Write access is not allowed
41111  */
41112 #define SNVS_HPLR_LPCALB_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
41113 
41114 #define SNVS_HPLR_MC_SL_MASK                     (0x10U)
41115 #define SNVS_HPLR_MC_SL_SHIFT                    (4U)
41116 /*! MC_SL
41117  *  0b0..Write access (increment) is allowed
41118  *  0b1..Write access (increment) is not allowed
41119  */
41120 #define SNVS_HPLR_MC_SL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
41121 
41122 #define SNVS_HPLR_GPR_SL_MASK                    (0x20U)
41123 #define SNVS_HPLR_GPR_SL_SHIFT                   (5U)
41124 /*! GPR_SL
41125  *  0b0..Write access is allowed
41126  *  0b1..Write access is not allowed
41127  */
41128 #define SNVS_HPLR_GPR_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
41129 
41130 #define SNVS_HPLR_LPSVCR_SL_MASK                 (0x40U)
41131 #define SNVS_HPLR_LPSVCR_SL_SHIFT                (6U)
41132 /*! LPSVCR_SL
41133  *  0b0..Write access is allowed
41134  *  0b1..Write access is not allowed
41135  */
41136 #define SNVS_HPLR_LPSVCR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
41137 
41138 #define SNVS_HPLR_LPSECR_SL_MASK                 (0x100U)
41139 #define SNVS_HPLR_LPSECR_SL_SHIFT                (8U)
41140 /*! LPSECR_SL
41141  *  0b0..Write access is allowed
41142  *  0b1..Write access is not allowed
41143  */
41144 #define SNVS_HPLR_LPSECR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
41145 
41146 #define SNVS_HPLR_MKS_SL_MASK                    (0x200U)
41147 #define SNVS_HPLR_MKS_SL_SHIFT                   (9U)
41148 /*! MKS_SL
41149  *  0b0..Write access is allowed
41150  *  0b1..Write access is not allowed
41151  */
41152 #define SNVS_HPLR_MKS_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
41153 
41154 #define SNVS_HPLR_HPSVCR_L_MASK                  (0x10000U)
41155 #define SNVS_HPLR_HPSVCR_L_SHIFT                 (16U)
41156 /*! HPSVCR_L
41157  *  0b0..Write access is allowed
41158  *  0b1..Write access is not allowed
41159  */
41160 #define SNVS_HPLR_HPSVCR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
41161 
41162 #define SNVS_HPLR_HPSICR_L_MASK                  (0x20000U)
41163 #define SNVS_HPLR_HPSICR_L_SHIFT                 (17U)
41164 /*! HPSICR_L
41165  *  0b0..Write access is allowed
41166  *  0b1..Write access is not allowed
41167  */
41168 #define SNVS_HPLR_HPSICR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
41169 
41170 #define SNVS_HPLR_HAC_L_MASK                     (0x40000U)
41171 #define SNVS_HPLR_HAC_L_SHIFT                    (18U)
41172 /*! HAC_L
41173  *  0b0..Write access is allowed
41174  *  0b1..Write access is not allowed
41175  */
41176 #define SNVS_HPLR_HAC_L(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
41177 /*! @} */
41178 
41179 /*! @name HPCOMR - SNVS_HP Command Register */
41180 /*! @{ */
41181 
41182 #define SNVS_HPCOMR_SSM_ST_MASK                  (0x1U)
41183 #define SNVS_HPCOMR_SSM_ST_SHIFT                 (0U)
41184 #define SNVS_HPCOMR_SSM_ST(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
41185 
41186 #define SNVS_HPCOMR_SSM_ST_DIS_MASK              (0x2U)
41187 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT             (1U)
41188 /*! SSM_ST_DIS
41189  *  0b0..Secure to Trusted State transition is enabled
41190  *  0b1..Secure to Trusted State transition is disabled
41191  */
41192 #define SNVS_HPCOMR_SSM_ST_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
41193 
41194 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK            (0x4U)
41195 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT           (2U)
41196 /*! SSM_SFNS_DIS
41197  *  0b0..Soft Fail to Non-Secure State transition is enabled
41198  *  0b1..Soft Fail to Non-Secure State transition is disabled
41199  */
41200 #define SNVS_HPCOMR_SSM_SFNS_DIS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
41201 
41202 #define SNVS_HPCOMR_LP_SWR_MASK                  (0x10U)
41203 #define SNVS_HPCOMR_LP_SWR_SHIFT                 (4U)
41204 /*! LP_SWR
41205  *  0b0..No Action
41206  *  0b1..Reset LP section
41207  */
41208 #define SNVS_HPCOMR_LP_SWR(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
41209 
41210 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              (0x20U)
41211 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             (5U)
41212 /*! LP_SWR_DIS
41213  *  0b0..LP software reset is enabled
41214  *  0b1..LP software reset is disabled
41215  */
41216 #define SNVS_HPCOMR_LP_SWR_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
41217 
41218 #define SNVS_HPCOMR_SW_SV_MASK                   (0x100U)
41219 #define SNVS_HPCOMR_SW_SV_SHIFT                  (8U)
41220 #define SNVS_HPCOMR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
41221 
41222 #define SNVS_HPCOMR_SW_FSV_MASK                  (0x200U)
41223 #define SNVS_HPCOMR_SW_FSV_SHIFT                 (9U)
41224 #define SNVS_HPCOMR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
41225 
41226 #define SNVS_HPCOMR_SW_LPSV_MASK                 (0x400U)
41227 #define SNVS_HPCOMR_SW_LPSV_SHIFT                (10U)
41228 #define SNVS_HPCOMR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
41229 
41230 #define SNVS_HPCOMR_PROG_ZMK_MASK                (0x1000U)
41231 #define SNVS_HPCOMR_PROG_ZMK_SHIFT               (12U)
41232 /*! PROG_ZMK
41233  *  0b0..No Action
41234  *  0b1..Activate hardware key programming mechanism
41235  */
41236 #define SNVS_HPCOMR_PROG_ZMK(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
41237 
41238 #define SNVS_HPCOMR_MKS_EN_MASK                  (0x2000U)
41239 #define SNVS_HPCOMR_MKS_EN_SHIFT                 (13U)
41240 /*! MKS_EN
41241  *  0b0..OTP master key is selected as an SNVS master key
41242  *  0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
41243  */
41244 #define SNVS_HPCOMR_MKS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
41245 
41246 #define SNVS_HPCOMR_HAC_EN_MASK                  (0x10000U)
41247 #define SNVS_HPCOMR_HAC_EN_SHIFT                 (16U)
41248 /*! HAC_EN
41249  *  0b0..High Assurance Counter is disabled
41250  *  0b1..High Assurance Counter is enabled
41251  */
41252 #define SNVS_HPCOMR_HAC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
41253 
41254 #define SNVS_HPCOMR_HAC_LOAD_MASK                (0x20000U)
41255 #define SNVS_HPCOMR_HAC_LOAD_SHIFT               (17U)
41256 /*! HAC_LOAD
41257  *  0b0..No Action
41258  *  0b1..Load the HAC
41259  */
41260 #define SNVS_HPCOMR_HAC_LOAD(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
41261 
41262 #define SNVS_HPCOMR_HAC_CLEAR_MASK               (0x40000U)
41263 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT              (18U)
41264 /*! HAC_CLEAR
41265  *  0b0..No Action
41266  *  0b1..Clear the HAC
41267  */
41268 #define SNVS_HPCOMR_HAC_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
41269 
41270 #define SNVS_HPCOMR_HAC_STOP_MASK                (0x80000U)
41271 #define SNVS_HPCOMR_HAC_STOP_SHIFT               (19U)
41272 #define SNVS_HPCOMR_HAC_STOP(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
41273 
41274 #define SNVS_HPCOMR_NPSWA_EN_MASK                (0x80000000U)
41275 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               (31U)
41276 #define SNVS_HPCOMR_NPSWA_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
41277 /*! @} */
41278 
41279 /*! @name HPCR - SNVS_HP Control Register */
41280 /*! @{ */
41281 
41282 #define SNVS_HPCR_RTC_EN_MASK                    (0x1U)
41283 #define SNVS_HPCR_RTC_EN_SHIFT                   (0U)
41284 /*! RTC_EN
41285  *  0b0..RTC is disabled
41286  *  0b1..RTC is enabled
41287  */
41288 #define SNVS_HPCR_RTC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
41289 
41290 #define SNVS_HPCR_HPTA_EN_MASK                   (0x2U)
41291 #define SNVS_HPCR_HPTA_EN_SHIFT                  (1U)
41292 /*! HPTA_EN
41293  *  0b0..HP Time Alarm Interrupt is disabled
41294  *  0b1..HP Time Alarm Interrupt is enabled
41295  */
41296 #define SNVS_HPCR_HPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
41297 
41298 #define SNVS_HPCR_DIS_PI_MASK                    (0x4U)
41299 #define SNVS_HPCR_DIS_PI_SHIFT                   (2U)
41300 /*! DIS_PI
41301  *  0b0..Periodic interrupt will trigger a functional interrupt
41302  *  0b1..Disable periodic interrupt in the function interrupt
41303  */
41304 #define SNVS_HPCR_DIS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
41305 
41306 #define SNVS_HPCR_PI_EN_MASK                     (0x8U)
41307 #define SNVS_HPCR_PI_EN_SHIFT                    (3U)
41308 /*! PI_EN
41309  *  0b0..HP Periodic Interrupt is disabled
41310  *  0b1..HP Periodic Interrupt is enabled
41311  */
41312 #define SNVS_HPCR_PI_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
41313 
41314 #define SNVS_HPCR_PI_FREQ_MASK                   (0xF0U)
41315 #define SNVS_HPCR_PI_FREQ_SHIFT                  (4U)
41316 /*! PI_FREQ
41317  *  0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
41318  *  0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
41319  *  0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
41320  *  0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
41321  *  0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
41322  *  0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
41323  *  0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
41324  *  0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
41325  *  0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
41326  *  0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
41327  *  0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
41328  *  0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
41329  *  0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
41330  *  0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
41331  *  0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
41332  *  0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
41333  */
41334 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
41335 
41336 #define SNVS_HPCR_HPCALB_EN_MASK                 (0x100U)
41337 #define SNVS_HPCR_HPCALB_EN_SHIFT                (8U)
41338 /*! HPCALB_EN
41339  *  0b0..HP Timer calibration disabled
41340  *  0b1..HP Timer calibration enabled
41341  */
41342 #define SNVS_HPCR_HPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
41343 
41344 #define SNVS_HPCR_HPCALB_VAL_MASK                (0x7C00U)
41345 #define SNVS_HPCR_HPCALB_VAL_SHIFT               (10U)
41346 /*! HPCALB_VAL
41347  *  0b00000..+0 counts per each 32768 ticks of the counter
41348  *  0b00001..+1 counts per each 32768 ticks of the counter
41349  *  0b00010..+2 counts per each 32768 ticks of the counter
41350  *  0b01111..+15 counts per each 32768 ticks of the counter
41351  *  0b10000..-16 counts per each 32768 ticks of the counter
41352  *  0b10001..-15 counts per each 32768 ticks of the counter
41353  *  0b11110..-2 counts per each 32768 ticks of the counter
41354  *  0b11111..-1 counts per each 32768 ticks of the counter
41355  */
41356 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
41357 
41358 #define SNVS_HPCR_HP_TS_MASK                     (0x10000U)
41359 #define SNVS_HPCR_HP_TS_SHIFT                    (16U)
41360 /*! HP_TS
41361  *  0b0..No Action
41362  *  0b1..Synchronize the HP Time Counter to the LP Time Counter
41363  */
41364 #define SNVS_HPCR_HP_TS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
41365 
41366 #define SNVS_HPCR_BTN_CONFIG_MASK                (0x7000000U)
41367 #define SNVS_HPCR_BTN_CONFIG_SHIFT               (24U)
41368 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
41369 
41370 #define SNVS_HPCR_BTN_MASK_MASK                  (0x8000000U)
41371 #define SNVS_HPCR_BTN_MASK_SHIFT                 (27U)
41372 #define SNVS_HPCR_BTN_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
41373 /*! @} */
41374 
41375 /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
41376 /*! @{ */
41377 
41378 #define SNVS_HPSICR_SV0_EN_MASK                  (0x1U)
41379 #define SNVS_HPSICR_SV0_EN_SHIFT                 (0U)
41380 /*! SV0_EN
41381  *  0b0..Security Violation 0 Interrupt is Disabled
41382  *  0b1..Security Violation 0 Interrupt is Enabled
41383  */
41384 #define SNVS_HPSICR_SV0_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
41385 
41386 #define SNVS_HPSICR_SV1_EN_MASK                  (0x2U)
41387 #define SNVS_HPSICR_SV1_EN_SHIFT                 (1U)
41388 /*! SV1_EN
41389  *  0b0..Security Violation 1 Interrupt is Disabled
41390  *  0b1..Security Violation 1 Interrupt is Enabled
41391  */
41392 #define SNVS_HPSICR_SV1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
41393 
41394 #define SNVS_HPSICR_SV2_EN_MASK                  (0x4U)
41395 #define SNVS_HPSICR_SV2_EN_SHIFT                 (2U)
41396 /*! SV2_EN
41397  *  0b0..Security Violation 2 Interrupt is Disabled
41398  *  0b1..Security Violation 2 Interrupt is Enabled
41399  */
41400 #define SNVS_HPSICR_SV2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
41401 
41402 #define SNVS_HPSICR_SV3_EN_MASK                  (0x8U)
41403 #define SNVS_HPSICR_SV3_EN_SHIFT                 (3U)
41404 /*! SV3_EN
41405  *  0b0..Security Violation 3 Interrupt is Disabled
41406  *  0b1..Security Violation 3 Interrupt is Enabled
41407  */
41408 #define SNVS_HPSICR_SV3_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
41409 
41410 #define SNVS_HPSICR_SV4_EN_MASK                  (0x10U)
41411 #define SNVS_HPSICR_SV4_EN_SHIFT                 (4U)
41412 /*! SV4_EN
41413  *  0b0..Security Violation 4 Interrupt is Disabled
41414  *  0b1..Security Violation 4 Interrupt is Enabled
41415  */
41416 #define SNVS_HPSICR_SV4_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
41417 
41418 #define SNVS_HPSICR_SV5_EN_MASK                  (0x20U)
41419 #define SNVS_HPSICR_SV5_EN_SHIFT                 (5U)
41420 /*! SV5_EN
41421  *  0b0..Security Violation 5 Interrupt is Disabled
41422  *  0b1..Security Violation 5 Interrupt is Enabled
41423  */
41424 #define SNVS_HPSICR_SV5_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
41425 
41426 #define SNVS_HPSICR_LPSVI_EN_MASK                (0x80000000U)
41427 #define SNVS_HPSICR_LPSVI_EN_SHIFT               (31U)
41428 /*! LPSVI_EN
41429  *  0b0..LP Security Violation Interrupt is Disabled
41430  *  0b1..LP Security Violation Interrupt is Enabled
41431  */
41432 #define SNVS_HPSICR_LPSVI_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
41433 /*! @} */
41434 
41435 /*! @name HPSVCR - SNVS_HP Security Violation Control Register */
41436 /*! @{ */
41437 
41438 #define SNVS_HPSVCR_SV0_CFG_MASK                 (0x1U)
41439 #define SNVS_HPSVCR_SV0_CFG_SHIFT                (0U)
41440 /*! SV0_CFG
41441  *  0b0..Security Violation 0 is a non-fatal violation
41442  *  0b1..Security Violation 0 is a fatal violation
41443  */
41444 #define SNVS_HPSVCR_SV0_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
41445 
41446 #define SNVS_HPSVCR_SV1_CFG_MASK                 (0x2U)
41447 #define SNVS_HPSVCR_SV1_CFG_SHIFT                (1U)
41448 /*! SV1_CFG
41449  *  0b0..Security Violation 1 is a non-fatal violation
41450  *  0b1..Security Violation 1 is a fatal violation
41451  */
41452 #define SNVS_HPSVCR_SV1_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
41453 
41454 #define SNVS_HPSVCR_SV2_CFG_MASK                 (0x4U)
41455 #define SNVS_HPSVCR_SV2_CFG_SHIFT                (2U)
41456 /*! SV2_CFG
41457  *  0b0..Security Violation 2 is a non-fatal violation
41458  *  0b1..Security Violation 2 is a fatal violation
41459  */
41460 #define SNVS_HPSVCR_SV2_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
41461 
41462 #define SNVS_HPSVCR_SV3_CFG_MASK                 (0x8U)
41463 #define SNVS_HPSVCR_SV3_CFG_SHIFT                (3U)
41464 /*! SV3_CFG
41465  *  0b0..Security Violation 3 is a non-fatal violation
41466  *  0b1..Security Violation 3 is a fatal violation
41467  */
41468 #define SNVS_HPSVCR_SV3_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
41469 
41470 #define SNVS_HPSVCR_SV4_CFG_MASK                 (0x10U)
41471 #define SNVS_HPSVCR_SV4_CFG_SHIFT                (4U)
41472 /*! SV4_CFG
41473  *  0b0..Security Violation 4 is a non-fatal violation
41474  *  0b1..Security Violation 4 is a fatal violation
41475  */
41476 #define SNVS_HPSVCR_SV4_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
41477 
41478 #define SNVS_HPSVCR_SV5_CFG_MASK                 (0x60U)
41479 #define SNVS_HPSVCR_SV5_CFG_SHIFT                (5U)
41480 /*! SV5_CFG
41481  *  0b00..Security Violation 5 is disabled
41482  *  0b01..Security Violation 5 is a non-fatal violation
41483  *  0b1x..Security Violation 5 is a fatal violation
41484  */
41485 #define SNVS_HPSVCR_SV5_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
41486 
41487 #define SNVS_HPSVCR_LPSV_CFG_MASK                (0xC0000000U)
41488 #define SNVS_HPSVCR_LPSV_CFG_SHIFT               (30U)
41489 /*! LPSV_CFG
41490  *  0b00..LP security violation is disabled
41491  *  0b01..LP security violation is a non-fatal violation
41492  *  0b1x..LP security violation is a fatal violation
41493  */
41494 #define SNVS_HPSVCR_LPSV_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
41495 /*! @} */
41496 
41497 /*! @name HPSR - SNVS_HP Status Register */
41498 /*! @{ */
41499 
41500 #define SNVS_HPSR_HPTA_MASK                      (0x1U)
41501 #define SNVS_HPSR_HPTA_SHIFT                     (0U)
41502 /*! HPTA
41503  *  0b0..No time alarm interrupt occurred.
41504  *  0b1..A time alarm interrupt occurred.
41505  */
41506 #define SNVS_HPSR_HPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
41507 
41508 #define SNVS_HPSR_PI_MASK                        (0x2U)
41509 #define SNVS_HPSR_PI_SHIFT                       (1U)
41510 /*! PI
41511  *  0b0..No periodic interrupt occurred.
41512  *  0b1..A periodic interrupt occurred.
41513  */
41514 #define SNVS_HPSR_PI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
41515 
41516 #define SNVS_HPSR_LPDIS_MASK                     (0x10U)
41517 #define SNVS_HPSR_LPDIS_SHIFT                    (4U)
41518 #define SNVS_HPSR_LPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
41519 
41520 #define SNVS_HPSR_BTN_MASK                       (0x40U)
41521 #define SNVS_HPSR_BTN_SHIFT                      (6U)
41522 #define SNVS_HPSR_BTN(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
41523 
41524 #define SNVS_HPSR_BI_MASK                        (0x80U)
41525 #define SNVS_HPSR_BI_SHIFT                       (7U)
41526 #define SNVS_HPSR_BI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
41527 
41528 #define SNVS_HPSR_SSM_STATE_MASK                 (0xF00U)
41529 #define SNVS_HPSR_SSM_STATE_SHIFT                (8U)
41530 /*! SSM_STATE
41531  *  0b0000..Init
41532  *  0b0001..Hard Fail
41533  *  0b0011..Soft Fail
41534  *  0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
41535  *  0b1001..Check
41536  *  0b1011..Non-Secure
41537  *  0b1101..Trusted
41538  *  0b1111..Secure
41539  */
41540 #define SNVS_HPSR_SSM_STATE(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
41541 
41542 #define SNVS_HPSR_SYS_SECURITY_CFG_MASK          (0x7000U)
41543 #define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT         (12U)
41544 /*! SYS_SECURITY_CFG
41545  *  0b000..Fab Configuration - the default configuration of newly fabricated chips
41546  *  0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown
41547  *  0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown
41548  *  0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis
41549  */
41550 #define SNVS_HPSR_SYS_SECURITY_CFG(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
41551 
41552 #define SNVS_HPSR_SYS_SECURE_BOOT_MASK           (0x8000U)
41553 #define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT          (15U)
41554 #define SNVS_HPSR_SYS_SECURE_BOOT(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
41555 
41556 #define SNVS_HPSR_OTPMK_SYNDROME_MASK            (0x1FF0000U)
41557 #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT           (16U)
41558 #define SNVS_HPSR_OTPMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
41559 
41560 #define SNVS_HPSR_OTPMK_ZERO_MASK                (0x8000000U)
41561 #define SNVS_HPSR_OTPMK_ZERO_SHIFT               (27U)
41562 /*! OTPMK_ZERO
41563  *  0b0..The OTPMK is not zero.
41564  *  0b1..The OTPMK is zero.
41565  */
41566 #define SNVS_HPSR_OTPMK_ZERO(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
41567 
41568 #define SNVS_HPSR_ZMK_ZERO_MASK                  (0x80000000U)
41569 #define SNVS_HPSR_ZMK_ZERO_SHIFT                 (31U)
41570 /*! ZMK_ZERO
41571  *  0b0..The ZMK is not zero.
41572  *  0b1..The ZMK is zero.
41573  */
41574 #define SNVS_HPSR_ZMK_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
41575 /*! @} */
41576 
41577 /*! @name HPSVSR - SNVS_HP Security Violation Status Register */
41578 /*! @{ */
41579 
41580 #define SNVS_HPSVSR_SV0_MASK                     (0x1U)
41581 #define SNVS_HPSVSR_SV0_SHIFT                    (0U)
41582 /*! SV0
41583  *  0b0..No Security Violation 0 security violation was detected.
41584  *  0b1..Security Violation 0 security violation was detected.
41585  */
41586 #define SNVS_HPSVSR_SV0(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
41587 
41588 #define SNVS_HPSVSR_SV1_MASK                     (0x2U)
41589 #define SNVS_HPSVSR_SV1_SHIFT                    (1U)
41590 /*! SV1
41591  *  0b0..No Security Violation 1 security violation was detected.
41592  *  0b1..Security Violation 1 security violation was detected.
41593  */
41594 #define SNVS_HPSVSR_SV1(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
41595 
41596 #define SNVS_HPSVSR_SV2_MASK                     (0x4U)
41597 #define SNVS_HPSVSR_SV2_SHIFT                    (2U)
41598 /*! SV2
41599  *  0b0..No Security Violation 2 security violation was detected.
41600  *  0b1..Security Violation 2 security violation was detected.
41601  */
41602 #define SNVS_HPSVSR_SV2(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
41603 
41604 #define SNVS_HPSVSR_SV3_MASK                     (0x8U)
41605 #define SNVS_HPSVSR_SV3_SHIFT                    (3U)
41606 /*! SV3
41607  *  0b0..No Security Violation 3 security violation was detected.
41608  *  0b1..Security Violation 3 security violation was detected.
41609  */
41610 #define SNVS_HPSVSR_SV3(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
41611 
41612 #define SNVS_HPSVSR_SV4_MASK                     (0x10U)
41613 #define SNVS_HPSVSR_SV4_SHIFT                    (4U)
41614 /*! SV4
41615  *  0b0..No Security Violation 4 security violation was detected.
41616  *  0b1..Security Violation 4 security violation was detected.
41617  */
41618 #define SNVS_HPSVSR_SV4(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
41619 
41620 #define SNVS_HPSVSR_SV5_MASK                     (0x20U)
41621 #define SNVS_HPSVSR_SV5_SHIFT                    (5U)
41622 /*! SV5
41623  *  0b0..No Security Violation 5 security violation was detected.
41624  *  0b1..Security Violation 5 security violation was detected.
41625  */
41626 #define SNVS_HPSVSR_SV5(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
41627 
41628 #define SNVS_HPSVSR_SW_SV_MASK                   (0x2000U)
41629 #define SNVS_HPSVSR_SW_SV_SHIFT                  (13U)
41630 #define SNVS_HPSVSR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
41631 
41632 #define SNVS_HPSVSR_SW_FSV_MASK                  (0x4000U)
41633 #define SNVS_HPSVSR_SW_FSV_SHIFT                 (14U)
41634 #define SNVS_HPSVSR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
41635 
41636 #define SNVS_HPSVSR_SW_LPSV_MASK                 (0x8000U)
41637 #define SNVS_HPSVSR_SW_LPSV_SHIFT                (15U)
41638 #define SNVS_HPSVSR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
41639 
41640 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK            (0x1FF0000U)
41641 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT           (16U)
41642 #define SNVS_HPSVSR_ZMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
41643 
41644 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK            (0x8000000U)
41645 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT           (27U)
41646 /*! ZMK_ECC_FAIL
41647  *  0b0..ZMK ECC Failure was not detected.
41648  *  0b1..ZMK ECC Failure was detected.
41649  */
41650 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
41651 
41652 #define SNVS_HPSVSR_LP_SEC_VIO_MASK              (0x80000000U)
41653 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT             (31U)
41654 #define SNVS_HPSVSR_LP_SEC_VIO(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
41655 /*! @} */
41656 
41657 /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
41658 /*! @{ */
41659 
41660 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK        (0xFFFFFFFFU)
41661 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT       (0U)
41662 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
41663 /*! @} */
41664 
41665 /*! @name HPHACR - SNVS_HP High Assurance Counter Register */
41666 /*! @{ */
41667 
41668 #define SNVS_HPHACR_HAC_COUNTER_MASK             (0xFFFFFFFFU)
41669 #define SNVS_HPHACR_HAC_COUNTER_SHIFT            (0U)
41670 #define SNVS_HPHACR_HAC_COUNTER(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
41671 /*! @} */
41672 
41673 /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
41674 /*! @{ */
41675 
41676 #define SNVS_HPRTCMR_RTC_MASK                    (0x7FFFU)
41677 #define SNVS_HPRTCMR_RTC_SHIFT                   (0U)
41678 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
41679 /*! @} */
41680 
41681 /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
41682 /*! @{ */
41683 
41684 #define SNVS_HPRTCLR_RTC_MASK                    (0xFFFFFFFFU)
41685 #define SNVS_HPRTCLR_RTC_SHIFT                   (0U)
41686 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
41687 /*! @} */
41688 
41689 /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
41690 /*! @{ */
41691 
41692 #define SNVS_HPTAMR_HPTA_MS_MASK                 (0x7FFFU)
41693 #define SNVS_HPTAMR_HPTA_MS_SHIFT                (0U)
41694 #define SNVS_HPTAMR_HPTA_MS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
41695 /*! @} */
41696 
41697 /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
41698 /*! @{ */
41699 
41700 #define SNVS_HPTALR_HPTA_LS_MASK                 (0xFFFFFFFFU)
41701 #define SNVS_HPTALR_HPTA_LS_SHIFT                (0U)
41702 #define SNVS_HPTALR_HPTA_LS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
41703 /*! @} */
41704 
41705 /*! @name LPLR - SNVS_LP Lock Register */
41706 /*! @{ */
41707 
41708 #define SNVS_LPLR_ZMK_WHL_MASK                   (0x1U)
41709 #define SNVS_LPLR_ZMK_WHL_SHIFT                  (0U)
41710 /*! ZMK_WHL
41711  *  0b0..Write access is allowed.
41712  *  0b1..Write access is not allowed.
41713  */
41714 #define SNVS_LPLR_ZMK_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
41715 
41716 #define SNVS_LPLR_ZMK_RHL_MASK                   (0x2U)
41717 #define SNVS_LPLR_ZMK_RHL_SHIFT                  (1U)
41718 /*! ZMK_RHL
41719  *  0b0..Read access is allowed (only in software programming mode).
41720  *  0b1..Read access is not allowed.
41721  */
41722 #define SNVS_LPLR_ZMK_RHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
41723 
41724 #define SNVS_LPLR_SRTC_HL_MASK                   (0x4U)
41725 #define SNVS_LPLR_SRTC_HL_SHIFT                  (2U)
41726 /*! SRTC_HL
41727  *  0b0..Write access is allowed.
41728  *  0b1..Write access is not allowed.
41729  */
41730 #define SNVS_LPLR_SRTC_HL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
41731 
41732 #define SNVS_LPLR_LPCALB_HL_MASK                 (0x8U)
41733 #define SNVS_LPLR_LPCALB_HL_SHIFT                (3U)
41734 /*! LPCALB_HL
41735  *  0b0..Write access is allowed.
41736  *  0b1..Write access is not allowed.
41737  */
41738 #define SNVS_LPLR_LPCALB_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
41739 
41740 #define SNVS_LPLR_MC_HL_MASK                     (0x10U)
41741 #define SNVS_LPLR_MC_HL_SHIFT                    (4U)
41742 /*! MC_HL
41743  *  0b0..Write access (increment) is allowed.
41744  *  0b1..Write access (increment) is not allowed.
41745  */
41746 #define SNVS_LPLR_MC_HL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
41747 
41748 #define SNVS_LPLR_GPR_HL_MASK                    (0x20U)
41749 #define SNVS_LPLR_GPR_HL_SHIFT                   (5U)
41750 /*! GPR_HL
41751  *  0b0..Write access is allowed.
41752  *  0b1..Write access is not allowed.
41753  */
41754 #define SNVS_LPLR_GPR_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
41755 
41756 #define SNVS_LPLR_LPSVCR_HL_MASK                 (0x40U)
41757 #define SNVS_LPLR_LPSVCR_HL_SHIFT                (6U)
41758 /*! LPSVCR_HL
41759  *  0b0..Write access is allowed.
41760  *  0b1..Write access is not allowed.
41761  */
41762 #define SNVS_LPLR_LPSVCR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
41763 
41764 #define SNVS_LPLR_LPSECR_HL_MASK                 (0x100U)
41765 #define SNVS_LPLR_LPSECR_HL_SHIFT                (8U)
41766 /*! LPSECR_HL
41767  *  0b0..Write access is allowed.
41768  *  0b1..Write access is not allowed.
41769  */
41770 #define SNVS_LPLR_LPSECR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
41771 
41772 #define SNVS_LPLR_MKS_HL_MASK                    (0x200U)
41773 #define SNVS_LPLR_MKS_HL_SHIFT                   (9U)
41774 /*! MKS_HL
41775  *  0b0..Write access is allowed.
41776  *  0b1..Write access is not allowed.
41777  */
41778 #define SNVS_LPLR_MKS_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
41779 /*! @} */
41780 
41781 /*! @name LPCR - SNVS_LP Control Register */
41782 /*! @{ */
41783 
41784 #define SNVS_LPCR_SRTC_ENV_MASK                  (0x1U)
41785 #define SNVS_LPCR_SRTC_ENV_SHIFT                 (0U)
41786 /*! SRTC_ENV
41787  *  0b0..SRTC is disabled or invalid.
41788  *  0b1..SRTC is enabled and valid.
41789  */
41790 #define SNVS_LPCR_SRTC_ENV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
41791 
41792 #define SNVS_LPCR_LPTA_EN_MASK                   (0x2U)
41793 #define SNVS_LPCR_LPTA_EN_SHIFT                  (1U)
41794 /*! LPTA_EN
41795  *  0b0..LP time alarm interrupt is disabled.
41796  *  0b1..LP time alarm interrupt is enabled.
41797  */
41798 #define SNVS_LPCR_LPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
41799 
41800 #define SNVS_LPCR_MC_ENV_MASK                    (0x4U)
41801 #define SNVS_LPCR_MC_ENV_SHIFT                   (2U)
41802 /*! MC_ENV
41803  *  0b0..MC is disabled or invalid.
41804  *  0b1..MC is enabled and valid.
41805  */
41806 #define SNVS_LPCR_MC_ENV(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
41807 
41808 #define SNVS_LPCR_LPWUI_EN_MASK                  (0x8U)
41809 #define SNVS_LPCR_LPWUI_EN_SHIFT                 (3U)
41810 #define SNVS_LPCR_LPWUI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
41811 
41812 #define SNVS_LPCR_SRTC_INV_EN_MASK               (0x10U)
41813 #define SNVS_LPCR_SRTC_INV_EN_SHIFT              (4U)
41814 /*! SRTC_INV_EN
41815  *  0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)).
41816  *  0b1..SRTC is invalidated in the case of security violation.
41817  */
41818 #define SNVS_LPCR_SRTC_INV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
41819 
41820 #define SNVS_LPCR_DP_EN_MASK                     (0x20U)
41821 #define SNVS_LPCR_DP_EN_SHIFT                    (5U)
41822 /*! DP_EN
41823  *  0b0..Smart PMIC enabled.
41824  *  0b1..Dumb PMIC enabled.
41825  */
41826 #define SNVS_LPCR_DP_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
41827 
41828 #define SNVS_LPCR_TOP_MASK                       (0x40U)
41829 #define SNVS_LPCR_TOP_SHIFT                      (6U)
41830 /*! TOP
41831  *  0b0..Leave system power on.
41832  *  0b1..Turn off system power.
41833  */
41834 #define SNVS_LPCR_TOP(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
41835 
41836 #define SNVS_LPCR_LVD_EN_MASK                    (0x80U)
41837 #define SNVS_LPCR_LVD_EN_SHIFT                   (7U)
41838 #define SNVS_LPCR_LVD_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
41839 
41840 #define SNVS_LPCR_LPCALB_EN_MASK                 (0x100U)
41841 #define SNVS_LPCR_LPCALB_EN_SHIFT                (8U)
41842 /*! LPCALB_EN
41843  *  0b0..SRTC Time calibration is disabled.
41844  *  0b1..SRTC Time calibration is enabled.
41845  */
41846 #define SNVS_LPCR_LPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
41847 
41848 #define SNVS_LPCR_LPCALB_VAL_MASK                (0x7C00U)
41849 #define SNVS_LPCR_LPCALB_VAL_SHIFT               (10U)
41850 /*! LPCALB_VAL
41851  *  0b00000..+0 counts per each 32768 ticks of the counter clock
41852  *  0b00001..+1 counts per each 32768 ticks of the counter clock
41853  *  0b00010..+2 counts per each 32768 ticks of the counter clock
41854  *  0b01111..+15 counts per each 32768 ticks of the counter clock
41855  *  0b10000..-16 counts per each 32768 ticks of the counter clock
41856  *  0b10001..-15 counts per each 32768 ticks of the counter clock
41857  *  0b11110..-2 counts per each 32768 ticks of the counter clock
41858  *  0b11111..-1 counts per each 32768 ticks of the counter clock
41859  */
41860 #define SNVS_LPCR_LPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
41861 
41862 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            (0x30000U)
41863 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           (16U)
41864 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
41865 
41866 #define SNVS_LPCR_DEBOUNCE_MASK                  (0xC0000U)
41867 #define SNVS_LPCR_DEBOUNCE_SHIFT                 (18U)
41868 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
41869 
41870 #define SNVS_LPCR_ON_TIME_MASK                   (0x300000U)
41871 #define SNVS_LPCR_ON_TIME_SHIFT                  (20U)
41872 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
41873 
41874 #define SNVS_LPCR_PK_EN_MASK                     (0x400000U)
41875 #define SNVS_LPCR_PK_EN_SHIFT                    (22U)
41876 #define SNVS_LPCR_PK_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
41877 
41878 #define SNVS_LPCR_PK_OVERRIDE_MASK               (0x800000U)
41879 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              (23U)
41880 #define SNVS_LPCR_PK_OVERRIDE(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
41881 
41882 #define SNVS_LPCR_GPR_Z_DIS_MASK                 (0x1000000U)
41883 #define SNVS_LPCR_GPR_Z_DIS_SHIFT                (24U)
41884 #define SNVS_LPCR_GPR_Z_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
41885 /*! @} */
41886 
41887 /*! @name LPMKCR - SNVS_LP Master Key Control Register */
41888 /*! @{ */
41889 
41890 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK          (0x3U)
41891 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT         (0U)
41892 /*! MASTER_KEY_SEL
41893  *  0b0x..Select one time programmable master key.
41894  *  0b10..Select zeroizable master key when MKS_EN bit is set .
41895  *  0b11..Select combined master key when MKS_EN bit is set .
41896  */
41897 #define SNVS_LPMKCR_MASTER_KEY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
41898 
41899 #define SNVS_LPMKCR_ZMK_HWP_MASK                 (0x4U)
41900 #define SNVS_LPMKCR_ZMK_HWP_SHIFT                (2U)
41901 /*! ZMK_HWP
41902  *  0b0..ZMK is in the software programming mode.
41903  *  0b1..ZMK is in the hardware programming mode.
41904  */
41905 #define SNVS_LPMKCR_ZMK_HWP(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
41906 
41907 #define SNVS_LPMKCR_ZMK_VAL_MASK                 (0x8U)
41908 #define SNVS_LPMKCR_ZMK_VAL_SHIFT                (3U)
41909 /*! ZMK_VAL
41910  *  0b0..ZMK is not valid.
41911  *  0b1..ZMK is valid.
41912  */
41913 #define SNVS_LPMKCR_ZMK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
41914 
41915 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK              (0x10U)
41916 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT             (4U)
41917 /*! ZMK_ECC_EN
41918  *  0b0..ZMK ECC check is disabled.
41919  *  0b1..ZMK ECC check is enabled.
41920  */
41921 #define SNVS_LPMKCR_ZMK_ECC_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
41922 
41923 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK           (0xFF80U)
41924 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT          (7U)
41925 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
41926 /*! @} */
41927 
41928 /*! @name LPSVCR - SNVS_LP Security Violation Control Register */
41929 /*! @{ */
41930 
41931 #define SNVS_LPSVCR_SV0_EN_MASK                  (0x1U)
41932 #define SNVS_LPSVCR_SV0_EN_SHIFT                 (0U)
41933 /*! SV0_EN
41934  *  0b0..Security Violation 0 is disabled in the LP domain.
41935  *  0b1..Security Violation 0 is enabled in the LP domain.
41936  */
41937 #define SNVS_LPSVCR_SV0_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
41938 
41939 #define SNVS_LPSVCR_SV1_EN_MASK                  (0x2U)
41940 #define SNVS_LPSVCR_SV1_EN_SHIFT                 (1U)
41941 /*! SV1_EN
41942  *  0b0..Security Violation 1 is disabled in the LP domain.
41943  *  0b1..Security Violation 1 is enabled in the LP domain.
41944  */
41945 #define SNVS_LPSVCR_SV1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
41946 
41947 #define SNVS_LPSVCR_SV2_EN_MASK                  (0x4U)
41948 #define SNVS_LPSVCR_SV2_EN_SHIFT                 (2U)
41949 /*! SV2_EN
41950  *  0b0..Security Violation 2 is disabled in the LP domain.
41951  *  0b1..Security Violation 2 is enabled in the LP domain.
41952  */
41953 #define SNVS_LPSVCR_SV2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
41954 
41955 #define SNVS_LPSVCR_SV3_EN_MASK                  (0x8U)
41956 #define SNVS_LPSVCR_SV3_EN_SHIFT                 (3U)
41957 /*! SV3_EN
41958  *  0b0..Security Violation 3 is disabled in the LP domain.
41959  *  0b1..Security Violation 3 is enabled in the LP domain.
41960  */
41961 #define SNVS_LPSVCR_SV3_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
41962 
41963 #define SNVS_LPSVCR_SV4_EN_MASK                  (0x10U)
41964 #define SNVS_LPSVCR_SV4_EN_SHIFT                 (4U)
41965 /*! SV4_EN
41966  *  0b0..Security Violation 4 is disabled in the LP domain.
41967  *  0b1..Security Violation 4 is enabled in the LP domain.
41968  */
41969 #define SNVS_LPSVCR_SV4_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
41970 
41971 #define SNVS_LPSVCR_SV5_EN_MASK                  (0x20U)
41972 #define SNVS_LPSVCR_SV5_EN_SHIFT                 (5U)
41973 /*! SV5_EN
41974  *  0b0..Security Violation 5 is disabled in the LP domain.
41975  *  0b1..Security Violation 5 is enabled in the LP domain.
41976  */
41977 #define SNVS_LPSVCR_SV5_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
41978 /*! @} */
41979 
41980 /*! @name LPSECR - SNVS_LP Security Events Configuration Register */
41981 /*! @{ */
41982 
41983 #define SNVS_LPSECR_SRTCR_EN_MASK                (0x2U)
41984 #define SNVS_LPSECR_SRTCR_EN_SHIFT               (1U)
41985 /*! SRTCR_EN
41986  *  0b0..SRTC rollover is disabled.
41987  *  0b1..SRTC rollover is enabled.
41988  */
41989 #define SNVS_LPSECR_SRTCR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK)
41990 
41991 #define SNVS_LPSECR_MCR_EN_MASK                  (0x4U)
41992 #define SNVS_LPSECR_MCR_EN_SHIFT                 (2U)
41993 /*! MCR_EN
41994  *  0b0..MC rollover is disabled.
41995  *  0b1..MC rollover is enabled.
41996  */
41997 #define SNVS_LPSECR_MCR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK)
41998 
41999 #define SNVS_LPSECR_PFD_OBSERV_MASK              (0x4000U)
42000 #define SNVS_LPSECR_PFD_OBSERV_SHIFT             (14U)
42001 #define SNVS_LPSECR_PFD_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_PFD_OBSERV_SHIFT)) & SNVS_LPSECR_PFD_OBSERV_MASK)
42002 
42003 #define SNVS_LPSECR_POR_OBSERV_MASK              (0x8000U)
42004 #define SNVS_LPSECR_POR_OBSERV_SHIFT             (15U)
42005 #define SNVS_LPSECR_POR_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_POR_OBSERV_SHIFT)) & SNVS_LPSECR_POR_OBSERV_MASK)
42006 
42007 #define SNVS_LPSECR_LTDC_MASK                    (0x70000U)
42008 #define SNVS_LPSECR_LTDC_SHIFT                   (16U)
42009 #define SNVS_LPSECR_LTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_LTDC_SHIFT)) & SNVS_LPSECR_LTDC_MASK)
42010 
42011 #define SNVS_LPSECR_HTDC_MASK                    (0x700000U)
42012 #define SNVS_LPSECR_HTDC_SHIFT                   (20U)
42013 #define SNVS_LPSECR_HTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_HTDC_SHIFT)) & SNVS_LPSECR_HTDC_MASK)
42014 
42015 #define SNVS_LPSECR_VRC_MASK                     (0x7000000U)
42016 #define SNVS_LPSECR_VRC_SHIFT                    (24U)
42017 #define SNVS_LPSECR_VRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_VRC_SHIFT)) & SNVS_LPSECR_VRC_MASK)
42018 
42019 #define SNVS_LPSECR_OSCB_MASK                    (0x10000000U)
42020 #define SNVS_LPSECR_OSCB_SHIFT                   (28U)
42021 /*! OSCB
42022  *  0b0..Normal SRTC clock oscillator not bypassed.
42023  *  0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
42024  */
42025 #define SNVS_LPSECR_OSCB(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK)
42026 /*! @} */
42027 
42028 /*! @name LPSR - SNVS_LP Status Register */
42029 /*! @{ */
42030 
42031 #define SNVS_LPSR_LPTA_MASK                      (0x1U)
42032 #define SNVS_LPSR_LPTA_SHIFT                     (0U)
42033 /*! LPTA
42034  *  0b0..No time alarm interrupt occurred.
42035  *  0b1..A time alarm interrupt occurred.
42036  */
42037 #define SNVS_LPSR_LPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
42038 
42039 #define SNVS_LPSR_SRTCR_MASK                     (0x2U)
42040 #define SNVS_LPSR_SRTCR_SHIFT                    (1U)
42041 /*! SRTCR
42042  *  0b0..SRTC has not reached its maximum value.
42043  *  0b1..SRTC has reached its maximum value.
42044  */
42045 #define SNVS_LPSR_SRTCR(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
42046 
42047 #define SNVS_LPSR_MCR_MASK                       (0x4U)
42048 #define SNVS_LPSR_MCR_SHIFT                      (2U)
42049 /*! MCR
42050  *  0b0..MC has not reached its maximum value.
42051  *  0b1..MC has reached its maximum value.
42052  */
42053 #define SNVS_LPSR_MCR(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
42054 
42055 #define SNVS_LPSR_LVD_MASK                       (0x8U)
42056 #define SNVS_LPSR_LVD_SHIFT                      (3U)
42057 /*! LVD
42058  *  0b0..No low voltage event detected.
42059  *  0b1..Low voltage event is detected.
42060  */
42061 #define SNVS_LPSR_LVD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
42062 
42063 #define SNVS_LPSR_ESVD_MASK                      (0x10000U)
42064 #define SNVS_LPSR_ESVD_SHIFT                     (16U)
42065 /*! ESVD
42066  *  0b0..No external security violation.
42067  *  0b1..External security violation is detected.
42068  */
42069 #define SNVS_LPSR_ESVD(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
42070 
42071 #define SNVS_LPSR_EO_MASK                        (0x20000U)
42072 #define SNVS_LPSR_EO_SHIFT                       (17U)
42073 /*! EO
42074  *  0b0..Emergency off was not detected.
42075  *  0b1..Emergency off was detected.
42076  */
42077 #define SNVS_LPSR_EO(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
42078 
42079 #define SNVS_LPSR_SPOF_MASK                      (0x40000U)
42080 #define SNVS_LPSR_SPOF_SHIFT                     (18U)
42081 /*! SPOF
42082  *  0b0..Set Power Off was not detected.
42083  *  0b1..Set Power Off was detected.
42084  */
42085 #define SNVS_LPSR_SPOF(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
42086 
42087 #define SNVS_LPSR_SPON_MASK                      (0x80000U)
42088 #define SNVS_LPSR_SPON_SHIFT                     (19U)
42089 /*! SPON
42090  *  0b0..Set Power On Interrupt was not detected.
42091  *  0b1..Set Power On Interrupt was detected.
42092  */
42093 #define SNVS_LPSR_SPON(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPON_SHIFT)) & SNVS_LPSR_SPON_MASK)
42094 
42095 #define SNVS_LPSR_LPNS_MASK                      (0x40000000U)
42096 #define SNVS_LPSR_LPNS_SHIFT                     (30U)
42097 /*! LPNS
42098  *  0b0..LP section was not programmed in the non-secure state.
42099  *  0b1..LP section was programmed in the non-secure state.
42100  */
42101 #define SNVS_LPSR_LPNS(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
42102 
42103 #define SNVS_LPSR_LPS_MASK                       (0x80000000U)
42104 #define SNVS_LPSR_LPS_SHIFT                      (31U)
42105 /*! LPS
42106  *  0b0..LP section was not programmed in secure or trusted state.
42107  *  0b1..LP section was programmed in secure or trusted state.
42108  */
42109 #define SNVS_LPSR_LPS(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
42110 /*! @} */
42111 
42112 /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
42113 /*! @{ */
42114 
42115 #define SNVS_LPSRTCMR_SRTC_MASK                  (0x7FFFU)
42116 #define SNVS_LPSRTCMR_SRTC_SHIFT                 (0U)
42117 #define SNVS_LPSRTCMR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
42118 /*! @} */
42119 
42120 /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
42121 /*! @{ */
42122 
42123 #define SNVS_LPSRTCLR_SRTC_MASK                  (0xFFFFFFFFU)
42124 #define SNVS_LPSRTCLR_SRTC_SHIFT                 (0U)
42125 #define SNVS_LPSRTCLR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
42126 /*! @} */
42127 
42128 /*! @name LPTAR - SNVS_LP Time Alarm Register */
42129 /*! @{ */
42130 
42131 #define SNVS_LPTAR_LPTA_MASK                     (0xFFFFFFFFU)
42132 #define SNVS_LPTAR_LPTA_SHIFT                    (0U)
42133 #define SNVS_LPTAR_LPTA(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
42134 /*! @} */
42135 
42136 /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
42137 /*! @{ */
42138 
42139 #define SNVS_LPSMCMR_MON_COUNTER_MASK            (0xFFFFU)
42140 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           (0U)
42141 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
42142 
42143 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            (0xFFFF0000U)
42144 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           (16U)
42145 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
42146 /*! @} */
42147 
42148 /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
42149 /*! @{ */
42150 
42151 #define SNVS_LPSMCLR_MON_COUNTER_MASK            (0xFFFFFFFFU)
42152 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           (0U)
42153 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
42154 /*! @} */
42155 
42156 /*! @name LPLVDR - SNVS_LP Digital Low-Voltage Detector Register */
42157 /*! @{ */
42158 
42159 #define SNVS_LPLVDR_LVD_MASK                     (0xFFFFFFFFU)
42160 #define SNVS_LPLVDR_LVD_SHIFT                    (0U)
42161 #define SNVS_LPLVDR_LVD(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
42162 /*! @} */
42163 
42164 /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
42165 /*! @{ */
42166 
42167 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK        (0xFFFFFFFFU)
42168 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT       (0U)
42169 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
42170 /*! @} */
42171 
42172 /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
42173 /*! @{ */
42174 
42175 #define SNVS_LPZMKR_ZMK_MASK                     (0xFFFFFFFFU)
42176 #define SNVS_LPZMKR_ZMK_SHIFT                    (0U)
42177 #define SNVS_LPZMKR_ZMK(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
42178 /*! @} */
42179 
42180 /* The count of SNVS_LPZMKR */
42181 #define SNVS_LPZMKR_COUNT                        (8U)
42182 
42183 /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
42184 /*! @{ */
42185 
42186 #define SNVS_LPGPR_ALIAS_GPR_MASK                (0xFFFFFFFFU)
42187 #define SNVS_LPGPR_ALIAS_GPR_SHIFT               (0U)
42188 #define SNVS_LPGPR_ALIAS_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
42189 /*! @} */
42190 
42191 /* The count of SNVS_LPGPR_ALIAS */
42192 #define SNVS_LPGPR_ALIAS_COUNT                   (4U)
42193 
42194 /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */
42195 /*! @{ */
42196 
42197 #define SNVS_LPGPR_GPR_MASK                      (0xFFFFFFFFU)
42198 #define SNVS_LPGPR_GPR_SHIFT                     (0U)
42199 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
42200 /*! @} */
42201 
42202 /* The count of SNVS_LPGPR */
42203 #define SNVS_LPGPR_COUNT                         (8U)
42204 
42205 /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
42206 /*! @{ */
42207 
42208 #define SNVS_HPVIDR1_MINOR_REV_MASK              (0xFFU)
42209 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             (0U)
42210 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
42211 
42212 #define SNVS_HPVIDR1_MAJOR_REV_MASK              (0xFF00U)
42213 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             (8U)
42214 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
42215 
42216 #define SNVS_HPVIDR1_IP_ID_MASK                  (0xFFFF0000U)
42217 #define SNVS_HPVIDR1_IP_ID_SHIFT                 (16U)
42218 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
42219 /*! @} */
42220 
42221 /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
42222 /*! @{ */
42223 
42224 #define SNVS_HPVIDR2_CONFIG_OPT_MASK             (0xFFU)
42225 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT            (0U)
42226 #define SNVS_HPVIDR2_CONFIG_OPT(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
42227 
42228 #define SNVS_HPVIDR2_ECO_REV_MASK                (0xFF00U)
42229 #define SNVS_HPVIDR2_ECO_REV_SHIFT               (8U)
42230 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
42231 
42232 #define SNVS_HPVIDR2_INTG_OPT_MASK               (0xFF0000U)
42233 #define SNVS_HPVIDR2_INTG_OPT_SHIFT              (16U)
42234 #define SNVS_HPVIDR2_INTG_OPT(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
42235 
42236 #define SNVS_HPVIDR2_IP_ERA_MASK                 (0xFF000000U)
42237 #define SNVS_HPVIDR2_IP_ERA_SHIFT                (24U)
42238 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
42239 /*! @} */
42240 
42241 
42242 /*!
42243  * @}
42244  */ /* end of group SNVS_Register_Masks */
42245 
42246 
42247 /* SNVS - Peripheral instance base addresses */
42248 /** Peripheral SNVS base address */
42249 #define SNVS_BASE                                (0x400D4000u)
42250 /** Peripheral SNVS base pointer */
42251 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
42252 /** Array initializer of SNVS peripheral base addresses */
42253 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
42254 /** Array initializer of SNVS peripheral base pointers */
42255 #define SNVS_BASE_PTRS                           { SNVS }
42256 /** Interrupt vectors for the SNVS peripheral type */
42257 #define SNVS_IRQS                                { SNVS_LP_WRAPPER_IRQn }
42258 #define SNVS_CONSOLIDATED_IRQS                   { SNVS_HP_WRAPPER_IRQn }
42259 #define SNVS_SECURITY_IRQS                       { SNVS_HP_WRAPPER_TZ_IRQn }
42260 
42261 /*!
42262  * @}
42263  */ /* end of group SNVS_Peripheral_Access_Layer */
42264 
42265 
42266 /* ----------------------------------------------------------------------------
42267    -- SPDIF Peripheral Access Layer
42268    ---------------------------------------------------------------------------- */
42269 
42270 /*!
42271  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
42272  * @{
42273  */
42274 
42275 /** SPDIF - Register Layout Typedef */
42276 typedef struct {
42277   __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
42278   __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
42279   __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
42280   __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
42281   union {                                          /* offset: 0x10 */
42282     __O  uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
42283     __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
42284   };
42285   __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
42286   __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
42287   __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
42288   __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
42289   __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
42290   __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
42291   __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
42292   __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
42293   __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
42294   __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
42295        uint8_t RESERVED_0[8];
42296   __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
42297        uint8_t RESERVED_1[8];
42298   __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
42299 } SPDIF_Type;
42300 
42301 /* ----------------------------------------------------------------------------
42302    -- SPDIF Register Masks
42303    ---------------------------------------------------------------------------- */
42304 
42305 /*!
42306  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
42307  * @{
42308  */
42309 
42310 /*! @name SCR - SPDIF Configuration Register */
42311 /*! @{ */
42312 
42313 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
42314 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
42315 /*! USrc_Sel
42316  *  0b00..No embedded U channel
42317  *  0b01..U channel from SPDIF receive block (CD mode)
42318  *  0b10..Reserved
42319  *  0b11..U channel from on chip transmitter
42320  */
42321 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
42322 
42323 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
42324 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
42325 /*! TxSel
42326  *  0b000..Off and output 0
42327  *  0b001..Feed-through SPDIFIN
42328  *  0b101..Tx Normal operation
42329  */
42330 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
42331 
42332 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
42333 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
42334 /*! ValCtrl
42335  *  0b0..Outgoing Validity always set
42336  *  0b1..Outgoing Validity always clear
42337  */
42338 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
42339 
42340 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
42341 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
42342 #define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
42343 
42344 #define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
42345 #define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
42346 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
42347 
42348 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
42349 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
42350 /*! TxFIFO_Ctrl
42351  *  0b00..Send out digital zero on SPDIF Tx
42352  *  0b01..Tx Normal operation
42353  *  0b10..Reset to 1 sample remaining
42354  *  0b11..Reserved
42355  */
42356 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
42357 
42358 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
42359 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
42360 #define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
42361 
42362 #define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
42363 #define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
42364 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
42365 
42366 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
42367 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
42368 /*! TxFIFOEmpty_Sel
42369  *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
42370  *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
42371  *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
42372  *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
42373  */
42374 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
42375 
42376 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
42377 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
42378 /*! TxAutoSync
42379  *  0b0..Tx FIFO auto sync off
42380  *  0b1..Tx FIFO auto sync on
42381  */
42382 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
42383 
42384 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
42385 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
42386 /*! RxAutoSync
42387  *  0b0..Rx FIFO auto sync off
42388  *  0b1..RxFIFO auto sync on
42389  */
42390 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
42391 
42392 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
42393 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
42394 /*! RxFIFOFull_Sel
42395  *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
42396  *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
42397  *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
42398  *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
42399  */
42400 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
42401 
42402 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
42403 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
42404 /*! RxFIFO_Rst
42405  *  0b0..Normal operation
42406  *  0b1..Reset register to 1 sample remaining
42407  */
42408 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
42409 
42410 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
42411 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
42412 /*! RxFIFO_Off_On
42413  *  0b0..SPDIF Rx FIFO is on
42414  *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
42415  */
42416 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
42417 
42418 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
42419 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
42420 /*! RxFIFO_Ctrl
42421  *  0b0..Normal operation
42422  *  0b1..Always read zero from Rx data register
42423  */
42424 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
42425 /*! @} */
42426 
42427 /*! @name SRCD - CDText Control Register */
42428 /*! @{ */
42429 
42430 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
42431 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
42432 /*! USyncMode
42433  *  0b0..Non-CD data
42434  *  0b1..CD user channel subcode
42435  */
42436 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
42437 /*! @} */
42438 
42439 /*! @name SRPC - PhaseConfig Register */
42440 /*! @{ */
42441 
42442 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
42443 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
42444 /*! GainSel
42445  *  0b000..24*(2**10)
42446  *  0b001..16*(2**10)
42447  *  0b010..12*(2**10)
42448  *  0b011..8*(2**10)
42449  *  0b100..6*(2**10)
42450  *  0b101..4*(2**10)
42451  *  0b110..3*(2**10)
42452  */
42453 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
42454 
42455 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
42456 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
42457 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
42458 
42459 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
42460 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
42461 /*! ClkSrc_Sel
42462  *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
42463  *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
42464  *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
42465  *  0b0101..REF_CLK_32K (XTALOSC)
42466  *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
42467  *  0b1000..SPDIF_EXT_CLK
42468  */
42469 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
42470 /*! @} */
42471 
42472 /*! @name SIE - InterruptEn Register */
42473 /*! @{ */
42474 
42475 #define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
42476 #define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
42477 #define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
42478 
42479 #define SPDIF_SIE_TXEM_MASK                      (0x2U)
42480 #define SPDIF_SIE_TXEM_SHIFT                     (1U)
42481 #define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
42482 
42483 #define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
42484 #define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
42485 #define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
42486 
42487 #define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
42488 #define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
42489 #define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
42490 
42491 #define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
42492 #define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
42493 #define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
42494 
42495 #define SPDIF_SIE_UQERR_MASK                     (0x20U)
42496 #define SPDIF_SIE_UQERR_SHIFT                    (5U)
42497 #define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
42498 
42499 #define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
42500 #define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
42501 #define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
42502 
42503 #define SPDIF_SIE_QRXOV_MASK                     (0x80U)
42504 #define SPDIF_SIE_QRXOV_SHIFT                    (7U)
42505 #define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
42506 
42507 #define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
42508 #define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
42509 #define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
42510 
42511 #define SPDIF_SIE_URXOV_MASK                     (0x200U)
42512 #define SPDIF_SIE_URXOV_SHIFT                    (9U)
42513 #define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
42514 
42515 #define SPDIF_SIE_URXFUL_MASK                    (0x400U)
42516 #define SPDIF_SIE_URXFUL_SHIFT                   (10U)
42517 #define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
42518 
42519 #define SPDIF_SIE_BITERR_MASK                    (0x4000U)
42520 #define SPDIF_SIE_BITERR_SHIFT                   (14U)
42521 #define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
42522 
42523 #define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
42524 #define SPDIF_SIE_SYMERR_SHIFT                   (15U)
42525 #define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
42526 
42527 #define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
42528 #define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
42529 #define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
42530 
42531 #define SPDIF_SIE_CNEW_MASK                      (0x20000U)
42532 #define SPDIF_SIE_CNEW_SHIFT                     (17U)
42533 #define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
42534 
42535 #define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
42536 #define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
42537 #define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
42538 
42539 #define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
42540 #define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
42541 #define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
42542 
42543 #define SPDIF_SIE_LOCK_MASK                      (0x100000U)
42544 #define SPDIF_SIE_LOCK_SHIFT                     (20U)
42545 #define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
42546 /*! @} */
42547 
42548 /*! @name SIC - InterruptClear Register */
42549 /*! @{ */
42550 
42551 #define SPDIF_SIC_LOCKLOSS_MASK                  (0x4U)
42552 #define SPDIF_SIC_LOCKLOSS_SHIFT                 (2U)
42553 #define SPDIF_SIC_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
42554 
42555 #define SPDIF_SIC_RXFIFORESYN_MASK               (0x8U)
42556 #define SPDIF_SIC_RXFIFORESYN_SHIFT              (3U)
42557 #define SPDIF_SIC_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
42558 
42559 #define SPDIF_SIC_RXFIFOUNOV_MASK                (0x10U)
42560 #define SPDIF_SIC_RXFIFOUNOV_SHIFT               (4U)
42561 #define SPDIF_SIC_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
42562 
42563 #define SPDIF_SIC_UQERR_MASK                     (0x20U)
42564 #define SPDIF_SIC_UQERR_SHIFT                    (5U)
42565 #define SPDIF_SIC_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
42566 
42567 #define SPDIF_SIC_UQSYNC_MASK                    (0x40U)
42568 #define SPDIF_SIC_UQSYNC_SHIFT                   (6U)
42569 #define SPDIF_SIC_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
42570 
42571 #define SPDIF_SIC_QRXOV_MASK                     (0x80U)
42572 #define SPDIF_SIC_QRXOV_SHIFT                    (7U)
42573 #define SPDIF_SIC_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
42574 
42575 #define SPDIF_SIC_URXOV_MASK                     (0x200U)
42576 #define SPDIF_SIC_URXOV_SHIFT                    (9U)
42577 #define SPDIF_SIC_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
42578 
42579 #define SPDIF_SIC_BITERR_MASK                    (0x4000U)
42580 #define SPDIF_SIC_BITERR_SHIFT                   (14U)
42581 #define SPDIF_SIC_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
42582 
42583 #define SPDIF_SIC_SYMERR_MASK                    (0x8000U)
42584 #define SPDIF_SIC_SYMERR_SHIFT                   (15U)
42585 #define SPDIF_SIC_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
42586 
42587 #define SPDIF_SIC_VALNOGOOD_MASK                 (0x10000U)
42588 #define SPDIF_SIC_VALNOGOOD_SHIFT                (16U)
42589 #define SPDIF_SIC_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
42590 
42591 #define SPDIF_SIC_CNEW_MASK                      (0x20000U)
42592 #define SPDIF_SIC_CNEW_SHIFT                     (17U)
42593 #define SPDIF_SIC_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
42594 
42595 #define SPDIF_SIC_TXRESYN_MASK                   (0x40000U)
42596 #define SPDIF_SIC_TXRESYN_SHIFT                  (18U)
42597 #define SPDIF_SIC_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
42598 
42599 #define SPDIF_SIC_TXUNOV_MASK                    (0x80000U)
42600 #define SPDIF_SIC_TXUNOV_SHIFT                   (19U)
42601 #define SPDIF_SIC_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
42602 
42603 #define SPDIF_SIC_LOCK_MASK                      (0x100000U)
42604 #define SPDIF_SIC_LOCK_SHIFT                     (20U)
42605 #define SPDIF_SIC_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
42606 /*! @} */
42607 
42608 /*! @name SIS - InterruptStat Register */
42609 /*! @{ */
42610 
42611 #define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
42612 #define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
42613 #define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
42614 
42615 #define SPDIF_SIS_TXEM_MASK                      (0x2U)
42616 #define SPDIF_SIS_TXEM_SHIFT                     (1U)
42617 #define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
42618 
42619 #define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
42620 #define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
42621 #define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
42622 
42623 #define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
42624 #define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
42625 #define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
42626 
42627 #define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
42628 #define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
42629 #define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
42630 
42631 #define SPDIF_SIS_UQERR_MASK                     (0x20U)
42632 #define SPDIF_SIS_UQERR_SHIFT                    (5U)
42633 #define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
42634 
42635 #define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
42636 #define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
42637 #define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
42638 
42639 #define SPDIF_SIS_QRXOV_MASK                     (0x80U)
42640 #define SPDIF_SIS_QRXOV_SHIFT                    (7U)
42641 #define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
42642 
42643 #define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
42644 #define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
42645 #define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
42646 
42647 #define SPDIF_SIS_URXOV_MASK                     (0x200U)
42648 #define SPDIF_SIS_URXOV_SHIFT                    (9U)
42649 #define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
42650 
42651 #define SPDIF_SIS_URXFUL_MASK                    (0x400U)
42652 #define SPDIF_SIS_URXFUL_SHIFT                   (10U)
42653 #define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
42654 
42655 #define SPDIF_SIS_BITERR_MASK                    (0x4000U)
42656 #define SPDIF_SIS_BITERR_SHIFT                   (14U)
42657 #define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
42658 
42659 #define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
42660 #define SPDIF_SIS_SYMERR_SHIFT                   (15U)
42661 #define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
42662 
42663 #define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
42664 #define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
42665 #define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
42666 
42667 #define SPDIF_SIS_CNEW_MASK                      (0x20000U)
42668 #define SPDIF_SIS_CNEW_SHIFT                     (17U)
42669 #define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
42670 
42671 #define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
42672 #define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
42673 #define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
42674 
42675 #define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
42676 #define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
42677 #define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
42678 
42679 #define SPDIF_SIS_LOCK_MASK                      (0x100000U)
42680 #define SPDIF_SIS_LOCK_SHIFT                     (20U)
42681 #define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
42682 /*! @} */
42683 
42684 /*! @name SRL - SPDIFRxLeft Register */
42685 /*! @{ */
42686 
42687 #define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
42688 #define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
42689 #define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
42690 /*! @} */
42691 
42692 /*! @name SRR - SPDIFRxRight Register */
42693 /*! @{ */
42694 
42695 #define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
42696 #define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
42697 #define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
42698 /*! @} */
42699 
42700 /*! @name SRCSH - SPDIFRxCChannel_h Register */
42701 /*! @{ */
42702 
42703 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
42704 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
42705 #define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
42706 /*! @} */
42707 
42708 /*! @name SRCSL - SPDIFRxCChannel_l Register */
42709 /*! @{ */
42710 
42711 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
42712 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
42713 #define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
42714 /*! @} */
42715 
42716 /*! @name SRU - UchannelRx Register */
42717 /*! @{ */
42718 
42719 #define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
42720 #define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
42721 #define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
42722 /*! @} */
42723 
42724 /*! @name SRQ - QchannelRx Register */
42725 /*! @{ */
42726 
42727 #define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
42728 #define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
42729 #define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
42730 /*! @} */
42731 
42732 /*! @name STL - SPDIFTxLeft Register */
42733 /*! @{ */
42734 
42735 #define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
42736 #define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
42737 #define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
42738 /*! @} */
42739 
42740 /*! @name STR - SPDIFTxRight Register */
42741 /*! @{ */
42742 
42743 #define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
42744 #define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
42745 #define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
42746 /*! @} */
42747 
42748 /*! @name STCSCH - SPDIFTxCChannelCons_h Register */
42749 /*! @{ */
42750 
42751 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
42752 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
42753 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
42754 /*! @} */
42755 
42756 /*! @name STCSCL - SPDIFTxCChannelCons_l Register */
42757 /*! @{ */
42758 
42759 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
42760 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
42761 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
42762 /*! @} */
42763 
42764 /*! @name SRFM - FreqMeas Register */
42765 /*! @{ */
42766 
42767 #define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
42768 #define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
42769 #define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
42770 /*! @} */
42771 
42772 /*! @name STC - SPDIFTxClk Register */
42773 /*! @{ */
42774 
42775 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
42776 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
42777 /*! TxClk_DF
42778  *  0b0000000..divider factor is 1
42779  *  0b0000001..divider factor is 2
42780  *  0b1111111..divider factor is 128
42781  */
42782 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
42783 
42784 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
42785 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
42786 /*! tx_all_clk_en
42787  *  0b0..disable transfer clock.
42788  *  0b1..enable transfer clock.
42789  */
42790 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
42791 
42792 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
42793 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
42794 /*! TxClk_Source
42795  *  0b000..XTALOSC input (XTALOSC clock)
42796  *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)
42797  *  0b010..tx_clk1 (from SAI1)
42798  *  0b011..tx_clk2 SPDIF_EXT_CLK, from pads
42799  *  0b100..tx_clk3 (from SAI2)
42800  *  0b101..ipg_clk input (frequency divided)
42801  *  0b110..tx_clk4 (from SAI3)
42802  */
42803 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
42804 
42805 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
42806 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
42807 /*! SYSCLK_DF
42808  *  0b000000000..no clock signal
42809  *  0b000000001..divider factor is 2
42810  *  0b111111111..divider factor is 512
42811  */
42812 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
42813 /*! @} */
42814 
42815 
42816 /*!
42817  * @}
42818  */ /* end of group SPDIF_Register_Masks */
42819 
42820 
42821 /* SPDIF - Peripheral instance base addresses */
42822 /** Peripheral SPDIF base address */
42823 #define SPDIF_BASE                               (0x40380000u)
42824 /** Peripheral SPDIF base pointer */
42825 #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
42826 /** Array initializer of SPDIF peripheral base addresses */
42827 #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
42828 /** Array initializer of SPDIF peripheral base pointers */
42829 #define SPDIF_BASE_PTRS                          { SPDIF }
42830 /** Interrupt vectors for the SPDIF peripheral type */
42831 #define SPDIF_IRQS                               { SPDIF_IRQn }
42832 
42833 /*!
42834  * @}
42835  */ /* end of group SPDIF_Peripheral_Access_Layer */
42836 
42837 
42838 /* ----------------------------------------------------------------------------
42839    -- SRC Peripheral Access Layer
42840    ---------------------------------------------------------------------------- */
42841 
42842 /*!
42843  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
42844  * @{
42845  */
42846 
42847 /** SRC - Register Layout Typedef */
42848 typedef struct {
42849   __IO uint32_t SCR;                               /**< SRC Control Register, offset: 0x0 */
42850   __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x4 */
42851   __IO uint32_t SRSR;                              /**< SRC Reset Status Register, offset: 0x8 */
42852        uint8_t RESERVED_0[16];
42853   __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0x1C */
42854   __IO uint32_t GPR[10];                           /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */
42855 } SRC_Type;
42856 
42857 /* ----------------------------------------------------------------------------
42858    -- SRC Register Masks
42859    ---------------------------------------------------------------------------- */
42860 
42861 /*!
42862  * @addtogroup SRC_Register_Masks SRC Register Masks
42863  * @{
42864  */
42865 
42866 /*! @name SCR - SRC Control Register */
42867 /*! @{ */
42868 
42869 #define SRC_SCR_MASK_WDOG_RST_MASK               (0x780U)
42870 #define SRC_SCR_MASK_WDOG_RST_SHIFT              (7U)
42871 /*! mask_wdog_rst
42872  *  0b0101..wdog_rst_b is masked
42873  *  0b1010..wdog_rst_b is not masked (default)
42874  */
42875 #define SRC_SCR_MASK_WDOG_RST(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
42876 
42877 #define SRC_SCR_CORE0_RST_MASK                   (0x2000U)
42878 #define SRC_SCR_CORE0_RST_SHIFT                  (13U)
42879 /*! core0_rst
42880  *  0b0..do not assert core0 reset
42881  *  0b1..assert core0 reset
42882  */
42883 #define SRC_SCR_CORE0_RST(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
42884 
42885 #define SRC_SCR_CORE0_DBG_RST_MASK               (0x20000U)
42886 #define SRC_SCR_CORE0_DBG_RST_SHIFT              (17U)
42887 /*! core0_dbg_rst
42888  *  0b0..do not assert core0 debug reset
42889  *  0b1..assert core0 debug reset
42890  */
42891 #define SRC_SCR_CORE0_DBG_RST(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
42892 
42893 #define SRC_SCR_DBG_RST_MSK_PG_MASK              (0x2000000U)
42894 #define SRC_SCR_DBG_RST_MSK_PG_SHIFT             (25U)
42895 /*! dbg_rst_msk_pg
42896  *  0b0..do not mask core debug resets (debug resets will be asserted after power gating event)
42897  *  0b1..mask core debug resets (debug resets won't be asserted after power gating event)
42898  */
42899 #define SRC_SCR_DBG_RST_MSK_PG(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
42900 
42901 #define SRC_SCR_MASK_WDOG3_RST_MASK              (0xF0000000U)
42902 #define SRC_SCR_MASK_WDOG3_RST_SHIFT             (28U)
42903 /*! mask_wdog3_rst
42904  *  0b0101..wdog3_rst_b is masked
42905  *  0b1010..wdog3_rst_b is not masked
42906  */
42907 #define SRC_SCR_MASK_WDOG3_RST(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
42908 /*! @} */
42909 
42910 /*! @name SBMR1 - SRC Boot Mode Register 1 */
42911 /*! @{ */
42912 
42913 #define SRC_SBMR1_BOOT_CFG1_MASK                 (0xFFU)
42914 #define SRC_SBMR1_BOOT_CFG1_SHIFT                (0U)
42915 #define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
42916 
42917 #define SRC_SBMR1_BOOT_CFG2_MASK                 (0xFF00U)
42918 #define SRC_SBMR1_BOOT_CFG2_SHIFT                (8U)
42919 #define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
42920 
42921 #define SRC_SBMR1_BOOT_CFG3_MASK                 (0xFF0000U)
42922 #define SRC_SBMR1_BOOT_CFG3_SHIFT                (16U)
42923 #define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
42924 
42925 #define SRC_SBMR1_BOOT_CFG4_MASK                 (0xFF000000U)
42926 #define SRC_SBMR1_BOOT_CFG4_SHIFT                (24U)
42927 #define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
42928 /*! @} */
42929 
42930 /*! @name SRSR - SRC Reset Status Register */
42931 /*! @{ */
42932 
42933 #define SRC_SRSR_IPP_RESET_B_MASK                (0x1U)
42934 #define SRC_SRSR_IPP_RESET_B_SHIFT               (0U)
42935 /*! ipp_reset_b
42936  *  0b0..Reset is not a result of ipp_reset_b pin.
42937  *  0b1..Reset is a result of ipp_reset_b pin.
42938  */
42939 #define SRC_SRSR_IPP_RESET_B(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
42940 
42941 #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK         (0x2U)
42942 #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT        (1U)
42943 /*! lockup_sysresetreq
42944  *  0b0..Reset is not a result of the mentioned case.
42945  *  0b1..Reset is a result of the mentioned case.
42946  */
42947 #define SRC_SRSR_LOCKUP_SYSRESETREQ(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
42948 
42949 #define SRC_SRSR_CSU_RESET_B_MASK                (0x4U)
42950 #define SRC_SRSR_CSU_RESET_B_SHIFT               (2U)
42951 /*! csu_reset_b
42952  *  0b0..Reset is not a result of the csu_reset_b event.
42953  *  0b1..Reset is a result of the csu_reset_b event.
42954  */
42955 #define SRC_SRSR_CSU_RESET_B(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
42956 
42957 #define SRC_SRSR_IPP_USER_RESET_B_MASK           (0x8U)
42958 #define SRC_SRSR_IPP_USER_RESET_B_SHIFT          (3U)
42959 /*! ipp_user_reset_b
42960  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
42961  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
42962  */
42963 #define SRC_SRSR_IPP_USER_RESET_B(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
42964 
42965 #define SRC_SRSR_WDOG_RST_B_MASK                 (0x10U)
42966 #define SRC_SRSR_WDOG_RST_B_SHIFT                (4U)
42967 /*! wdog_rst_b
42968  *  0b0..Reset is not a result of the watchdog time-out event.
42969  *  0b1..Reset is a result of the watchdog time-out event.
42970  */
42971 #define SRC_SRSR_WDOG_RST_B(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
42972 
42973 #define SRC_SRSR_JTAG_RST_B_MASK                 (0x20U)
42974 #define SRC_SRSR_JTAG_RST_B_SHIFT                (5U)
42975 /*! jtag_rst_b
42976  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
42977  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
42978  */
42979 #define SRC_SRSR_JTAG_RST_B(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
42980 
42981 #define SRC_SRSR_JTAG_SW_RST_MASK                (0x40U)
42982 #define SRC_SRSR_JTAG_SW_RST_SHIFT               (6U)
42983 /*! jtag_sw_rst
42984  *  0b0..Reset is not a result of the mentioned case.
42985  *  0b1..Reset is a result of the mentioned case.
42986  */
42987 #define SRC_SRSR_JTAG_SW_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
42988 
42989 #define SRC_SRSR_WDOG3_RST_B_MASK                (0x80U)
42990 #define SRC_SRSR_WDOG3_RST_B_SHIFT               (7U)
42991 /*! wdog3_rst_b
42992  *  0b0..Reset is not a result of the watchdog3 time-out event.
42993  *  0b1..Reset is a result of the watchdog3 time-out event.
42994  */
42995 #define SRC_SRSR_WDOG3_RST_B(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
42996 
42997 #define SRC_SRSR_TEMPSENSE_RST_B_MASK            (0x100U)
42998 #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT           (8U)
42999 /*! tempsense_rst_b
43000  *  0b0..Reset is not a result of software reset from Temperature Sensor.
43001  *  0b1..Reset is a result of software reset from Temperature Sensor.
43002  */
43003 #define SRC_SRSR_TEMPSENSE_RST_B(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
43004 /*! @} */
43005 
43006 /*! @name SBMR2 - SRC Boot Mode Register 2 */
43007 /*! @{ */
43008 
43009 #define SRC_SBMR2_SEC_CONFIG_MASK                (0x3U)
43010 #define SRC_SBMR2_SEC_CONFIG_SHIFT               (0U)
43011 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
43012 
43013 #define SRC_SBMR2_BT_FUSE_SEL_MASK               (0x10U)
43014 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              (4U)
43015 #define SRC_SBMR2_BT_FUSE_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
43016 
43017 #define SRC_SBMR2_BMOD_MASK                      (0x3000000U)
43018 #define SRC_SBMR2_BMOD_SHIFT                     (24U)
43019 #define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
43020 /*! @} */
43021 
43022 /*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */
43023 /*! @{ */
43024 
43025 #define SRC_GPR_PERSISTENT_ARG0_MASK             (0xFFFFFFFFU)
43026 #define SRC_GPR_PERSISTENT_ARG0_SHIFT            (0U)
43027 #define SRC_GPR_PERSISTENT_ARG0(x)               (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
43028 
43029 #define SRC_GPR_PERSISTENT_ENTRY0_MASK           (0xFFFFFFFFU)
43030 #define SRC_GPR_PERSISTENT_ENTRY0_SHIFT          (0U)
43031 #define SRC_GPR_PERSISTENT_ENTRY0(x)             (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
43032 
43033 #define SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK      (0xC000000U)
43034 #define SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT     (26U)
43035 #define SRC_GPR_PERSIST_REDUNDANT_BOOT(x)        (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT)) & SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK)
43036 
43037 #define SRC_GPR_PERSIST_SECONDARY_BOOT_MASK      (0x40000000U)
43038 #define SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT     (30U)
43039 #define SRC_GPR_PERSIST_SECONDARY_BOOT(x)        (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT)) & SRC_GPR_PERSIST_SECONDARY_BOOT_MASK)
43040 /*! @} */
43041 
43042 /* The count of SRC_GPR */
43043 #define SRC_GPR_COUNT                            (10U)
43044 
43045 
43046 /*!
43047  * @}
43048  */ /* end of group SRC_Register_Masks */
43049 
43050 
43051 /* SRC - Peripheral instance base addresses */
43052 /** Peripheral SRC base address */
43053 #define SRC_BASE                                 (0x400F8000u)
43054 /** Peripheral SRC base pointer */
43055 #define SRC                                      ((SRC_Type *)SRC_BASE)
43056 /** Array initializer of SRC peripheral base addresses */
43057 #define SRC_BASE_ADDRS                           { SRC_BASE }
43058 /** Array initializer of SRC peripheral base pointers */
43059 #define SRC_BASE_PTRS                            { SRC }
43060 /** Interrupt vectors for the SRC peripheral type */
43061 #define SRC_IRQS                                 { SRC_IRQn }
43062 /* Backward compatibility */
43063 #define SRC_SCR_MWDR_MASK                      SRC_SCR_MASK_WDOG_RST_MASK
43064 #define SRC_SCR_MWDR_SHIFT                     SRC_SCR_MASK_WDOG_RST_SHIFT
43065 #define SRC_SCR_MWDR(x)                        SRC_SCR_MASK_WDOG_RST(x)
43066 #define SRC_SRSR_WDOG_MASK                     SRC_SRSR_WDOG_RST_B_MASK
43067 #define SRC_SRSR_WDOG_SHIFT                    SRC_SRSR_WDOG_RST_B_SHIFT
43068 #define SRC_SRSR_WDOG(x)                       SRC_SRSR_WDOG_RST_B(x)
43069 #define SRC_SRSR_JTAG_MASK                     SRC_SRSR_JTAG_RST_B_MASK
43070 #define SRC_SRSR_JTAG_SHIFT                    SRC_SRSR_JTAG_RST_B_SHIFT
43071 #define SRC_SRSR_JTAG(x)                       SRC_SRSR_JTAG_RST_B(x)
43072 #define SRC_SRSR_SJC_MASK                      SRC_SRSR_JTAG_SW_RST_MASK
43073 #define SRC_SRSR_SJC_SHIFT                     SRC_SRSR_JTAG_SW_RST_SHIFT
43074 #define SRC_SRSR_SJC(x)                        SRC_SRSR_JTAG_SW_RST(x)
43075 #define SRC_SRSR_TSR_MASK                      SRC_SRSR_TEMPSENSE_RST_B_MASK
43076 #define SRC_SRSR_TSR_SHIFT                     SRC_SRSR_TEMPSENSE_RST_B_SHIFT
43077 #define SRC_SRSR_TSR(x)                        SRC_SRSR_TEMPSENSE_RST_B(x)
43078 /* Extra definition */
43079 #define SRC_SRSR_W1C_BITS_MASK  ( SRC_SRSR_WDOG3_RST_B_MASK \
43080                                 | SRC_SRSR_JTAG_SW_RST_MASK \
43081                                 | SRC_SRSR_JTAG_RST_B_MASK \
43082                                 | SRC_SRSR_WDOG_RST_B_MASK \
43083                                 | SRC_SRSR_IPP_USER_RESET_B_MASK \
43084                                 | SRC_SRSR_CSU_RESET_B_MASK \
43085                                 | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
43086                                 | SRC_SRSR_IPP_RESET_B_MASK)
43087 
43088 
43089 /*!
43090  * @}
43091  */ /* end of group SRC_Peripheral_Access_Layer */
43092 
43093 
43094 /* ----------------------------------------------------------------------------
43095    -- TEMPMON Peripheral Access Layer
43096    ---------------------------------------------------------------------------- */
43097 
43098 /*!
43099  * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
43100  * @{
43101  */
43102 
43103 /** TEMPMON - Register Layout Typedef */
43104 typedef struct {
43105        uint8_t RESERVED_0[384];
43106   __IO uint32_t TEMPSENSE0;                        /**< Tempsensor Control Register 0, offset: 0x180 */
43107   __IO uint32_t TEMPSENSE0_SET;                    /**< Tempsensor Control Register 0, offset: 0x184 */
43108   __IO uint32_t TEMPSENSE0_CLR;                    /**< Tempsensor Control Register 0, offset: 0x188 */
43109   __IO uint32_t TEMPSENSE0_TOG;                    /**< Tempsensor Control Register 0, offset: 0x18C */
43110   __IO uint32_t TEMPSENSE1;                        /**< Tempsensor Control Register 1, offset: 0x190 */
43111   __IO uint32_t TEMPSENSE1_SET;                    /**< Tempsensor Control Register 1, offset: 0x194 */
43112   __IO uint32_t TEMPSENSE1_CLR;                    /**< Tempsensor Control Register 1, offset: 0x198 */
43113   __IO uint32_t TEMPSENSE1_TOG;                    /**< Tempsensor Control Register 1, offset: 0x19C */
43114        uint8_t RESERVED_1[240];
43115   __IO uint32_t TEMPSENSE2;                        /**< Tempsensor Control Register 2, offset: 0x290 */
43116   __IO uint32_t TEMPSENSE2_SET;                    /**< Tempsensor Control Register 2, offset: 0x294 */
43117   __IO uint32_t TEMPSENSE2_CLR;                    /**< Tempsensor Control Register 2, offset: 0x298 */
43118   __IO uint32_t TEMPSENSE2_TOG;                    /**< Tempsensor Control Register 2, offset: 0x29C */
43119 } TEMPMON_Type;
43120 
43121 /* ----------------------------------------------------------------------------
43122    -- TEMPMON Register Masks
43123    ---------------------------------------------------------------------------- */
43124 
43125 /*!
43126  * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks
43127  * @{
43128  */
43129 
43130 /*! @name TEMPSENSE0 - Tempsensor Control Register 0 */
43131 /*! @{ */
43132 
43133 #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK       (0x1U)
43134 #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT      (0U)
43135 /*! POWER_DOWN
43136  *  0b0..Enable power to the temperature sensor.
43137  *  0b1..Power down the temperature sensor.
43138  */
43139 #define TEMPMON_TEMPSENSE0_POWER_DOWN(x)         (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
43140 
43141 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK     (0x2U)
43142 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT    (1U)
43143 /*! MEASURE_TEMP
43144  *  0b0..Do not start the measurement process.
43145  *  0b1..Start the measurement process.
43146  */
43147 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
43148 
43149 #define TEMPMON_TEMPSENSE0_FINISHED_MASK         (0x4U)
43150 #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT        (2U)
43151 /*! FINISHED
43152  *  0b0..Last measurement is not ready yet.
43153  *  0b1..Last measurement is valid.
43154  */
43155 #define TEMPMON_TEMPSENSE0_FINISHED(x)           (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
43156 
43157 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK         (0xFFF00U)
43158 #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT        (8U)
43159 #define TEMPMON_TEMPSENSE0_TEMP_CNT(x)           (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
43160 
43161 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK      (0xFFF00000U)
43162 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT     (20U)
43163 #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x)        (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
43164 /*! @} */
43165 
43166 /*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */
43167 /*! @{ */
43168 
43169 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK   (0x1U)
43170 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT  (0U)
43171 /*! POWER_DOWN
43172  *  0b0..Enable power to the temperature sensor.
43173  *  0b1..Power down the temperature sensor.
43174  */
43175 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
43176 
43177 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
43178 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
43179 /*! MEASURE_TEMP
43180  *  0b0..Do not start the measurement process.
43181  *  0b1..Start the measurement process.
43182  */
43183 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
43184 
43185 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK     (0x4U)
43186 #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT    (2U)
43187 /*! FINISHED
43188  *  0b0..Last measurement is not ready yet.
43189  *  0b1..Last measurement is valid.
43190  */
43191 #define TEMPMON_TEMPSENSE0_SET_FINISHED(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
43192 
43193 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK     (0xFFF00U)
43194 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT    (8U)
43195 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
43196 
43197 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK  (0xFFF00000U)
43198 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
43199 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
43200 /*! @} */
43201 
43202 /*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */
43203 /*! @{ */
43204 
43205 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK   (0x1U)
43206 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT  (0U)
43207 /*! POWER_DOWN
43208  *  0b0..Enable power to the temperature sensor.
43209  *  0b1..Power down the temperature sensor.
43210  */
43211 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
43212 
43213 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
43214 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
43215 /*! MEASURE_TEMP
43216  *  0b0..Do not start the measurement process.
43217  *  0b1..Start the measurement process.
43218  */
43219 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
43220 
43221 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK     (0x4U)
43222 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT    (2U)
43223 /*! FINISHED
43224  *  0b0..Last measurement is not ready yet.
43225  *  0b1..Last measurement is valid.
43226  */
43227 #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
43228 
43229 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK     (0xFFF00U)
43230 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT    (8U)
43231 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
43232 
43233 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK  (0xFFF00000U)
43234 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
43235 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
43236 /*! @} */
43237 
43238 /*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */
43239 /*! @{ */
43240 
43241 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK   (0x1U)
43242 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT  (0U)
43243 /*! POWER_DOWN
43244  *  0b0..Enable power to the temperature sensor.
43245  *  0b1..Power down the temperature sensor.
43246  */
43247 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
43248 
43249 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
43250 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
43251 /*! MEASURE_TEMP
43252  *  0b0..Do not start the measurement process.
43253  *  0b1..Start the measurement process.
43254  */
43255 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
43256 
43257 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK     (0x4U)
43258 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT    (2U)
43259 /*! FINISHED
43260  *  0b0..Last measurement is not ready yet.
43261  *  0b1..Last measurement is valid.
43262  */
43263 #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
43264 
43265 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK     (0xFFF00U)
43266 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT    (8U)
43267 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
43268 
43269 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK  (0xFFF00000U)
43270 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
43271 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
43272 /*! @} */
43273 
43274 /*! @name TEMPSENSE1 - Tempsensor Control Register 1 */
43275 /*! @{ */
43276 
43277 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK     (0xFFFFU)
43278 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT    (0U)
43279 /*! MEASURE_FREQ
43280  *  0b0000000000000000..Defines a single measurement with no repeat.
43281  *  0b0000000000000001..Updates the temperature value at a RTC clock rate.
43282  *  0b0000000000000010..Updates the temperature value at a RTC/2 clock rate.
43283  *  0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.
43284  */
43285 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
43286 /*! @} */
43287 
43288 /*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */
43289 /*! @{ */
43290 
43291 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
43292 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
43293 /*! MEASURE_FREQ
43294  *  0b0000000000000000..Defines a single measurement with no repeat.
43295  *  0b0000000000000001..Updates the temperature value at a RTC clock rate.
43296  *  0b0000000000000010..Updates the temperature value at a RTC/2 clock rate.
43297  *  0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.
43298  */
43299 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
43300 /*! @} */
43301 
43302 /*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */
43303 /*! @{ */
43304 
43305 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
43306 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
43307 /*! MEASURE_FREQ
43308  *  0b0000000000000000..Defines a single measurement with no repeat.
43309  *  0b0000000000000001..Updates the temperature value at a RTC clock rate.
43310  *  0b0000000000000010..Updates the temperature value at a RTC/2 clock rate.
43311  *  0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.
43312  */
43313 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
43314 /*! @} */
43315 
43316 /*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */
43317 /*! @{ */
43318 
43319 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
43320 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
43321 /*! MEASURE_FREQ
43322  *  0b0000000000000000..Defines a single measurement with no repeat.
43323  *  0b0000000000000001..Updates the temperature value at a RTC clock rate.
43324  *  0b0000000000000010..Updates the temperature value at a RTC/2 clock rate.
43325  *  0b1111111111111111..Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock.
43326  */
43327 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
43328 /*! @} */
43329 
43330 /*! @name TEMPSENSE2 - Tempsensor Control Register 2 */
43331 /*! @{ */
43332 
43333 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK  (0xFFFU)
43334 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
43335 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x)    (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
43336 
43337 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43338 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
43339 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
43340 /*! @} */
43341 
43342 /*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */
43343 /*! @{ */
43344 
43345 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
43346 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
43347 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
43348 
43349 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43350 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
43351 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
43352 /*! @} */
43353 
43354 /*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */
43355 /*! @{ */
43356 
43357 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
43358 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
43359 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
43360 
43361 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43362 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
43363 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
43364 /*! @} */
43365 
43366 /*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */
43367 /*! @{ */
43368 
43369 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
43370 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
43371 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
43372 
43373 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43374 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
43375 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
43376 /*! @} */
43377 
43378 
43379 /*!
43380  * @}
43381  */ /* end of group TEMPMON_Register_Masks */
43382 
43383 
43384 /* TEMPMON - Peripheral instance base addresses */
43385 /** Peripheral TEMPMON base address */
43386 #define TEMPMON_BASE                             (0x400D8000u)
43387 /** Peripheral TEMPMON base pointer */
43388 #define TEMPMON                                  ((TEMPMON_Type *)TEMPMON_BASE)
43389 /** Array initializer of TEMPMON peripheral base addresses */
43390 #define TEMPMON_BASE_ADDRS                       { TEMPMON_BASE }
43391 /** Array initializer of TEMPMON peripheral base pointers */
43392 #define TEMPMON_BASE_PTRS                        { TEMPMON }
43393 
43394 /*!
43395  * @}
43396  */ /* end of group TEMPMON_Peripheral_Access_Layer */
43397 
43398 
43399 /* ----------------------------------------------------------------------------
43400    -- TMR Peripheral Access Layer
43401    ---------------------------------------------------------------------------- */
43402 
43403 /*!
43404  * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
43405  * @{
43406  */
43407 
43408 /** TMR - Register Layout Typedef */
43409 typedef struct {
43410   struct {                                         /* offset: 0x0, array step: 0x20 */
43411     __IO uint16_t COMP1;                             /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
43412     __IO uint16_t COMP2;                             /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
43413     __IO uint16_t CAPT;                              /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
43414     __IO uint16_t LOAD;                              /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
43415     __IO uint16_t HOLD;                              /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
43416     __IO uint16_t CNTR;                              /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
43417     __IO uint16_t CTRL;                              /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
43418     __IO uint16_t SCTRL;                             /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
43419     __IO uint16_t CMPLD1;                            /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
43420     __IO uint16_t CMPLD2;                            /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
43421     __IO uint16_t CSCTRL;                            /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
43422     __IO uint16_t FILT;                              /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
43423     __IO uint16_t DMA;                               /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
43424          uint8_t RESERVED_0[4];
43425     __IO uint16_t ENBL;                              /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */
43426   } CHANNEL[4];
43427 } TMR_Type;
43428 
43429 /* ----------------------------------------------------------------------------
43430    -- TMR Register Masks
43431    ---------------------------------------------------------------------------- */
43432 
43433 /*!
43434  * @addtogroup TMR_Register_Masks TMR Register Masks
43435  * @{
43436  */
43437 
43438 /*! @name COMP1 - Timer Channel Compare Register 1 */
43439 /*! @{ */
43440 
43441 #define TMR_COMP1_COMPARISON_1_MASK              (0xFFFFU)
43442 #define TMR_COMP1_COMPARISON_1_SHIFT             (0U)
43443 /*! COMPARISON_1 - Comparison Value 1
43444  */
43445 #define TMR_COMP1_COMPARISON_1(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
43446 /*! @} */
43447 
43448 /* The count of TMR_COMP1 */
43449 #define TMR_COMP1_COUNT                          (4U)
43450 
43451 /*! @name COMP2 - Timer Channel Compare Register 2 */
43452 /*! @{ */
43453 
43454 #define TMR_COMP2_COMPARISON_2_MASK              (0xFFFFU)
43455 #define TMR_COMP2_COMPARISON_2_SHIFT             (0U)
43456 /*! COMPARISON_2 - Comparison Value 2
43457  */
43458 #define TMR_COMP2_COMPARISON_2(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
43459 /*! @} */
43460 
43461 /* The count of TMR_COMP2 */
43462 #define TMR_COMP2_COUNT                          (4U)
43463 
43464 /*! @name CAPT - Timer Channel Capture Register */
43465 /*! @{ */
43466 
43467 #define TMR_CAPT_CAPTURE_MASK                    (0xFFFFU)
43468 #define TMR_CAPT_CAPTURE_SHIFT                   (0U)
43469 /*! CAPTURE - Capture Value
43470  */
43471 #define TMR_CAPT_CAPTURE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
43472 /*! @} */
43473 
43474 /* The count of TMR_CAPT */
43475 #define TMR_CAPT_COUNT                           (4U)
43476 
43477 /*! @name LOAD - Timer Channel Load Register */
43478 /*! @{ */
43479 
43480 #define TMR_LOAD_LOAD_MASK                       (0xFFFFU)
43481 #define TMR_LOAD_LOAD_SHIFT                      (0U)
43482 /*! LOAD - Timer Load Register
43483  */
43484 #define TMR_LOAD_LOAD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
43485 /*! @} */
43486 
43487 /* The count of TMR_LOAD */
43488 #define TMR_LOAD_COUNT                           (4U)
43489 
43490 /*! @name HOLD - Timer Channel Hold Register */
43491 /*! @{ */
43492 
43493 #define TMR_HOLD_HOLD_MASK                       (0xFFFFU)
43494 #define TMR_HOLD_HOLD_SHIFT                      (0U)
43495 #define TMR_HOLD_HOLD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
43496 /*! @} */
43497 
43498 /* The count of TMR_HOLD */
43499 #define TMR_HOLD_COUNT                           (4U)
43500 
43501 /*! @name CNTR - Timer Channel Counter Register */
43502 /*! @{ */
43503 
43504 #define TMR_CNTR_COUNTER_MASK                    (0xFFFFU)
43505 #define TMR_CNTR_COUNTER_SHIFT                   (0U)
43506 #define TMR_CNTR_COUNTER(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
43507 /*! @} */
43508 
43509 /* The count of TMR_CNTR */
43510 #define TMR_CNTR_COUNT                           (4U)
43511 
43512 /*! @name CTRL - Timer Channel Control Register */
43513 /*! @{ */
43514 
43515 #define TMR_CTRL_OUTMODE_MASK                    (0x7U)
43516 #define TMR_CTRL_OUTMODE_SHIFT                   (0U)
43517 /*! OUTMODE - Output Mode
43518  *  0b000..Asserted while counter is active
43519  *  0b001..Clear OFLAG output on successful compare
43520  *  0b010..Set OFLAG output on successful compare
43521  *  0b011..Toggle OFLAG output on successful compare
43522  *  0b100..Toggle OFLAG output using alternating compare registers
43523  *  0b101..Set on compare, cleared on secondary source input edge
43524  *  0b110..Set on compare, cleared on counter rollover
43525  *  0b111..Enable gated clock output while counter is active
43526  */
43527 #define TMR_CTRL_OUTMODE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
43528 
43529 #define TMR_CTRL_COINIT_MASK                     (0x8U)
43530 #define TMR_CTRL_COINIT_SHIFT                    (3U)
43531 /*! COINIT - Co-Channel Initialization
43532  *  0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
43533  *  0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
43534  */
43535 #define TMR_CTRL_COINIT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
43536 
43537 #define TMR_CTRL_DIR_MASK                        (0x10U)
43538 #define TMR_CTRL_DIR_SHIFT                       (4U)
43539 /*! DIR - Count Direction
43540  *  0b0..Count up.
43541  *  0b1..Count down.
43542  */
43543 #define TMR_CTRL_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
43544 
43545 #define TMR_CTRL_LENGTH_MASK                     (0x20U)
43546 #define TMR_CTRL_LENGTH_SHIFT                    (5U)
43547 /*! LENGTH - Count Length
43548  *  0b0..Count until roll over at $FFFF and continue from $0000.
43549  *  0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
43550  *       reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
43551  *       When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
43552  *       comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
43553  *       value is reached, re-initializes, counts until COMP1 value is reached, and so on.
43554  */
43555 #define TMR_CTRL_LENGTH(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
43556 
43557 #define TMR_CTRL_ONCE_MASK                       (0x40U)
43558 #define TMR_CTRL_ONCE_SHIFT                      (6U)
43559 /*! ONCE - Count Once
43560  *  0b0..Count repeatedly.
43561  *  0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
43562  *       COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
43563  *       output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
43564  *       the COMP2 value, and then stops.
43565  */
43566 #define TMR_CTRL_ONCE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
43567 
43568 #define TMR_CTRL_SCS_MASK                        (0x180U)
43569 #define TMR_CTRL_SCS_SHIFT                       (7U)
43570 /*! SCS - Secondary Count Source
43571  *  0b00..Counter 0 input pin
43572  *  0b01..Counter 1 input pin
43573  *  0b10..Counter 2 input pin
43574  *  0b11..Counter 3 input pin
43575  */
43576 #define TMR_CTRL_SCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
43577 
43578 #define TMR_CTRL_PCS_MASK                        (0x1E00U)
43579 #define TMR_CTRL_PCS_SHIFT                       (9U)
43580 /*! PCS - Primary Count Source
43581  *  0b0000..Counter 0 input pin
43582  *  0b0001..Counter 1 input pin
43583  *  0b0010..Counter 2 input pin
43584  *  0b0011..Counter 3 input pin
43585  *  0b0100..Counter 0 output
43586  *  0b0101..Counter 1 output
43587  *  0b0110..Counter 2 output
43588  *  0b0111..Counter 3 output
43589  *  0b1000..IP bus clock divide by 1 prescaler
43590  *  0b1001..IP bus clock divide by 2 prescaler
43591  *  0b1010..IP bus clock divide by 4 prescaler
43592  *  0b1011..IP bus clock divide by 8 prescaler
43593  *  0b1100..IP bus clock divide by 16 prescaler
43594  *  0b1101..IP bus clock divide by 32 prescaler
43595  *  0b1110..IP bus clock divide by 64 prescaler
43596  *  0b1111..IP bus clock divide by 128 prescaler
43597  */
43598 #define TMR_CTRL_PCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
43599 
43600 #define TMR_CTRL_CM_MASK                         (0xE000U)
43601 #define TMR_CTRL_CM_SHIFT                        (13U)
43602 /*! CM - Count Mode
43603  *  0b000..No operation
43604  *  0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
43605  *         are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
43606  *         edges are counted regardless of the value of SCTRL[IPS].
43607  *  0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
43608  *  0b011..Count rising edges of primary source while secondary input high active
43609  *  0b100..Quadrature count mode, uses primary and secondary sources
43610  *  0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
43611  *         when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
43612  *  0b110..Edge of secondary source triggers primary count until compare
43613  *  0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
43614  */
43615 #define TMR_CTRL_CM(x)                           (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
43616 /*! @} */
43617 
43618 /* The count of TMR_CTRL */
43619 #define TMR_CTRL_COUNT                           (4U)
43620 
43621 /*! @name SCTRL - Timer Channel Status and Control Register */
43622 /*! @{ */
43623 
43624 #define TMR_SCTRL_OEN_MASK                       (0x1U)
43625 #define TMR_SCTRL_OEN_SHIFT                      (0U)
43626 /*! OEN - Output Enable
43627  *  0b0..The external pin is configured as an input.
43628  *  0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
43629  *       their input see the driven value. The polarity of the signal is determined by OPS.
43630  */
43631 #define TMR_SCTRL_OEN(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
43632 
43633 #define TMR_SCTRL_OPS_MASK                       (0x2U)
43634 #define TMR_SCTRL_OPS_SHIFT                      (1U)
43635 /*! OPS - Output Polarity Select
43636  *  0b0..True polarity.
43637  *  0b1..Inverted polarity.
43638  */
43639 #define TMR_SCTRL_OPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
43640 
43641 #define TMR_SCTRL_FORCE_MASK                     (0x4U)
43642 #define TMR_SCTRL_FORCE_SHIFT                    (2U)
43643 /*! FORCE - Force OFLAG Output
43644  */
43645 #define TMR_SCTRL_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
43646 
43647 #define TMR_SCTRL_VAL_MASK                       (0x8U)
43648 #define TMR_SCTRL_VAL_SHIFT                      (3U)
43649 /*! VAL - Forced OFLAG Value
43650  */
43651 #define TMR_SCTRL_VAL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
43652 
43653 #define TMR_SCTRL_EEOF_MASK                      (0x10U)
43654 #define TMR_SCTRL_EEOF_SHIFT                     (4U)
43655 /*! EEOF - Enable External OFLAG Force
43656  */
43657 #define TMR_SCTRL_EEOF(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
43658 
43659 #define TMR_SCTRL_MSTR_MASK                      (0x20U)
43660 #define TMR_SCTRL_MSTR_SHIFT                     (5U)
43661 /*! MSTR - Master Mode
43662  */
43663 #define TMR_SCTRL_MSTR(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
43664 
43665 #define TMR_SCTRL_CAPTURE_MODE_MASK              (0xC0U)
43666 #define TMR_SCTRL_CAPTURE_MODE_SHIFT             (6U)
43667 /*! CAPTURE_MODE - Input Capture Mode
43668  *  0b00..Capture function is disabled
43669  *  0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
43670  *  0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
43671  *  0b11..Load capture register on both edges of input
43672  */
43673 #define TMR_SCTRL_CAPTURE_MODE(x)                (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
43674 
43675 #define TMR_SCTRL_INPUT_MASK                     (0x100U)
43676 #define TMR_SCTRL_INPUT_SHIFT                    (8U)
43677 /*! INPUT - External Input Signal
43678  */
43679 #define TMR_SCTRL_INPUT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
43680 
43681 #define TMR_SCTRL_IPS_MASK                       (0x200U)
43682 #define TMR_SCTRL_IPS_SHIFT                      (9U)
43683 /*! IPS - Input Polarity Select
43684  */
43685 #define TMR_SCTRL_IPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
43686 
43687 #define TMR_SCTRL_IEFIE_MASK                     (0x400U)
43688 #define TMR_SCTRL_IEFIE_SHIFT                    (10U)
43689 /*! IEFIE - Input Edge Flag Interrupt Enable
43690  */
43691 #define TMR_SCTRL_IEFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
43692 
43693 #define TMR_SCTRL_IEF_MASK                       (0x800U)
43694 #define TMR_SCTRL_IEF_SHIFT                      (11U)
43695 /*! IEF - Input Edge Flag
43696  */
43697 #define TMR_SCTRL_IEF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
43698 
43699 #define TMR_SCTRL_TOFIE_MASK                     (0x1000U)
43700 #define TMR_SCTRL_TOFIE_SHIFT                    (12U)
43701 /*! TOFIE - Timer Overflow Flag Interrupt Enable
43702  */
43703 #define TMR_SCTRL_TOFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
43704 
43705 #define TMR_SCTRL_TOF_MASK                       (0x2000U)
43706 #define TMR_SCTRL_TOF_SHIFT                      (13U)
43707 /*! TOF - Timer Overflow Flag
43708  */
43709 #define TMR_SCTRL_TOF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
43710 
43711 #define TMR_SCTRL_TCFIE_MASK                     (0x4000U)
43712 #define TMR_SCTRL_TCFIE_SHIFT                    (14U)
43713 /*! TCFIE - Timer Compare Flag Interrupt Enable
43714  */
43715 #define TMR_SCTRL_TCFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
43716 
43717 #define TMR_SCTRL_TCF_MASK                       (0x8000U)
43718 #define TMR_SCTRL_TCF_SHIFT                      (15U)
43719 /*! TCF - Timer Compare Flag
43720  */
43721 #define TMR_SCTRL_TCF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
43722 /*! @} */
43723 
43724 /* The count of TMR_SCTRL */
43725 #define TMR_SCTRL_COUNT                          (4U)
43726 
43727 /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
43728 /*! @{ */
43729 
43730 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK        (0xFFFFU)
43731 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT       (0U)
43732 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
43733 /*! @} */
43734 
43735 /* The count of TMR_CMPLD1 */
43736 #define TMR_CMPLD1_COUNT                         (4U)
43737 
43738 /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
43739 /*! @{ */
43740 
43741 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK        (0xFFFFU)
43742 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT       (0U)
43743 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
43744 /*! @} */
43745 
43746 /* The count of TMR_CMPLD2 */
43747 #define TMR_CMPLD2_COUNT                         (4U)
43748 
43749 /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
43750 /*! @{ */
43751 
43752 #define TMR_CSCTRL_CL1_MASK                      (0x3U)
43753 #define TMR_CSCTRL_CL1_SHIFT                     (0U)
43754 /*! CL1 - Compare Load Control 1
43755  *  0b00..Never preload
43756  *  0b01..Load upon successful compare with the value in COMP1
43757  *  0b10..Load upon successful compare with the value in COMP2
43758  *  0b11..Reserved
43759  */
43760 #define TMR_CSCTRL_CL1(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
43761 
43762 #define TMR_CSCTRL_CL2_MASK                      (0xCU)
43763 #define TMR_CSCTRL_CL2_SHIFT                     (2U)
43764 /*! CL2 - Compare Load Control 2
43765  *  0b00..Never preload
43766  *  0b01..Load upon successful compare with the value in COMP1
43767  *  0b10..Load upon successful compare with the value in COMP2
43768  *  0b11..Reserved
43769  */
43770 #define TMR_CSCTRL_CL2(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
43771 
43772 #define TMR_CSCTRL_TCF1_MASK                     (0x10U)
43773 #define TMR_CSCTRL_TCF1_SHIFT                    (4U)
43774 /*! TCF1 - Timer Compare 1 Interrupt Flag
43775  */
43776 #define TMR_CSCTRL_TCF1(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
43777 
43778 #define TMR_CSCTRL_TCF2_MASK                     (0x20U)
43779 #define TMR_CSCTRL_TCF2_SHIFT                    (5U)
43780 /*! TCF2 - Timer Compare 2 Interrupt Flag
43781  */
43782 #define TMR_CSCTRL_TCF2(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
43783 
43784 #define TMR_CSCTRL_TCF1EN_MASK                   (0x40U)
43785 #define TMR_CSCTRL_TCF1EN_SHIFT                  (6U)
43786 /*! TCF1EN - Timer Compare 1 Interrupt Enable
43787  */
43788 #define TMR_CSCTRL_TCF1EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
43789 
43790 #define TMR_CSCTRL_TCF2EN_MASK                   (0x80U)
43791 #define TMR_CSCTRL_TCF2EN_SHIFT                  (7U)
43792 /*! TCF2EN - Timer Compare 2 Interrupt Enable
43793  */
43794 #define TMR_CSCTRL_TCF2EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
43795 
43796 #define TMR_CSCTRL_UP_MASK                       (0x200U)
43797 #define TMR_CSCTRL_UP_SHIFT                      (9U)
43798 /*! UP - Counting Direction Indicator
43799  *  0b0..The last count was in the DOWN direction.
43800  *  0b1..The last count was in the UP direction.
43801  */
43802 #define TMR_CSCTRL_UP(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
43803 
43804 #define TMR_CSCTRL_TCI_MASK                      (0x400U)
43805 #define TMR_CSCTRL_TCI_SHIFT                     (10U)
43806 /*! TCI - Triggered Count Initialization Control
43807  *  0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
43808  *  0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
43809  */
43810 #define TMR_CSCTRL_TCI(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
43811 
43812 #define TMR_CSCTRL_ROC_MASK                      (0x800U)
43813 #define TMR_CSCTRL_ROC_SHIFT                     (11U)
43814 /*! ROC - Reload on Capture
43815  *  0b0..Do not reload the counter on a capture event.
43816  *  0b1..Reload the counter on a capture event.
43817  */
43818 #define TMR_CSCTRL_ROC(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
43819 
43820 #define TMR_CSCTRL_ALT_LOAD_MASK                 (0x1000U)
43821 #define TMR_CSCTRL_ALT_LOAD_SHIFT                (12U)
43822 /*! ALT_LOAD - Alternative Load Enable
43823  *  0b0..Counter can be re-initialized only with the LOAD register.
43824  *  0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
43825  */
43826 #define TMR_CSCTRL_ALT_LOAD(x)                   (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
43827 
43828 #define TMR_CSCTRL_FAULT_MASK                    (0x2000U)
43829 #define TMR_CSCTRL_FAULT_SHIFT                   (13U)
43830 /*! FAULT - Fault Enable
43831  *  0b0..Fault function disabled.
43832  *  0b1..Fault function enabled.
43833  */
43834 #define TMR_CSCTRL_FAULT(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
43835 
43836 #define TMR_CSCTRL_DBG_EN_MASK                   (0xC000U)
43837 #define TMR_CSCTRL_DBG_EN_SHIFT                  (14U)
43838 /*! DBG_EN - Debug Actions Enable
43839  *  0b00..Continue with normal operation during debug mode. (default)
43840  *  0b01..Halt TMR counter during debug mode.
43841  *  0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
43842  *  0b11..Both halt counter and force output to 0 during debug mode.
43843  */
43844 #define TMR_CSCTRL_DBG_EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
43845 /*! @} */
43846 
43847 /* The count of TMR_CSCTRL */
43848 #define TMR_CSCTRL_COUNT                         (4U)
43849 
43850 /*! @name FILT - Timer Channel Input Filter Register */
43851 /*! @{ */
43852 
43853 #define TMR_FILT_FILT_PER_MASK                   (0xFFU)
43854 #define TMR_FILT_FILT_PER_SHIFT                  (0U)
43855 /*! FILT_PER - Input Filter Sample Period
43856  */
43857 #define TMR_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
43858 
43859 #define TMR_FILT_FILT_CNT_MASK                   (0x700U)
43860 #define TMR_FILT_FILT_CNT_SHIFT                  (8U)
43861 /*! FILT_CNT - Input Filter Sample Count
43862  */
43863 #define TMR_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
43864 /*! @} */
43865 
43866 /* The count of TMR_FILT */
43867 #define TMR_FILT_COUNT                           (4U)
43868 
43869 /*! @name DMA - Timer Channel DMA Enable Register */
43870 /*! @{ */
43871 
43872 #define TMR_DMA_IEFDE_MASK                       (0x1U)
43873 #define TMR_DMA_IEFDE_SHIFT                      (0U)
43874 /*! IEFDE - Input Edge Flag DMA Enable
43875  */
43876 #define TMR_DMA_IEFDE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
43877 
43878 #define TMR_DMA_CMPLD1DE_MASK                    (0x2U)
43879 #define TMR_DMA_CMPLD1DE_SHIFT                   (1U)
43880 /*! CMPLD1DE - Comparator Preload Register 1 DMA Enable
43881  */
43882 #define TMR_DMA_CMPLD1DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
43883 
43884 #define TMR_DMA_CMPLD2DE_MASK                    (0x4U)
43885 #define TMR_DMA_CMPLD2DE_SHIFT                   (2U)
43886 /*! CMPLD2DE - Comparator Preload Register 2 DMA Enable
43887  */
43888 #define TMR_DMA_CMPLD2DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
43889 /*! @} */
43890 
43891 /* The count of TMR_DMA */
43892 #define TMR_DMA_COUNT                            (4U)
43893 
43894 /*! @name ENBL - Timer Channel Enable Register */
43895 /*! @{ */
43896 
43897 #define TMR_ENBL_ENBL_MASK                       (0xFU)
43898 #define TMR_ENBL_ENBL_SHIFT                      (0U)
43899 /*! ENBL - Timer Channel Enable
43900  *  0b0000..Timer channel is disabled.
43901  *  0b0001..Timer channel is enabled. (default)
43902  */
43903 #define TMR_ENBL_ENBL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
43904 /*! @} */
43905 
43906 /* The count of TMR_ENBL */
43907 #define TMR_ENBL_COUNT                           (4U)
43908 
43909 
43910 /*!
43911  * @}
43912  */ /* end of group TMR_Register_Masks */
43913 
43914 
43915 /* TMR - Peripheral instance base addresses */
43916 /** Peripheral TMR1 base address */
43917 #define TMR1_BASE                                (0x401DC000u)
43918 /** Peripheral TMR1 base pointer */
43919 #define TMR1                                     ((TMR_Type *)TMR1_BASE)
43920 /** Peripheral TMR2 base address */
43921 #define TMR2_BASE                                (0x401E0000u)
43922 /** Peripheral TMR2 base pointer */
43923 #define TMR2                                     ((TMR_Type *)TMR2_BASE)
43924 /** Peripheral TMR3 base address */
43925 #define TMR3_BASE                                (0x401E4000u)
43926 /** Peripheral TMR3 base pointer */
43927 #define TMR3                                     ((TMR_Type *)TMR3_BASE)
43928 /** Peripheral TMR4 base address */
43929 #define TMR4_BASE                                (0x401E8000u)
43930 /** Peripheral TMR4 base pointer */
43931 #define TMR4                                     ((TMR_Type *)TMR4_BASE)
43932 /** Array initializer of TMR peripheral base addresses */
43933 #define TMR_BASE_ADDRS                           { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
43934 /** Array initializer of TMR peripheral base pointers */
43935 #define TMR_BASE_PTRS                            { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
43936 /** Interrupt vectors for the TMR peripheral type */
43937 #define TMR_IRQS                                 { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
43938 
43939 /*!
43940  * @}
43941  */ /* end of group TMR_Peripheral_Access_Layer */
43942 
43943 
43944 /* ----------------------------------------------------------------------------
43945    -- TRNG Peripheral Access Layer
43946    ---------------------------------------------------------------------------- */
43947 
43948 /*!
43949  * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
43950  * @{
43951  */
43952 
43953 /** TRNG - Register Layout Typedef */
43954 typedef struct {
43955   __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
43956   __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
43957   __IO uint32_t PKRRNG;                            /**< Poker Range Register, offset: 0x8 */
43958   union {                                          /* offset: 0xC */
43959     __IO uint32_t PKRMAX;                            /**< Poker Maximum Limit Register, offset: 0xC */
43960     __I  uint32_t PKRSQ;                             /**< Poker Square Calculation Result Register, offset: 0xC */
43961   };
43962   __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
43963   union {                                          /* offset: 0x14 */
43964     __IO uint32_t SBLIM;                             /**< Sparse Bit Limit Register, offset: 0x14 */
43965     __I  uint32_t TOTSAM;                            /**< Total Samples Register, offset: 0x14 */
43966   };
43967   __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
43968   union {                                          /* offset: 0x1C */
43969     __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
43970     __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
43971   };
43972   union {                                          /* offset: 0x20 */
43973     __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
43974     __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
43975   };
43976   union {                                          /* offset: 0x24 */
43977     __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
43978     __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
43979   };
43980   union {                                          /* offset: 0x28 */
43981     __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
43982     __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
43983   };
43984   union {                                          /* offset: 0x2C */
43985     __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
43986     __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
43987   };
43988   union {                                          /* offset: 0x30 */
43989     __I  uint32_t SCR4C;                             /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
43990     __IO uint32_t SCR4L;                             /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
43991   };
43992   union {                                          /* offset: 0x34 */
43993     __I  uint32_t SCR5C;                             /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
43994     __IO uint32_t SCR5L;                             /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
43995   };
43996   union {                                          /* offset: 0x38 */
43997     __I  uint32_t SCR6PC;                            /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
43998     __IO uint32_t SCR6PL;                            /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
43999   };
44000   __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
44001   __I  uint32_t ENT[16];                           /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
44002   __I  uint32_t PKRCNT10;                          /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
44003   __I  uint32_t PKRCNT32;                          /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
44004   __I  uint32_t PKRCNT54;                          /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
44005   __I  uint32_t PKRCNT76;                          /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
44006   __I  uint32_t PKRCNT98;                          /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
44007   __I  uint32_t PKRCNTBA;                          /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
44008   __I  uint32_t PKRCNTDC;                          /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
44009   __I  uint32_t PKRCNTFE;                          /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
44010   __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xA0 */
44011   __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xA4 */
44012   __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xA8 */
44013   __I  uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xAC */
44014        uint8_t RESERVED_0[64];
44015   __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
44016   __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
44017 } TRNG_Type;
44018 
44019 /* ----------------------------------------------------------------------------
44020    -- TRNG Register Masks
44021    ---------------------------------------------------------------------------- */
44022 
44023 /*!
44024  * @addtogroup TRNG_Register_Masks TRNG Register Masks
44025  * @{
44026  */
44027 
44028 /*! @name MCTL - Miscellaneous Control Register */
44029 /*! @{ */
44030 
44031 #define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
44032 #define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
44033 /*! SAMP_MODE
44034  *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
44035  *  0b01..use raw data into both Entropy shifter and Statistical Checker
44036  *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
44037  *  0b11..undefined/reserved.
44038  */
44039 #define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
44040 
44041 #define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
44042 #define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
44043 /*! OSC_DIV
44044  *  0b00..use ring oscillator with no divide
44045  *  0b01..use ring oscillator divided-by-2
44046  *  0b10..use ring oscillator divided-by-4
44047  *  0b11..use ring oscillator divided-by-8
44048  */
44049 #define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
44050 
44051 #define TRNG_MCTL_UNUSED4_MASK                   (0x10U)
44052 #define TRNG_MCTL_UNUSED4_SHIFT                  (4U)
44053 #define TRNG_MCTL_UNUSED4(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
44054 
44055 #define TRNG_MCTL_UNUSED5_MASK                   (0x20U)
44056 #define TRNG_MCTL_UNUSED5_SHIFT                  (5U)
44057 #define TRNG_MCTL_UNUSED5(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
44058 
44059 #define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
44060 #define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
44061 #define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
44062 
44063 #define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
44064 #define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
44065 #define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
44066 
44067 #define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
44068 #define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
44069 #define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
44070 
44071 #define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
44072 #define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
44073 #define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
44074 
44075 #define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
44076 #define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
44077 #define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
44078 
44079 #define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
44080 #define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
44081 #define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
44082 
44083 #define TRNG_MCTL_ERR_MASK                       (0x1000U)
44084 #define TRNG_MCTL_ERR_SHIFT                      (12U)
44085 #define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
44086 
44087 #define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
44088 #define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
44089 #define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
44090 
44091 #define TRNG_MCTL_LRUN_CONT_MASK                 (0x4000U)
44092 #define TRNG_MCTL_LRUN_CONT_SHIFT                (14U)
44093 #define TRNG_MCTL_LRUN_CONT(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
44094 
44095 #define TRNG_MCTL_PRGM_MASK                      (0x10000U)
44096 #define TRNG_MCTL_PRGM_SHIFT                     (16U)
44097 #define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
44098 /*! @} */
44099 
44100 /*! @name SCMISC - Statistical Check Miscellaneous Register */
44101 /*! @{ */
44102 
44103 #define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
44104 #define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
44105 #define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
44106 
44107 #define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
44108 #define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
44109 #define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
44110 /*! @} */
44111 
44112 /*! @name PKRRNG - Poker Range Register */
44113 /*! @{ */
44114 
44115 #define TRNG_PKRRNG_PKR_RNG_MASK                 (0xFFFFU)
44116 #define TRNG_PKRRNG_PKR_RNG_SHIFT                (0U)
44117 #define TRNG_PKRRNG_PKR_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
44118 /*! @} */
44119 
44120 /*! @name PKRMAX - Poker Maximum Limit Register */
44121 /*! @{ */
44122 
44123 #define TRNG_PKRMAX_PKR_MAX_MASK                 (0xFFFFFFU)
44124 #define TRNG_PKRMAX_PKR_MAX_SHIFT                (0U)
44125 /*! PKR_MAX - Poker Maximum Limit.
44126  */
44127 #define TRNG_PKRMAX_PKR_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
44128 /*! @} */
44129 
44130 /*! @name PKRSQ - Poker Square Calculation Result Register */
44131 /*! @{ */
44132 
44133 #define TRNG_PKRSQ_PKR_SQ_MASK                   (0xFFFFFFU)
44134 #define TRNG_PKRSQ_PKR_SQ_SHIFT                  (0U)
44135 /*! PKR_SQ - Poker Square Calculation Result.
44136  */
44137 #define TRNG_PKRSQ_PKR_SQ(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
44138 /*! @} */
44139 
44140 /*! @name SDCTL - Seed Control Register */
44141 /*! @{ */
44142 
44143 #define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
44144 #define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
44145 #define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
44146 
44147 #define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
44148 #define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
44149 #define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
44150 /*! @} */
44151 
44152 /*! @name SBLIM - Sparse Bit Limit Register */
44153 /*! @{ */
44154 
44155 #define TRNG_SBLIM_SB_LIM_MASK                   (0x3FFU)
44156 #define TRNG_SBLIM_SB_LIM_SHIFT                  (0U)
44157 #define TRNG_SBLIM_SB_LIM(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
44158 /*! @} */
44159 
44160 /*! @name TOTSAM - Total Samples Register */
44161 /*! @{ */
44162 
44163 #define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
44164 #define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
44165 #define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
44166 /*! @} */
44167 
44168 /*! @name FRQMIN - Frequency Count Minimum Limit Register */
44169 /*! @{ */
44170 
44171 #define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
44172 #define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
44173 #define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
44174 /*! @} */
44175 
44176 /*! @name FRQCNT - Frequency Count Register */
44177 /*! @{ */
44178 
44179 #define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
44180 #define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
44181 #define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
44182 /*! @} */
44183 
44184 /*! @name FRQMAX - Frequency Count Maximum Limit Register */
44185 /*! @{ */
44186 
44187 #define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
44188 #define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
44189 #define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
44190 /*! @} */
44191 
44192 /*! @name SCMC - Statistical Check Monobit Count Register */
44193 /*! @{ */
44194 
44195 #define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
44196 #define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
44197 #define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
44198 /*! @} */
44199 
44200 /*! @name SCML - Statistical Check Monobit Limit Register */
44201 /*! @{ */
44202 
44203 #define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
44204 #define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
44205 #define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
44206 
44207 #define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
44208 #define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
44209 #define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
44210 /*! @} */
44211 
44212 /*! @name SCR1C - Statistical Check Run Length 1 Count Register */
44213 /*! @{ */
44214 
44215 #define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
44216 #define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
44217 #define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
44218 
44219 #define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
44220 #define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
44221 #define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
44222 /*! @} */
44223 
44224 /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
44225 /*! @{ */
44226 
44227 #define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
44228 #define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
44229 #define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
44230 
44231 #define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
44232 #define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
44233 #define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
44234 /*! @} */
44235 
44236 /*! @name SCR2C - Statistical Check Run Length 2 Count Register */
44237 /*! @{ */
44238 
44239 #define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
44240 #define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
44241 #define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
44242 
44243 #define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
44244 #define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
44245 #define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
44246 /*! @} */
44247 
44248 /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
44249 /*! @{ */
44250 
44251 #define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
44252 #define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
44253 #define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
44254 
44255 #define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
44256 #define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
44257 #define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
44258 /*! @} */
44259 
44260 /*! @name SCR3C - Statistical Check Run Length 3 Count Register */
44261 /*! @{ */
44262 
44263 #define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
44264 #define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
44265 #define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
44266 
44267 #define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
44268 #define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
44269 #define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
44270 /*! @} */
44271 
44272 /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
44273 /*! @{ */
44274 
44275 #define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
44276 #define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
44277 #define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
44278 
44279 #define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
44280 #define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
44281 #define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
44282 /*! @} */
44283 
44284 /*! @name SCR4C - Statistical Check Run Length 4 Count Register */
44285 /*! @{ */
44286 
44287 #define TRNG_SCR4C_R4_0_CT_MASK                  (0xFFFU)
44288 #define TRNG_SCR4C_R4_0_CT_SHIFT                 (0U)
44289 #define TRNG_SCR4C_R4_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
44290 
44291 #define TRNG_SCR4C_R4_1_CT_MASK                  (0xFFF0000U)
44292 #define TRNG_SCR4C_R4_1_CT_SHIFT                 (16U)
44293 #define TRNG_SCR4C_R4_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
44294 /*! @} */
44295 
44296 /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
44297 /*! @{ */
44298 
44299 #define TRNG_SCR4L_RUN4_MAX_MASK                 (0xFFFU)
44300 #define TRNG_SCR4L_RUN4_MAX_SHIFT                (0U)
44301 #define TRNG_SCR4L_RUN4_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
44302 
44303 #define TRNG_SCR4L_RUN4_RNG_MASK                 (0xFFF0000U)
44304 #define TRNG_SCR4L_RUN4_RNG_SHIFT                (16U)
44305 #define TRNG_SCR4L_RUN4_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
44306 /*! @} */
44307 
44308 /*! @name SCR5C - Statistical Check Run Length 5 Count Register */
44309 /*! @{ */
44310 
44311 #define TRNG_SCR5C_R5_0_CT_MASK                  (0x7FFU)
44312 #define TRNG_SCR5C_R5_0_CT_SHIFT                 (0U)
44313 #define TRNG_SCR5C_R5_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
44314 
44315 #define TRNG_SCR5C_R5_1_CT_MASK                  (0x7FF0000U)
44316 #define TRNG_SCR5C_R5_1_CT_SHIFT                 (16U)
44317 #define TRNG_SCR5C_R5_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
44318 /*! @} */
44319 
44320 /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
44321 /*! @{ */
44322 
44323 #define TRNG_SCR5L_RUN5_MAX_MASK                 (0x7FFU)
44324 #define TRNG_SCR5L_RUN5_MAX_SHIFT                (0U)
44325 #define TRNG_SCR5L_RUN5_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
44326 
44327 #define TRNG_SCR5L_RUN5_RNG_MASK                 (0x7FF0000U)
44328 #define TRNG_SCR5L_RUN5_RNG_SHIFT                (16U)
44329 #define TRNG_SCR5L_RUN5_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
44330 /*! @} */
44331 
44332 /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
44333 /*! @{ */
44334 
44335 #define TRNG_SCR6PC_R6P_0_CT_MASK                (0x7FFU)
44336 #define TRNG_SCR6PC_R6P_0_CT_SHIFT               (0U)
44337 #define TRNG_SCR6PC_R6P_0_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
44338 
44339 #define TRNG_SCR6PC_R6P_1_CT_MASK                (0x7FF0000U)
44340 #define TRNG_SCR6PC_R6P_1_CT_SHIFT               (16U)
44341 #define TRNG_SCR6PC_R6P_1_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
44342 /*! @} */
44343 
44344 /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
44345 /*! @{ */
44346 
44347 #define TRNG_SCR6PL_RUN6P_MAX_MASK               (0x7FFU)
44348 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT              (0U)
44349 #define TRNG_SCR6PL_RUN6P_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
44350 
44351 #define TRNG_SCR6PL_RUN6P_RNG_MASK               (0x7FF0000U)
44352 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT              (16U)
44353 #define TRNG_SCR6PL_RUN6P_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
44354 /*! @} */
44355 
44356 /*! @name STATUS - Status Register */
44357 /*! @{ */
44358 
44359 #define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
44360 #define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
44361 #define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
44362 
44363 #define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
44364 #define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
44365 #define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
44366 
44367 #define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
44368 #define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
44369 #define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
44370 
44371 #define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
44372 #define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
44373 #define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
44374 
44375 #define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
44376 #define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
44377 #define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
44378 
44379 #define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
44380 #define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
44381 #define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
44382 
44383 #define TRNG_STATUS_TF4BR0_MASK                  (0x40U)
44384 #define TRNG_STATUS_TF4BR0_SHIFT                 (6U)
44385 #define TRNG_STATUS_TF4BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
44386 
44387 #define TRNG_STATUS_TF4BR1_MASK                  (0x80U)
44388 #define TRNG_STATUS_TF4BR1_SHIFT                 (7U)
44389 #define TRNG_STATUS_TF4BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
44390 
44391 #define TRNG_STATUS_TF5BR0_MASK                  (0x100U)
44392 #define TRNG_STATUS_TF5BR0_SHIFT                 (8U)
44393 #define TRNG_STATUS_TF5BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
44394 
44395 #define TRNG_STATUS_TF5BR1_MASK                  (0x200U)
44396 #define TRNG_STATUS_TF5BR1_SHIFT                 (9U)
44397 #define TRNG_STATUS_TF5BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
44398 
44399 #define TRNG_STATUS_TF6PBR0_MASK                 (0x400U)
44400 #define TRNG_STATUS_TF6PBR0_SHIFT                (10U)
44401 #define TRNG_STATUS_TF6PBR0(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
44402 
44403 #define TRNG_STATUS_TF6PBR1_MASK                 (0x800U)
44404 #define TRNG_STATUS_TF6PBR1_SHIFT                (11U)
44405 #define TRNG_STATUS_TF6PBR1(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
44406 
44407 #define TRNG_STATUS_TFSB_MASK                    (0x1000U)
44408 #define TRNG_STATUS_TFSB_SHIFT                   (12U)
44409 #define TRNG_STATUS_TFSB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
44410 
44411 #define TRNG_STATUS_TFLR_MASK                    (0x2000U)
44412 #define TRNG_STATUS_TFLR_SHIFT                   (13U)
44413 #define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
44414 
44415 #define TRNG_STATUS_TFP_MASK                     (0x4000U)
44416 #define TRNG_STATUS_TFP_SHIFT                    (14U)
44417 #define TRNG_STATUS_TFP(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
44418 
44419 #define TRNG_STATUS_TFMB_MASK                    (0x8000U)
44420 #define TRNG_STATUS_TFMB_SHIFT                   (15U)
44421 #define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
44422 
44423 #define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
44424 #define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
44425 #define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
44426 /*! @} */
44427 
44428 /*! @name ENT - Entropy Read Register */
44429 /*! @{ */
44430 
44431 #define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
44432 #define TRNG_ENT_ENT_SHIFT                       (0U)
44433 #define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
44434 /*! @} */
44435 
44436 /* The count of TRNG_ENT */
44437 #define TRNG_ENT_COUNT                           (16U)
44438 
44439 /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
44440 /*! @{ */
44441 
44442 #define TRNG_PKRCNT10_PKR_0_CT_MASK              (0xFFFFU)
44443 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT             (0U)
44444 #define TRNG_PKRCNT10_PKR_0_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
44445 
44446 #define TRNG_PKRCNT10_PKR_1_CT_MASK              (0xFFFF0000U)
44447 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT             (16U)
44448 #define TRNG_PKRCNT10_PKR_1_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
44449 /*! @} */
44450 
44451 /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
44452 /*! @{ */
44453 
44454 #define TRNG_PKRCNT32_PKR_2_CT_MASK              (0xFFFFU)
44455 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT             (0U)
44456 #define TRNG_PKRCNT32_PKR_2_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
44457 
44458 #define TRNG_PKRCNT32_PKR_3_CT_MASK              (0xFFFF0000U)
44459 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT             (16U)
44460 #define TRNG_PKRCNT32_PKR_3_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
44461 /*! @} */
44462 
44463 /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
44464 /*! @{ */
44465 
44466 #define TRNG_PKRCNT54_PKR_4_CT_MASK              (0xFFFFU)
44467 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT             (0U)
44468 #define TRNG_PKRCNT54_PKR_4_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
44469 
44470 #define TRNG_PKRCNT54_PKR_5_CT_MASK              (0xFFFF0000U)
44471 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT             (16U)
44472 #define TRNG_PKRCNT54_PKR_5_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
44473 /*! @} */
44474 
44475 /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
44476 /*! @{ */
44477 
44478 #define TRNG_PKRCNT76_PKR_6_CT_MASK              (0xFFFFU)
44479 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT             (0U)
44480 #define TRNG_PKRCNT76_PKR_6_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
44481 
44482 #define TRNG_PKRCNT76_PKR_7_CT_MASK              (0xFFFF0000U)
44483 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT             (16U)
44484 #define TRNG_PKRCNT76_PKR_7_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
44485 /*! @} */
44486 
44487 /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
44488 /*! @{ */
44489 
44490 #define TRNG_PKRCNT98_PKR_8_CT_MASK              (0xFFFFU)
44491 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT             (0U)
44492 #define TRNG_PKRCNT98_PKR_8_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
44493 
44494 #define TRNG_PKRCNT98_PKR_9_CT_MASK              (0xFFFF0000U)
44495 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT             (16U)
44496 #define TRNG_PKRCNT98_PKR_9_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
44497 /*! @} */
44498 
44499 /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
44500 /*! @{ */
44501 
44502 #define TRNG_PKRCNTBA_PKR_A_CT_MASK              (0xFFFFU)
44503 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT             (0U)
44504 #define TRNG_PKRCNTBA_PKR_A_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
44505 
44506 #define TRNG_PKRCNTBA_PKR_B_CT_MASK              (0xFFFF0000U)
44507 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT             (16U)
44508 #define TRNG_PKRCNTBA_PKR_B_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
44509 /*! @} */
44510 
44511 /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
44512 /*! @{ */
44513 
44514 #define TRNG_PKRCNTDC_PKR_C_CT_MASK              (0xFFFFU)
44515 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT             (0U)
44516 #define TRNG_PKRCNTDC_PKR_C_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
44517 
44518 #define TRNG_PKRCNTDC_PKR_D_CT_MASK              (0xFFFF0000U)
44519 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT             (16U)
44520 #define TRNG_PKRCNTDC_PKR_D_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
44521 /*! @} */
44522 
44523 /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
44524 /*! @{ */
44525 
44526 #define TRNG_PKRCNTFE_PKR_E_CT_MASK              (0xFFFFU)
44527 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT             (0U)
44528 #define TRNG_PKRCNTFE_PKR_E_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
44529 
44530 #define TRNG_PKRCNTFE_PKR_F_CT_MASK              (0xFFFF0000U)
44531 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT             (16U)
44532 #define TRNG_PKRCNTFE_PKR_F_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
44533 /*! @} */
44534 
44535 /*! @name SEC_CFG - Security Configuration Register */
44536 /*! @{ */
44537 
44538 #define TRNG_SEC_CFG_SH0_MASK                    (0x1U)
44539 #define TRNG_SEC_CFG_SH0_SHIFT                   (0U)
44540 /*! SH0
44541  *  0b0..See DRNG version.
44542  *  0b1..See DRNG version.
44543  */
44544 #define TRNG_SEC_CFG_SH0(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
44545 
44546 #define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
44547 #define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
44548 /*! NO_PRGM
44549  *  0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
44550  *  0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
44551  */
44552 #define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
44553 
44554 #define TRNG_SEC_CFG_SK_VAL_MASK                 (0x4U)
44555 #define TRNG_SEC_CFG_SK_VAL_SHIFT                (2U)
44556 /*! SK_VAL
44557  *  0b0..See DRNG version.
44558  *  0b1..See DRNG version.
44559  */
44560 #define TRNG_SEC_CFG_SK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
44561 /*! @} */
44562 
44563 /*! @name INT_CTRL - Interrupt Control Register */
44564 /*! @{ */
44565 
44566 #define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
44567 #define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
44568 /*! HW_ERR
44569  *  0b0..Corresponding bit of INT_STATUS cleared.
44570  *  0b1..Corresponding bit of INT_STATUS active.
44571  */
44572 #define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
44573 
44574 #define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
44575 #define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
44576 /*! ENT_VAL
44577  *  0b0..Same behavior as bit 0 above.
44578  *  0b1..Same behavior as bit 0 above.
44579  */
44580 #define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
44581 
44582 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
44583 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
44584 /*! FRQ_CT_FAIL
44585  *  0b0..Same behavior as bit 0 above.
44586  *  0b1..Same behavior as bit 0 above.
44587  */
44588 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
44589 
44590 #define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
44591 #define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
44592 #define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
44593 /*! @} */
44594 
44595 /*! @name INT_MASK - Mask Register */
44596 /*! @{ */
44597 
44598 #define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
44599 #define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
44600 /*! HW_ERR
44601  *  0b0..Corresponding interrupt of INT_STATUS is masked.
44602  *  0b1..Corresponding bit of INT_STATUS is active.
44603  */
44604 #define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
44605 
44606 #define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
44607 #define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
44608 /*! ENT_VAL
44609  *  0b0..Same behavior as bit 0 above.
44610  *  0b1..Same behavior as bit 0 above.
44611  */
44612 #define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
44613 
44614 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
44615 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
44616 /*! FRQ_CT_FAIL
44617  *  0b0..Same behavior as bit 0 above.
44618  *  0b1..Same behavior as bit 0 above.
44619  */
44620 #define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
44621 /*! @} */
44622 
44623 /*! @name INT_STATUS - Interrupt Status Register */
44624 /*! @{ */
44625 
44626 #define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
44627 #define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
44628 /*! HW_ERR
44629  *  0b0..no error
44630  *  0b1..error detected.
44631  */
44632 #define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
44633 
44634 #define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
44635 #define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
44636 /*! ENT_VAL
44637  *  0b0..Busy generation entropy. Any value read is invalid.
44638  *  0b1..TRNG can be stopped and entropy is valid if read.
44639  */
44640 #define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
44641 
44642 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
44643 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
44644 /*! FRQ_CT_FAIL
44645  *  0b0..No hardware nor self test frequency errors.
44646  *  0b1..The frequency counter has detected a failure.
44647  */
44648 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
44649 /*! @} */
44650 
44651 /*! @name VID1 - Version ID Register (MS) */
44652 /*! @{ */
44653 
44654 #define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
44655 #define TRNG_VID1_MIN_REV_SHIFT                  (0U)
44656 /*! MIN_REV
44657  *  0b00000000..Minor revision number for TRNG.
44658  */
44659 #define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
44660 
44661 #define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
44662 #define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
44663 /*! MAJ_REV
44664  *  0b00000001..Major revision number for TRNG.
44665  */
44666 #define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
44667 
44668 #define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
44669 #define TRNG_VID1_IP_ID_SHIFT                    (16U)
44670 /*! IP_ID
44671  *  0b0000000000110000..ID for TRNG.
44672  */
44673 #define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
44674 /*! @} */
44675 
44676 /*! @name VID2 - Version ID Register (LS) */
44677 /*! @{ */
44678 
44679 #define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
44680 #define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
44681 /*! CONFIG_OPT
44682  *  0b00000000..TRNG_CONFIG_OPT for TRNG.
44683  */
44684 #define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
44685 
44686 #define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
44687 #define TRNG_VID2_ECO_REV_SHIFT                  (8U)
44688 /*! ECO_REV
44689  *  0b00000000..TRNG_ECO_REV for TRNG.
44690  */
44691 #define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
44692 
44693 #define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
44694 #define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
44695 /*! INTG_OPT
44696  *  0b00000000..INTG_OPT for TRNG.
44697  */
44698 #define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
44699 
44700 #define TRNG_VID2_ERA_MASK                       (0xFF000000U)
44701 #define TRNG_VID2_ERA_SHIFT                      (24U)
44702 /*! ERA
44703  *  0b00000000..COMPILE_OPT for TRNG.
44704  */
44705 #define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
44706 /*! @} */
44707 
44708 
44709 /*!
44710  * @}
44711  */ /* end of group TRNG_Register_Masks */
44712 
44713 
44714 /* TRNG - Peripheral instance base addresses */
44715 /** Peripheral TRNG base address */
44716 #define TRNG_BASE                                (0x400CC000u)
44717 /** Peripheral TRNG base pointer */
44718 #define TRNG                                     ((TRNG_Type *)TRNG_BASE)
44719 /** Array initializer of TRNG peripheral base addresses */
44720 #define TRNG_BASE_ADDRS                          { TRNG_BASE }
44721 /** Array initializer of TRNG peripheral base pointers */
44722 #define TRNG_BASE_PTRS                           { TRNG }
44723 /** Interrupt vectors for the TRNG peripheral type */
44724 #define TRNG_IRQS                                { TRNG_IRQn }
44725 
44726 /*!
44727  * @}
44728  */ /* end of group TRNG_Peripheral_Access_Layer */
44729 
44730 
44731 /* ----------------------------------------------------------------------------
44732    -- TSC Peripheral Access Layer
44733    ---------------------------------------------------------------------------- */
44734 
44735 /*!
44736  * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer
44737  * @{
44738  */
44739 
44740 /** TSC - Register Layout Typedef */
44741 typedef struct {
44742   __IO uint32_t BASIC_SETTING;                     /**< Basic Setting, offset: 0x0 */
44743        uint8_t RESERVED_0[12];
44744   __IO uint32_t PRE_CHARGE_TIME;                   /**< Pre-charge Time, offset: 0x10 */
44745        uint8_t RESERVED_1[12];
44746   __IO uint32_t FLOW_CONTROL;                      /**< Flow Control, offset: 0x20 */
44747        uint8_t RESERVED_2[12];
44748   __I  uint32_t MEASEURE_VALUE;                    /**< Measure Value, offset: 0x30 */
44749        uint8_t RESERVED_3[12];
44750   __IO uint32_t INT_EN;                            /**< Interrupt Enable, offset: 0x40 */
44751        uint8_t RESERVED_4[12];
44752   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Signal Enable, offset: 0x50 */
44753        uint8_t RESERVED_5[12];
44754   __IO uint32_t INT_STATUS;                        /**< Intterrupt Status, offset: 0x60 */
44755        uint8_t RESERVED_6[12];
44756   __IO uint32_t DEBUG_MODE;                        /**< Debug Mode Register, offset: 0x70 */
44757        uint8_t RESERVED_7[12];
44758   __IO uint32_t DEBUG_MODE2;                       /**< Debug Mode Register 2, offset: 0x80 */
44759 } TSC_Type;
44760 
44761 /* ----------------------------------------------------------------------------
44762    -- TSC Register Masks
44763    ---------------------------------------------------------------------------- */
44764 
44765 /*!
44766  * @addtogroup TSC_Register_Masks TSC Register Masks
44767  * @{
44768  */
44769 
44770 /*! @name BASIC_SETTING - Basic Setting */
44771 /*! @{ */
44772 
44773 #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK      (0x1U)
44774 #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT     (0U)
44775 /*! AUTO_MEASURE - Auto Measure
44776  *  0b0..Disable Auto Measure
44777  *  0b1..Auto Measure
44778  */
44779 #define TSC_BASIC_SETTING_AUTO_MEASURE(x)        (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
44780 
44781 #define TSC_BASIC_SETTING_WIRE_4_5_MASK          (0x10U)
44782 #define TSC_BASIC_SETTING_WIRE_4_5_SHIFT         (4U)
44783 /*! WIRE_4_5 - 4/5 Wire detection
44784  *  0b0..4-Wire Detection Mode
44785  *  0b1..5-Wire Detection Mode
44786  */
44787 #define TSC_BASIC_SETTING_WIRE_4_5(x)            (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_WIRE_4_5_SHIFT)) & TSC_BASIC_SETTING_WIRE_4_5_MASK)
44788 
44789 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
44790 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
44791 /*! MEASURE_DELAY_TIME - Measure Delay Time
44792  */
44793 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x)  (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
44794 /*! @} */
44795 
44796 /*! @name PRE_CHARGE_TIME - Pre-charge Time */
44797 /*! @{ */
44798 
44799 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
44800 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
44801 #define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x)   (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
44802 /*! @} */
44803 
44804 /*! @name FLOW_CONTROL - Flow Control */
44805 /*! @{ */
44806 
44807 #define TSC_FLOW_CONTROL_SW_RST_MASK             (0x1U)
44808 #define TSC_FLOW_CONTROL_SW_RST_SHIFT            (0U)
44809 /*! SW_RST - Soft Reset
44810  */
44811 #define TSC_FLOW_CONTROL_SW_RST(x)               (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
44812 
44813 #define TSC_FLOW_CONTROL_START_MEASURE_MASK      (0x10U)
44814 #define TSC_FLOW_CONTROL_START_MEASURE_SHIFT     (4U)
44815 /*! START_MEASURE - Start Measure
44816  *  0b0..Do not start measure for now
44817  *  0b1..Start measure the X/Y coordinate value
44818  */
44819 #define TSC_FLOW_CONTROL_START_MEASURE(x)        (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
44820 
44821 #define TSC_FLOW_CONTROL_DROP_MEASURE_MASK       (0x100U)
44822 #define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT      (8U)
44823 /*! DROP_MEASURE - Drop Measure
44824  *  0b0..Do not drop measure for now
44825  *  0b1..Drop the measure and controller return to idle status
44826  */
44827 #define TSC_FLOW_CONTROL_DROP_MEASURE(x)         (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
44828 
44829 #define TSC_FLOW_CONTROL_START_SENSE_MASK        (0x1000U)
44830 #define TSC_FLOW_CONTROL_START_SENSE_SHIFT       (12U)
44831 /*! START_SENSE - Start Sense
44832  *  0b0..Stay at idle status
44833  *  0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch
44834  */
44835 #define TSC_FLOW_CONTROL_START_SENSE(x)          (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
44836 
44837 #define TSC_FLOW_CONTROL_DISABLE_MASK            (0x10000U)
44838 #define TSC_FLOW_CONTROL_DISABLE_SHIFT           (16U)
44839 /*! DISABLE
44840  *  0b0..Leave HW state machine control
44841  *  0b1..SW set to idle status
44842  */
44843 #define TSC_FLOW_CONTROL_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
44844 /*! @} */
44845 
44846 /*! @name MEASEURE_VALUE - Measure Value */
44847 /*! @{ */
44848 
44849 #define TSC_MEASEURE_VALUE_Y_VALUE_MASK          (0xFFFU)
44850 #define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT         (0U)
44851 /*! Y_VALUE - Y Value
44852  */
44853 #define TSC_MEASEURE_VALUE_Y_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
44854 
44855 #define TSC_MEASEURE_VALUE_X_VALUE_MASK          (0xFFF0000U)
44856 #define TSC_MEASEURE_VALUE_X_VALUE_SHIFT         (16U)
44857 /*! X_VALUE - X Value
44858  */
44859 #define TSC_MEASEURE_VALUE_X_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
44860 /*! @} */
44861 
44862 /*! @name INT_EN - Interrupt Enable */
44863 /*! @{ */
44864 
44865 #define TSC_INT_EN_MEASURE_INT_EN_MASK           (0x1U)
44866 #define TSC_INT_EN_MEASURE_INT_EN_SHIFT          (0U)
44867 /*! MEASURE_INT_EN - Measure Interrupt Enable
44868  *  0b0..Disable measure interrupt
44869  *  0b1..Enable measure interrupt
44870  */
44871 #define TSC_INT_EN_MEASURE_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
44872 
44873 #define TSC_INT_EN_DETECT_INT_EN_MASK            (0x10U)
44874 #define TSC_INT_EN_DETECT_INT_EN_SHIFT           (4U)
44875 /*! DETECT_INT_EN - Detect Interrupt Enable
44876  *  0b0..Disable detect interrupt
44877  *  0b1..Enable detect interrupt
44878  */
44879 #define TSC_INT_EN_DETECT_INT_EN(x)              (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
44880 
44881 #define TSC_INT_EN_IDLE_SW_INT_EN_MASK           (0x1000U)
44882 #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT          (12U)
44883 /*! IDLE_SW_INT_EN - Idle Software Interrupt Enable
44884  *  0b0..Disable idle software interrupt
44885  *  0b1..Enable idle software interrupt
44886  */
44887 #define TSC_INT_EN_IDLE_SW_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
44888 /*! @} */
44889 
44890 /*! @name INT_SIG_EN - Interrupt Signal Enable */
44891 /*! @{ */
44892 
44893 #define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK       (0x1U)
44894 #define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT      (0U)
44895 /*! MEASURE_SIG_EN - Measure Signal Enable
44896  */
44897 #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x)         (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
44898 
44899 #define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK        (0x10U)
44900 #define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT       (4U)
44901 /*! DETECT_SIG_EN - Detect Signal Enable
44902  *  0b0..Disable detect signal
44903  *  0b1..Enable detect signal
44904  */
44905 #define TSC_INT_SIG_EN_DETECT_SIG_EN(x)          (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
44906 
44907 #define TSC_INT_SIG_EN_VALID_SIG_EN_MASK         (0x100U)
44908 #define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT        (8U)
44909 /*! VALID_SIG_EN - Valid Signal Enable
44910  *  0b0..Disable valid signal
44911  *  0b1..Enable valid signal
44912  */
44913 #define TSC_INT_SIG_EN_VALID_SIG_EN(x)           (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
44914 
44915 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK       (0x1000U)
44916 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT      (12U)
44917 /*! IDLE_SW_SIG_EN - Idle Software Signal Enable
44918  *  0b0..Disable idle software signal
44919  *  0b1..Enable idle software signal
44920  */
44921 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x)         (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
44922 /*! @} */
44923 
44924 /*! @name INT_STATUS - Intterrupt Status */
44925 /*! @{ */
44926 
44927 #define TSC_INT_STATUS_MEASURE_MASK              (0x1U)
44928 #define TSC_INT_STATUS_MEASURE_SHIFT             (0U)
44929 /*! MEASURE - Measure Signal
44930  *  0b0..Does not exist a measure signal
44931  *  0b1..Exist a measure signal
44932  */
44933 #define TSC_INT_STATUS_MEASURE(x)                (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
44934 
44935 #define TSC_INT_STATUS_DETECT_MASK               (0x10U)
44936 #define TSC_INT_STATUS_DETECT_SHIFT              (4U)
44937 /*! DETECT - Detect Signal
44938  *  0b0..Does not exist a detect signal
44939  *  0b1..Exist detect signal
44940  */
44941 #define TSC_INT_STATUS_DETECT(x)                 (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
44942 
44943 #define TSC_INT_STATUS_VALID_MASK                (0x100U)
44944 #define TSC_INT_STATUS_VALID_SHIFT               (8U)
44945 /*! VALID - Valid Signal
44946  *  0b0..There is no touch detected after measurement, indicates that the measured value is not valid
44947  *  0b1..There is touch detection after measurement, indicates that the measure is valid
44948  */
44949 #define TSC_INT_STATUS_VALID(x)                  (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
44950 
44951 #define TSC_INT_STATUS_IDLE_SW_MASK              (0x1000U)
44952 #define TSC_INT_STATUS_IDLE_SW_SHIFT             (12U)
44953 /*! IDLE_SW - Idle Software
44954  *  0b0..Haven't return to idle status
44955  *  0b1..Already return to idle status
44956  */
44957 #define TSC_INT_STATUS_IDLE_SW(x)                (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
44958 /*! @} */
44959 
44960 /*! @name DEBUG_MODE - Debug Mode Register */
44961 /*! @{ */
44962 
44963 #define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK       (0xFFFU)
44964 #define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT      (0U)
44965 /*! ADC_CONV_VALUE - ADC Conversion Value
44966  */
44967 #define TSC_DEBUG_MODE_ADC_CONV_VALUE(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
44968 
44969 #define TSC_DEBUG_MODE_ADC_COCO_MASK             (0x1000U)
44970 #define TSC_DEBUG_MODE_ADC_COCO_SHIFT            (12U)
44971 /*! ADC_COCO - ADC COCO Signal
44972  */
44973 #define TSC_DEBUG_MODE_ADC_COCO(x)               (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
44974 
44975 #define TSC_DEBUG_MODE_EXT_HWTS_MASK             (0x1F0000U)
44976 #define TSC_DEBUG_MODE_EXT_HWTS_SHIFT            (16U)
44977 /*! EXT_HWTS - Hardware Trigger Select Signal
44978  */
44979 #define TSC_DEBUG_MODE_EXT_HWTS(x)               (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
44980 
44981 #define TSC_DEBUG_MODE_TRIGGER_MASK              (0x1000000U)
44982 #define TSC_DEBUG_MODE_TRIGGER_SHIFT             (24U)
44983 /*! TRIGGER - Trigger
44984  *  0b0..No hardware trigger signal
44985  *  0b1..Hardware trigger signal, the signal must last at least 1 ips clock period
44986  */
44987 #define TSC_DEBUG_MODE_TRIGGER(x)                (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
44988 
44989 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK       (0x2000000U)
44990 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT      (25U)
44991 /*! ADC_COCO_CLEAR - ADC Coco Clear
44992  *  0b0..No ADC COCO clear
44993  *  0b1..Set ADC COCO clear
44994  */
44995 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
44996 
44997 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
44998 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
44999 /*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable
45000  *  0b0..Allow TSC hardware generates ADC COCO clear
45001  *  0b1..Prevent TSC from generate ADC COCO clear signal
45002  */
45003 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
45004 
45005 #define TSC_DEBUG_MODE_DEBUG_EN_MASK             (0x10000000U)
45006 #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT            (28U)
45007 /*! DEBUG_EN - Debug Enable
45008  *  0b0..Enable debug mode
45009  *  0b1..Disable debug mode
45010  */
45011 #define TSC_DEBUG_MODE_DEBUG_EN(x)               (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
45012 /*! @} */
45013 
45014 /*! @name DEBUG_MODE2 - Debug Mode Register 2 */
45015 /*! @{ */
45016 
45017 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK      (0x1U)
45018 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT     (0U)
45019 /*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch
45020  *  0b0..Close the switch
45021  *  0b1..Open up the switch
45022  */
45023 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
45024 
45025 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK        (0x2U)
45026 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT       (1U)
45027 /*! XPUL_PULL_UP - XPUL Wire Pull Up Switch
45028  *  0b0..Close the switch
45029  *  0b1..Open up the switch
45030  */
45031 #define TSC_DEBUG_MODE2_XPUL_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
45032 
45033 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK   (0x4U)
45034 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT  (2U)
45035 /*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch
45036  *  0b0..Close the switch
45037  *  0b1..Open up the switch
45038  */
45039 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
45040 
45041 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK      (0x8U)
45042 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT     (3U)
45043 /*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch
45044  *  0b0..Close the switch
45045  *  0b1..Open up the switch
45046  */
45047 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
45048 
45049 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK        (0x10U)
45050 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT       (4U)
45051 /*! XNUR_PULL_UP - XNUR Wire Pull Up Switch
45052  *  0b0..Close the switch
45053  *  0b1..Open up the switch
45054  */
45055 #define TSC_DEBUG_MODE2_XNUR_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
45056 
45057 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK   (0x20U)
45058 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT  (5U)
45059 /*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch
45060  *  0b0..Close the switch
45061  *  0b1..Open up the switch
45062  */
45063 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
45064 
45065 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK      (0x40U)
45066 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT     (6U)
45067 /*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch
45068  *  0b0..Close the switch
45069  *  0b1..Open up the switch
45070  */
45071 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
45072 
45073 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK        (0x80U)
45074 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT       (7U)
45075 /*! YPLL_PULL_UP - YPLL Wire Pull Up Switch
45076  *  0b0..Close the switch
45077  *  0b1..Open the switch
45078  */
45079 #define TSC_DEBUG_MODE2_YPLL_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
45080 
45081 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK   (0x100U)
45082 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT  (8U)
45083 /*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch
45084  *  0b0..Close the switch
45085  *  0b1..Open up the switch
45086  */
45087 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
45088 
45089 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK      (0x200U)
45090 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT     (9U)
45091 /*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch
45092  *  0b0..Close the switch
45093  *  0b1..Open up the switch
45094  */
45095 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
45096 
45097 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK        (0x400U)
45098 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT       (10U)
45099 /*! YNLR_PULL_UP - YNLR Wire Pull Up Switch
45100  *  0b0..Close the switch
45101  *  0b1..Open up the switch
45102  */
45103 #define TSC_DEBUG_MODE2_YNLR_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
45104 
45105 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK   (0x800U)
45106 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT  (11U)
45107 /*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch
45108  *  0b0..Close the switch
45109  *  0b1..Open up the switch
45110  */
45111 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
45112 
45113 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK     (0x1000U)
45114 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT    (12U)
45115 /*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch
45116  *  0b0..Close the switch
45117  *  0b1..Open up the switch
45118  */
45119 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x)       (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
45120 
45121 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK       (0x2000U)
45122 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT      (13U)
45123 /*! WIPER_PULL_UP - Wiper Wire Pull Up Switch
45124  *  0b0..Close the switch
45125  *  0b1..Open up the switch
45126  */
45127 #define TSC_DEBUG_MODE2_WIPER_PULL_UP(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
45128 
45129 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK  (0x4000U)
45130 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
45131 /*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch
45132  *  0b0..Close the switch
45133  *  0b1..Open up the switch
45134  */
45135 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x)    (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
45136 
45137 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK    (0x10000U)
45138 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT   (16U)
45139 /*! DETECT_FOUR_WIRE - Detect Four Wire
45140  *  0b0..No detect signal
45141  *  0b1..Yes, there is a detect on the touch screen.
45142  */
45143 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x)      (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
45144 
45145 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK    (0x20000U)
45146 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT   (17U)
45147 /*! DETECT_FIVE_WIRE - Detect Five Wire
45148  *  0b0..No detect signal
45149  *  0b1..Yes, there is a detect on the touch screen.
45150  */
45151 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x)      (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
45152 
45153 #define TSC_DEBUG_MODE2_STATE_MACHINE_MASK       (0x700000U)
45154 #define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT      (20U)
45155 /*! STATE_MACHINE - State Machine
45156  *  0b000..Idle
45157  *  0b001..Pre-charge
45158  *  0b010..Detect
45159  *  0b011..X-measure
45160  *  0b100..Y-measure
45161  *  0b101..Pre-charge
45162  *  0b110..Detect
45163  */
45164 #define TSC_DEBUG_MODE2_STATE_MACHINE(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
45165 
45166 #define TSC_DEBUG_MODE2_INTERMEDIATE_MASK        (0x800000U)
45167 #define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT       (23U)
45168 /*! INTERMEDIATE - Intermediate State
45169  *  0b0..Not in intermedia
45170  *  0b1..Intermedia
45171  */
45172 #define TSC_DEBUG_MODE2_INTERMEDIATE(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
45173 
45174 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
45175 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
45176 /*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire
45177  *  0b0..Do not read four wire detect value, read default value from analogue
45178  *  0b1..Read four wire detect status from analogue
45179  */
45180 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
45181 
45182 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
45183 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
45184 /*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire
45185  *  0b0..Do not read five wire detect value, read default value from analogue
45186  *  0b1..Read five wire detect status from analogue
45187  */
45188 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
45189 
45190 #define TSC_DEBUG_MODE2_DE_GLITCH_MASK           (0x60000000U)
45191 #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT          (29U)
45192 /*! DE_GLITCH
45193  *  0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles
45194  *  0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles
45195  *  0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles
45196  *  0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles
45197  */
45198 #define TSC_DEBUG_MODE2_DE_GLITCH(x)             (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
45199 /*! @} */
45200 
45201 
45202 /*!
45203  * @}
45204  */ /* end of group TSC_Register_Masks */
45205 
45206 
45207 /* TSC - Peripheral instance base addresses */
45208 /** Peripheral TSC base address */
45209 #define TSC_BASE                                 (0x400E0000u)
45210 /** Peripheral TSC base pointer */
45211 #define TSC                                      ((TSC_Type *)TSC_BASE)
45212 /** Array initializer of TSC peripheral base addresses */
45213 #define TSC_BASE_ADDRS                           { TSC_BASE }
45214 /** Array initializer of TSC peripheral base pointers */
45215 #define TSC_BASE_PTRS                            { TSC }
45216 /** Interrupt vectors for the TSC peripheral type */
45217 #define TSC_IRQS                                 { TSC_DIG_IRQn }
45218 /* Backward compatibility */
45219 #define TSC_BASIC_SETTING__4_5_WIRE_MASK          TSC_BASIC_SETTING_WIRE_4_5_MASK
45220 #define TSC_BASIC_SETTING__4_5_WIRE_SHIFT         TSC_BASIC_SETTING_WIRE_4_5_SHIFT
45221 #define TSC_BASIC_SETTING__4_5_WIRE(x)            TSC_BASIC_SETTING_WIRE_4_5(x)
45222 
45223 
45224 /*!
45225  * @}
45226  */ /* end of group TSC_Peripheral_Access_Layer */
45227 
45228 
45229 /* ----------------------------------------------------------------------------
45230    -- USB Peripheral Access Layer
45231    ---------------------------------------------------------------------------- */
45232 
45233 /*!
45234  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
45235  * @{
45236  */
45237 
45238 /** USB - Register Layout Typedef */
45239 typedef struct {
45240   __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
45241   __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
45242   __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
45243   __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
45244   __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
45245   __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
45246        uint8_t RESERVED_0[104];
45247   __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
45248   __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
45249   __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
45250   __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
45251   __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
45252        uint8_t RESERVED_1[108];
45253   __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
45254        uint8_t RESERVED_2[1];
45255   __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
45256   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
45257   __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
45258        uint8_t RESERVED_3[20];
45259   __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
45260        uint8_t RESERVED_4[2];
45261   __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
45262        uint8_t RESERVED_5[24];
45263   __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
45264   __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
45265   __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
45266   __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
45267        uint8_t RESERVED_6[4];
45268   union {                                          /* offset: 0x154 */
45269     __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
45270     __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
45271   };
45272   union {                                          /* offset: 0x158 */
45273     __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
45274     __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
45275   };
45276        uint8_t RESERVED_7[4];
45277   __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
45278   __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
45279        uint8_t RESERVED_8[16];
45280   __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
45281   __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
45282   __I  uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
45283   __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
45284        uint8_t RESERVED_9[28];
45285   __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
45286   __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
45287   __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
45288   __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
45289   __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
45290   __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
45291   __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
45292   __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
45293   __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
45294 } USB_Type;
45295 
45296 /* ----------------------------------------------------------------------------
45297    -- USB Register Masks
45298    ---------------------------------------------------------------------------- */
45299 
45300 /*!
45301  * @addtogroup USB_Register_Masks USB Register Masks
45302  * @{
45303  */
45304 
45305 /*! @name ID - Identification register */
45306 /*! @{ */
45307 
45308 #define USB_ID_ID_MASK                           (0x3FU)
45309 #define USB_ID_ID_SHIFT                          (0U)
45310 #define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
45311 
45312 #define USB_ID_NID_MASK                          (0x3F00U)
45313 #define USB_ID_NID_SHIFT                         (8U)
45314 #define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
45315 
45316 #define USB_ID_REVISION_MASK                     (0xFF0000U)
45317 #define USB_ID_REVISION_SHIFT                    (16U)
45318 #define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
45319 /*! @} */
45320 
45321 /*! @name HWGENERAL - Hardware General */
45322 /*! @{ */
45323 
45324 #define USB_HWGENERAL_PHYW_MASK                  (0x30U)
45325 #define USB_HWGENERAL_PHYW_SHIFT                 (4U)
45326 /*! PHYW
45327  *  0b00..8 bit wide data bus Software non-programmable
45328  *  0b01..16 bit wide data bus Software non-programmable
45329  *  0b10..Reset to 8 bit wide data bus Software programmable
45330  *  0b11..Reset to 16 bit wide data bus Software programmable
45331  */
45332 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
45333 
45334 #define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
45335 #define USB_HWGENERAL_PHYM_SHIFT                 (6U)
45336 /*! PHYM
45337  *  0b000..UTMI/UMTI+
45338  *  0b001..ULPI DDR
45339  *  0b010..ULPI
45340  *  0b011..Serial Only
45341  *  0b100..Software programmable - reset to UTMI/UTMI+
45342  *  0b101..Software programmable - reset to ULPI DDR
45343  *  0b110..Software programmable - reset to ULPI
45344  *  0b111..Software programmable - reset to Serial
45345  */
45346 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
45347 
45348 #define USB_HWGENERAL_SM_MASK                    (0x600U)
45349 #define USB_HWGENERAL_SM_SHIFT                   (9U)
45350 /*! SM
45351  *  0b00..No Serial Engine, always use parallel signalling.
45352  *  0b01..Serial Engine present, always use serial signalling for FS/LS.
45353  *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
45354  *  0b11..Software programmable - Reset to use serial signalling for FS/LS
45355  */
45356 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
45357 /*! @} */
45358 
45359 /*! @name HWHOST - Host Hardware Parameters */
45360 /*! @{ */
45361 
45362 #define USB_HWHOST_HC_MASK                       (0x1U)
45363 #define USB_HWHOST_HC_SHIFT                      (0U)
45364 /*! HC
45365  *  0b1..Supported
45366  *  0b0..Not supported
45367  */
45368 #define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
45369 
45370 #define USB_HWHOST_NPORT_MASK                    (0xEU)
45371 #define USB_HWHOST_NPORT_SHIFT                   (1U)
45372 #define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
45373 /*! @} */
45374 
45375 /*! @name HWDEVICE - Device Hardware Parameters */
45376 /*! @{ */
45377 
45378 #define USB_HWDEVICE_DC_MASK                     (0x1U)
45379 #define USB_HWDEVICE_DC_SHIFT                    (0U)
45380 /*! DC
45381  *  0b1..Supported
45382  *  0b0..Not supported
45383  */
45384 #define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
45385 
45386 #define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
45387 #define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
45388 #define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
45389 /*! @} */
45390 
45391 /*! @name HWTXBUF - TX Buffer Hardware Parameters */
45392 /*! @{ */
45393 
45394 #define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
45395 #define USB_HWTXBUF_TXBURST_SHIFT                (0U)
45396 #define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
45397 
45398 #define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
45399 #define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
45400 #define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
45401 /*! @} */
45402 
45403 /*! @name HWRXBUF - RX Buffer Hardware Parameters */
45404 /*! @{ */
45405 
45406 #define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
45407 #define USB_HWRXBUF_RXBURST_SHIFT                (0U)
45408 #define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
45409 
45410 #define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
45411 #define USB_HWRXBUF_RXADD_SHIFT                  (8U)
45412 #define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
45413 /*! @} */
45414 
45415 /*! @name GPTIMER0LD - General Purpose Timer #0 Load */
45416 /*! @{ */
45417 
45418 #define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
45419 #define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
45420 #define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
45421 /*! @} */
45422 
45423 /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
45424 /*! @{ */
45425 
45426 #define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
45427 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
45428 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
45429 
45430 #define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
45431 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
45432 /*! GPTMODE
45433  *  0b0..One Shot Mode
45434  *  0b1..Repeat Mode
45435  */
45436 #define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
45437 
45438 #define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
45439 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
45440 /*! GPTRST
45441  *  0b0..No action
45442  *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
45443  */
45444 #define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
45445 
45446 #define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
45447 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
45448 /*! GPTRUN
45449  *  0b0..Stop counting
45450  *  0b1..Run
45451  */
45452 #define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
45453 /*! @} */
45454 
45455 /*! @name GPTIMER1LD - General Purpose Timer #1 Load */
45456 /*! @{ */
45457 
45458 #define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
45459 #define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
45460 #define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
45461 /*! @} */
45462 
45463 /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
45464 /*! @{ */
45465 
45466 #define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
45467 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
45468 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
45469 
45470 #define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
45471 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
45472 /*! GPTMODE
45473  *  0b0..One Shot Mode
45474  *  0b1..Repeat Mode
45475  */
45476 #define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
45477 
45478 #define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
45479 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
45480 /*! GPTRST
45481  *  0b0..No action
45482  *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
45483  */
45484 #define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
45485 
45486 #define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
45487 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
45488 /*! GPTRUN
45489  *  0b0..Stop counting
45490  *  0b1..Run
45491  */
45492 #define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
45493 /*! @} */
45494 
45495 /*! @name SBUSCFG - System Bus Config */
45496 /*! @{ */
45497 
45498 #define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
45499 #define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
45500 /*! AHBBRST
45501  *  0b000..Incremental burst of unspecified length only
45502  *  0b001..INCR4 burst, then single transfer
45503  *  0b010..INCR8 burst, INCR4 burst, then single transfer
45504  *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
45505  *  0b100..Reserved, don't use
45506  *  0b101..INCR4 burst, then incremental burst of unspecified length
45507  *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
45508  *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
45509  */
45510 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
45511 /*! @} */
45512 
45513 /*! @name CAPLENGTH - Capability Registers Length */
45514 /*! @{ */
45515 
45516 #define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
45517 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
45518 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
45519 /*! @} */
45520 
45521 /*! @name HCIVERSION - Host Controller Interface Version */
45522 /*! @{ */
45523 
45524 #define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
45525 #define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
45526 #define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
45527 /*! @} */
45528 
45529 /*! @name HCSPARAMS - Host Controller Structural Parameters */
45530 /*! @{ */
45531 
45532 #define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
45533 #define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
45534 #define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
45535 
45536 #define USB_HCSPARAMS_PPC_MASK                   (0x10U)
45537 #define USB_HCSPARAMS_PPC_SHIFT                  (4U)
45538 #define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
45539 
45540 #define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
45541 #define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
45542 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
45543 
45544 #define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
45545 #define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
45546 /*! N_CC
45547  *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
45548  *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
45549  */
45550 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
45551 
45552 #define USB_HCSPARAMS_PI_MASK                    (0x10000U)
45553 #define USB_HCSPARAMS_PI_SHIFT                   (16U)
45554 #define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
45555 
45556 #define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
45557 #define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
45558 #define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
45559 
45560 #define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
45561 #define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
45562 #define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
45563 /*! @} */
45564 
45565 /*! @name HCCPARAMS - Host Controller Capability Parameters */
45566 /*! @{ */
45567 
45568 #define USB_HCCPARAMS_ADC_MASK                   (0x1U)
45569 #define USB_HCCPARAMS_ADC_SHIFT                  (0U)
45570 #define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
45571 
45572 #define USB_HCCPARAMS_PFL_MASK                   (0x2U)
45573 #define USB_HCCPARAMS_PFL_SHIFT                  (1U)
45574 #define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
45575 
45576 #define USB_HCCPARAMS_ASP_MASK                   (0x4U)
45577 #define USB_HCCPARAMS_ASP_SHIFT                  (2U)
45578 #define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
45579 
45580 #define USB_HCCPARAMS_IST_MASK                   (0xF0U)
45581 #define USB_HCCPARAMS_IST_SHIFT                  (4U)
45582 #define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
45583 
45584 #define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
45585 #define USB_HCCPARAMS_EECP_SHIFT                 (8U)
45586 #define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
45587 /*! @} */
45588 
45589 /*! @name DCIVERSION - Device Controller Interface Version */
45590 /*! @{ */
45591 
45592 #define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
45593 #define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
45594 #define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
45595 /*! @} */
45596 
45597 /*! @name DCCPARAMS - Device Controller Capability Parameters */
45598 /*! @{ */
45599 
45600 #define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
45601 #define USB_DCCPARAMS_DEN_SHIFT                  (0U)
45602 #define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
45603 
45604 #define USB_DCCPARAMS_DC_MASK                    (0x80U)
45605 #define USB_DCCPARAMS_DC_SHIFT                   (7U)
45606 #define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
45607 
45608 #define USB_DCCPARAMS_HC_MASK                    (0x100U)
45609 #define USB_DCCPARAMS_HC_SHIFT                   (8U)
45610 #define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
45611 /*! @} */
45612 
45613 /*! @name USBCMD - USB Command Register */
45614 /*! @{ */
45615 
45616 #define USB_USBCMD_RS_MASK                       (0x1U)
45617 #define USB_USBCMD_RS_SHIFT                      (0U)
45618 #define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
45619 
45620 #define USB_USBCMD_RST_MASK                      (0x2U)
45621 #define USB_USBCMD_RST_SHIFT                     (1U)
45622 #define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
45623 
45624 #define USB_USBCMD_FS_1_MASK                     (0xCU)
45625 #define USB_USBCMD_FS_1_SHIFT                    (2U)
45626 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
45627 
45628 #define USB_USBCMD_PSE_MASK                      (0x10U)
45629 #define USB_USBCMD_PSE_SHIFT                     (4U)
45630 /*! PSE
45631  *  0b0..Do not process the Periodic Schedule
45632  *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
45633  */
45634 #define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
45635 
45636 #define USB_USBCMD_ASE_MASK                      (0x20U)
45637 #define USB_USBCMD_ASE_SHIFT                     (5U)
45638 /*! ASE
45639  *  0b0..Do not process the Asynchronous Schedule.
45640  *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
45641  */
45642 #define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
45643 
45644 #define USB_USBCMD_IAA_MASK                      (0x40U)
45645 #define USB_USBCMD_IAA_SHIFT                     (6U)
45646 #define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
45647 
45648 #define USB_USBCMD_ASP_MASK                      (0x300U)
45649 #define USB_USBCMD_ASP_SHIFT                     (8U)
45650 #define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
45651 
45652 #define USB_USBCMD_ASPE_MASK                     (0x800U)
45653 #define USB_USBCMD_ASPE_SHIFT                    (11U)
45654 #define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
45655 
45656 #define USB_USBCMD_SUTW_MASK                     (0x2000U)
45657 #define USB_USBCMD_SUTW_SHIFT                    (13U)
45658 #define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
45659 
45660 #define USB_USBCMD_ATDTW_MASK                    (0x4000U)
45661 #define USB_USBCMD_ATDTW_SHIFT                   (14U)
45662 #define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
45663 
45664 #define USB_USBCMD_FS_2_MASK                     (0x8000U)
45665 #define USB_USBCMD_FS_2_SHIFT                    (15U)
45666 /*! FS_2
45667  *  0b0..1024 elements (4096 bytes) Default value
45668  *  0b1..512 elements (2048 bytes)
45669  */
45670 #define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
45671 
45672 #define USB_USBCMD_ITC_MASK                      (0xFF0000U)
45673 #define USB_USBCMD_ITC_SHIFT                     (16U)
45674 /*! ITC
45675  *  0b00000000..Immediate (no threshold)
45676  *  0b00000001..1 micro-frame
45677  *  0b00000010..2 micro-frames
45678  *  0b00000100..4 micro-frames
45679  *  0b00001000..8 micro-frames
45680  *  0b00010000..16 micro-frames
45681  *  0b00100000..32 micro-frames
45682  *  0b01000000..64 micro-frames
45683  */
45684 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
45685 /*! @} */
45686 
45687 /*! @name USBSTS - USB Status Register */
45688 /*! @{ */
45689 
45690 #define USB_USBSTS_UI_MASK                       (0x1U)
45691 #define USB_USBSTS_UI_SHIFT                      (0U)
45692 #define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
45693 
45694 #define USB_USBSTS_UEI_MASK                      (0x2U)
45695 #define USB_USBSTS_UEI_SHIFT                     (1U)
45696 #define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
45697 
45698 #define USB_USBSTS_PCI_MASK                      (0x4U)
45699 #define USB_USBSTS_PCI_SHIFT                     (2U)
45700 #define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
45701 
45702 #define USB_USBSTS_FRI_MASK                      (0x8U)
45703 #define USB_USBSTS_FRI_SHIFT                     (3U)
45704 #define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
45705 
45706 #define USB_USBSTS_SEI_MASK                      (0x10U)
45707 #define USB_USBSTS_SEI_SHIFT                     (4U)
45708 #define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
45709 
45710 #define USB_USBSTS_AAI_MASK                      (0x20U)
45711 #define USB_USBSTS_AAI_SHIFT                     (5U)
45712 #define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
45713 
45714 #define USB_USBSTS_URI_MASK                      (0x40U)
45715 #define USB_USBSTS_URI_SHIFT                     (6U)
45716 #define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
45717 
45718 #define USB_USBSTS_SRI_MASK                      (0x80U)
45719 #define USB_USBSTS_SRI_SHIFT                     (7U)
45720 #define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
45721 
45722 #define USB_USBSTS_SLI_MASK                      (0x100U)
45723 #define USB_USBSTS_SLI_SHIFT                     (8U)
45724 #define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
45725 
45726 #define USB_USBSTS_ULPII_MASK                    (0x400U)
45727 #define USB_USBSTS_ULPII_SHIFT                   (10U)
45728 #define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
45729 
45730 #define USB_USBSTS_HCH_MASK                      (0x1000U)
45731 #define USB_USBSTS_HCH_SHIFT                     (12U)
45732 #define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
45733 
45734 #define USB_USBSTS_RCL_MASK                      (0x2000U)
45735 #define USB_USBSTS_RCL_SHIFT                     (13U)
45736 #define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
45737 
45738 #define USB_USBSTS_PS_MASK                       (0x4000U)
45739 #define USB_USBSTS_PS_SHIFT                      (14U)
45740 #define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
45741 
45742 #define USB_USBSTS_AS_MASK                       (0x8000U)
45743 #define USB_USBSTS_AS_SHIFT                      (15U)
45744 #define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
45745 
45746 #define USB_USBSTS_NAKI_MASK                     (0x10000U)
45747 #define USB_USBSTS_NAKI_SHIFT                    (16U)
45748 #define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
45749 
45750 #define USB_USBSTS_TI0_MASK                      (0x1000000U)
45751 #define USB_USBSTS_TI0_SHIFT                     (24U)
45752 #define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
45753 
45754 #define USB_USBSTS_TI1_MASK                      (0x2000000U)
45755 #define USB_USBSTS_TI1_SHIFT                     (25U)
45756 #define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
45757 /*! @} */
45758 
45759 /*! @name USBINTR - Interrupt Enable Register */
45760 /*! @{ */
45761 
45762 #define USB_USBINTR_UE_MASK                      (0x1U)
45763 #define USB_USBINTR_UE_SHIFT                     (0U)
45764 #define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
45765 
45766 #define USB_USBINTR_UEE_MASK                     (0x2U)
45767 #define USB_USBINTR_UEE_SHIFT                    (1U)
45768 #define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
45769 
45770 #define USB_USBINTR_PCE_MASK                     (0x4U)
45771 #define USB_USBINTR_PCE_SHIFT                    (2U)
45772 #define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
45773 
45774 #define USB_USBINTR_FRE_MASK                     (0x8U)
45775 #define USB_USBINTR_FRE_SHIFT                    (3U)
45776 #define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
45777 
45778 #define USB_USBINTR_SEE_MASK                     (0x10U)
45779 #define USB_USBINTR_SEE_SHIFT                    (4U)
45780 #define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
45781 
45782 #define USB_USBINTR_AAE_MASK                     (0x20U)
45783 #define USB_USBINTR_AAE_SHIFT                    (5U)
45784 #define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
45785 
45786 #define USB_USBINTR_URE_MASK                     (0x40U)
45787 #define USB_USBINTR_URE_SHIFT                    (6U)
45788 #define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
45789 
45790 #define USB_USBINTR_SRE_MASK                     (0x80U)
45791 #define USB_USBINTR_SRE_SHIFT                    (7U)
45792 #define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
45793 
45794 #define USB_USBINTR_SLE_MASK                     (0x100U)
45795 #define USB_USBINTR_SLE_SHIFT                    (8U)
45796 #define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
45797 
45798 #define USB_USBINTR_ULPIE_MASK                   (0x400U)
45799 #define USB_USBINTR_ULPIE_SHIFT                  (10U)
45800 #define USB_USBINTR_ULPIE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
45801 
45802 #define USB_USBINTR_NAKE_MASK                    (0x10000U)
45803 #define USB_USBINTR_NAKE_SHIFT                   (16U)
45804 #define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
45805 
45806 #define USB_USBINTR_UAIE_MASK                    (0x40000U)
45807 #define USB_USBINTR_UAIE_SHIFT                   (18U)
45808 #define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
45809 
45810 #define USB_USBINTR_UPIE_MASK                    (0x80000U)
45811 #define USB_USBINTR_UPIE_SHIFT                   (19U)
45812 #define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
45813 
45814 #define USB_USBINTR_TIE0_MASK                    (0x1000000U)
45815 #define USB_USBINTR_TIE0_SHIFT                   (24U)
45816 #define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
45817 
45818 #define USB_USBINTR_TIE1_MASK                    (0x2000000U)
45819 #define USB_USBINTR_TIE1_SHIFT                   (25U)
45820 #define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
45821 /*! @} */
45822 
45823 /*! @name FRINDEX - USB Frame Index */
45824 /*! @{ */
45825 
45826 #define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
45827 #define USB_FRINDEX_FRINDEX_SHIFT                (0U)
45828 /*! FRINDEX
45829  *  0b00000000000000..(1024) 12
45830  *  0b00000000000001..(512) 11
45831  *  0b00000000000010..(256) 10
45832  *  0b00000000000011..(128) 9
45833  *  0b00000000000100..(64) 8
45834  *  0b00000000000101..(32) 7
45835  *  0b00000000000110..(16) 6
45836  *  0b00000000000111..(8) 5
45837  */
45838 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
45839 /*! @} */
45840 
45841 /*! @name DEVICEADDR - Device Address */
45842 /*! @{ */
45843 
45844 #define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
45845 #define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
45846 #define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
45847 
45848 #define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
45849 #define USB_DEVICEADDR_USBADR_SHIFT              (25U)
45850 #define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
45851 /*! @} */
45852 
45853 /*! @name PERIODICLISTBASE - Frame List Base Address */
45854 /*! @{ */
45855 
45856 #define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
45857 #define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
45858 #define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
45859 /*! @} */
45860 
45861 /*! @name ASYNCLISTADDR - Next Asynch. Address */
45862 /*! @{ */
45863 
45864 #define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
45865 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
45866 #define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
45867 /*! @} */
45868 
45869 /*! @name ENDPTLISTADDR - Endpoint List Address */
45870 /*! @{ */
45871 
45872 #define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
45873 #define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
45874 #define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
45875 /*! @} */
45876 
45877 /*! @name BURSTSIZE - Programmable Burst Size */
45878 /*! @{ */
45879 
45880 #define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
45881 #define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
45882 #define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
45883 
45884 #define USB_BURSTSIZE_TXPBURST_MASK              (0x1FF00U)
45885 #define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
45886 #define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
45887 /*! @} */
45888 
45889 /*! @name TXFILLTUNING - TX FIFO Fill Tuning */
45890 /*! @{ */
45891 
45892 #define USB_TXFILLTUNING_TXSCHOH_MASK            (0xFFU)
45893 #define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
45894 #define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
45895 
45896 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
45897 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
45898 #define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
45899 
45900 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
45901 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
45902 #define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
45903 /*! @} */
45904 
45905 /*! @name ENDPTNAK - Endpoint NAK */
45906 /*! @{ */
45907 
45908 #define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
45909 #define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
45910 #define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
45911 
45912 #define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
45913 #define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
45914 #define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
45915 /*! @} */
45916 
45917 /*! @name ENDPTNAKEN - Endpoint NAK Enable */
45918 /*! @{ */
45919 
45920 #define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
45921 #define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
45922 #define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
45923 
45924 #define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
45925 #define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
45926 #define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
45927 /*! @} */
45928 
45929 /*! @name CONFIGFLAG - Configure Flag Register */
45930 /*! @{ */
45931 
45932 #define USB_CONFIGFLAG_CF_MASK                   (0x1U)
45933 #define USB_CONFIGFLAG_CF_SHIFT                  (0U)
45934 /*! CF
45935  *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
45936  *  0b1..Port routing control logic default-routes all ports to this host controller.
45937  */
45938 #define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
45939 /*! @} */
45940 
45941 /*! @name PORTSC1 - Port Status & Control */
45942 /*! @{ */
45943 
45944 #define USB_PORTSC1_CCS_MASK                     (0x1U)
45945 #define USB_PORTSC1_CCS_SHIFT                    (0U)
45946 #define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
45947 
45948 #define USB_PORTSC1_CSC_MASK                     (0x2U)
45949 #define USB_PORTSC1_CSC_SHIFT                    (1U)
45950 #define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
45951 
45952 #define USB_PORTSC1_PE_MASK                      (0x4U)
45953 #define USB_PORTSC1_PE_SHIFT                     (2U)
45954 #define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
45955 
45956 #define USB_PORTSC1_PEC_MASK                     (0x8U)
45957 #define USB_PORTSC1_PEC_SHIFT                    (3U)
45958 #define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
45959 
45960 #define USB_PORTSC1_OCA_MASK                     (0x10U)
45961 #define USB_PORTSC1_OCA_SHIFT                    (4U)
45962 /*! OCA
45963  *  0b1..This port currently has an over-current condition
45964  *  0b0..This port does not have an over-current condition.
45965  */
45966 #define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
45967 
45968 #define USB_PORTSC1_OCC_MASK                     (0x20U)
45969 #define USB_PORTSC1_OCC_SHIFT                    (5U)
45970 #define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
45971 
45972 #define USB_PORTSC1_FPR_MASK                     (0x40U)
45973 #define USB_PORTSC1_FPR_SHIFT                    (6U)
45974 #define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
45975 
45976 #define USB_PORTSC1_SUSP_MASK                    (0x80U)
45977 #define USB_PORTSC1_SUSP_SHIFT                   (7U)
45978 #define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
45979 
45980 #define USB_PORTSC1_PR_MASK                      (0x100U)
45981 #define USB_PORTSC1_PR_SHIFT                     (8U)
45982 #define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
45983 
45984 #define USB_PORTSC1_HSP_MASK                     (0x200U)
45985 #define USB_PORTSC1_HSP_SHIFT                    (9U)
45986 #define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
45987 
45988 #define USB_PORTSC1_LS_MASK                      (0xC00U)
45989 #define USB_PORTSC1_LS_SHIFT                     (10U)
45990 /*! LS
45991  *  0b00..SE0
45992  *  0b10..J-state
45993  *  0b01..K-state
45994  *  0b11..Undefined
45995  */
45996 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
45997 
45998 #define USB_PORTSC1_PP_MASK                      (0x1000U)
45999 #define USB_PORTSC1_PP_SHIFT                     (12U)
46000 #define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
46001 
46002 #define USB_PORTSC1_PO_MASK                      (0x2000U)
46003 #define USB_PORTSC1_PO_SHIFT                     (13U)
46004 #define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
46005 
46006 #define USB_PORTSC1_PIC_MASK                     (0xC000U)
46007 #define USB_PORTSC1_PIC_SHIFT                    (14U)
46008 /*! PIC
46009  *  0b00..Port indicators are off
46010  *  0b01..Amber
46011  *  0b10..Green
46012  *  0b11..Undefined
46013  */
46014 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
46015 
46016 #define USB_PORTSC1_PTC_MASK                     (0xF0000U)
46017 #define USB_PORTSC1_PTC_SHIFT                    (16U)
46018 /*! PTC
46019  *  0b0000..TEST_MODE_DISABLE
46020  *  0b0001..J_STATE
46021  *  0b0010..K_STATE
46022  *  0b0011..SE0 (host) / NAK (device)
46023  *  0b0100..Packet
46024  *  0b0101..FORCE_ENABLE_HS
46025  *  0b0110..FORCE_ENABLE_FS
46026  *  0b0111..FORCE_ENABLE_LS
46027  *  0b1000-0b1111..Reserved
46028  */
46029 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
46030 
46031 #define USB_PORTSC1_WKCN_MASK                    (0x100000U)
46032 #define USB_PORTSC1_WKCN_SHIFT                   (20U)
46033 #define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
46034 
46035 #define USB_PORTSC1_WKDC_MASK                    (0x200000U)
46036 #define USB_PORTSC1_WKDC_SHIFT                   (21U)
46037 #define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
46038 
46039 #define USB_PORTSC1_WKOC_MASK                    (0x400000U)
46040 #define USB_PORTSC1_WKOC_SHIFT                   (22U)
46041 #define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
46042 
46043 #define USB_PORTSC1_PHCD_MASK                    (0x800000U)
46044 #define USB_PORTSC1_PHCD_SHIFT                   (23U)
46045 /*! PHCD
46046  *  0b1..Disable PHY clock
46047  *  0b0..Enable PHY clock
46048  */
46049 #define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
46050 
46051 #define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
46052 #define USB_PORTSC1_PFSC_SHIFT                   (24U)
46053 /*! PFSC
46054  *  0b1..Forced to full speed
46055  *  0b0..Normal operation
46056  */
46057 #define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
46058 
46059 #define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
46060 #define USB_PORTSC1_PTS_2_SHIFT                  (25U)
46061 #define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
46062 
46063 #define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
46064 #define USB_PORTSC1_PSPD_SHIFT                   (26U)
46065 /*! PSPD
46066  *  0b00..Full Speed
46067  *  0b01..Low Speed
46068  *  0b10..High Speed
46069  *  0b11..Undefined
46070  */
46071 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
46072 
46073 #define USB_PORTSC1_PTW_MASK                     (0x10000000U)
46074 #define USB_PORTSC1_PTW_SHIFT                    (28U)
46075 /*! PTW
46076  *  0b0..Select the 8-bit UTMI interface [60MHz]
46077  *  0b1..Select the 16-bit UTMI interface [30MHz]
46078  */
46079 #define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
46080 
46081 #define USB_PORTSC1_STS_MASK                     (0x20000000U)
46082 #define USB_PORTSC1_STS_SHIFT                    (29U)
46083 #define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
46084 
46085 #define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
46086 #define USB_PORTSC1_PTS_1_SHIFT                  (30U)
46087 #define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
46088 /*! @} */
46089 
46090 /*! @name OTGSC - On-The-Go Status & control */
46091 /*! @{ */
46092 
46093 #define USB_OTGSC_VD_MASK                        (0x1U)
46094 #define USB_OTGSC_VD_SHIFT                       (0U)
46095 #define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
46096 
46097 #define USB_OTGSC_VC_MASK                        (0x2U)
46098 #define USB_OTGSC_VC_SHIFT                       (1U)
46099 #define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
46100 
46101 #define USB_OTGSC_OT_MASK                        (0x8U)
46102 #define USB_OTGSC_OT_SHIFT                       (3U)
46103 #define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
46104 
46105 #define USB_OTGSC_DP_MASK                        (0x10U)
46106 #define USB_OTGSC_DP_SHIFT                       (4U)
46107 #define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
46108 
46109 #define USB_OTGSC_IDPU_MASK                      (0x20U)
46110 #define USB_OTGSC_IDPU_SHIFT                     (5U)
46111 #define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
46112 
46113 #define USB_OTGSC_ID_MASK                        (0x100U)
46114 #define USB_OTGSC_ID_SHIFT                       (8U)
46115 #define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
46116 
46117 #define USB_OTGSC_AVV_MASK                       (0x200U)
46118 #define USB_OTGSC_AVV_SHIFT                      (9U)
46119 #define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
46120 
46121 #define USB_OTGSC_ASV_MASK                       (0x400U)
46122 #define USB_OTGSC_ASV_SHIFT                      (10U)
46123 #define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
46124 
46125 #define USB_OTGSC_BSV_MASK                       (0x800U)
46126 #define USB_OTGSC_BSV_SHIFT                      (11U)
46127 #define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
46128 
46129 #define USB_OTGSC_BSE_MASK                       (0x1000U)
46130 #define USB_OTGSC_BSE_SHIFT                      (12U)
46131 #define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
46132 
46133 #define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
46134 #define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
46135 #define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
46136 
46137 #define USB_OTGSC_DPS_MASK                       (0x4000U)
46138 #define USB_OTGSC_DPS_SHIFT                      (14U)
46139 #define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
46140 
46141 #define USB_OTGSC_IDIS_MASK                      (0x10000U)
46142 #define USB_OTGSC_IDIS_SHIFT                     (16U)
46143 #define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
46144 
46145 #define USB_OTGSC_AVVIS_MASK                     (0x20000U)
46146 #define USB_OTGSC_AVVIS_SHIFT                    (17U)
46147 #define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
46148 
46149 #define USB_OTGSC_ASVIS_MASK                     (0x40000U)
46150 #define USB_OTGSC_ASVIS_SHIFT                    (18U)
46151 #define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
46152 
46153 #define USB_OTGSC_BSVIS_MASK                     (0x80000U)
46154 #define USB_OTGSC_BSVIS_SHIFT                    (19U)
46155 #define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
46156 
46157 #define USB_OTGSC_BSEIS_MASK                     (0x100000U)
46158 #define USB_OTGSC_BSEIS_SHIFT                    (20U)
46159 #define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
46160 
46161 #define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
46162 #define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
46163 #define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
46164 
46165 #define USB_OTGSC_DPIS_MASK                      (0x400000U)
46166 #define USB_OTGSC_DPIS_SHIFT                     (22U)
46167 #define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
46168 
46169 #define USB_OTGSC_IDIE_MASK                      (0x1000000U)
46170 #define USB_OTGSC_IDIE_SHIFT                     (24U)
46171 #define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
46172 
46173 #define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
46174 #define USB_OTGSC_AVVIE_SHIFT                    (25U)
46175 #define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
46176 
46177 #define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
46178 #define USB_OTGSC_ASVIE_SHIFT                    (26U)
46179 #define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
46180 
46181 #define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
46182 #define USB_OTGSC_BSVIE_SHIFT                    (27U)
46183 #define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
46184 
46185 #define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
46186 #define USB_OTGSC_BSEIE_SHIFT                    (28U)
46187 #define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
46188 
46189 #define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
46190 #define USB_OTGSC_EN_1MS_SHIFT                   (29U)
46191 #define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
46192 
46193 #define USB_OTGSC_DPIE_MASK                      (0x40000000U)
46194 #define USB_OTGSC_DPIE_SHIFT                     (30U)
46195 #define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
46196 /*! @} */
46197 
46198 /*! @name USBMODE - USB Device Mode */
46199 /*! @{ */
46200 
46201 #define USB_USBMODE_CM_MASK                      (0x3U)
46202 #define USB_USBMODE_CM_SHIFT                     (0U)
46203 /*! CM
46204  *  0b00..Idle [Default for combination host/device]
46205  *  0b01..Reserved
46206  *  0b10..Device Controller [Default for device only controller]
46207  *  0b11..Host Controller [Default for host only controller]
46208  */
46209 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
46210 
46211 #define USB_USBMODE_ES_MASK                      (0x4U)
46212 #define USB_USBMODE_ES_SHIFT                     (2U)
46213 /*! ES
46214  *  0b0..Little Endian [Default]
46215  *  0b1..Big Endian
46216  */
46217 #define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
46218 
46219 #define USB_USBMODE_SLOM_MASK                    (0x8U)
46220 #define USB_USBMODE_SLOM_SHIFT                   (3U)
46221 /*! SLOM
46222  *  0b0..Setup Lockouts On (default);
46223  *  0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .
46224  */
46225 #define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
46226 
46227 #define USB_USBMODE_SDIS_MASK                    (0x10U)
46228 #define USB_USBMODE_SDIS_SHIFT                   (4U)
46229 #define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
46230 /*! @} */
46231 
46232 /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
46233 /*! @{ */
46234 
46235 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
46236 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
46237 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
46238 /*! @} */
46239 
46240 /*! @name ENDPTPRIME - Endpoint Prime */
46241 /*! @{ */
46242 
46243 #define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
46244 #define USB_ENDPTPRIME_PERB_SHIFT                (0U)
46245 #define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
46246 
46247 #define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
46248 #define USB_ENDPTPRIME_PETB_SHIFT                (16U)
46249 #define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
46250 /*! @} */
46251 
46252 /*! @name ENDPTFLUSH - Endpoint Flush */
46253 /*! @{ */
46254 
46255 #define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
46256 #define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
46257 #define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
46258 
46259 #define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
46260 #define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
46261 #define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
46262 /*! @} */
46263 
46264 /*! @name ENDPTSTAT - Endpoint Status */
46265 /*! @{ */
46266 
46267 #define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
46268 #define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
46269 #define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
46270 
46271 #define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
46272 #define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
46273 #define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
46274 /*! @} */
46275 
46276 /*! @name ENDPTCOMPLETE - Endpoint Complete */
46277 /*! @{ */
46278 
46279 #define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
46280 #define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
46281 #define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
46282 
46283 #define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
46284 #define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
46285 #define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
46286 /*! @} */
46287 
46288 /*! @name ENDPTCTRL0 - Endpoint Control0 */
46289 /*! @{ */
46290 
46291 #define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
46292 #define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
46293 #define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
46294 
46295 #define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
46296 #define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
46297 #define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
46298 
46299 #define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
46300 #define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
46301 #define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
46302 
46303 #define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
46304 #define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
46305 #define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
46306 
46307 #define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
46308 #define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
46309 #define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
46310 
46311 #define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
46312 #define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
46313 #define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
46314 /*! @} */
46315 
46316 /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
46317 /*! @{ */
46318 
46319 #define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
46320 #define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
46321 #define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
46322 
46323 #define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
46324 #define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
46325 #define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
46326 
46327 #define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
46328 #define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
46329 #define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
46330 
46331 #define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
46332 #define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
46333 #define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
46334 
46335 #define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
46336 #define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
46337 #define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
46338 
46339 #define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
46340 #define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
46341 #define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
46342 
46343 #define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
46344 #define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
46345 #define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
46346 
46347 #define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
46348 #define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
46349 #define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
46350 
46351 #define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
46352 #define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
46353 #define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
46354 
46355 #define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
46356 #define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
46357 #define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
46358 
46359 #define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
46360 #define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
46361 #define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
46362 
46363 #define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
46364 #define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
46365 #define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
46366 /*! @} */
46367 
46368 /* The count of USB_ENDPTCTRL */
46369 #define USB_ENDPTCTRL_COUNT                      (7U)
46370 
46371 
46372 /*!
46373  * @}
46374  */ /* end of group USB_Register_Masks */
46375 
46376 
46377 /* USB - Peripheral instance base addresses */
46378 /** Peripheral USB1 base address */
46379 #define USB1_BASE                                (0x402E0000u)
46380 /** Peripheral USB1 base pointer */
46381 #define USB1                                     ((USB_Type *)USB1_BASE)
46382 /** Peripheral USB2 base address */
46383 #define USB2_BASE                                (0x402E0200u)
46384 /** Peripheral USB2 base pointer */
46385 #define USB2                                     ((USB_Type *)USB2_BASE)
46386 /** Array initializer of USB peripheral base addresses */
46387 #define USB_BASE_ADDRS                           { 0u, USB1_BASE, USB2_BASE }
46388 /** Array initializer of USB peripheral base pointers */
46389 #define USB_BASE_PTRS                            { (USB_Type *)0u, USB1, USB2 }
46390 /** Interrupt vectors for the USB peripheral type */
46391 #define USB_IRQS                                 { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
46392 /* Backward compatibility */
46393 #define GPTIMER0CTL                              GPTIMER0CTRL
46394 #define GPTIMER1CTL                              GPTIMER1CTRL
46395 #define USB_SBUSCFG                              SBUSCFG
46396 #define EPLISTADDR                               ENDPTLISTADDR
46397 #define EPSETUPSR                                ENDPTSETUPSTAT
46398 #define EPPRIME                                  ENDPTPRIME
46399 #define EPFLUSH                                  ENDPTFLUSH
46400 #define EPSR                                     ENDPTSTAT
46401 #define EPCOMPLETE                               ENDPTCOMPLETE
46402 #define EPCR                                     ENDPTCTRL
46403 #define EPCR0                                    ENDPTCTRL0
46404 #define USBHS_ID_ID_MASK                         USB_ID_ID_MASK
46405 #define USBHS_ID_ID_SHIFT                        USB_ID_ID_SHIFT
46406 #define USBHS_ID_ID(x)                           USB_ID_ID(x)
46407 #define USBHS_ID_NID_MASK                        USB_ID_NID_MASK
46408 #define USBHS_ID_NID_SHIFT                       USB_ID_NID_SHIFT
46409 #define USBHS_ID_NID(x)                          USB_ID_NID(x)
46410 #define USBHS_ID_REVISION_MASK                   USB_ID_REVISION_MASK
46411 #define USBHS_ID_REVISION_SHIFT                  USB_ID_REVISION_SHIFT
46412 #define USBHS_ID_REVISION(x)                     USB_ID_REVISION(x)
46413 #define USBHS_HWGENERAL_PHYW_MASK                USB_HWGENERAL_PHYW_MASK
46414 #define USBHS_HWGENERAL_PHYW_SHIFT               USB_HWGENERAL_PHYW_SHIFT
46415 #define USBHS_HWGENERAL_PHYW(x)                  USB_HWGENERAL_PHYW(x)
46416 #define USBHS_HWGENERAL_PHYM_MASK                USB_HWGENERAL_PHYM_MASK
46417 #define USBHS_HWGENERAL_PHYM_SHIFT               USB_HWGENERAL_PHYM_SHIFT
46418 #define USBHS_HWGENERAL_PHYM(x)                  USB_HWGENERAL_PHYM(x)
46419 #define USBHS_HWGENERAL_SM_MASK                  USB_HWGENERAL_SM_MASK
46420 #define USBHS_HWGENERAL_SM_SHIFT                 USB_HWGENERAL_SM_SHIFT
46421 #define USBHS_HWGENERAL_SM(x)                    USB_HWGENERAL_SM(x)
46422 #define USBHS_HWHOST_HC_MASK                     USB_HWHOST_HC_MASK
46423 #define USBHS_HWHOST_HC_SHIFT                    USB_HWHOST_HC_SHIFT
46424 #define USBHS_HWHOST_HC(x)                       USB_HWHOST_HC(x)
46425 #define USBHS_HWHOST_NPORT_MASK                  USB_HWHOST_NPORT_MASK
46426 #define USBHS_HWHOST_NPORT_SHIFT                 USB_HWHOST_NPORT_SHIFT
46427 #define USBHS_HWHOST_NPORT(x)                    USB_HWHOST_NPORT(x)
46428 #define USBHS_HWDEVICE_DC_MASK                   USB_HWDEVICE_DC_MASK
46429 #define USBHS_HWDEVICE_DC_SHIFT                  USB_HWDEVICE_DC_SHIFT
46430 #define USBHS_HWDEVICE_DC(x)                     USB_HWDEVICE_DC(x)
46431 #define USBHS_HWDEVICE_DEVEP_MASK                USB_HWDEVICE_DEVEP_MASK
46432 #define USBHS_HWDEVICE_DEVEP_SHIFT               USB_HWDEVICE_DEVEP_SHIFT
46433 #define USBHS_HWDEVICE_DEVEP(x)                  USB_HWDEVICE_DEVEP(x)
46434 #define USBHS_HWTXBUF_TXBURST_MASK               USB_HWTXBUF_TXBURST_MASK
46435 #define USBHS_HWTXBUF_TXBURST_SHIFT              USB_HWTXBUF_TXBURST_SHIFT
46436 #define USBHS_HWTXBUF_TXBURST(x)                 USB_HWTXBUF_TXBURST(x)
46437 #define USBHS_HWTXBUF_TXCHANADD_MASK             USB_HWTXBUF_TXCHANADD_MASK
46438 #define USBHS_HWTXBUF_TXCHANADD_SHIFT            USB_HWTXBUF_TXCHANADD_SHIFT
46439 #define USBHS_HWTXBUF_TXCHANADD(x)               USB_HWTXBUF_TXCHANADD(x)
46440 #define USBHS_HWRXBUF_RXBURST_MASK               USB_HWRXBUF_RXBURST_MASK
46441 #define USBHS_HWRXBUF_RXBURST_SHIFT              USB_HWRXBUF_RXBURST_SHIFT
46442 #define USBHS_HWRXBUF_RXBURST(x)                 USB_HWRXBUF_RXBURST(x)
46443 #define USBHS_HWRXBUF_RXADD_MASK                 USB_HWRXBUF_RXADD_MASK
46444 #define USBHS_HWRXBUF_RXADD_SHIFT                USB_HWRXBUF_RXADD_SHIFT
46445 #define USBHS_HWRXBUF_RXADD(x)                   USB_HWRXBUF_RXADD(x)
46446 #define USBHS_GPTIMER0LD_GPTLD_MASK              USB_GPTIMER0LD_GPTLD_MASK
46447 #define USBHS_GPTIMER0LD_GPTLD_SHIFT             USB_GPTIMER0LD_GPTLD_SHIFT
46448 #define USBHS_GPTIMER0LD_GPTLD(x)                USB_GPTIMER0LD_GPTLD(x)
46449 #define USBHS_GPTIMER0CTL_GPTCNT_MASK            USB_GPTIMER0CTRL_GPTCNT_MASK
46450 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USB_GPTIMER0CTRL_GPTCNT_SHIFT
46451 #define USBHS_GPTIMER0CTL_GPTCNT(x)              USB_GPTIMER0CTRL_GPTCNT(x)
46452 #define USBHS_GPTIMER0CTL_MODE_MASK              USB_GPTIMER0CTRL_GPTMODE_MASK
46453 #define USBHS_GPTIMER0CTL_MODE_SHIFT             USB_GPTIMER0CTRL_GPTMODE_SHIFT
46454 #define USBHS_GPTIMER0CTL_MODE(x)                USB_GPTIMER0CTRL_GPTMODE(x)
46455 #define USBHS_GPTIMER0CTL_RST_MASK               USB_GPTIMER0CTRL_GPTRST_MASK
46456 #define USBHS_GPTIMER0CTL_RST_SHIFT              USB_GPTIMER0CTRL_GPTRST_SHIFT
46457 #define USBHS_GPTIMER0CTL_RST(x)                 USB_GPTIMER0CTRL_GPTRST(x)
46458 #define USBHS_GPTIMER0CTL_RUN_MASK               USB_GPTIMER0CTRL_GPTRUN_MASK
46459 #define USBHS_GPTIMER0CTL_RUN_SHIFT              USB_GPTIMER0CTRL_GPTRUN_SHIFT
46460 #define USBHS_GPTIMER0CTL_RUN(x)                 USB_GPTIMER0CTRL_GPTRUN(x)
46461 #define USBHS_GPTIMER1LD_GPTLD_MASK              USB_GPTIMER1LD_GPTLD_MASK
46462 #define USBHS_GPTIMER1LD_GPTLD_SHIFT             USB_GPTIMER1LD_GPTLD_SHIFT
46463 #define USBHS_GPTIMER1LD_GPTLD(x)                USB_GPTIMER1LD_GPTLD(x)
46464 #define USBHS_GPTIMER1CTL_GPTCNT_MASK            USB_GPTIMER1CTRL_GPTCNT_MASK
46465 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USB_GPTIMER1CTRL_GPTCNT_SHIFT
46466 #define USBHS_GPTIMER1CTL_GPTCNT(x)              USB_GPTIMER1CTRL_GPTCNT(x)
46467 #define USBHS_GPTIMER1CTL_MODE_MASK              USB_GPTIMER1CTRL_GPTMODE_MASK
46468 #define USBHS_GPTIMER1CTL_MODE_SHIFT             USB_GPTIMER1CTRL_GPTMODE_SHIFT
46469 #define USBHS_GPTIMER1CTL_MODE(x)                USB_GPTIMER1CTRL_GPTMODE(x)
46470 #define USBHS_GPTIMER1CTL_RST_MASK               USB_GPTIMER1CTRL_GPTRST_MASK
46471 #define USBHS_GPTIMER1CTL_RST_SHIFT              USB_GPTIMER1CTRL_GPTRST_SHIFT
46472 #define USBHS_GPTIMER1CTL_RST(x)                 USB_GPTIMER1CTRL_GPTRST(x)
46473 #define USBHS_GPTIMER1CTL_RUN_MASK               USB_GPTIMER1CTRL_GPTRUN_MASK
46474 #define USBHS_GPTIMER1CTL_RUN_SHIFT              USB_GPTIMER1CTRL_GPTRUN_SHIFT
46475 #define USBHS_GPTIMER1CTL_RUN(x)                 USB_GPTIMER1CTRL_GPTRUN(x)
46476 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK         USB_SBUSCFG_AHBBRST_MASK
46477 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT        USB_SBUSCFG_AHBBRST_SHIFT
46478 #define USBHS_USB_SBUSCFG_BURSTMODE(x)           USB_SBUSCFG_AHBBRST(x)
46479 #define USBHS_HCIVERSION_CAPLENGTH(x)            USB_HCIVERSION_CAPLENGTH(x)
46480 #define USBHS_HCIVERSION_HCIVERSION_MASK         USB_HCIVERSION_HCIVERSION_MASK
46481 #define USBHS_HCIVERSION_HCIVERSION_SHIFT        USB_HCIVERSION_HCIVERSION_SHIFT
46482 #define USBHS_HCIVERSION_HCIVERSION(x)           USB_HCIVERSION_HCIVERSION(x)
46483 #define USBHS_HCSPARAMS_N_PORTS_MASK             USB_HCSPARAMS_N_PORTS_MASK
46484 #define USBHS_HCSPARAMS_N_PORTS_SHIFT            USB_HCSPARAMS_N_PORTS_SHIFT
46485 #define USBHS_HCSPARAMS_N_PORTS(x)               USB_HCSPARAMS_N_PORTS(x)
46486 #define USBHS_HCSPARAMS_PPC_MASK                 USB_HCSPARAMS_PPC_MASK
46487 #define USBHS_HCSPARAMS_PPC_SHIFT                USB_HCSPARAMS_PPC_SHIFT
46488 #define USBHS_HCSPARAMS_PPC(x)                   USB_HCSPARAMS_PPC(x)
46489 #define USBHS_HCSPARAMS_N_PCC_MASK               USB_HCSPARAMS_N_PCC_MASK
46490 #define USBHS_HCSPARAMS_N_PCC_SHIFT              USB_HCSPARAMS_N_PCC_SHIFT
46491 #define USBHS_HCSPARAMS_N_PCC(x)                 USB_HCSPARAMS_N_PCC(x)
46492 #define USBHS_HCSPARAMS_N_CC_MASK                USB_HCSPARAMS_N_CC_MASK
46493 #define USBHS_HCSPARAMS_N_CC_SHIFT               USB_HCSPARAMS_N_CC_SHIFT
46494 #define USBHS_HCSPARAMS_N_CC(x)                  USB_HCSPARAMS_N_CC(x)
46495 #define USBHS_HCSPARAMS_PI_MASK                  USB_HCSPARAMS_PI_MASK
46496 #define USBHS_HCSPARAMS_PI_SHIFT                 USB_HCSPARAMS_PI_SHIFT
46497 #define USBHS_HCSPARAMS_PI(x)                    USB_HCSPARAMS_PI(x)
46498 #define USBHS_HCSPARAMS_N_PTT_MASK               USB_HCSPARAMS_N_PTT_MASK
46499 #define USBHS_HCSPARAMS_N_PTT_SHIFT              USB_HCSPARAMS_N_PTT_SHIFT
46500 #define USBHS_HCSPARAMS_N_PTT(x)                 USB_HCSPARAMS_N_PTT(x)
46501 #define USBHS_HCSPARAMS_N_TT_MASK                USB_HCSPARAMS_N_TT_MASK
46502 #define USBHS_HCSPARAMS_N_TT_SHIFT               USB_HCSPARAMS_N_TT_SHIFT
46503 #define USBHS_HCSPARAMS_N_TT(x)                  USB_HCSPARAMS_N_TT(x)
46504 #define USBHS_HCCPARAMS_ADC_MASK                 USB_HCCPARAMS_ADC_MASK
46505 #define USBHS_HCCPARAMS_ADC_SHIFT                USB_HCCPARAMS_ADC_SHIFT
46506 #define USBHS_HCCPARAMS_ADC(x)                   USB_HCCPARAMS_ADC(x)
46507 #define USBHS_HCCPARAMS_PFL_MASK                 USB_HCCPARAMS_PFL_MASK
46508 #define USBHS_HCCPARAMS_PFL_SHIFT                USB_HCCPARAMS_PFL_SHIFT
46509 #define USBHS_HCCPARAMS_PFL(x)                   USB_HCCPARAMS_PFL(x)
46510 #define USBHS_HCCPARAMS_ASP_MASK                 USB_HCCPARAMS_ASP_MASK
46511 #define USBHS_HCCPARAMS_ASP_SHIFT                USB_HCCPARAMS_ASP_SHIFT
46512 #define USBHS_HCCPARAMS_ASP(x)                   USB_HCCPARAMS_ASP(x)
46513 #define USBHS_HCCPARAMS_IST_MASK                 USB_HCCPARAMS_IST_MASK
46514 #define USBHS_HCCPARAMS_IST_SHIFT                USB_HCCPARAMS_IST_SHIFT
46515 #define USBHS_HCCPARAMS_IST(x)                   USB_HCCPARAMS_IST(x)
46516 #define USBHS_HCCPARAMS_EECP_MASK                USB_HCCPARAMS_EECP_MASK
46517 #define USBHS_HCCPARAMS_EECP_SHIFT               USB_HCCPARAMS_EECP_SHIFT
46518 #define USBHS_HCCPARAMS_EECP(x)                  USB_HCCPARAMS_EECP(x)
46519 #define USBHS_DCIVERSION_DCIVERSION_MASK         USB_DCIVERSION_DCIVERSION_MASK
46520 #define USBHS_DCIVERSION_DCIVERSION_SHIFT        USB_DCIVERSION_DCIVERSION_SHIFT
46521 #define USBHS_DCIVERSION_DCIVERSION(x)           USB_DCIVERSION_DCIVERSION(x)
46522 #define USBHS_DCCPARAMS_DEN_MASK                 USB_DCCPARAMS_DEN_MASK
46523 #define USBHS_DCCPARAMS_DEN_SHIFT                USB_DCCPARAMS_DEN_SHIFT
46524 #define USBHS_DCCPARAMS_DEN(x)                   USB_DCCPARAMS_DEN(x)
46525 #define USBHS_DCCPARAMS_DC_MASK                  USB_DCCPARAMS_DC_MASK
46526 #define USBHS_DCCPARAMS_DC_SHIFT                 USB_DCCPARAMS_DC_SHIFT
46527 #define USBHS_DCCPARAMS_DC(x)                    USB_DCCPARAMS_DC(x)
46528 #define USBHS_DCCPARAMS_HC_MASK                  USB_DCCPARAMS_HC_MASK
46529 #define USBHS_DCCPARAMS_HC_SHIFT                 USB_DCCPARAMS_HC_SHIFT
46530 #define USBHS_DCCPARAMS_HC(x)                    USB_DCCPARAMS_HC(x)
46531 #define USBHS_USBCMD_RS_MASK                     USB_USBCMD_RS_MASK
46532 #define USBHS_USBCMD_RS_SHIFT                    USB_USBCMD_RS_SHIFT
46533 #define USBHS_USBCMD_RS(x)                       USB_USBCMD_RS(x)
46534 #define USBHS_USBCMD_RST_MASK                    USB_USBCMD_RST_MASK
46535 #define USBHS_USBCMD_RST_SHIFT                   USB_USBCMD_RST_SHIFT
46536 #define USBHS_USBCMD_RST(x)                      USB_USBCMD_RST(x)
46537 #define USBHS_USBCMD_FS_MASK                     USB_USBCMD_FS_1_MASK
46538 #define USBHS_USBCMD_FS_SHIFT                    USB_USBCMD_FS_1_SHIFT
46539 #define USBHS_USBCMD_FS(x)                       USB_USBCMD_FS_1(x)
46540 #define USBHS_USBCMD_PSE_MASK                    USB_USBCMD_PSE_MASK
46541 #define USBHS_USBCMD_PSE_SHIFT                   USB_USBCMD_PSE_SHIFT
46542 #define USBHS_USBCMD_PSE(x)                      USB_USBCMD_PSE(x)
46543 #define USBHS_USBCMD_ASE_MASK                    USB_USBCMD_ASE_MASK
46544 #define USBHS_USBCMD_ASE_SHIFT                   USB_USBCMD_ASE_SHIFT
46545 #define USBHS_USBCMD_ASE(x)                      USB_USBCMD_ASE(x)
46546 #define USBHS_USBCMD_IAA_MASK                    USB_USBCMD_IAA_MASK
46547 #define USBHS_USBCMD_IAA_SHIFT                   USB_USBCMD_IAA_SHIFT
46548 #define USBHS_USBCMD_IAA(x)                      USB_USBCMD_IAA(x)
46549 #define USBHS_USBCMD_ASP_MASK                    USB_USBCMD_ASP_MASK
46550 #define USBHS_USBCMD_ASP_SHIFT                   USB_USBCMD_ASP_SHIFT
46551 #define USBHS_USBCMD_ASP(x)                      USB_USBCMD_ASP(x)
46552 #define USBHS_USBCMD_ASPE_MASK                   USB_USBCMD_ASPE_MASK
46553 #define USBHS_USBCMD_ASPE_SHIFT                  USB_USBCMD_ASPE_SHIFT
46554 #define USBHS_USBCMD_ASPE(x)                     USB_USBCMD_ASPE(x)
46555 #define USBHS_USBCMD_ATDTW_MASK                  USB_USBCMD_ATDTW_MASK
46556 #define USBHS_USBCMD_ATDTW_SHIFT                 USB_USBCMD_ATDTW_SHIFT
46557 #define USBHS_USBCMD_ATDTW(x)                    USB_USBCMD_ATDTW(x)
46558 #define USBHS_USBCMD_SUTW_MASK                   USB_USBCMD_SUTW_MASK
46559 #define USBHS_USBCMD_SUTW_SHIFT                  USB_USBCMD_SUTW_SHIFT
46560 #define USBHS_USBCMD_SUTW(x)                     USB_USBCMD_SUTW(x)
46561 #define USBHS_USBCMD_FS2_MASK                    USB_USBCMD_FS_2_MASK
46562 #define USBHS_USBCMD_FS2_SHIFT                   USB_USBCMD_FS_2_SHIFT
46563 #define USBHS_USBCMD_FS2(x)                      USB_USBCMD_FS_2(x)
46564 #define USBHS_USBCMD_ITC_MASK                    USB_USBCMD_ITC_MASK
46565 #define USBHS_USBCMD_ITC_SHIFT                   USB_USBCMD_ITC_SHIFT
46566 #define USBHS_USBCMD_ITC(x)                      USB_USBCMD_ITC(x)
46567 #define USBHS_USBSTS_UI_MASK                     USB_USBSTS_UI_MASK
46568 #define USBHS_USBSTS_UI_SHIFT                    USB_USBSTS_UI_SHIFT
46569 #define USBHS_USBSTS_UI(x)                       USB_USBSTS_UI(x)
46570 #define USBHS_USBSTS_UEI_MASK                    USB_USBSTS_UEI_MASK
46571 #define USBHS_USBSTS_UEI_SHIFT                   USB_USBSTS_UEI_SHIFT
46572 #define USBHS_USBSTS_UEI(x)                      USB_USBSTS_UEI(x)
46573 #define USBHS_USBSTS_PCI_MASK                    USB_USBSTS_PCI_MASK
46574 #define USBHS_USBSTS_PCI_SHIFT                   USB_USBSTS_PCI_SHIFT
46575 #define USBHS_USBSTS_PCI(x)                      USB_USBSTS_PCI(x)
46576 #define USBHS_USBSTS_FRI_MASK                    USB_USBSTS_FRI_MASK
46577 #define USBHS_USBSTS_FRI_SHIFT                   USB_USBSTS_FRI_SHIFT
46578 #define USBHS_USBSTS_FRI(x)                      USB_USBSTS_FRI(x)
46579 #define USBHS_USBSTS_SEI_MASK                    USB_USBSTS_SEI_MASK
46580 #define USBHS_USBSTS_SEI_SHIFT                   USB_USBSTS_SEI_SHIFT
46581 #define USBHS_USBSTS_SEI(x)                      USB_USBSTS_SEI(x)
46582 #define USBHS_USBSTS_AAI_MASK                    USB_USBSTS_AAI_MASK
46583 #define USBHS_USBSTS_AAI_SHIFT                   USB_USBSTS_AAI_SHIFT
46584 #define USBHS_USBSTS_AAI(x)                      USB_USBSTS_AAI(x)
46585 #define USBHS_USBSTS_URI_MASK                    USB_USBSTS_URI_MASK
46586 #define USBHS_USBSTS_URI_SHIFT                   USB_USBSTS_URI_SHIFT
46587 #define USBHS_USBSTS_URI(x)                      USB_USBSTS_URI(x)
46588 #define USBHS_USBSTS_SRI_MASK                    USB_USBSTS_SRI_MASK
46589 #define USBHS_USBSTS_SRI_SHIFT                   USB_USBSTS_SRI_SHIFT
46590 #define USBHS_USBSTS_SRI(x)                      USB_USBSTS_SRI(x)
46591 #define USBHS_USBSTS_SLI_MASK                    USB_USBSTS_SLI_MASK
46592 #define USBHS_USBSTS_SLI_SHIFT                   USB_USBSTS_SLI_SHIFT
46593 #define USBHS_USBSTS_SLI(x)                      USB_USBSTS_SLI(x)
46594 #define USBHS_USBSTS_ULPII_MASK                  USB_USBSTS_ULPII_MASK
46595 #define USBHS_USBSTS_ULPII_SHIFT                 USB_USBSTS_ULPII_SHIFT
46596 #define USBHS_USBSTS_ULPII(x)                    USB_USBSTS_ULPII(x)
46597 #define USBHS_USBSTS_HCH_MASK                    USB_USBSTS_HCH_MASK
46598 #define USBHS_USBSTS_HCH_SHIFT                   USB_USBSTS_HCH_SHIFT
46599 #define USBHS_USBSTS_HCH(x)                      USB_USBSTS_HCH(x)
46600 #define USBHS_USBSTS_RCL_MASK                    USB_USBSTS_RCL_MASK
46601 #define USBHS_USBSTS_RCL_SHIFT                   USB_USBSTS_RCL_SHIFT
46602 #define USBHS_USBSTS_RCL(x)                      USB_USBSTS_RCL(x)
46603 #define USBHS_USBSTS_PS_MASK                     USB_USBSTS_PS_MASK
46604 #define USBHS_USBSTS_PS_SHIFT                    USB_USBSTS_PS_SHIFT
46605 #define USBHS_USBSTS_PS(x)                       USB_USBSTS_PS(x)
46606 #define USBHS_USBSTS_AS_MASK                     USB_USBSTS_AS_MASK
46607 #define USBHS_USBSTS_AS_SHIFT                    USB_USBSTS_AS_SHIFT
46608 #define USBHS_USBSTS_AS(x)                       USB_USBSTS_AS(x)
46609 #define USBHS_USBSTS_NAKI_MASK                   USB_USBSTS_NAKI_MASK
46610 #define USBHS_USBSTS_NAKI_SHIFT                  USB_USBSTS_NAKI_SHIFT
46611 #define USBHS_USBSTS_NAKI(x)                     USB_USBSTS_NAKI(x)
46612 #define USBHS_USBSTS_TI0_MASK                    USB_USBSTS_TI0_MASK
46613 #define USBHS_USBSTS_TI0_SHIFT                   USB_USBSTS_TI0_SHIFT
46614 #define USBHS_USBSTS_TI0(x)                      USB_USBSTS_TI0(x)
46615 #define USBHS_USBSTS_TI1_MASK                    USB_USBSTS_TI1_MASK
46616 #define USBHS_USBSTS_TI1_SHIFT                   USB_USBSTS_TI1_SHIFT
46617 #define USBHS_USBSTS_TI1(x)                      USB_USBSTS_TI1(x)
46618 #define USBHS_USBINTR_UE_MASK                    USB_USBINTR_UE_MASK
46619 #define USBHS_USBINTR_UE_SHIFT                   USB_USBINTR_UE_SHIFT
46620 #define USBHS_USBINTR_UE(x)                      USB_USBINTR_UE(x)
46621 #define USBHS_USBINTR_UEE_MASK                   USB_USBINTR_UEE_MASK
46622 #define USBHS_USBINTR_UEE_SHIFT                  USB_USBINTR_UEE_SHIFT
46623 #define USBHS_USBINTR_UEE(x)                     USB_USBINTR_UEE(x)
46624 #define USBHS_USBINTR_PCE_MASK                   USB_USBINTR_PCE_MASK
46625 #define USBHS_USBINTR_PCE_SHIFT                  USB_USBINTR_PCE_SHIFT
46626 #define USBHS_USBINTR_PCE(x)                     USB_USBINTR_PCE(x)
46627 #define USBHS_USBINTR_FRE_MASK                   USB_USBINTR_FRE_MASK
46628 #define USBHS_USBINTR_FRE_SHIFT                  USB_USBINTR_FRE_SHIFT
46629 #define USBHS_USBINTR_FRE(x)                     USB_USBINTR_FRE(x)
46630 #define USBHS_USBINTR_SEE_MASK                   USB_USBINTR_SEE_MASK
46631 #define USBHS_USBINTR_SEE_SHIFT                  USB_USBINTR_SEE_SHIFT
46632 #define USBHS_USBINTR_SEE(x)                     USB_USBINTR_SEE(x)
46633 #define USBHS_USBINTR_AAE_MASK                   USB_USBINTR_AAE_MASK
46634 #define USBHS_USBINTR_AAE_SHIFT                  USB_USBINTR_AAE_SHIFT
46635 #define USBHS_USBINTR_AAE(x)                     USB_USBINTR_AAE(x)
46636 #define USBHS_USBINTR_URE_MASK                   USB_USBINTR_URE_MASK
46637 #define USBHS_USBINTR_URE_SHIFT                  USB_USBINTR_URE_SHIFT
46638 #define USBHS_USBINTR_URE(x)                     USB_USBINTR_URE(x)
46639 #define USBHS_USBINTR_SRE_MASK                   USB_USBINTR_SRE_MASK
46640 #define USBHS_USBINTR_SRE_SHIFT                  USB_USBINTR_SRE_SHIFT
46641 #define USBHS_USBINTR_SRE(x)                     USB_USBINTR_SRE(x)
46642 #define USBHS_USBINTR_SLE_MASK                   USB_USBINTR_SLE_MASK
46643 #define USBHS_USBINTR_SLE_SHIFT                  USB_USBINTR_SLE_SHIFT
46644 #define USBHS_USBINTR_SLE(x)                     USB_USBINTR_SLE(x)
46645 #define USBHS_USBINTR_ULPIE_MASK                 USB_USBINTR_ULPIE_MASK
46646 #define USBHS_USBINTR_ULPIE_SHIFT                USB_USBINTR_ULPIE_SHIFT
46647 #define USBHS_USBINTR_ULPIE(x)                   USB_USBINTR_ULPIE(x)
46648 #define USBHS_USBINTR_NAKE_MASK                  USB_USBINTR_NAKE_MASK
46649 #define USBHS_USBINTR_NAKE_SHIFT                 USB_USBINTR_NAKE_SHIFT
46650 #define USBHS_USBINTR_NAKE(x)                    USB_USBINTR_NAKE(x)
46651 #define USBHS_USBINTR_UAIE_MASK                  USB_USBINTR_UAIE_MASK
46652 #define USBHS_USBINTR_UAIE_SHIFT                 USB_USBINTR_UAIE_SHIFT
46653 #define USBHS_USBINTR_UAIE(x)                    USB_USBINTR_UAIE(x)
46654 #define USBHS_USBINTR_UPIE_MASK                  USB_USBINTR_UPIE_MASK
46655 #define USBHS_USBINTR_UPIE_SHIFT                 USB_USBINTR_UPIE_SHIFT
46656 #define USBHS_USBINTR_UPIE(x)                    USB_USBINTR_UPIE(x)
46657 #define USBHS_USBINTR_TIE0_MASK                  USB_USBINTR_TIE0_MASK
46658 #define USBHS_USBINTR_TIE0_SHIFT                 USB_USBINTR_TIE0_SHIFT
46659 #define USBHS_USBINTR_TIE0(x)                    USB_USBINTR_TIE0(x)
46660 #define USBHS_USBINTR_TIE1_MASK                  USB_USBINTR_TIE1_MASK
46661 #define USBHS_USBINTR_TIE1_SHIFT                 USB_USBINTR_TIE1_SHIFT
46662 #define USBHS_USBINTR_TIE1(x)                    USB_USBINTR_TIE1(x)
46663 #define USBHS_FRINDEX_FRINDEX_MASK               USB_FRINDEX_FRINDEX_MASK
46664 #define USBHS_FRINDEX_FRINDEX_SHIFT              USB_FRINDEX_FRINDEX_SHIFT
46665 #define USBHS_FRINDEX_FRINDEX(x)                 USB_FRINDEX_FRINDEX(x)
46666 #define USBHS_DEVICEADDR_USBADRA_MASK            USB_DEVICEADDR_USBADRA_MASK
46667 #define USBHS_DEVICEADDR_USBADRA_SHIFT           USB_DEVICEADDR_USBADRA_SHIFT
46668 #define USBHS_DEVICEADDR_USBADRA(x)              USB_DEVICEADDR_USBADRA(x)
46669 #define USBHS_DEVICEADDR_USBADR_MASK             USB_DEVICEADDR_USBADR_MASK
46670 #define USBHS_DEVICEADDR_USBADR_SHIFT            USB_DEVICEADDR_USBADR_SHIFT
46671 #define USBHS_DEVICEADDR_USBADR(x)               USB_DEVICEADDR_USBADR(x)
46672 #define USBHS_PERIODICLISTBASE_PERBASE_MASK      USB_PERIODICLISTBASE_BASEADR_MASK
46673 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     USB_PERIODICLISTBASE_BASEADR_SHIFT
46674 #define USBHS_PERIODICLISTBASE_PERBASE(x)        USB_PERIODICLISTBASE_BASEADR(x)
46675 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK         USB_ASYNCLISTADDR_ASYBASE_MASK
46676 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        USB_ASYNCLISTADDR_ASYBASE_SHIFT
46677 #define USBHS_ASYNCLISTADDR_ASYBASE(x)           USB_ASYNCLISTADDR_ASYBASE(x)
46678 #define USBHS_EPLISTADDR_EPBASE_MASK             USB_ENDPTLISTADDR_EPBASE_MASK
46679 #define USBHS_EPLISTADDR_EPBASE_SHIFT            USB_ENDPTLISTADDR_EPBASE_SHIFT
46680 #define USBHS_EPLISTADDR_EPBASE(x)               USB_ENDPTLISTADDR_EPBASE(x)
46681 #define USBHS_BURSTSIZE_RXPBURST_MASK            USB_BURSTSIZE_RXPBURST_MASK
46682 #define USBHS_BURSTSIZE_RXPBURST_SHIFT           USB_BURSTSIZE_RXPBURST_SHIFT
46683 #define USBHS_BURSTSIZE_RXPBURST(x)              USB_BURSTSIZE_RXPBURST(x)
46684 #define USBHS_BURSTSIZE_TXPBURST_MASK            USB_BURSTSIZE_TXPBURST_MASK
46685 #define USBHS_BURSTSIZE_TXPBURST_SHIFT           USB_BURSTSIZE_TXPBURST_SHIFT
46686 #define USBHS_BURSTSIZE_TXPBURST(x)              USB_BURSTSIZE_TXPBURST(x)
46687 #define USBHS_TXFILLTUNING_TXSCHOH_MASK          USB_TXFILLTUNING_TXSCHOH_MASK
46688 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         USB_TXFILLTUNING_TXSCHOH_SHIFT
46689 #define USBHS_TXFILLTUNING_TXSCHOH(x)            USB_TXFILLTUNING_TXSCHOH(x)
46690 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      USB_TXFILLTUNING_TXSCHHEALTH_MASK
46691 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
46692 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        USB_TXFILLTUNING_TXSCHHEALTH(x)
46693 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      USB_TXFILLTUNING_TXFIFOTHRES_MASK
46694 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
46695 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        USB_TXFILLTUNING_TXFIFOTHRES(x)
46696 #define USBHS_ENDPTNAK_EPRN_MASK                 USB_ENDPTNAK_EPRN_MASK
46697 #define USBHS_ENDPTNAK_EPRN_SHIFT                USB_ENDPTNAK_EPRN_SHIFT
46698 #define USBHS_ENDPTNAK_EPRN(x)                   USB_ENDPTNAK_EPRN(x)
46699 #define USBHS_ENDPTNAK_EPTN_MASK                 USB_ENDPTNAK_EPTN_MASK
46700 #define USBHS_ENDPTNAK_EPTN_SHIFT                USB_ENDPTNAK_EPTN_SHIFT
46701 #define USBHS_ENDPTNAK_EPTN(x)                   USB_ENDPTNAK_EPTN(x)
46702 #define USBHS_ENDPTNAKEN_EPRNE_MASK              USB_ENDPTNAKEN_EPRNE_MASK
46703 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT             USB_ENDPTNAKEN_EPRNE_SHIFT
46704 #define USBHS_ENDPTNAKEN_EPRNE(x)                USB_ENDPTNAKEN_EPRNE(x)
46705 #define USBHS_ENDPTNAKEN_EPTNE_MASK              USB_ENDPTNAKEN_EPTNE_MASK
46706 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT             USB_ENDPTNAKEN_EPTNE_SHIFT
46707 #define USBHS_ENDPTNAKEN_EPTNE(x)                USB_ENDPTNAKEN_EPTNE(x)
46708 #define USBHS_CONFIGFLAG_CF_MASK                 USB_CONFIGFLAG_CF_MASK
46709 #define USBHS_CONFIGFLAG_CF_SHIFT                USB_CONFIGFLAG_CF_SHIFT
46710 #define USBHS_CONFIGFLAG_CF(x)                   USB_CONFIGFLAG_CF(x)
46711 #define USBHS_PORTSC1_CCS_MASK                   USB_PORTSC1_CCS_MASK
46712 #define USBHS_PORTSC1_CCS_SHIFT                  USB_PORTSC1_CCS_SHIFT
46713 #define USBHS_PORTSC1_CCS(x)                     USB_PORTSC1_CCS(x)
46714 #define USBHS_PORTSC1_CSC_MASK                   USB_PORTSC1_CSC_MASK
46715 #define USBHS_PORTSC1_CSC_SHIFT                  USB_PORTSC1_CSC_SHIFT
46716 #define USBHS_PORTSC1_CSC(x)                     USB_PORTSC1_CSC(x)
46717 #define USBHS_PORTSC1_PE_MASK                    USB_PORTSC1_PE_MASK
46718 #define USBHS_PORTSC1_PE_SHIFT                   USB_PORTSC1_PE_SHIFT
46719 #define USBHS_PORTSC1_PE(x)                      USB_PORTSC1_PE(x)
46720 #define USBHS_PORTSC1_PEC_MASK                   USB_PORTSC1_PEC_MASK
46721 #define USBHS_PORTSC1_PEC_SHIFT                  USB_PORTSC1_PEC_SHIFT
46722 #define USBHS_PORTSC1_PEC(x)                     USB_PORTSC1_PEC(x)
46723 #define USBHS_PORTSC1_OCA_MASK                   USB_PORTSC1_OCA_MASK
46724 #define USBHS_PORTSC1_OCA_SHIFT                  USB_PORTSC1_OCA_SHIFT
46725 #define USBHS_PORTSC1_OCA(x)                     USB_PORTSC1_OCA(x)
46726 #define USBHS_PORTSC1_OCC_MASK                   USB_PORTSC1_OCC_MASK
46727 #define USBHS_PORTSC1_OCC_SHIFT                  USB_PORTSC1_OCC_SHIFT
46728 #define USBHS_PORTSC1_OCC(x)                     USB_PORTSC1_OCC(x)
46729 #define USBHS_PORTSC1_FPR_MASK                   USB_PORTSC1_FPR_MASK
46730 #define USBHS_PORTSC1_FPR_SHIFT                  USB_PORTSC1_FPR_SHIFT
46731 #define USBHS_PORTSC1_FPR(x)                     USB_PORTSC1_FPR(x)
46732 #define USBHS_PORTSC1_SUSP_MASK                  USB_PORTSC1_SUSP_MASK
46733 #define USBHS_PORTSC1_SUSP_SHIFT                 USB_PORTSC1_SUSP_SHIFT
46734 #define USBHS_PORTSC1_SUSP(x)                    USB_PORTSC1_SUSP(x)
46735 #define USBHS_PORTSC1_PR_MASK                    USB_PORTSC1_PR_MASK
46736 #define USBHS_PORTSC1_PR_SHIFT                   USB_PORTSC1_PR_SHIFT
46737 #define USBHS_PORTSC1_PR(x)                      USB_PORTSC1_PR(x)
46738 #define USBHS_PORTSC1_HSP_MASK                   USB_PORTSC1_HSP_MASK
46739 #define USBHS_PORTSC1_HSP_SHIFT                  USB_PORTSC1_HSP_SHIFT
46740 #define USBHS_PORTSC1_HSP(x)                     USB_PORTSC1_HSP(x)
46741 #define USBHS_PORTSC1_LS_MASK                    USB_PORTSC1_LS_MASK
46742 #define USBHS_PORTSC1_LS_SHIFT                   USB_PORTSC1_LS_SHIFT
46743 #define USBHS_PORTSC1_LS(x)                      USB_PORTSC1_LS(x)
46744 #define USBHS_PORTSC1_PP_MASK                    USB_PORTSC1_PP_MASK
46745 #define USBHS_PORTSC1_PP_SHIFT                   USB_PORTSC1_PP_SHIFT
46746 #define USBHS_PORTSC1_PP(x)                      USB_PORTSC1_PP(x)
46747 #define USBHS_PORTSC1_PO_MASK                    USB_PORTSC1_PO_MASK
46748 #define USBHS_PORTSC1_PO_SHIFT                   USB_PORTSC1_PO_SHIFT
46749 #define USBHS_PORTSC1_PO(x)                      USB_PORTSC1_PO(x)
46750 #define USBHS_PORTSC1_PIC_MASK                   USB_PORTSC1_PIC_MASK
46751 #define USBHS_PORTSC1_PIC_SHIFT                  USB_PORTSC1_PIC_SHIFT
46752 #define USBHS_PORTSC1_PIC(x)                     USB_PORTSC1_PIC(x)
46753 #define USBHS_PORTSC1_PTC_MASK                   USB_PORTSC1_PTC_MASK
46754 #define USBHS_PORTSC1_PTC_SHIFT                  USB_PORTSC1_PTC_SHIFT
46755 #define USBHS_PORTSC1_PTC(x)                     USB_PORTSC1_PTC(x)
46756 #define USBHS_PORTSC1_WKCN_MASK                  USB_PORTSC1_WKCN_MASK
46757 #define USBHS_PORTSC1_WKCN_SHIFT                 USB_PORTSC1_WKCN_SHIFT
46758 #define USBHS_PORTSC1_WKCN(x)                    USB_PORTSC1_WKCN(x)
46759 #define USBHS_PORTSC1_WKDS_MASK                  USB_PORTSC1_WKDC_MASK
46760 #define USBHS_PORTSC1_WKDS_SHIFT                 USB_PORTSC1_WKDC_SHIFT
46761 #define USBHS_PORTSC1_WKDS(x)                    USB_PORTSC1_WKDC(x)
46762 #define USBHS_PORTSC1_WKOC_MASK                  USB_PORTSC1_WKOC_MASK
46763 #define USBHS_PORTSC1_WKOC_SHIFT                 USB_PORTSC1_WKOC_SHIFT
46764 #define USBHS_PORTSC1_WKOC(x)                    USB_PORTSC1_WKOC(x)
46765 #define USBHS_PORTSC1_PHCD_MASK                  USB_PORTSC1_PHCD_MASK
46766 #define USBHS_PORTSC1_PHCD_SHIFT                 USB_PORTSC1_PHCD_SHIFT
46767 #define USBHS_PORTSC1_PHCD(x)                    USB_PORTSC1_PHCD(x)
46768 #define USBHS_PORTSC1_PFSC_MASK                  USB_PORTSC1_PFSC_MASK
46769 #define USBHS_PORTSC1_PFSC_SHIFT                 USB_PORTSC1_PFSC_SHIFT
46770 #define USBHS_PORTSC1_PFSC(x)                    USB_PORTSC1_PFSC(x)
46771 #define USBHS_PORTSC1_PTS2_MASK                  USB_PORTSC1_PTS_2_MASK
46772 #define USBHS_PORTSC1_PTS2_SHIFT                 USB_PORTSC1_PTS_2_SHIFT
46773 #define USBHS_PORTSC1_PTS2(x)                    USB_PORTSC1_PTS_2(x)
46774 #define USBHS_PORTSC1_PSPD_MASK                  USB_PORTSC1_PSPD_MASK
46775 #define USBHS_PORTSC1_PSPD_SHIFT                 USB_PORTSC1_PSPD_SHIFT
46776 #define USBHS_PORTSC1_PSPD(x)                    USB_PORTSC1_PSPD(x)
46777 #define USBHS_PORTSC1_PTW_MASK                   USB_PORTSC1_PTW_MASK
46778 #define USBHS_PORTSC1_PTW_SHIFT                  USB_PORTSC1_PTW_SHIFT
46779 #define USBHS_PORTSC1_PTW(x)                     USB_PORTSC1_PTW(x)
46780 #define USBHS_PORTSC1_STS_MASK                   USB_PORTSC1_STS_MASK
46781 #define USBHS_PORTSC1_STS_SHIFT                  USB_PORTSC1_STS_SHIFT
46782 #define USBHS_PORTSC1_STS(x)                     USB_PORTSC1_STS(x)
46783 #define USBHS_PORTSC1_PTS_MASK                   USB_PORTSC1_PTS_1_MASK
46784 #define USBHS_PORTSC1_PTS_SHIFT                  USB_PORTSC1_PTS_1_SHIFT
46785 #define USBHS_PORTSC1_PTS(x)                     USB_PORTSC1_PTS_1(x)
46786 #define USBHS_OTGSC_VD_MASK                      USB_OTGSC_VD_MASK
46787 #define USBHS_OTGSC_VD_SHIFT                     USB_OTGSC_VD_SHIFT
46788 #define USBHS_OTGSC_VD(x)                        USB_OTGSC_VD(x)
46789 #define USBHS_OTGSC_VC_MASK                      USB_OTGSC_VC_MASK
46790 #define USBHS_OTGSC_VC_SHIFT                     USB_OTGSC_VC_SHIFT
46791 #define USBHS_OTGSC_VC(x)                        USB_OTGSC_VC(x)
46792 #define USBHS_OTGSC_OT_MASK                      USB_OTGSC_OT_MASK
46793 #define USBHS_OTGSC_OT_SHIFT                     USB_OTGSC_OT_SHIFT
46794 #define USBHS_OTGSC_OT(x)                        USB_OTGSC_OT(x)
46795 #define USBHS_OTGSC_DP_MASK                      USB_OTGSC_DP_MASK
46796 #define USBHS_OTGSC_DP_SHIFT                     USB_OTGSC_DP_SHIFT
46797 #define USBHS_OTGSC_DP(x)                        USB_OTGSC_DP(x)
46798 #define USBHS_OTGSC_IDPU_MASK                    USB_OTGSC_IDPU_MASK
46799 #define USBHS_OTGSC_IDPU_SHIFT                   USB_OTGSC_IDPU_SHIFT
46800 #define USBHS_OTGSC_IDPU(x)                      USB_OTGSC_IDPU(x)
46801 #define USBHS_OTGSC_ID_MASK                      USB_OTGSC_ID_MASK
46802 #define USBHS_OTGSC_ID_SHIFT                     USB_OTGSC_ID_SHIFT
46803 #define USBHS_OTGSC_ID(x)                        USB_OTGSC_ID(x)
46804 #define USBHS_OTGSC_AVV_MASK                     USB_OTGSC_AVV_MASK
46805 #define USBHS_OTGSC_AVV_SHIFT                    USB_OTGSC_AVV_SHIFT
46806 #define USBHS_OTGSC_AVV(x)                       USB_OTGSC_AVV(x)
46807 #define USBHS_OTGSC_ASV_MASK                     USB_OTGSC_ASV_MASK
46808 #define USBHS_OTGSC_ASV_SHIFT                    USB_OTGSC_ASV_SHIFT
46809 #define USBHS_OTGSC_ASV(x)                       USB_OTGSC_ASV(x)
46810 #define USBHS_OTGSC_BSV_MASK                     USB_OTGSC_BSV_MASK
46811 #define USBHS_OTGSC_BSV_SHIFT                    USB_OTGSC_BSV_SHIFT
46812 #define USBHS_OTGSC_BSV(x)                       USB_OTGSC_BSV(x)
46813 #define USBHS_OTGSC_BSE_MASK                     USB_OTGSC_BSE_MASK
46814 #define USBHS_OTGSC_BSE_SHIFT                    USB_OTGSC_BSE_SHIFT
46815 #define USBHS_OTGSC_BSE(x)                       USB_OTGSC_BSE(x)
46816 #define USBHS_OTGSC_MST_MASK                     USB_OTGSC_TOG_1MS_MASK
46817 #define USBHS_OTGSC_MST_SHIFT                    USB_OTGSC_TOG_1MS_SHIFT
46818 #define USBHS_OTGSC_MST(x)                       USB_OTGSC_TOG_1MS(x)
46819 #define USBHS_OTGSC_DPS_MASK                     USB_OTGSC_DPS_MASK
46820 #define USBHS_OTGSC_DPS_SHIFT                    USB_OTGSC_DPS_SHIFT
46821 #define USBHS_OTGSC_DPS(x)                       USB_OTGSC_DPS(x)
46822 #define USBHS_OTGSC_IDIS_MASK                    USB_OTGSC_IDIS_MASK
46823 #define USBHS_OTGSC_IDIS_SHIFT                   USB_OTGSC_IDIS_SHIFT
46824 #define USBHS_OTGSC_IDIS(x)                      USB_OTGSC_IDIS(x)
46825 #define USBHS_OTGSC_AVVIS_MASK                   USB_OTGSC_AVVIS_MASK
46826 #define USBHS_OTGSC_AVVIS_SHIFT                  USB_OTGSC_AVVIS_SHIFT
46827 #define USBHS_OTGSC_AVVIS(x)                     USB_OTGSC_AVVIS(x)
46828 #define USBHS_OTGSC_ASVIS_MASK                   USB_OTGSC_ASVIS_MASK
46829 #define USBHS_OTGSC_ASVIS_SHIFT                  USB_OTGSC_ASVIS_SHIFT
46830 #define USBHS_OTGSC_ASVIS(x)                     USB_OTGSC_ASVIS(x)
46831 #define USBHS_OTGSC_BSVIS_MASK                   USB_OTGSC_BSVIS_MASK
46832 #define USBHS_OTGSC_BSVIS_SHIFT                  USB_OTGSC_BSVIS_SHIFT
46833 #define USBHS_OTGSC_BSVIS(x)                     USB_OTGSC_BSVIS(x)
46834 #define USBHS_OTGSC_BSEIS_MASK                   USB_OTGSC_BSEIS_MASK
46835 #define USBHS_OTGSC_BSEIS_SHIFT                  USB_OTGSC_BSEIS_SHIFT
46836 #define USBHS_OTGSC_BSEIS(x)                     USB_OTGSC_BSEIS(x)
46837 #define USBHS_OTGSC_MSS_MASK                     USB_OTGSC_STATUS_1MS_MASK
46838 #define USBHS_OTGSC_MSS_SHIFT                    USB_OTGSC_STATUS_1MS_SHIFT
46839 #define USBHS_OTGSC_MSS(x)                       USB_OTGSC_STATUS_1MS(x)
46840 #define USBHS_OTGSC_DPIS_MASK                    USB_OTGSC_DPIS_MASK
46841 #define USBHS_OTGSC_DPIS_SHIFT                   USB_OTGSC_DPIS_SHIFT
46842 #define USBHS_OTGSC_DPIS(x)                      USB_OTGSC_DPIS(x)
46843 #define USBHS_OTGSC_IDIE_MASK                    USB_OTGSC_IDIE_MASK
46844 #define USBHS_OTGSC_IDIE_SHIFT                   USB_OTGSC_IDIE_SHIFT
46845 #define USBHS_OTGSC_IDIE(x)                      USB_OTGSC_IDIE(x)
46846 #define USBHS_OTGSC_AVVIE_MASK                   USB_OTGSC_AVVIE_MASK
46847 #define USBHS_OTGSC_AVVIE_SHIFT                  USB_OTGSC_AVVIE_SHIFT
46848 #define USBHS_OTGSC_AVVIE(x)                     USB_OTGSC_AVVIE(x)
46849 #define USBHS_OTGSC_ASVIE_MASK                   USB_OTGSC_ASVIE_MASK
46850 #define USBHS_OTGSC_ASVIE_SHIFT                  USB_OTGSC_ASVIE_SHIFT
46851 #define USBHS_OTGSC_ASVIE(x)                     USB_OTGSC_ASVIE(x)
46852 #define USBHS_OTGSC_BSVIE_MASK                   USB_OTGSC_BSVIE_MASK
46853 #define USBHS_OTGSC_BSVIE_SHIFT                  USB_OTGSC_BSVIE_SHIFT
46854 #define USBHS_OTGSC_BSVIE(x)                     USB_OTGSC_BSVIE(x)
46855 #define USBHS_OTGSC_BSEIE_MASK                   USB_OTGSC_BSEIE_MASK
46856 #define USBHS_OTGSC_BSEIE_SHIFT                  USB_OTGSC_BSEIE_SHIFT
46857 #define USBHS_OTGSC_BSEIE(x)                     USB_OTGSC_BSEIE(x)
46858 #define USBHS_OTGSC_MSE_MASK                     USB_OTGSC_EN_1MS_MASK
46859 #define USBHS_OTGSC_MSE_SHIFT                    USB_OTGSC_EN_1MS_SHIFT
46860 #define USBHS_OTGSC_MSE(x)                       USB_OTGSC_EN_1MS(x)
46861 #define USBHS_OTGSC_DPIE_MASK                    USB_OTGSC_DPIE_MASK
46862 #define USBHS_OTGSC_DPIE_SHIFT                   USB_OTGSC_DPIE_SHIFT
46863 #define USBHS_OTGSC_DPIE(x)                      USB_OTGSC_DPIE(x)
46864 #define USBHS_USBMODE_CM_MASK                    USB_USBMODE_CM_MASK
46865 #define USBHS_USBMODE_CM_SHIFT                   USB_USBMODE_CM_SHIFT
46866 #define USBHS_USBMODE_CM(x)                      USB_USBMODE_CM(x)
46867 #define USBHS_USBMODE_ES_MASK                    USB_USBMODE_ES_MASK
46868 #define USBHS_USBMODE_ES_SHIFT                   USB_USBMODE_ES_SHIFT
46869 #define USBHS_USBMODE_ES(x)                      USB_USBMODE_ES(x)
46870 #define USBHS_USBMODE_SLOM_MASK                  USB_USBMODE_SLOM_MASK
46871 #define USBHS_USBMODE_SLOM_SHIFT                 USB_USBMODE_SLOM_SHIFT
46872 #define USBHS_USBMODE_SLOM(x)                    USB_USBMODE_SLOM(x)
46873 #define USBHS_USBMODE_SDIS_MASK                  USB_USBMODE_SDIS_MASK
46874 #define USBHS_USBMODE_SDIS_SHIFT                 USB_USBMODE_SDIS_SHIFT
46875 #define USBHS_USBMODE_SDIS(x)                    USB_USBMODE_SDIS(x)
46876 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
46877 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
46878 #define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
46879 #define USBHS_EPPRIME_PERB_MASK                  USB_ENDPTPRIME_PERB_MASK
46880 #define USBHS_EPPRIME_PERB_SHIFT                 USB_ENDPTPRIME_PERB_SHIFT
46881 #define USBHS_EPPRIME_PERB(x)                    USB_ENDPTPRIME_PERB(x)
46882 #define USBHS_EPPRIME_PETB_MASK                  USB_ENDPTPRIME_PETB_MASK
46883 #define USBHS_EPPRIME_PETB_SHIFT                 USB_ENDPTPRIME_PETB_SHIFT
46884 #define USBHS_EPPRIME_PETB(x)                    USB_ENDPTPRIME_PETB(x)
46885 #define USBHS_EPFLUSH_FERB_MASK                  USB_ENDPTFLUSH_FERB_MASK
46886 #define USBHS_EPFLUSH_FERB_SHIFT                 USB_ENDPTFLUSH_FERB_SHIFT
46887 #define USBHS_EPFLUSH_FERB(x)                    USB_ENDPTFLUSH_FERB(x)
46888 #define USBHS_EPFLUSH_FETB_MASK                  USB_ENDPTFLUSH_FETB_MASK
46889 #define USBHS_EPFLUSH_FETB_SHIFT                 USB_ENDPTFLUSH_FETB_SHIFT
46890 #define USBHS_EPFLUSH_FETB(x)                    USB_ENDPTFLUSH_FETB(x)
46891 #define USBHS_EPSR_ERBR_MASK                     USB_ENDPTSTAT_ERBR_MASK
46892 #define USBHS_EPSR_ERBR_SHIFT                    USB_ENDPTSTAT_ERBR_SHIFT
46893 #define USBHS_EPSR_ERBR(x)                       USB_ENDPTSTAT_ERBR(x)
46894 #define USBHS_EPSR_ETBR_MASK                     USB_ENDPTSTAT_ETBR_MASK
46895 #define USBHS_EPSR_ETBR_SHIFT                    USB_ENDPTSTAT_ETBR_SHIFT
46896 #define USBHS_EPSR_ETBR(x)                       USB_ENDPTSTAT_ETBR(x)
46897 #define USBHS_EPCOMPLETE_ERCE_MASK               USB_ENDPTCOMPLETE_ERCE_MASK
46898 #define USBHS_EPCOMPLETE_ERCE_SHIFT              USB_ENDPTCOMPLETE_ERCE_SHIFT
46899 #define USBHS_EPCOMPLETE_ERCE(x)                 USB_ENDPTCOMPLETE_ERCE(x)
46900 #define USBHS_EPCOMPLETE_ETCE_MASK               USB_ENDPTCOMPLETE_ETCE_MASK
46901 #define USBHS_EPCOMPLETE_ETCE_SHIFT              USB_ENDPTCOMPLETE_ETCE_SHIFT
46902 #define USBHS_EPCOMPLETE_ETCE(x)                 USB_ENDPTCOMPLETE_ETCE(x)
46903 #define USBHS_EPCR0_RXS_MASK                     USB_ENDPTCTRL0_RXS_MASK
46904 #define USBHS_EPCR0_RXS_SHIFT                    USB_ENDPTCTRL0_RXS_SHIFT
46905 #define USBHS_EPCR0_RXS(x)                       USB_ENDPTCTRL0_RXS(x)
46906 #define USBHS_EPCR0_RXT_MASK                     USB_ENDPTCTRL0_RXT_MASK
46907 #define USBHS_EPCR0_RXT_SHIFT                    USB_ENDPTCTRL0_RXT_SHIFT
46908 #define USBHS_EPCR0_RXT(x)                       USB_ENDPTCTRL0_RXT(x)
46909 #define USBHS_EPCR0_RXE_MASK                     USB_ENDPTCTRL0_RXE_MASK
46910 #define USBHS_EPCR0_RXE_SHIFT                    USB_ENDPTCTRL0_RXE_SHIFT
46911 #define USBHS_EPCR0_RXE(x)                       USB_ENDPTCTRL0_RXE(x)
46912 #define USBHS_EPCR0_TXS_MASK                     USB_ENDPTCTRL0_TXS_MASK
46913 #define USBHS_EPCR0_TXS_SHIFT                    USB_ENDPTCTRL0_TXS_SHIFT
46914 #define USBHS_EPCR0_TXS(x)                       USB_ENDPTCTRL0_TXS(x)
46915 #define USBHS_EPCR0_TXT_MASK                     USB_ENDPTCTRL0_TXT_MASK
46916 #define USBHS_EPCR0_TXT_SHIFT                    USB_ENDPTCTRL0_TXT_SHIFT
46917 #define USBHS_EPCR0_TXT(x)                       USB_ENDPTCTRL0_TXT(x)
46918 #define USBHS_EPCR0_TXE_MASK                     USB_ENDPTCTRL0_TXE_MASK
46919 #define USBHS_EPCR0_TXE_SHIFT                    USB_ENDPTCTRL0_TXE_SHIFT
46920 #define USBHS_EPCR0_TXE(x)                       USB_ENDPTCTRL0_TXE(x)
46921 #define USBHS_EPCR_RXS_MASK                      USB_ENDPTCTRL_RXS_MASK
46922 #define USBHS_EPCR_RXS_SHIFT                     USB_ENDPTCTRL_RXS_SHIFT
46923 #define USBHS_EPCR_RXS(x)                        USB_ENDPTCTRL_RXS(x)
46924 #define USBHS_EPCR_RXD_MASK                      USB_ENDPTCTRL_RXD_MASK
46925 #define USBHS_EPCR_RXD_SHIFT                     USB_ENDPTCTRL_RXD_SHIFT
46926 #define USBHS_EPCR_RXD(x)                        USB_ENDPTCTRL_RXD(x)
46927 #define USBHS_EPCR_RXT_MASK                      USB_ENDPTCTRL_RXT_MASK
46928 #define USBHS_EPCR_RXT_SHIFT                     USB_ENDPTCTRL_RXT_SHIFT
46929 #define USBHS_EPCR_RXT(x)                        USB_ENDPTCTRL_RXT(x)
46930 #define USBHS_EPCR_RXI_MASK                      USB_ENDPTCTRL_RXI_MASK
46931 #define USBHS_EPCR_RXI_SHIFT                     USB_ENDPTCTRL_RXI_SHIFT
46932 #define USBHS_EPCR_RXI(x)                        USB_ENDPTCTRL_RXI(x)
46933 #define USBHS_EPCR_RXR_MASK                      USB_ENDPTCTRL_RXR_MASK
46934 #define USBHS_EPCR_RXR_SHIFT                     USB_ENDPTCTRL_RXR_SHIFT
46935 #define USBHS_EPCR_RXR(x)                        USB_ENDPTCTRL_RXR(x)
46936 #define USBHS_EPCR_RXE_MASK                      USB_ENDPTCTRL_RXE_MASK
46937 #define USBHS_EPCR_RXE_SHIFT                     USB_ENDPTCTRL_RXE_SHIFT
46938 #define USBHS_EPCR_RXE(x)                        USB_ENDPTCTRL_RXE(x)
46939 #define USBHS_EPCR_TXS_MASK                      USB_ENDPTCTRL_TXS_MASK
46940 #define USBHS_EPCR_TXS_SHIFT                     USB_ENDPTCTRL_TXS_SHIFT
46941 #define USBHS_EPCR_TXS(x)                        USB_ENDPTCTRL_TXS(x)
46942 #define USBHS_EPCR_TXD_MASK                      USB_ENDPTCTRL_TXD_MASK
46943 #define USBHS_EPCR_TXD_SHIFT                     USB_ENDPTCTRL_TXD_SHIFT
46944 #define USBHS_EPCR_TXD(x)                        USB_ENDPTCTRL_TXD(x)
46945 #define USBHS_EPCR_TXT_MASK                      USB_ENDPTCTRL_TXT_MASK
46946 #define USBHS_EPCR_TXT_SHIFT                     USB_ENDPTCTRL_TXT_SHIFT
46947 #define USBHS_EPCR_TXT(x)                        USB_ENDPTCTRL_TXT(x)
46948 #define USBHS_EPCR_TXI_MASK                      USB_ENDPTCTRL_TXI_MASK
46949 #define USBHS_EPCR_TXI_SHIFT                     USB_ENDPTCTRL_TXI_SHIFT
46950 #define USBHS_EPCR_TXI(x)                        USB_ENDPTCTRL_TXI(x)
46951 #define USBHS_EPCR_TXR_MASK                      USB_ENDPTCTRL_TXR_MASK
46952 #define USBHS_EPCR_TXR_SHIFT                     USB_ENDPTCTRL_TXR_SHIFT
46953 #define USBHS_EPCR_TXR(x)                        USB_ENDPTCTRL_TXR(x)
46954 #define USBHS_EPCR_TXE_MASK                      USB_ENDPTCTRL_TXE_MASK
46955 #define USBHS_EPCR_TXE_SHIFT                     USB_ENDPTCTRL_TXE_SHIFT
46956 #define USBHS_EPCR_TXE(x)                        USB_ENDPTCTRL_TXE(x)
46957 #define USBHS_EPCR_COUNT                         USB_ENDPTCTRL_COUNT
46958 #define USBHS_Type                               USB_Type
46959 #define USBHS_BASE_ADDRS                         USB_BASE_ADDRS
46960 #define USBHS_IRQS                               { USB_OTG1_IRQn, USB_OTG2_IRQn }
46961 #define USBHS_IRQHandler                         USB_OTG1_IRQHandler
46962 #define USBHS_STACK_BASE_ADDRS                   { USB1_BASE, USB2_BASE }
46963 
46964 
46965 /*!
46966  * @}
46967  */ /* end of group USB_Peripheral_Access_Layer */
46968 
46969 
46970 /* ----------------------------------------------------------------------------
46971    -- USBNC Peripheral Access Layer
46972    ---------------------------------------------------------------------------- */
46973 
46974 /*!
46975  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
46976  * @{
46977  */
46978 
46979 /** USBNC - Register Layout Typedef */
46980 typedef struct {
46981        uint8_t RESERVED_0[2048];
46982   __IO uint32_t USB_OTGn_CTRL;                     /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */
46983        uint8_t RESERVED_1[20];
46984   __IO uint32_t USB_OTGn_PHY_CTRL_0;               /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */
46985 } USBNC_Type;
46986 
46987 /* ----------------------------------------------------------------------------
46988    -- USBNC Register Masks
46989    ---------------------------------------------------------------------------- */
46990 
46991 /*!
46992  * @addtogroup USBNC_Register_Masks USBNC Register Masks
46993  * @{
46994  */
46995 
46996 /*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */
46997 /*! @{ */
46998 
46999 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK    (0x80U)
47000 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT   (7U)
47001 /*! OVER_CUR_DIS
47002  *  0b1..Disables overcurrent detection
47003  *  0b0..Enables overcurrent detection
47004  */
47005 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
47006 
47007 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK    (0x100U)
47008 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT   (8U)
47009 /*! OVER_CUR_POL
47010  *  0b1..Low active (low on this signal represents an overcurrent condition)
47011  *  0b0..High active (high on this signal represents an overcurrent condition)
47012  */
47013 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
47014 
47015 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK         (0x200U)
47016 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT        (9U)
47017 /*! PWR_POL
47018  *  0b1..PMIC Power Pin is High active.
47019  *  0b0..PMIC Power Pin is Low active.
47020  */
47021 #define USBNC_USB_OTGn_CTRL_PWR_POL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
47022 
47023 #define USBNC_USB_OTGn_CTRL_WIE_MASK             (0x400U)
47024 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT            (10U)
47025 /*! WIE
47026  *  0b1..Interrupt Enabled
47027  *  0b0..Interrupt Disabled
47028  */
47029 #define USBNC_USB_OTGn_CTRL_WIE(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
47030 
47031 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK      (0x4000U)
47032 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT     (14U)
47033 /*! WKUP_SW_EN
47034  *  0b1..Enable
47035  *  0b0..Disable
47036  */
47037 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
47038 
47039 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK         (0x8000U)
47040 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT        (15U)
47041 /*! WKUP_SW
47042  *  0b1..Force wake-up
47043  *  0b0..Inactive
47044  */
47045 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
47046 
47047 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK      (0x10000U)
47048 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT     (16U)
47049 /*! WKUP_ID_EN
47050  *  0b1..Enable
47051  *  0b0..Disable
47052  */
47053 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
47054 
47055 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK    (0x20000U)
47056 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT   (17U)
47057 /*! WKUP_VBUS_EN
47058  *  0b1..Enable
47059  *  0b0..Disable
47060  */
47061 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
47062 
47063 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK    (0x20000000U)
47064 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT   (29U)
47065 /*! WKUP_DPDM_EN
47066  *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
47067  *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
47068  */
47069 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
47070 
47071 #define USBNC_USB_OTGn_CTRL_WIR_MASK             (0x80000000U)
47072 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT            (31U)
47073 /*! WIR
47074  *  0b1..Wake-up Interrupt Request received
47075  *  0b0..No wake-up interrupt request received
47076  */
47077 #define USBNC_USB_OTGn_CTRL_WIR(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
47078 /*! @} */
47079 
47080 /*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */
47081 /*! @{ */
47082 
47083 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
47084 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
47085 /*! UTMI_CLK_VLD
47086  *  0b1..Valid
47087  *  0b0..Invalid
47088  */
47089 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
47090 /*! @} */
47091 
47092 
47093 /*!
47094  * @}
47095  */ /* end of group USBNC_Register_Masks */
47096 
47097 
47098 /* USBNC - Peripheral instance base addresses */
47099 /** Peripheral USBNC1 base address */
47100 #define USBNC1_BASE                              (0x402E0000u)
47101 /** Peripheral USBNC1 base pointer */
47102 #define USBNC1                                   ((USBNC_Type *)USBNC1_BASE)
47103 /** Peripheral USBNC2 base address */
47104 #define USBNC2_BASE                              (0x402E0004u)
47105 /** Peripheral USBNC2 base pointer */
47106 #define USBNC2                                   ((USBNC_Type *)USBNC2_BASE)
47107 /** Array initializer of USBNC peripheral base addresses */
47108 #define USBNC_BASE_ADDRS                         { 0u, USBNC1_BASE, USBNC2_BASE }
47109 /** Array initializer of USBNC peripheral base pointers */
47110 #define USBNC_BASE_PTRS                          { (USBNC_Type *)0u, USBNC1, USBNC2 }
47111 /* Backward compatibility */
47112 #define USBNC_STACK_BASE_ADDRS                   { USBNC1_BASE, USBNC2_BASE }
47113 
47114 /*!
47115  * @}
47116  */ /* end of group USBNC_Peripheral_Access_Layer */
47117 
47118 
47119 /* ----------------------------------------------------------------------------
47120    -- USBPHY Peripheral Access Layer
47121    ---------------------------------------------------------------------------- */
47122 
47123 /*!
47124  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
47125  * @{
47126  */
47127 
47128 /** USBPHY - Register Layout Typedef */
47129 typedef struct {
47130   __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
47131   __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
47132   __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
47133   __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
47134   __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
47135   __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
47136   __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
47137   __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
47138   __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
47139   __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
47140   __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
47141   __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
47142   __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
47143   __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
47144   __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
47145   __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
47146   __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
47147        uint8_t RESERVED_0[12];
47148   __IO uint32_t DEBUGr;                            /**< USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
47149   __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
47150   __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
47151   __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
47152   __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
47153        uint8_t RESERVED_1[12];
47154   __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
47155   __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
47156   __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
47157   __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
47158   __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
47159 } USBPHY_Type;
47160 
47161 /* ----------------------------------------------------------------------------
47162    -- USBPHY Register Masks
47163    ---------------------------------------------------------------------------- */
47164 
47165 /*!
47166  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
47167  * @{
47168  */
47169 
47170 /*! @name PWD - USB PHY Power-Down Register */
47171 /*! @{ */
47172 
47173 #define USBPHY_PWD_RSVD0_MASK                    (0x3FFU)
47174 #define USBPHY_PWD_RSVD0_SHIFT                   (0U)
47175 #define USBPHY_PWD_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
47176 
47177 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
47178 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
47179 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
47180 
47181 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
47182 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
47183 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
47184 
47185 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
47186 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
47187 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
47188 
47189 #define USBPHY_PWD_RSVD1_MASK                    (0x1E000U)
47190 #define USBPHY_PWD_RSVD1_SHIFT                   (13U)
47191 #define USBPHY_PWD_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
47192 
47193 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
47194 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
47195 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
47196 
47197 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
47198 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
47199 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
47200 
47201 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
47202 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
47203 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
47204 
47205 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
47206 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
47207 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
47208 
47209 #define USBPHY_PWD_RSVD2_MASK                    (0xFFE00000U)
47210 #define USBPHY_PWD_RSVD2_SHIFT                   (21U)
47211 #define USBPHY_PWD_RSVD2(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
47212 /*! @} */
47213 
47214 /*! @name PWD_SET - USB PHY Power-Down Register */
47215 /*! @{ */
47216 
47217 #define USBPHY_PWD_SET_RSVD0_MASK                (0x3FFU)
47218 #define USBPHY_PWD_SET_RSVD0_SHIFT               (0U)
47219 #define USBPHY_PWD_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
47220 
47221 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
47222 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
47223 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
47224 
47225 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
47226 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
47227 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
47228 
47229 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
47230 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
47231 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
47232 
47233 #define USBPHY_PWD_SET_RSVD1_MASK                (0x1E000U)
47234 #define USBPHY_PWD_SET_RSVD1_SHIFT               (13U)
47235 #define USBPHY_PWD_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
47236 
47237 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
47238 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
47239 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
47240 
47241 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
47242 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
47243 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
47244 
47245 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
47246 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
47247 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
47248 
47249 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
47250 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
47251 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
47252 
47253 #define USBPHY_PWD_SET_RSVD2_MASK                (0xFFE00000U)
47254 #define USBPHY_PWD_SET_RSVD2_SHIFT               (21U)
47255 #define USBPHY_PWD_SET_RSVD2(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
47256 /*! @} */
47257 
47258 /*! @name PWD_CLR - USB PHY Power-Down Register */
47259 /*! @{ */
47260 
47261 #define USBPHY_PWD_CLR_RSVD0_MASK                (0x3FFU)
47262 #define USBPHY_PWD_CLR_RSVD0_SHIFT               (0U)
47263 #define USBPHY_PWD_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
47264 
47265 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
47266 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
47267 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
47268 
47269 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
47270 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
47271 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
47272 
47273 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
47274 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
47275 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
47276 
47277 #define USBPHY_PWD_CLR_RSVD1_MASK                (0x1E000U)
47278 #define USBPHY_PWD_CLR_RSVD1_SHIFT               (13U)
47279 #define USBPHY_PWD_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
47280 
47281 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
47282 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
47283 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
47284 
47285 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
47286 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
47287 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
47288 
47289 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
47290 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
47291 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
47292 
47293 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
47294 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
47295 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
47296 
47297 #define USBPHY_PWD_CLR_RSVD2_MASK                (0xFFE00000U)
47298 #define USBPHY_PWD_CLR_RSVD2_SHIFT               (21U)
47299 #define USBPHY_PWD_CLR_RSVD2(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
47300 /*! @} */
47301 
47302 /*! @name PWD_TOG - USB PHY Power-Down Register */
47303 /*! @{ */
47304 
47305 #define USBPHY_PWD_TOG_RSVD0_MASK                (0x3FFU)
47306 #define USBPHY_PWD_TOG_RSVD0_SHIFT               (0U)
47307 #define USBPHY_PWD_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
47308 
47309 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
47310 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
47311 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
47312 
47313 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
47314 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
47315 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
47316 
47317 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
47318 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
47319 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
47320 
47321 #define USBPHY_PWD_TOG_RSVD1_MASK                (0x1E000U)
47322 #define USBPHY_PWD_TOG_RSVD1_SHIFT               (13U)
47323 #define USBPHY_PWD_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
47324 
47325 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
47326 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
47327 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
47328 
47329 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
47330 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
47331 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
47332 
47333 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
47334 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
47335 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
47336 
47337 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
47338 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
47339 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
47340 
47341 #define USBPHY_PWD_TOG_RSVD2_MASK                (0xFFE00000U)
47342 #define USBPHY_PWD_TOG_RSVD2_SHIFT               (21U)
47343 #define USBPHY_PWD_TOG_RSVD2(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
47344 /*! @} */
47345 
47346 /*! @name TX - USB PHY Transmitter Control Register */
47347 /*! @{ */
47348 
47349 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
47350 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
47351 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
47352 
47353 #define USBPHY_TX_RSVD0_MASK                     (0xF0U)
47354 #define USBPHY_TX_RSVD0_SHIFT                    (4U)
47355 #define USBPHY_TX_RSVD0(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
47356 
47357 #define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
47358 #define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
47359 #define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
47360 
47361 #define USBPHY_TX_RSVD1_MASK                     (0xF000U)
47362 #define USBPHY_TX_RSVD1_SHIFT                    (12U)
47363 #define USBPHY_TX_RSVD1(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
47364 
47365 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
47366 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
47367 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
47368 
47369 #define USBPHY_TX_RSVD2_MASK                     (0x3F00000U)
47370 #define USBPHY_TX_RSVD2_SHIFT                    (20U)
47371 #define USBPHY_TX_RSVD2(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
47372 
47373 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK        (0x1C000000U)
47374 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT       (26U)
47375 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
47376 
47377 #define USBPHY_TX_RSVD5_MASK                     (0xE0000000U)
47378 #define USBPHY_TX_RSVD5_SHIFT                    (29U)
47379 #define USBPHY_TX_RSVD5(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
47380 /*! @} */
47381 
47382 /*! @name TX_SET - USB PHY Transmitter Control Register */
47383 /*! @{ */
47384 
47385 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
47386 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
47387 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
47388 
47389 #define USBPHY_TX_SET_RSVD0_MASK                 (0xF0U)
47390 #define USBPHY_TX_SET_RSVD0_SHIFT                (4U)
47391 #define USBPHY_TX_SET_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
47392 
47393 #define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
47394 #define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
47395 #define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
47396 
47397 #define USBPHY_TX_SET_RSVD1_MASK                 (0xF000U)
47398 #define USBPHY_TX_SET_RSVD1_SHIFT                (12U)
47399 #define USBPHY_TX_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
47400 
47401 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
47402 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
47403 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
47404 
47405 #define USBPHY_TX_SET_RSVD2_MASK                 (0x3F00000U)
47406 #define USBPHY_TX_SET_RSVD2_SHIFT                (20U)
47407 #define USBPHY_TX_SET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
47408 
47409 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
47410 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT   (26U)
47411 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
47412 
47413 #define USBPHY_TX_SET_RSVD5_MASK                 (0xE0000000U)
47414 #define USBPHY_TX_SET_RSVD5_SHIFT                (29U)
47415 #define USBPHY_TX_SET_RSVD5(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
47416 /*! @} */
47417 
47418 /*! @name TX_CLR - USB PHY Transmitter Control Register */
47419 /*! @{ */
47420 
47421 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
47422 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
47423 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
47424 
47425 #define USBPHY_TX_CLR_RSVD0_MASK                 (0xF0U)
47426 #define USBPHY_TX_CLR_RSVD0_SHIFT                (4U)
47427 #define USBPHY_TX_CLR_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
47428 
47429 #define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
47430 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
47431 #define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
47432 
47433 #define USBPHY_TX_CLR_RSVD1_MASK                 (0xF000U)
47434 #define USBPHY_TX_CLR_RSVD1_SHIFT                (12U)
47435 #define USBPHY_TX_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
47436 
47437 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
47438 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
47439 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
47440 
47441 #define USBPHY_TX_CLR_RSVD2_MASK                 (0x3F00000U)
47442 #define USBPHY_TX_CLR_RSVD2_SHIFT                (20U)
47443 #define USBPHY_TX_CLR_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
47444 
47445 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
47446 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT   (26U)
47447 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
47448 
47449 #define USBPHY_TX_CLR_RSVD5_MASK                 (0xE0000000U)
47450 #define USBPHY_TX_CLR_RSVD5_SHIFT                (29U)
47451 #define USBPHY_TX_CLR_RSVD5(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
47452 /*! @} */
47453 
47454 /*! @name TX_TOG - USB PHY Transmitter Control Register */
47455 /*! @{ */
47456 
47457 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
47458 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
47459 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
47460 
47461 #define USBPHY_TX_TOG_RSVD0_MASK                 (0xF0U)
47462 #define USBPHY_TX_TOG_RSVD0_SHIFT                (4U)
47463 #define USBPHY_TX_TOG_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
47464 
47465 #define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
47466 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
47467 #define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
47468 
47469 #define USBPHY_TX_TOG_RSVD1_MASK                 (0xF000U)
47470 #define USBPHY_TX_TOG_RSVD1_SHIFT                (12U)
47471 #define USBPHY_TX_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
47472 
47473 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
47474 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
47475 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
47476 
47477 #define USBPHY_TX_TOG_RSVD2_MASK                 (0x3F00000U)
47478 #define USBPHY_TX_TOG_RSVD2_SHIFT                (20U)
47479 #define USBPHY_TX_TOG_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
47480 
47481 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
47482 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT   (26U)
47483 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
47484 
47485 #define USBPHY_TX_TOG_RSVD5_MASK                 (0xE0000000U)
47486 #define USBPHY_TX_TOG_RSVD5_SHIFT                (29U)
47487 #define USBPHY_TX_TOG_RSVD5(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
47488 /*! @} */
47489 
47490 /*! @name RX - USB PHY Receiver Control Register */
47491 /*! @{ */
47492 
47493 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
47494 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
47495 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
47496 
47497 #define USBPHY_RX_RSVD0_MASK                     (0x8U)
47498 #define USBPHY_RX_RSVD0_SHIFT                    (3U)
47499 #define USBPHY_RX_RSVD0(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
47500 
47501 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
47502 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
47503 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
47504 
47505 #define USBPHY_RX_RSVD1_MASK                     (0x3FFF80U)
47506 #define USBPHY_RX_RSVD1_SHIFT                    (7U)
47507 #define USBPHY_RX_RSVD1(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
47508 
47509 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
47510 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
47511 #define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
47512 
47513 #define USBPHY_RX_RSVD2_MASK                     (0xFF800000U)
47514 #define USBPHY_RX_RSVD2_SHIFT                    (23U)
47515 #define USBPHY_RX_RSVD2(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
47516 /*! @} */
47517 
47518 /*! @name RX_SET - USB PHY Receiver Control Register */
47519 /*! @{ */
47520 
47521 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
47522 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
47523 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
47524 
47525 #define USBPHY_RX_SET_RSVD0_MASK                 (0x8U)
47526 #define USBPHY_RX_SET_RSVD0_SHIFT                (3U)
47527 #define USBPHY_RX_SET_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
47528 
47529 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
47530 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
47531 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
47532 
47533 #define USBPHY_RX_SET_RSVD1_MASK                 (0x3FFF80U)
47534 #define USBPHY_RX_SET_RSVD1_SHIFT                (7U)
47535 #define USBPHY_RX_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
47536 
47537 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
47538 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
47539 #define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
47540 
47541 #define USBPHY_RX_SET_RSVD2_MASK                 (0xFF800000U)
47542 #define USBPHY_RX_SET_RSVD2_SHIFT                (23U)
47543 #define USBPHY_RX_SET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
47544 /*! @} */
47545 
47546 /*! @name RX_CLR - USB PHY Receiver Control Register */
47547 /*! @{ */
47548 
47549 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
47550 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
47551 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
47552 
47553 #define USBPHY_RX_CLR_RSVD0_MASK                 (0x8U)
47554 #define USBPHY_RX_CLR_RSVD0_SHIFT                (3U)
47555 #define USBPHY_RX_CLR_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
47556 
47557 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
47558 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
47559 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
47560 
47561 #define USBPHY_RX_CLR_RSVD1_MASK                 (0x3FFF80U)
47562 #define USBPHY_RX_CLR_RSVD1_SHIFT                (7U)
47563 #define USBPHY_RX_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
47564 
47565 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
47566 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
47567 #define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
47568 
47569 #define USBPHY_RX_CLR_RSVD2_MASK                 (0xFF800000U)
47570 #define USBPHY_RX_CLR_RSVD2_SHIFT                (23U)
47571 #define USBPHY_RX_CLR_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
47572 /*! @} */
47573 
47574 /*! @name RX_TOG - USB PHY Receiver Control Register */
47575 /*! @{ */
47576 
47577 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
47578 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
47579 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
47580 
47581 #define USBPHY_RX_TOG_RSVD0_MASK                 (0x8U)
47582 #define USBPHY_RX_TOG_RSVD0_SHIFT                (3U)
47583 #define USBPHY_RX_TOG_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
47584 
47585 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
47586 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
47587 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
47588 
47589 #define USBPHY_RX_TOG_RSVD1_MASK                 (0x3FFF80U)
47590 #define USBPHY_RX_TOG_RSVD1_SHIFT                (7U)
47591 #define USBPHY_RX_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
47592 
47593 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
47594 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
47595 #define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
47596 
47597 #define USBPHY_RX_TOG_RSVD2_MASK                 (0xFF800000U)
47598 #define USBPHY_RX_TOG_RSVD2_SHIFT                (23U)
47599 #define USBPHY_RX_TOG_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
47600 /*! @} */
47601 
47602 /*! @name CTRL - USB PHY General Control Register */
47603 /*! @{ */
47604 
47605 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        (0x1U)
47606 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       (0U)
47607 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
47608 
47609 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
47610 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
47611 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
47612 
47613 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
47614 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
47615 #define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
47616 
47617 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
47618 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
47619 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
47620 
47621 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
47622 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
47623 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
47624 
47625 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
47626 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
47627 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
47628 
47629 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          (0x40U)
47630 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         (6U)
47631 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
47632 
47633 #define USBPHY_CTRL_ENOTGIDDETECT_MASK           (0x80U)
47634 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          (7U)
47635 #define USBPHY_CTRL_ENOTGIDDETECT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
47636 
47637 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
47638 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
47639 #define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
47640 
47641 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
47642 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
47643 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
47644 
47645 #define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
47646 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
47647 #define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
47648 
47649 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
47650 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
47651 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
47652 
47653 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
47654 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
47655 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
47656 
47657 #define USBPHY_CTRL_DATA_ON_LRADC_MASK           (0x2000U)
47658 #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT          (13U)
47659 #define USBPHY_CTRL_DATA_ON_LRADC(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
47660 
47661 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
47662 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
47663 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
47664 
47665 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
47666 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
47667 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
47668 
47669 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
47670 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
47671 #define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
47672 
47673 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
47674 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
47675 #define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
47676 
47677 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK        (0x40000U)
47678 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT       (18U)
47679 #define USBPHY_CTRL_ENAUTO_PWRON_PLL(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
47680 
47681 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
47682 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
47683 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
47684 
47685 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
47686 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
47687 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
47688 
47689 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          (0x200000U)
47690 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         (21U)
47691 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
47692 
47693 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK            (0x400000U)
47694 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           (22U)
47695 #define USBPHY_CTRL_ENIDCHG_WKUP(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
47696 
47697 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          (0x800000U)
47698 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         (23U)
47699 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
47700 
47701 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
47702 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
47703 #define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
47704 
47705 #define USBPHY_CTRL_RSVD1_MASK                   (0x6000000U)
47706 #define USBPHY_CTRL_RSVD1_SHIFT                  (25U)
47707 #define USBPHY_CTRL_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
47708 
47709 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
47710 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
47711 #define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
47712 
47713 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
47714 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
47715 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
47716 
47717 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
47718 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
47719 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
47720 
47721 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
47722 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
47723 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
47724 
47725 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
47726 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
47727 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
47728 /*! @} */
47729 
47730 /*! @name CTRL_SET - USB PHY General Control Register */
47731 /*! @{ */
47732 
47733 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
47734 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
47735 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
47736 
47737 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
47738 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
47739 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
47740 
47741 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
47742 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
47743 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
47744 
47745 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
47746 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
47747 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
47748 
47749 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
47750 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
47751 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
47752 
47753 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
47754 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
47755 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
47756 
47757 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      (0x40U)
47758 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     (6U)
47759 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
47760 
47761 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       (0x80U)
47762 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      (7U)
47763 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
47764 
47765 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
47766 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
47767 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
47768 
47769 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
47770 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
47771 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
47772 
47773 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
47774 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
47775 #define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
47776 
47777 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
47778 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
47779 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
47780 
47781 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
47782 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
47783 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
47784 
47785 #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK       (0x2000U)
47786 #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT      (13U)
47787 #define USBPHY_CTRL_SET_DATA_ON_LRADC(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
47788 
47789 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
47790 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
47791 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
47792 
47793 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
47794 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
47795 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
47796 
47797 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
47798 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
47799 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
47800 
47801 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
47802 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
47803 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
47804 
47805 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK    (0x40000U)
47806 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT   (18U)
47807 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
47808 
47809 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
47810 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
47811 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
47812 
47813 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
47814 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
47815 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
47816 
47817 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      (0x200000U)
47818 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     (21U)
47819 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
47820 
47821 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        (0x400000U)
47822 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       (22U)
47823 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
47824 
47825 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      (0x800000U)
47826 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     (23U)
47827 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
47828 
47829 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
47830 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
47831 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
47832 
47833 #define USBPHY_CTRL_SET_RSVD1_MASK               (0x6000000U)
47834 #define USBPHY_CTRL_SET_RSVD1_SHIFT              (25U)
47835 #define USBPHY_CTRL_SET_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
47836 
47837 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
47838 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
47839 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
47840 
47841 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
47842 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
47843 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
47844 
47845 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
47846 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
47847 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
47848 
47849 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
47850 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
47851 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
47852 
47853 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
47854 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
47855 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
47856 /*! @} */
47857 
47858 /*! @name CTRL_CLR - USB PHY General Control Register */
47859 /*! @{ */
47860 
47861 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
47862 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
47863 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
47864 
47865 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
47866 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
47867 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
47868 
47869 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
47870 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
47871 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
47872 
47873 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
47874 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
47875 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
47876 
47877 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
47878 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
47879 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
47880 
47881 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
47882 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
47883 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
47884 
47885 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      (0x40U)
47886 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     (6U)
47887 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
47888 
47889 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       (0x80U)
47890 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      (7U)
47891 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
47892 
47893 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
47894 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
47895 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
47896 
47897 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
47898 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
47899 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
47900 
47901 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
47902 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
47903 #define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
47904 
47905 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
47906 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
47907 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
47908 
47909 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
47910 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
47911 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
47912 
47913 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK       (0x2000U)
47914 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT      (13U)
47915 #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
47916 
47917 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
47918 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
47919 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
47920 
47921 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
47922 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
47923 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
47924 
47925 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
47926 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
47927 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
47928 
47929 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
47930 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
47931 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
47932 
47933 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK    (0x40000U)
47934 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT   (18U)
47935 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
47936 
47937 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
47938 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
47939 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
47940 
47941 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
47942 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
47943 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
47944 
47945 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      (0x200000U)
47946 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     (21U)
47947 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
47948 
47949 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        (0x400000U)
47950 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       (22U)
47951 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
47952 
47953 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      (0x800000U)
47954 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     (23U)
47955 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
47956 
47957 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
47958 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
47959 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
47960 
47961 #define USBPHY_CTRL_CLR_RSVD1_MASK               (0x6000000U)
47962 #define USBPHY_CTRL_CLR_RSVD1_SHIFT              (25U)
47963 #define USBPHY_CTRL_CLR_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
47964 
47965 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
47966 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
47967 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
47968 
47969 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
47970 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
47971 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
47972 
47973 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
47974 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
47975 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
47976 
47977 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
47978 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
47979 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
47980 
47981 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
47982 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
47983 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
47984 /*! @} */
47985 
47986 /*! @name CTRL_TOG - USB PHY General Control Register */
47987 /*! @{ */
47988 
47989 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
47990 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
47991 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
47992 
47993 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
47994 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
47995 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
47996 
47997 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
47998 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
47999 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
48000 
48001 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
48002 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
48003 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
48004 
48005 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
48006 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
48007 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
48008 
48009 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
48010 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
48011 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
48012 
48013 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      (0x40U)
48014 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     (6U)
48015 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
48016 
48017 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       (0x80U)
48018 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      (7U)
48019 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
48020 
48021 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
48022 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
48023 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
48024 
48025 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
48026 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
48027 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
48028 
48029 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
48030 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
48031 #define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
48032 
48033 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
48034 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
48035 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
48036 
48037 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
48038 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
48039 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
48040 
48041 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK       (0x2000U)
48042 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT      (13U)
48043 #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
48044 
48045 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
48046 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
48047 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
48048 
48049 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
48050 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
48051 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
48052 
48053 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
48054 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
48055 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
48056 
48057 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
48058 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
48059 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
48060 
48061 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK    (0x40000U)
48062 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT   (18U)
48063 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
48064 
48065 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
48066 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
48067 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
48068 
48069 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
48070 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
48071 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
48072 
48073 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      (0x200000U)
48074 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     (21U)
48075 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
48076 
48077 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        (0x400000U)
48078 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       (22U)
48079 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
48080 
48081 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      (0x800000U)
48082 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     (23U)
48083 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
48084 
48085 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
48086 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
48087 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
48088 
48089 #define USBPHY_CTRL_TOG_RSVD1_MASK               (0x6000000U)
48090 #define USBPHY_CTRL_TOG_RSVD1_SHIFT              (25U)
48091 #define USBPHY_CTRL_TOG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
48092 
48093 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
48094 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
48095 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
48096 
48097 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
48098 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
48099 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
48100 
48101 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
48102 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
48103 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
48104 
48105 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
48106 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
48107 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
48108 
48109 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
48110 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
48111 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
48112 /*! @} */
48113 
48114 /*! @name STATUS - USB PHY Status Register */
48115 /*! @{ */
48116 
48117 #define USBPHY_STATUS_RSVD0_MASK                 (0x7U)
48118 #define USBPHY_STATUS_RSVD0_SHIFT                (0U)
48119 #define USBPHY_STATUS_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
48120 
48121 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
48122 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
48123 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
48124 
48125 #define USBPHY_STATUS_RSVD1_MASK                 (0x30U)
48126 #define USBPHY_STATUS_RSVD1_SHIFT                (4U)
48127 #define USBPHY_STATUS_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
48128 
48129 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
48130 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
48131 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
48132 
48133 #define USBPHY_STATUS_RSVD2_MASK                 (0x80U)
48134 #define USBPHY_STATUS_RSVD2_SHIFT                (7U)
48135 #define USBPHY_STATUS_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
48136 
48137 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
48138 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
48139 #define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
48140 
48141 #define USBPHY_STATUS_RSVD3_MASK                 (0x200U)
48142 #define USBPHY_STATUS_RSVD3_SHIFT                (9U)
48143 #define USBPHY_STATUS_RSVD3(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
48144 
48145 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
48146 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
48147 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
48148 
48149 #define USBPHY_STATUS_RSVD4_MASK                 (0xFFFFF800U)
48150 #define USBPHY_STATUS_RSVD4_SHIFT                (11U)
48151 #define USBPHY_STATUS_RSVD4(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
48152 /*! @} */
48153 
48154 /*! @name DEBUG - USB PHY Debug Register */
48155 /*! @{ */
48156 
48157 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
48158 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
48159 #define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
48160 
48161 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
48162 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
48163 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
48164 
48165 #define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
48166 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
48167 #define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
48168 
48169 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
48170 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
48171 #define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
48172 
48173 #define USBPHY_DEBUG_RSVD0_MASK                  (0xC0U)
48174 #define USBPHY_DEBUG_RSVD0_SHIFT                 (6U)
48175 #define USBPHY_DEBUG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
48176 
48177 #define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
48178 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
48179 #define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
48180 
48181 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
48182 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
48183 #define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
48184 
48185 #define USBPHY_DEBUG_RSVD1_MASK                  (0xE000U)
48186 #define USBPHY_DEBUG_RSVD1_SHIFT                 (13U)
48187 #define USBPHY_DEBUG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
48188 
48189 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
48190 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
48191 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
48192 
48193 #define USBPHY_DEBUG_RSVD2_MASK                  (0xE00000U)
48194 #define USBPHY_DEBUG_RSVD2_SHIFT                 (21U)
48195 #define USBPHY_DEBUG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
48196 
48197 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
48198 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
48199 #define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
48200 
48201 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
48202 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
48203 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
48204 
48205 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
48206 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
48207 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
48208 
48209 #define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
48210 #define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
48211 #define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
48212 
48213 #define USBPHY_DEBUG_RSVD3_MASK                  (0x80000000U)
48214 #define USBPHY_DEBUG_RSVD3_SHIFT                 (31U)
48215 #define USBPHY_DEBUG_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
48216 /*! @} */
48217 
48218 /*! @name DEBUG_SET - USB PHY Debug Register */
48219 /*! @{ */
48220 
48221 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
48222 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
48223 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
48224 
48225 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48226 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48227 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
48228 
48229 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
48230 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
48231 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
48232 
48233 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
48234 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
48235 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
48236 
48237 #define USBPHY_DEBUG_SET_RSVD0_MASK              (0xC0U)
48238 #define USBPHY_DEBUG_SET_RSVD0_SHIFT             (6U)
48239 #define USBPHY_DEBUG_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
48240 
48241 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
48242 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
48243 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
48244 
48245 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
48246 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
48247 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
48248 
48249 #define USBPHY_DEBUG_SET_RSVD1_MASK              (0xE000U)
48250 #define USBPHY_DEBUG_SET_RSVD1_SHIFT             (13U)
48251 #define USBPHY_DEBUG_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
48252 
48253 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
48254 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
48255 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
48256 
48257 #define USBPHY_DEBUG_SET_RSVD2_MASK              (0xE00000U)
48258 #define USBPHY_DEBUG_SET_RSVD2_SHIFT             (21U)
48259 #define USBPHY_DEBUG_SET_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
48260 
48261 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
48262 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
48263 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
48264 
48265 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48266 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
48267 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
48268 
48269 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
48270 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
48271 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
48272 
48273 #define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
48274 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
48275 #define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
48276 
48277 #define USBPHY_DEBUG_SET_RSVD3_MASK              (0x80000000U)
48278 #define USBPHY_DEBUG_SET_RSVD3_SHIFT             (31U)
48279 #define USBPHY_DEBUG_SET_RSVD3(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
48280 /*! @} */
48281 
48282 /*! @name DEBUG_CLR - USB PHY Debug Register */
48283 /*! @{ */
48284 
48285 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
48286 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
48287 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
48288 
48289 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48290 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48291 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
48292 
48293 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
48294 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
48295 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
48296 
48297 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
48298 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
48299 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
48300 
48301 #define USBPHY_DEBUG_CLR_RSVD0_MASK              (0xC0U)
48302 #define USBPHY_DEBUG_CLR_RSVD0_SHIFT             (6U)
48303 #define USBPHY_DEBUG_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
48304 
48305 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
48306 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
48307 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
48308 
48309 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
48310 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
48311 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
48312 
48313 #define USBPHY_DEBUG_CLR_RSVD1_MASK              (0xE000U)
48314 #define USBPHY_DEBUG_CLR_RSVD1_SHIFT             (13U)
48315 #define USBPHY_DEBUG_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
48316 
48317 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
48318 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
48319 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
48320 
48321 #define USBPHY_DEBUG_CLR_RSVD2_MASK              (0xE00000U)
48322 #define USBPHY_DEBUG_CLR_RSVD2_SHIFT             (21U)
48323 #define USBPHY_DEBUG_CLR_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
48324 
48325 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
48326 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
48327 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
48328 
48329 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48330 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
48331 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
48332 
48333 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
48334 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
48335 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
48336 
48337 #define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
48338 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
48339 #define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
48340 
48341 #define USBPHY_DEBUG_CLR_RSVD3_MASK              (0x80000000U)
48342 #define USBPHY_DEBUG_CLR_RSVD3_SHIFT             (31U)
48343 #define USBPHY_DEBUG_CLR_RSVD3(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
48344 /*! @} */
48345 
48346 /*! @name DEBUG_TOG - USB PHY Debug Register */
48347 /*! @{ */
48348 
48349 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
48350 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
48351 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
48352 
48353 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48354 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48355 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
48356 
48357 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
48358 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
48359 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
48360 
48361 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
48362 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
48363 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
48364 
48365 #define USBPHY_DEBUG_TOG_RSVD0_MASK              (0xC0U)
48366 #define USBPHY_DEBUG_TOG_RSVD0_SHIFT             (6U)
48367 #define USBPHY_DEBUG_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
48368 
48369 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
48370 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
48371 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
48372 
48373 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
48374 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
48375 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
48376 
48377 #define USBPHY_DEBUG_TOG_RSVD1_MASK              (0xE000U)
48378 #define USBPHY_DEBUG_TOG_RSVD1_SHIFT             (13U)
48379 #define USBPHY_DEBUG_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
48380 
48381 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
48382 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
48383 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
48384 
48385 #define USBPHY_DEBUG_TOG_RSVD2_MASK              (0xE00000U)
48386 #define USBPHY_DEBUG_TOG_RSVD2_SHIFT             (21U)
48387 #define USBPHY_DEBUG_TOG_RSVD2(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
48388 
48389 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
48390 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
48391 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
48392 
48393 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48394 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
48395 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
48396 
48397 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
48398 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
48399 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
48400 
48401 #define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
48402 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
48403 #define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
48404 
48405 #define USBPHY_DEBUG_TOG_RSVD3_MASK              (0x80000000U)
48406 #define USBPHY_DEBUG_TOG_RSVD3_SHIFT             (31U)
48407 #define USBPHY_DEBUG_TOG_RSVD3(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
48408 /*! @} */
48409 
48410 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
48411 /*! @{ */
48412 
48413 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
48414 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
48415 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
48416 
48417 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
48418 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
48419 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
48420 
48421 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
48422 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
48423 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
48424 /*! @} */
48425 
48426 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
48427 /*! @{ */
48428 
48429 #define USBPHY_DEBUG1_RSVD0_MASK                 (0x1FFFU)
48430 #define USBPHY_DEBUG1_RSVD0_SHIFT                (0U)
48431 #define USBPHY_DEBUG1_RSVD0(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
48432 
48433 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
48434 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
48435 #define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
48436 
48437 #define USBPHY_DEBUG1_RSVD1_MASK                 (0xFFFF8000U)
48438 #define USBPHY_DEBUG1_RSVD1_SHIFT                (15U)
48439 #define USBPHY_DEBUG1_RSVD1(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
48440 /*! @} */
48441 
48442 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
48443 /*! @{ */
48444 
48445 #define USBPHY_DEBUG1_SET_RSVD0_MASK             (0x1FFFU)
48446 #define USBPHY_DEBUG1_SET_RSVD0_SHIFT            (0U)
48447 #define USBPHY_DEBUG1_SET_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
48448 
48449 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
48450 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
48451 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
48452 
48453 #define USBPHY_DEBUG1_SET_RSVD1_MASK             (0xFFFF8000U)
48454 #define USBPHY_DEBUG1_SET_RSVD1_SHIFT            (15U)
48455 #define USBPHY_DEBUG1_SET_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
48456 /*! @} */
48457 
48458 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
48459 /*! @{ */
48460 
48461 #define USBPHY_DEBUG1_CLR_RSVD0_MASK             (0x1FFFU)
48462 #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT            (0U)
48463 #define USBPHY_DEBUG1_CLR_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
48464 
48465 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
48466 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
48467 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
48468 
48469 #define USBPHY_DEBUG1_CLR_RSVD1_MASK             (0xFFFF8000U)
48470 #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT            (15U)
48471 #define USBPHY_DEBUG1_CLR_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
48472 /*! @} */
48473 
48474 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
48475 /*! @{ */
48476 
48477 #define USBPHY_DEBUG1_TOG_RSVD0_MASK             (0x1FFFU)
48478 #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT            (0U)
48479 #define USBPHY_DEBUG1_TOG_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
48480 
48481 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
48482 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
48483 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
48484 
48485 #define USBPHY_DEBUG1_TOG_RSVD1_MASK             (0xFFFF8000U)
48486 #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT            (15U)
48487 #define USBPHY_DEBUG1_TOG_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
48488 /*! @} */
48489 
48490 /*! @name VERSION - UTMI RTL Version */
48491 /*! @{ */
48492 
48493 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
48494 #define USBPHY_VERSION_STEP_SHIFT                (0U)
48495 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
48496 
48497 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
48498 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
48499 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
48500 
48501 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
48502 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
48503 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
48504 /*! @} */
48505 
48506 
48507 /*!
48508  * @}
48509  */ /* end of group USBPHY_Register_Masks */
48510 
48511 
48512 /* USBPHY - Peripheral instance base addresses */
48513 /** Peripheral USBPHY1 base address */
48514 #define USBPHY1_BASE                             (0x400D9000u)
48515 /** Peripheral USBPHY1 base pointer */
48516 #define USBPHY1                                  ((USBPHY_Type *)USBPHY1_BASE)
48517 /** Peripheral USBPHY2 base address */
48518 #define USBPHY2_BASE                             (0x400DA000u)
48519 /** Peripheral USBPHY2 base pointer */
48520 #define USBPHY2                                  ((USBPHY_Type *)USBPHY2_BASE)
48521 /** Array initializer of USBPHY peripheral base addresses */
48522 #define USBPHY_BASE_ADDRS                        { 0u, USBPHY1_BASE, USBPHY2_BASE }
48523 /** Array initializer of USBPHY peripheral base pointers */
48524 #define USBPHY_BASE_PTRS                         { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
48525 /** Interrupt vectors for the USBPHY peripheral type */
48526 #define USBPHY_IRQS                              { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
48527 /* Backward compatibility */
48528 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
48529 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
48530 #define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
48531 #define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
48532 #define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
48533 #define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)
48534 #define USBPHY_STACK_BASE_ADDRS             { USBPHY1_BASE, USBPHY2_BASE }
48535 
48536 
48537 /*!
48538  * @}
48539  */ /* end of group USBPHY_Peripheral_Access_Layer */
48540 
48541 
48542 /* ----------------------------------------------------------------------------
48543    -- USB_ANALOG Peripheral Access Layer
48544    ---------------------------------------------------------------------------- */
48545 
48546 /*!
48547  * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer
48548  * @{
48549  */
48550 
48551 /** USB_ANALOG - Register Layout Typedef */
48552 typedef struct {
48553        uint8_t RESERVED_0[416];
48554   struct {                                         /* offset: 0x1A0, array step: 0x60 */
48555     __IO uint32_t VBUS_DETECT;                       /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */
48556     __IO uint32_t VBUS_DETECT_SET;                   /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */
48557     __IO uint32_t VBUS_DETECT_CLR;                   /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */
48558     __IO uint32_t VBUS_DETECT_TOG;                   /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */
48559     __IO uint32_t CHRG_DETECT;                       /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */
48560     __IO uint32_t CHRG_DETECT_SET;                   /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */
48561     __IO uint32_t CHRG_DETECT_CLR;                   /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */
48562     __IO uint32_t CHRG_DETECT_TOG;                   /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */
48563     __I  uint32_t VBUS_DETECT_STAT;                  /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */
48564          uint8_t RESERVED_0[12];
48565     __I  uint32_t CHRG_DETECT_STAT;                  /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */
48566          uint8_t RESERVED_1[12];
48567     __IO uint32_t LOOPBACK;                          /**< USB Loopback Test Register, array offset: 0x1E0, array step: 0x60 */
48568     __IO uint32_t LOOPBACK_SET;                      /**< USB Loopback Test Register, array offset: 0x1E4, array step: 0x60 */
48569     __IO uint32_t LOOPBACK_CLR;                      /**< USB Loopback Test Register, array offset: 0x1E8, array step: 0x60 */
48570     __IO uint32_t LOOPBACK_TOG;                      /**< USB Loopback Test Register, array offset: 0x1EC, array step: 0x60 */
48571     __IO uint32_t MISC;                              /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
48572     __IO uint32_t MISC_SET;                          /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
48573     __IO uint32_t MISC_CLR;                          /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
48574     __IO uint32_t MISC_TOG;                          /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
48575   } INSTANCE[2];
48576   __I  uint32_t DIGPROG;                           /**< Chip Silicon Version, offset: 0x260 */
48577 } USB_ANALOG_Type;
48578 
48579 /* ----------------------------------------------------------------------------
48580    -- USB_ANALOG Register Masks
48581    ---------------------------------------------------------------------------- */
48582 
48583 /*!
48584  * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks
48585  * @{
48586  */
48587 
48588 /*! @name VBUS_DETECT - USB VBUS Detect Register */
48589 /*! @{ */
48590 
48591 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
48592 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
48593 /*! VBUSVALID_THRESH
48594  *  0b000..4.0V
48595  *  0b001..4.1V
48596  *  0b010..4.2V
48597  *  0b011..4.3V
48598  *  0b100..4.4V (default)
48599  *  0b101..4.5V
48600  *  0b110..4.6V
48601  *  0b111..4.7V
48602  */
48603 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
48604 
48605 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48606 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48607 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
48608 
48609 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
48610 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
48611 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
48612 
48613 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK  (0x8000000U)
48614 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
48615 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x)    (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
48616 /*! @} */
48617 
48618 /* The count of USB_ANALOG_VBUS_DETECT */
48619 #define USB_ANALOG_VBUS_DETECT_COUNT             (2U)
48620 
48621 /*! @name VBUS_DETECT_SET - USB VBUS Detect Register */
48622 /*! @{ */
48623 
48624 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
48625 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
48626 /*! VBUSVALID_THRESH
48627  *  0b000..4.0V
48628  *  0b001..4.1V
48629  *  0b010..4.2V
48630  *  0b011..4.3V
48631  *  0b100..4.4V (default)
48632  *  0b101..4.5V
48633  *  0b110..4.6V
48634  *  0b111..4.7V
48635  */
48636 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
48637 
48638 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48639 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48640 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
48641 
48642 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
48643 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
48644 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
48645 
48646 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
48647 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
48648 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
48649 /*! @} */
48650 
48651 /* The count of USB_ANALOG_VBUS_DETECT_SET */
48652 #define USB_ANALOG_VBUS_DETECT_SET_COUNT         (2U)
48653 
48654 /*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */
48655 /*! @{ */
48656 
48657 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
48658 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
48659 /*! VBUSVALID_THRESH
48660  *  0b000..4.0V
48661  *  0b001..4.1V
48662  *  0b010..4.2V
48663  *  0b011..4.3V
48664  *  0b100..4.4V (default)
48665  *  0b101..4.5V
48666  *  0b110..4.6V
48667  *  0b111..4.7V
48668  */
48669 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
48670 
48671 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48672 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48673 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
48674 
48675 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
48676 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
48677 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
48678 
48679 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
48680 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
48681 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
48682 /*! @} */
48683 
48684 /* The count of USB_ANALOG_VBUS_DETECT_CLR */
48685 #define USB_ANALOG_VBUS_DETECT_CLR_COUNT         (2U)
48686 
48687 /*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */
48688 /*! @{ */
48689 
48690 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
48691 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
48692 /*! VBUSVALID_THRESH
48693  *  0b000..4.0V
48694  *  0b001..4.1V
48695  *  0b010..4.2V
48696  *  0b011..4.3V
48697  *  0b100..4.4V (default)
48698  *  0b101..4.5V
48699  *  0b110..4.6V
48700  *  0b111..4.7V
48701  */
48702 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
48703 
48704 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48705 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48706 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
48707 
48708 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
48709 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
48710 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
48711 
48712 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
48713 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
48714 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
48715 /*! @} */
48716 
48717 /* The count of USB_ANALOG_VBUS_DETECT_TOG */
48718 #define USB_ANALOG_VBUS_DETECT_TOG_COUNT         (2U)
48719 
48720 /*! @name CHRG_DETECT - USB Charger Detect Register */
48721 /*! @{ */
48722 
48723 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK  (0x40000U)
48724 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
48725 /*! CHK_CONTACT - Check the contact of USB plug
48726  *  0b0..Do not check the contact of USB plug.
48727  *  0b1..Check whether the USB plug has been in contact with each other
48728  */
48729 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x)    (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
48730 
48731 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK   (0x80000U)
48732 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT  (19U)
48733 /*! CHK_CHRG_B - Check the charger connection
48734  *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
48735  *  0b1..Do not check whether a charger is connected to the USB port.
48736  */
48737 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x)     (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
48738 
48739 #define USB_ANALOG_CHRG_DETECT_EN_B_MASK         (0x100000U)
48740 #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT        (20U)
48741 /*! EN_B
48742  *  0b0..Enable the charger detector.
48743  *  0b1..Disable the charger detector.
48744  */
48745 #define USB_ANALOG_CHRG_DETECT_EN_B(x)           (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
48746 /*! @} */
48747 
48748 /* The count of USB_ANALOG_CHRG_DETECT */
48749 #define USB_ANALOG_CHRG_DETECT_COUNT             (2U)
48750 
48751 /*! @name CHRG_DETECT_SET - USB Charger Detect Register */
48752 /*! @{ */
48753 
48754 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
48755 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
48756 /*! CHK_CONTACT - Check the contact of USB plug
48757  *  0b0..Do not check the contact of USB plug.
48758  *  0b1..Check whether the USB plug has been in contact with each other
48759  */
48760 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
48761 
48762 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
48763 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
48764 /*! CHK_CHRG_B - Check the charger connection
48765  *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
48766  *  0b1..Do not check whether a charger is connected to the USB port.
48767  */
48768 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
48769 
48770 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK     (0x100000U)
48771 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT    (20U)
48772 /*! EN_B
48773  *  0b0..Enable the charger detector.
48774  *  0b1..Disable the charger detector.
48775  */
48776 #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
48777 /*! @} */
48778 
48779 /* The count of USB_ANALOG_CHRG_DETECT_SET */
48780 #define USB_ANALOG_CHRG_DETECT_SET_COUNT         (2U)
48781 
48782 /*! @name CHRG_DETECT_CLR - USB Charger Detect Register */
48783 /*! @{ */
48784 
48785 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
48786 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
48787 /*! CHK_CONTACT - Check the contact of USB plug
48788  *  0b0..Do not check the contact of USB plug.
48789  *  0b1..Check whether the USB plug has been in contact with each other
48790  */
48791 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
48792 
48793 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
48794 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
48795 /*! CHK_CHRG_B - Check the charger connection
48796  *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
48797  *  0b1..Do not check whether a charger is connected to the USB port.
48798  */
48799 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
48800 
48801 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK     (0x100000U)
48802 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT    (20U)
48803 /*! EN_B
48804  *  0b0..Enable the charger detector.
48805  *  0b1..Disable the charger detector.
48806  */
48807 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
48808 /*! @} */
48809 
48810 /* The count of USB_ANALOG_CHRG_DETECT_CLR */
48811 #define USB_ANALOG_CHRG_DETECT_CLR_COUNT         (2U)
48812 
48813 /*! @name CHRG_DETECT_TOG - USB Charger Detect Register */
48814 /*! @{ */
48815 
48816 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
48817 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
48818 /*! CHK_CONTACT - Check the contact of USB plug
48819  *  0b0..Do not check the contact of USB plug.
48820  *  0b1..Check whether the USB plug has been in contact with each other
48821  */
48822 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
48823 
48824 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
48825 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
48826 /*! CHK_CHRG_B - Check the charger connection
48827  *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
48828  *  0b1..Do not check whether a charger is connected to the USB port.
48829  */
48830 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
48831 
48832 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK     (0x100000U)
48833 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT    (20U)
48834 /*! EN_B
48835  *  0b0..Enable the charger detector.
48836  *  0b1..Disable the charger detector.
48837  */
48838 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
48839 /*! @} */
48840 
48841 /* The count of USB_ANALOG_CHRG_DETECT_TOG */
48842 #define USB_ANALOG_CHRG_DETECT_TOG_COUNT         (2U)
48843 
48844 /*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */
48845 /*! @{ */
48846 
48847 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
48848 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
48849 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x)   (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
48850 
48851 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK  (0x2U)
48852 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
48853 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x)    (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
48854 
48855 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK  (0x4U)
48856 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
48857 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x)    (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
48858 
48859 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
48860 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
48861 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
48862 /*! @} */
48863 
48864 /* The count of USB_ANALOG_VBUS_DETECT_STAT */
48865 #define USB_ANALOG_VBUS_DETECT_STAT_COUNT        (2U)
48866 
48867 /*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */
48868 /*! @{ */
48869 
48870 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
48871 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
48872 /*! PLUG_CONTACT
48873  *  0b0..The USB plug has not made contact.
48874  *  0b1..The USB plug has made good contact.
48875  */
48876 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
48877 
48878 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
48879 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
48880 /*! CHRG_DETECTED
48881  *  0b0..The USB port is not connected to a charger.
48882  *  0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port.
48883  */
48884 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
48885 
48886 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
48887 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
48888 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x)  (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
48889 
48890 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
48891 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
48892 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x)  (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
48893 /*! @} */
48894 
48895 /* The count of USB_ANALOG_CHRG_DETECT_STAT */
48896 #define USB_ANALOG_CHRG_DETECT_STAT_COUNT        (2U)
48897 
48898 /*! @name LOOPBACK - USB Loopback Test Register */
48899 /*! @{ */
48900 
48901 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK  (0x1U)
48902 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
48903 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x)    (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
48904 /*! @} */
48905 
48906 /* The count of USB_ANALOG_LOOPBACK */
48907 #define USB_ANALOG_LOOPBACK_COUNT                (2U)
48908 
48909 /*! @name LOOPBACK_SET - USB Loopback Test Register */
48910 /*! @{ */
48911 
48912 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
48913 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
48914 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
48915 /*! @} */
48916 
48917 /* The count of USB_ANALOG_LOOPBACK_SET */
48918 #define USB_ANALOG_LOOPBACK_SET_COUNT            (2U)
48919 
48920 /*! @name LOOPBACK_CLR - USB Loopback Test Register */
48921 /*! @{ */
48922 
48923 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
48924 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
48925 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
48926 /*! @} */
48927 
48928 /* The count of USB_ANALOG_LOOPBACK_CLR */
48929 #define USB_ANALOG_LOOPBACK_CLR_COUNT            (2U)
48930 
48931 /*! @name LOOPBACK_TOG - USB Loopback Test Register */
48932 /*! @{ */
48933 
48934 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
48935 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
48936 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
48937 /*! @} */
48938 
48939 /* The count of USB_ANALOG_LOOPBACK_TOG */
48940 #define USB_ANALOG_LOOPBACK_TOG_COUNT            (2U)
48941 
48942 /*! @name MISC - USB Misc Register */
48943 /*! @{ */
48944 
48945 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK   (0x1U)
48946 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT  (0U)
48947 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x)     (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
48948 
48949 #define USB_ANALOG_MISC_EN_DEGLITCH_MASK         (0x2U)
48950 #define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT        (1U)
48951 #define USB_ANALOG_MISC_EN_DEGLITCH(x)           (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
48952 
48953 #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK         (0x40000000U)
48954 #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT        (30U)
48955 #define USB_ANALOG_MISC_EN_CLK_UTMI(x)           (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
48956 /*! @} */
48957 
48958 /* The count of USB_ANALOG_MISC */
48959 #define USB_ANALOG_MISC_COUNT                    (2U)
48960 
48961 /*! @name MISC_SET - USB Misc Register */
48962 /*! @{ */
48963 
48964 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
48965 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
48966 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
48967 
48968 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK     (0x2U)
48969 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT    (1U)
48970 #define USB_ANALOG_MISC_SET_EN_DEGLITCH(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
48971 
48972 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK     (0x40000000U)
48973 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT    (30U)
48974 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
48975 /*! @} */
48976 
48977 /* The count of USB_ANALOG_MISC_SET */
48978 #define USB_ANALOG_MISC_SET_COUNT                (2U)
48979 
48980 /*! @name MISC_CLR - USB Misc Register */
48981 /*! @{ */
48982 
48983 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
48984 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
48985 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
48986 
48987 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK     (0x2U)
48988 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT    (1U)
48989 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
48990 
48991 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK     (0x40000000U)
48992 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT    (30U)
48993 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
48994 /*! @} */
48995 
48996 /* The count of USB_ANALOG_MISC_CLR */
48997 #define USB_ANALOG_MISC_CLR_COUNT                (2U)
48998 
48999 /*! @name MISC_TOG - USB Misc Register */
49000 /*! @{ */
49001 
49002 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
49003 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
49004 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
49005 
49006 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK     (0x2U)
49007 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT    (1U)
49008 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
49009 
49010 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK     (0x40000000U)
49011 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT    (30U)
49012 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
49013 /*! @} */
49014 
49015 /* The count of USB_ANALOG_MISC_TOG */
49016 #define USB_ANALOG_MISC_TOG_COUNT                (2U)
49017 
49018 /*! @name DIGPROG - Chip Silicon Version */
49019 /*! @{ */
49020 
49021 #define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
49022 #define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
49023 /*! SILICON_REVISION
49024  *  0b00000000011010100000000000000001..Silicon revision 1.1
49025  */
49026 #define USB_ANALOG_DIGPROG_SILICON_REVISION(x)   (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
49027 /*! @} */
49028 
49029 
49030 /*!
49031  * @}
49032  */ /* end of group USB_ANALOG_Register_Masks */
49033 
49034 
49035 /* USB_ANALOG - Peripheral instance base addresses */
49036 /** Peripheral USB_ANALOG base address */
49037 #define USB_ANALOG_BASE                          (0x400D8000u)
49038 /** Peripheral USB_ANALOG base pointer */
49039 #define USB_ANALOG                               ((USB_ANALOG_Type *)USB_ANALOG_BASE)
49040 /** Array initializer of USB_ANALOG peripheral base addresses */
49041 #define USB_ANALOG_BASE_ADDRS                    { USB_ANALOG_BASE }
49042 /** Array initializer of USB_ANALOG peripheral base pointers */
49043 #define USB_ANALOG_BASE_PTRS                     { USB_ANALOG }
49044 
49045 /*!
49046  * @}
49047  */ /* end of group USB_ANALOG_Peripheral_Access_Layer */
49048 
49049 
49050 /* ----------------------------------------------------------------------------
49051    -- USDHC Peripheral Access Layer
49052    ---------------------------------------------------------------------------- */
49053 
49054 /*!
49055  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
49056  * @{
49057  */
49058 
49059 /** USDHC - Register Layout Typedef */
49060 typedef struct {
49061   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
49062   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
49063   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
49064   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
49065   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
49066   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
49067   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
49068   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
49069   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
49070   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
49071   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
49072   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
49073   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
49074   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
49075   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
49076   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
49077   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
49078   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
49079   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
49080        uint8_t RESERVED_0[4];
49081   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
49082   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
49083   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
49084        uint8_t RESERVED_1[4];
49085   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
49086   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
49087   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
49088        uint8_t RESERVED_2[84];
49089   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
49090   __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
49091   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
49092   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
49093 } USDHC_Type;
49094 
49095 /* ----------------------------------------------------------------------------
49096    -- USDHC Register Masks
49097    ---------------------------------------------------------------------------- */
49098 
49099 /*!
49100  * @addtogroup USDHC_Register_Masks USDHC Register Masks
49101  * @{
49102  */
49103 
49104 /*! @name DS_ADDR - DMA System Address */
49105 /*! @{ */
49106 
49107 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
49108 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
49109 /*! DS_ADDR - System address
49110  */
49111 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
49112 /*! @} */
49113 
49114 /*! @name BLK_ATT - Block Attributes */
49115 /*! @{ */
49116 
49117 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
49118 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
49119 /*! BLKSIZE - Transfer block size
49120  *  0b1000000000000..4096 bytes
49121  *  0b0100000000000..2048 bytes
49122  *  0b0001000000000..512 bytes
49123  *  0b0000111111111..511 bytes
49124  *  0b0000000000100..4 bytes
49125  *  0b0000000000011..3 bytes
49126  *  0b0000000000010..2 bytes
49127  *  0b0000000000001..1 byte
49128  *  0b0000000000000..No data transfer
49129  */
49130 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
49131 
49132 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
49133 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
49134 /*! BLKCNT - Blocks count for current transfer
49135  *  0b1111111111111111..65535 blocks
49136  *  0b0000000000000010..2 blocks
49137  *  0b0000000000000001..1 block
49138  *  0b0000000000000000..Stop count
49139  */
49140 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
49141 /*! @} */
49142 
49143 /*! @name CMD_ARG - Command Argument */
49144 /*! @{ */
49145 
49146 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
49147 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
49148 /*! CMDARG - Command argument
49149  */
49150 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
49151 /*! @} */
49152 
49153 /*! @name CMD_XFR_TYP - Command Transfer Type */
49154 /*! @{ */
49155 
49156 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
49157 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
49158 /*! RSPTYP - Response type select
49159  *  0b00..No response
49160  *  0b01..Response length 136
49161  *  0b10..Response length 48
49162  *  0b11..Response length 48, check busy after response
49163  */
49164 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
49165 
49166 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
49167 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
49168 /*! CCCEN - Command CRC check enable
49169  *  0b1..Enables command CRC check
49170  *  0b0..Disables command CRC check
49171  */
49172 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
49173 
49174 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
49175 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
49176 /*! CICEN - Command index check enable
49177  *  0b1..Enables command index check
49178  *  0b0..Disable command index check
49179  */
49180 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
49181 
49182 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
49183 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
49184 /*! DPSEL - Data present select
49185  *  0b1..Data present
49186  *  0b0..No data present
49187  */
49188 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
49189 
49190 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
49191 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
49192 /*! CMDTYP - Command type
49193  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
49194  *  0b10..Resume CMD52 for writing function select in CCCR
49195  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
49196  *  0b00..Normal other commands
49197  */
49198 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
49199 
49200 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
49201 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
49202 /*! CMDINX - Command index
49203  */
49204 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
49205 /*! @} */
49206 
49207 /*! @name CMD_RSP0 - Command Response0 */
49208 /*! @{ */
49209 
49210 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
49211 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
49212 /*! CMDRSP0 - Command response 0
49213  */
49214 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
49215 /*! @} */
49216 
49217 /*! @name CMD_RSP1 - Command Response1 */
49218 /*! @{ */
49219 
49220 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
49221 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
49222 /*! CMDRSP1 - Command response 1
49223  */
49224 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
49225 /*! @} */
49226 
49227 /*! @name CMD_RSP2 - Command Response2 */
49228 /*! @{ */
49229 
49230 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
49231 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
49232 /*! CMDRSP2 - Command response 2
49233  */
49234 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
49235 /*! @} */
49236 
49237 /*! @name CMD_RSP3 - Command Response3 */
49238 /*! @{ */
49239 
49240 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
49241 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
49242 /*! CMDRSP3 - Command response 3
49243  */
49244 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
49245 /*! @} */
49246 
49247 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
49248 /*! @{ */
49249 
49250 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
49251 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
49252 /*! DATCONT - Data content
49253  */
49254 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
49255 /*! @} */
49256 
49257 /*! @name PRES_STATE - Present State */
49258 /*! @{ */
49259 
49260 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
49261 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
49262 /*! CIHB - Command inhibit (CMD)
49263  *  0b1..Cannot issue command
49264  *  0b0..Can issue command using only CMD line
49265  */
49266 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
49267 
49268 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
49269 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
49270 /*! CDIHB - Command inhibit (DATA)
49271  *  0b1..Cannot issue command that uses the DATA line
49272  *  0b0..Can issue command that uses the DATA line
49273  */
49274 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
49275 
49276 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
49277 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
49278 /*! DLA - Data line active
49279  *  0b1..DATA line active
49280  *  0b0..DATA line inactive
49281  */
49282 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
49283 
49284 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
49285 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
49286 /*! SDSTB - SD clock stable
49287  *  0b1..Clock is stable.
49288  *  0b0..Clock is changing frequency and not stable.
49289  */
49290 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
49291 
49292 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
49293 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
49294 /*! IPGOFF - Peripheral clock gated off internally
49295  *  0b1..Peripheral clock is gated off.
49296  *  0b0..Peripheral clock is active.
49297  */
49298 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
49299 
49300 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
49301 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
49302 /*! HCKOFF - HCLK gated off internally
49303  *  0b1..HCLK is gated off.
49304  *  0b0..HCLK is active.
49305  */
49306 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
49307 
49308 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
49309 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
49310 /*! PEROFF - IPG_PERCLK gated off internally
49311  *  0b1..IPG_PERCLK is gated off.
49312  *  0b0..IPG_PERCLK is active.
49313  */
49314 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
49315 
49316 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
49317 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
49318 /*! SDOFF - SD clock gated off internally
49319  *  0b1..SD clock is gated off.
49320  *  0b0..SD clock is active.
49321  */
49322 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
49323 
49324 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
49325 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
49326 /*! WTA - Write transfer active
49327  *  0b1..Transferring data
49328  *  0b0..No valid data
49329  */
49330 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
49331 
49332 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
49333 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
49334 /*! RTA - Read transfer active
49335  *  0b1..Transferring data
49336  *  0b0..No valid data
49337  */
49338 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
49339 
49340 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
49341 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
49342 /*! BWEN - Buffer write enable
49343  *  0b1..Write enable
49344  *  0b0..Write disable
49345  */
49346 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
49347 
49348 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
49349 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
49350 /*! BREN - Buffer read enable
49351  *  0b1..Read enable
49352  *  0b0..Read disable
49353  */
49354 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
49355 
49356 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
49357 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
49358 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
49359  *  0b1..Sampling clock needs re-tuning
49360  *  0b0..Fixed or well tuned sampling clock
49361  */
49362 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
49363 
49364 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
49365 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
49366 /*! TSCD - Tape select change done
49367  *  0b1..Delay cell select change is finished.
49368  *  0b0..Delay cell select change is not finished.
49369  */
49370 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
49371 
49372 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
49373 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
49374 /*! CINST - Card inserted
49375  *  0b1..Card inserted
49376  *  0b0..Power on reset or no card
49377  */
49378 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
49379 
49380 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
49381 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
49382 /*! CDPL - Card detect pin level
49383  *  0b1..Card present (CD_B = 0)
49384  *  0b0..No card present (CD_B = 1)
49385  */
49386 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
49387 
49388 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
49389 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
49390 /*! WPSPL - Write protect switch pin level
49391  *  0b1..Write enabled (WP = 0)
49392  *  0b0..Write protected (WP = 1)
49393  */
49394 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
49395 
49396 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
49397 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
49398 /*! CLSL - CMD line signal level
49399  */
49400 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
49401 
49402 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
49403 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
49404 /*! DLSL - DATA[7:0] line signal level
49405  *  0b00000111..Data 7 line signal level
49406  *  0b00000110..Data 6 line signal level
49407  *  0b00000101..Data 5 line signal level
49408  *  0b00000100..Data 4 line signal level
49409  *  0b00000011..Data 3 line signal level
49410  *  0b00000010..Data 2 line signal level
49411  *  0b00000001..Data 1 line signal level
49412  *  0b00000000..Data 0 line signal level
49413  */
49414 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
49415 /*! @} */
49416 
49417 /*! @name PROT_CTRL - Protocol Control */
49418 /*! @{ */
49419 
49420 #define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
49421 #define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
49422 /*! LCTL - LED control
49423  *  0b1..LED on
49424  *  0b0..LED off
49425  */
49426 #define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
49427 
49428 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
49429 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
49430 /*! DTW - Data transfer width
49431  *  0b10..8-bit mode
49432  *  0b01..4-bit mode
49433  *  0b00..1-bit mode
49434  *  0b11..Reserved
49435  */
49436 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
49437 
49438 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
49439 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
49440 /*! D3CD - DATA3 as card detection pin
49441  *  0b1..DATA3 as card detection pin
49442  *  0b0..DATA3 does not monitor card insertion
49443  */
49444 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
49445 
49446 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
49447 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
49448 /*! EMODE - Endian mode
49449  *  0b00..Big endian mode
49450  *  0b01..Half word big endian mode
49451  *  0b10..Little endian mode
49452  *  0b11..Reserved
49453  */
49454 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
49455 
49456 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
49457 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
49458 /*! CDTL - Card detect test level
49459  *  0b1..Card detect test level is 1, card inserted
49460  *  0b0..Card detect test level is 0, no card inserted
49461  */
49462 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
49463 
49464 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
49465 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
49466 /*! CDSS - Card detect signal selection
49467  *  0b1..Card detection test level is selected (for test purpose).
49468  *  0b0..Card detection level is selected (for normal purpose).
49469  */
49470 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
49471 
49472 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
49473 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
49474 /*! DMASEL - DMA select
49475  *  0b00..No DMA or simple DMA is selected.
49476  *  0b01..ADMA1 is selected.
49477  *  0b10..ADMA2 is selected.
49478  *  0b11..Reserved
49479  */
49480 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
49481 
49482 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
49483 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
49484 /*! SABGREQ - Stop at block gap request
49485  *  0b1..Stop
49486  *  0b0..Transfer
49487  */
49488 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
49489 
49490 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
49491 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
49492 /*! CREQ - Continue request
49493  *  0b1..Restart
49494  *  0b0..No effect
49495  */
49496 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
49497 
49498 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
49499 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
49500 /*! RWCTL - Read wait control
49501  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
49502  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
49503  */
49504 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
49505 
49506 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
49507 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
49508 /*! IABG - Interrupt at block gap
49509  *  0b1..Enables interrupt at block gap
49510  *  0b0..Disables interrupt at block gap
49511  */
49512 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
49513 
49514 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
49515 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
49516 /*! RD_DONE_NO_8CLK - Read performed number 8 clock
49517  */
49518 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
49519 
49520 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
49521 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
49522 /*! WECINT - Wakeup event enable on card interrupt
49523  *  0b1..Enables wakeup event enable on card interrupt
49524  *  0b0..Disables wakeup event enable on card interrupt
49525  */
49526 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
49527 
49528 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
49529 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
49530 /*! WECINS - Wakeup event enable on SD card insertion
49531  *  0b1..Enable wakeup event enable on SD card insertion
49532  *  0b0..Disable wakeup event enable on SD card insertion
49533  */
49534 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
49535 
49536 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
49537 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
49538 /*! WECRM - Wakeup event enable on SD card removal
49539  *  0b1..Enables wakeup event enable on SD card removal
49540  *  0b0..Disables wakeup event enable on SD card removal
49541  */
49542 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
49543 
49544 #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK        (0x38000000U)
49545 #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       (27U)
49546 /*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
49547  *  0bxx1..Burst length is enabled for INCR.
49548  *  0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16.
49549  *  0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP.
49550  */
49551 #define USDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
49552 
49553 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
49554 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
49555 /*! NON_EXACT_BLK_RD - Non-exact block read
49556  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
49557  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
49558  */
49559 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
49560 /*! @} */
49561 
49562 /*! @name SYS_CTRL - System Control */
49563 /*! @{ */
49564 
49565 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
49566 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
49567 /*! DVS - Divisor
49568  *  0b0000..Divide-by-1
49569  *  0b0001..Divide-by-2
49570  *  0b1110..Divide-by-15
49571  *  0b1111..Divide-by-16
49572  */
49573 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
49574 
49575 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
49576 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
49577 /*! SDCLKFS - SDCLK frequency select
49578  */
49579 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
49580 
49581 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
49582 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
49583 /*! DTOCV - Data timeout counter value
49584  *  0b1111..SDCLK x 2 31 recommend to use for HS400 mode
49585  *  0b1110..SDCLK x 2 30 recommend to use for HS200/SDR104 mode
49586  *  0b1101..SDCLK x 2 29 recommend to use for other speed mode except HS400/HS200/SDR104 mode
49587  *  0b0011..SDCLK x 2 19
49588  *  0b0010..SDCLK x 2 18
49589  *  0b0001..SDCLK x 2 33
49590  *  0b0000..SDCLK x 2 32
49591  */
49592 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
49593 
49594 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
49595 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
49596 /*! IPP_RST_N - Hardware reset
49597  */
49598 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
49599 
49600 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
49601 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
49602 /*! RSTA - Software reset for all
49603  *  0b1..Reset
49604  *  0b0..No reset
49605  */
49606 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
49607 
49608 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
49609 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
49610 /*! RSTC - Software reset for CMD line
49611  *  0b1..Reset
49612  *  0b0..No reset
49613  */
49614 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
49615 
49616 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
49617 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
49618 /*! RSTD - Software reset for data line
49619  *  0b1..Reset
49620  *  0b0..No reset
49621  */
49622 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
49623 
49624 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
49625 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
49626 /*! INITA - Initialization active
49627  */
49628 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
49629 
49630 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
49631 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
49632 /*! RSTT - Reset tuning
49633  */
49634 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
49635 /*! @} */
49636 
49637 /*! @name INT_STATUS - Interrupt Status */
49638 /*! @{ */
49639 
49640 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
49641 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
49642 /*! CC - Command complete
49643  *  0b1..Command complete
49644  *  0b0..Command not complete
49645  */
49646 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
49647 
49648 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
49649 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
49650 /*! TC - Transfer complete
49651  *  0b1..Transfer complete
49652  *  0b0..Transfer does not complete
49653  */
49654 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
49655 
49656 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
49657 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
49658 /*! BGE - Block gap event
49659  *  0b1..Transaction stopped at block gap
49660  *  0b0..No block gap event
49661  */
49662 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
49663 
49664 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
49665 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
49666 /*! DINT - DMA interrupt
49667  *  0b1..DMA interrupt is generated.
49668  *  0b0..No DMA interrupt
49669  */
49670 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
49671 
49672 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
49673 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
49674 /*! BWR - Buffer write ready
49675  *  0b1..Ready to write buffer
49676  *  0b0..Not ready to write buffer
49677  */
49678 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
49679 
49680 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
49681 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
49682 /*! BRR - Buffer read ready
49683  *  0b1..Ready to read buffer
49684  *  0b0..Not ready to read buffer
49685  */
49686 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
49687 
49688 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
49689 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
49690 /*! CINS - Card insertion
49691  *  0b1..Card inserted
49692  *  0b0..Card state unstable or removed
49693  */
49694 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
49695 
49696 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
49697 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
49698 /*! CRM - Card removal
49699  *  0b1..Card removed
49700  *  0b0..Card state unstable or inserted
49701  */
49702 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
49703 
49704 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
49705 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
49706 /*! CINT - Card interrupt
49707  *  0b1..Generate card interrupt
49708  *  0b0..No card interrupt
49709  */
49710 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
49711 
49712 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
49713 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
49714 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
49715  *  0b1..Re-tuning should be performed.
49716  *  0b0..Re-tuning is not required.
49717  */
49718 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
49719 
49720 #define USDHC_INT_STATUS_TP_MASK                 (0x4000U)
49721 #define USDHC_INT_STATUS_TP_SHIFT                (14U)
49722 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
49723  */
49724 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
49725 
49726 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
49727 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
49728 /*! CTOE - Command timeout error
49729  *  0b1..Time out
49730  *  0b0..No error
49731  */
49732 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
49733 
49734 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
49735 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
49736 /*! CCE - Command CRC error
49737  *  0b1..CRC error generated
49738  *  0b0..No error
49739  */
49740 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
49741 
49742 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
49743 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
49744 /*! CEBE - Command end bit error
49745  *  0b1..End bit error generated
49746  *  0b0..No error
49747  */
49748 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
49749 
49750 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
49751 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
49752 /*! CIE - Command index error
49753  *  0b1..Error
49754  *  0b0..No error
49755  */
49756 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
49757 
49758 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
49759 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
49760 /*! DTOE - Data timeout error
49761  *  0b1..Time out
49762  *  0b0..No error
49763  */
49764 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
49765 
49766 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
49767 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
49768 /*! DCE - Data CRC error
49769  *  0b1..Error
49770  *  0b0..No error
49771  */
49772 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
49773 
49774 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
49775 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
49776 /*! DEBE - Data end bit error
49777  *  0b1..Error
49778  *  0b0..No error
49779  */
49780 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
49781 
49782 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
49783 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
49784 /*! AC12E - Auto CMD12 error
49785  *  0b1..Error
49786  *  0b0..No error
49787  */
49788 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
49789 
49790 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
49791 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
49792 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
49793  */
49794 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
49795 
49796 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
49797 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
49798 /*! DMAE - DMA error
49799  *  0b1..Error
49800  *  0b0..No error
49801  */
49802 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
49803 /*! @} */
49804 
49805 /*! @name INT_STATUS_EN - Interrupt Status Enable */
49806 /*! @{ */
49807 
49808 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
49809 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
49810 /*! CCSEN - Command complete status enable
49811  *  0b1..Enabled
49812  *  0b0..Masked
49813  */
49814 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
49815 
49816 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
49817 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
49818 /*! TCSEN - Transfer complete status enable
49819  *  0b1..Enabled
49820  *  0b0..Masked
49821  */
49822 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
49823 
49824 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
49825 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
49826 /*! BGESEN - Block gap event status enable
49827  *  0b1..Enabled
49828  *  0b0..Masked
49829  */
49830 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
49831 
49832 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
49833 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
49834 /*! DINTSEN - DMA interrupt status enable
49835  *  0b1..Enabled
49836  *  0b0..Masked
49837  */
49838 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
49839 
49840 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
49841 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
49842 /*! BWRSEN - Buffer write ready status enable
49843  *  0b1..Enabled
49844  *  0b0..Masked
49845  */
49846 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
49847 
49848 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
49849 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
49850 /*! BRRSEN - Buffer read ready status enable
49851  *  0b1..Enabled
49852  *  0b0..Masked
49853  */
49854 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
49855 
49856 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
49857 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
49858 /*! CINSSEN - Card insertion status enable
49859  *  0b1..Enabled
49860  *  0b0..Masked
49861  */
49862 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
49863 
49864 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
49865 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
49866 /*! CRMSEN - Card removal status enable
49867  *  0b1..Enabled
49868  *  0b0..Masked
49869  */
49870 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
49871 
49872 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
49873 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
49874 /*! CINTSEN - Card interrupt status enable
49875  *  0b1..Enabled
49876  *  0b0..Masked
49877  */
49878 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
49879 
49880 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
49881 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
49882 /*! RTESEN - Re-tuning event status enable
49883  *  0b1..Enabled
49884  *  0b0..Masked
49885  */
49886 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
49887 
49888 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x4000U)
49889 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (14U)
49890 /*! TPSEN - Tuning pass status enable
49891  *  0b1..Enabled
49892  *  0b0..Masked
49893  */
49894 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
49895 
49896 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
49897 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
49898 /*! CTOESEN - Command timeout error status enable
49899  *  0b1..Enabled
49900  *  0b0..Masked
49901  */
49902 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
49903 
49904 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
49905 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
49906 /*! CCESEN - Command CRC error status enable
49907  *  0b1..Enabled
49908  *  0b0..Masked
49909  */
49910 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
49911 
49912 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
49913 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
49914 /*! CEBESEN - Command end bit error status enable
49915  *  0b1..Enabled
49916  *  0b0..Masked
49917  */
49918 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
49919 
49920 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
49921 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
49922 /*! CIESEN - Command index error status enable
49923  *  0b1..Enabled
49924  *  0b0..Masked
49925  */
49926 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
49927 
49928 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
49929 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
49930 /*! DTOESEN - Data timeout error status enable
49931  *  0b1..Enabled
49932  *  0b0..Masked
49933  */
49934 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
49935 
49936 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
49937 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
49938 /*! DCESEN - Data CRC error status enable
49939  *  0b1..Enabled
49940  *  0b0..Masked
49941  */
49942 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
49943 
49944 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
49945 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
49946 /*! DEBESEN - Data end bit error status enable
49947  *  0b1..Enabled
49948  *  0b0..Masked
49949  */
49950 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
49951 
49952 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
49953 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
49954 /*! AC12ESEN - Auto CMD12 error status enable
49955  *  0b1..Enabled
49956  *  0b0..Masked
49957  */
49958 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
49959 
49960 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
49961 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
49962 /*! TNESEN - Tuning error status enable
49963  *  0b1..Enabled
49964  *  0b0..Masked
49965  */
49966 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
49967 
49968 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
49969 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
49970 /*! DMAESEN - DMA error status enable
49971  *  0b1..Enabled
49972  *  0b0..Masked
49973  */
49974 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
49975 /*! @} */
49976 
49977 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
49978 /*! @{ */
49979 
49980 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
49981 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
49982 /*! CCIEN - Command complete interrupt enable
49983  *  0b1..Enabled
49984  *  0b0..Masked
49985  */
49986 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
49987 
49988 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
49989 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
49990 /*! TCIEN - Transfer complete interrupt enable
49991  *  0b1..Enabled
49992  *  0b0..Masked
49993  */
49994 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
49995 
49996 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
49997 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
49998 /*! BGEIEN - Block gap event interrupt enable
49999  *  0b1..Enabled
50000  *  0b0..Masked
50001  */
50002 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
50003 
50004 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
50005 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
50006 /*! DINTIEN - DMA interrupt enable
50007  *  0b1..Enabled
50008  *  0b0..Masked
50009  */
50010 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
50011 
50012 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
50013 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
50014 /*! BWRIEN - Buffer write ready interrupt enable
50015  *  0b1..Enabled
50016  *  0b0..Masked
50017  */
50018 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
50019 
50020 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
50021 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
50022 /*! BRRIEN - Buffer read ready interrupt enable
50023  *  0b1..Enabled
50024  *  0b0..Masked
50025  */
50026 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
50027 
50028 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
50029 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
50030 /*! CINSIEN - Card insertion interrupt enable
50031  *  0b1..Enabled
50032  *  0b0..Masked
50033  */
50034 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
50035 
50036 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
50037 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
50038 /*! CRMIEN - Card removal interrupt enable
50039  *  0b1..Enabled
50040  *  0b0..Masked
50041  */
50042 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
50043 
50044 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
50045 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
50046 /*! CINTIEN - Card interrupt enable
50047  *  0b1..Enabled
50048  *  0b0..Masked
50049  */
50050 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
50051 
50052 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
50053 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
50054 /*! RTEIEN - Re-tuning event interrupt enable
50055  *  0b1..Enabled
50056  *  0b0..Masked
50057  */
50058 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
50059 
50060 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x4000U)
50061 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (14U)
50062 /*! TPIEN - Tuning Pass interrupt enable
50063  *  0b1..Enabled
50064  *  0b0..Masked
50065  */
50066 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
50067 
50068 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
50069 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
50070 /*! CTOEIEN - Command timeout error interrupt enable
50071  *  0b1..Enabled
50072  *  0b0..Masked
50073  */
50074 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
50075 
50076 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
50077 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
50078 /*! CCEIEN - Command CRC error interrupt enable
50079  *  0b1..Enabled
50080  *  0b0..Masked
50081  */
50082 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
50083 
50084 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
50085 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
50086 /*! CEBEIEN - Command end bit error interrupt enable
50087  *  0b1..Enabled
50088  *  0b0..Masked
50089  */
50090 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
50091 
50092 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
50093 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
50094 /*! CIEIEN - Command index error interrupt enable
50095  *  0b1..Enabled
50096  *  0b0..Masked
50097  */
50098 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
50099 
50100 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
50101 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
50102 /*! DTOEIEN - Data timeout error interrupt enable
50103  *  0b1..Enabled
50104  *  0b0..Masked
50105  */
50106 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
50107 
50108 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
50109 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
50110 /*! DCEIEN - Data CRC error interrupt enable
50111  *  0b1..Enabled
50112  *  0b0..Masked
50113  */
50114 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
50115 
50116 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
50117 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
50118 /*! DEBEIEN - Data end bit error interrupt enable
50119  *  0b1..Enabled
50120  *  0b0..Masked
50121  */
50122 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
50123 
50124 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
50125 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
50126 /*! AC12EIEN - Auto CMD12 error interrupt enable
50127  *  0b1..Enabled
50128  *  0b0..Masked
50129  */
50130 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
50131 
50132 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
50133 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
50134 /*! TNEIEN - Tuning error interrupt enable
50135  *  0b1..Enabled
50136  *  0b0..Masked
50137  */
50138 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
50139 
50140 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
50141 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
50142 /*! DMAEIEN - DMA error interrupt enable
50143  *  0b1..Enable
50144  *  0b0..Masked
50145  */
50146 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
50147 /*! @} */
50148 
50149 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
50150 /*! @{ */
50151 
50152 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
50153 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
50154 /*! AC12NE - Auto CMD12 not executed
50155  *  0b1..Not executed
50156  *  0b0..Executed
50157  */
50158 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
50159 
50160 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
50161 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
50162 /*! AC12TOE - Auto CMD12 / 23 timeout error
50163  *  0b1..Time out
50164  *  0b0..No error
50165  */
50166 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
50167 
50168 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
50169 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
50170 /*! AC12EBE - Auto CMD12 / 23 end bit error
50171  *  0b1..End bit error generated
50172  *  0b0..No error
50173  */
50174 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
50175 
50176 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
50177 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
50178 /*! AC12CE - Auto CMD12 / 23 CRC error
50179  *  0b1..CRC error met in Auto CMD12/23 response
50180  *  0b0..No CRC error
50181  */
50182 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
50183 
50184 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
50185 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
50186 /*! AC12IE - Auto CMD12 / 23 index error
50187  *  0b1..Error, the CMD index in response is not CMD12/23
50188  *  0b0..No error
50189  */
50190 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
50191 
50192 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
50193 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
50194 /*! CNIBAC12E - Command not issued by Auto CMD12 error
50195  *  0b1..Not issued
50196  *  0b0..No error
50197  */
50198 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
50199 
50200 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
50201 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
50202 /*! EXECUTE_TUNING - Execute tuning
50203  */
50204 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
50205 
50206 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
50207 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
50208 /*! SMP_CLK_SEL - Sample clock select
50209  *  0b1..Tuned clock is used to sample data
50210  *  0b0..Fixed clock is used to sample data
50211  */
50212 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
50213 /*! @} */
50214 
50215 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
50216 /*! @{ */
50217 
50218 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
50219 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
50220 /*! SDR50_SUPPORT - SDR50 support
50221  */
50222 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
50223 
50224 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
50225 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
50226 /*! SDR104_SUPPORT - SDR104 support
50227  */
50228 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
50229 
50230 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
50231 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
50232 /*! DDR50_SUPPORT - DDR50 support
50233  */
50234 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
50235 
50236 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
50237 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
50238 /*! TIME_COUNT_RETUNING - Time counter for retuning
50239  */
50240 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
50241 
50242 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
50243 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
50244 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
50245  *  0b1..SDR50 requires tuning.
50246  *  0b0..SDR does not require tuning.
50247  */
50248 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
50249 
50250 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK   (0xC000U)
50251 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT  (14U)
50252 /*! RETUNING_MODE - Retuning Mode
50253  *  0b00..Mode 1
50254  *  0b01..Mode 2
50255  *  0b10..Mode 3
50256  *  0b11..Reserved
50257  */
50258 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
50259 
50260 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
50261 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
50262 /*! MBL - Max block length
50263  *  0b000..512 bytes
50264  *  0b001..1024 bytes
50265  *  0b010..2048 bytes
50266  *  0b011..4096 bytes
50267  */
50268 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
50269 
50270 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
50271 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
50272 /*! ADMAS - ADMA support
50273  *  0b1..Advanced DMA supported
50274  *  0b0..Advanced DMA not supported
50275  */
50276 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
50277 
50278 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
50279 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
50280 /*! HSS - High speed support
50281  *  0b1..High speed supported
50282  *  0b0..High speed not supported
50283  */
50284 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
50285 
50286 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
50287 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
50288 /*! DMAS - DMA support
50289  *  0b1..DMA supported
50290  *  0b0..DMA not supported
50291  */
50292 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
50293 
50294 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
50295 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
50296 /*! SRS - Suspend / resume support
50297  *  0b1..Supported
50298  *  0b0..Not supported
50299  */
50300 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
50301 
50302 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
50303 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
50304 /*! VS33 - Voltage support 3.3 V
50305  *  0b1..3.3 V supported
50306  *  0b0..3.3 V not supported
50307  */
50308 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
50309 
50310 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
50311 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
50312 /*! VS30 - Voltage support 3.0 V
50313  *  0b1..3.0 V supported
50314  *  0b0..3.0 V not supported
50315  */
50316 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
50317 
50318 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
50319 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
50320 /*! VS18 - Voltage support 1.8 V
50321  *  0b1..1.8 V supported
50322  *  0b0..1.8 V not supported
50323  */
50324 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
50325 /*! @} */
50326 
50327 /*! @name WTMK_LVL - Watermark Level */
50328 /*! @{ */
50329 
50330 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
50331 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
50332 /*! RD_WML - Read watermark level
50333  */
50334 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
50335 
50336 #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK          (0x1F00U)
50337 #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         (8U)
50338 /*! RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16
50339  */
50340 #define USDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
50341 
50342 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
50343 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
50344 /*! WR_WML - Write watermark level
50345  */
50346 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
50347 
50348 #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK          (0x1F000000U)
50349 #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         (24U)
50350 /*! WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16
50351  */
50352 #define USDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
50353 /*! @} */
50354 
50355 /*! @name MIX_CTRL - Mixer Control */
50356 /*! @{ */
50357 
50358 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
50359 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
50360 /*! DMAEN - DMA enable
50361  *  0b1..Enable
50362  *  0b0..Disable
50363  */
50364 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
50365 
50366 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
50367 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
50368 /*! BCEN - Block count enable
50369  *  0b1..Enable
50370  *  0b0..Disable
50371  */
50372 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
50373 
50374 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
50375 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
50376 /*! AC12EN - Auto CMD12 enable
50377  *  0b1..Enable
50378  *  0b0..Disable
50379  */
50380 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
50381 
50382 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
50383 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
50384 /*! DDR_EN - Dual data rate mode selection
50385  */
50386 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
50387 
50388 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
50389 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
50390 /*! DTDSEL - Data transfer direction select
50391  *  0b1..Read (Card to host)
50392  *  0b0..Write (Host to card)
50393  */
50394 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
50395 
50396 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
50397 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
50398 /*! MSBSEL - Multi / Single block select
50399  *  0b1..Multiple blocks
50400  *  0b0..Single block
50401  */
50402 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
50403 
50404 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
50405 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
50406 /*! NIBBLE_POS - Nibble position indication
50407  */
50408 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
50409 
50410 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
50411 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
50412 /*! AC23EN - Auto CMD23 enable
50413  */
50414 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
50415 
50416 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
50417 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
50418 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
50419  *  0b1..Execute tuning
50420  *  0b0..Not tuned or tuning completed
50421  */
50422 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
50423 
50424 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
50425 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
50426 /*! SMP_CLK_SEL - Clock selection
50427  *  0b1..Tuned clock is used to sample data / cmd
50428  *  0b0..Fixed clock is used to sample data / cmd
50429  */
50430 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
50431 
50432 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
50433 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
50434 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
50435  *  0b1..Enable auto tuning
50436  *  0b0..Disable auto tuning
50437  */
50438 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
50439 
50440 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
50441 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
50442 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
50443  *  0b1..Feedback clock comes from the ipp_card_clk_out
50444  *  0b0..Feedback clock comes from the loopback CLK
50445  */
50446 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
50447 /*! @} */
50448 
50449 /*! @name FORCE_EVENT - Force Event */
50450 /*! @{ */
50451 
50452 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
50453 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
50454 /*! FEVTAC12NE - Force event auto command 12 not executed
50455  */
50456 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
50457 
50458 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
50459 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
50460 /*! FEVTAC12TOE - Force event auto command 12 time out error
50461  */
50462 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
50463 
50464 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
50465 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
50466 /*! FEVTAC12CE - Force event auto command 12 CRC error
50467  */
50468 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
50469 
50470 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
50471 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
50472 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error
50473  */
50474 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
50475 
50476 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
50477 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
50478 /*! FEVTAC12IE - Force event Auto Command 12 index error
50479  */
50480 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
50481 
50482 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
50483 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
50484 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
50485  */
50486 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
50487 
50488 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
50489 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
50490 /*! FEVTCTOE - Force event command time out error
50491  */
50492 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
50493 
50494 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
50495 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
50496 /*! FEVTCCE - Force event command CRC error
50497  */
50498 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
50499 
50500 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
50501 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
50502 /*! FEVTCEBE - Force event command end bit error
50503  */
50504 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
50505 
50506 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
50507 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
50508 /*! FEVTCIE - Force event command index error
50509  */
50510 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
50511 
50512 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
50513 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
50514 /*! FEVTDTOE - Force event data time out error
50515  */
50516 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
50517 
50518 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
50519 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
50520 /*! FEVTDCE - Force event data CRC error
50521  */
50522 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
50523 
50524 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
50525 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
50526 /*! FEVTDEBE - Force event data end bit error
50527  */
50528 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
50529 
50530 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
50531 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
50532 /*! FEVTAC12E - Force event Auto Command 12 error
50533  */
50534 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
50535 
50536 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
50537 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
50538 /*! FEVTTNE - Force tuning error
50539  */
50540 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
50541 
50542 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
50543 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
50544 /*! FEVTDMAE - Force event DMA error
50545  */
50546 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
50547 
50548 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
50549 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
50550 /*! FEVTCINT - Force event card interrupt
50551  */
50552 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
50553 /*! @} */
50554 
50555 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
50556 /*! @{ */
50557 
50558 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
50559 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
50560 /*! ADMAES - ADMA error state (when ADMA error is occurred)
50561  */
50562 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
50563 
50564 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
50565 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
50566 /*! ADMALME - ADMA length mismatch error
50567  *  0b1..Error
50568  *  0b0..No error
50569  */
50570 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
50571 
50572 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
50573 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
50574 /*! ADMADCE - ADMA descriptor error
50575  *  0b1..Error
50576  *  0b0..No error
50577  */
50578 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
50579 /*! @} */
50580 
50581 /*! @name ADMA_SYS_ADDR - ADMA System Address */
50582 /*! @{ */
50583 
50584 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
50585 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
50586 /*! ADS_ADDR - ADMA system address
50587  */
50588 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
50589 /*! @} */
50590 
50591 /*! @name DLL_CTRL - DLL (Delay Line) Control */
50592 /*! @{ */
50593 
50594 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
50595 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
50596 /*! DLL_CTRL_ENABLE - DLL and delay chain
50597  */
50598 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
50599 
50600 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
50601 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
50602 /*! DLL_CTRL_RESET - DLL reset
50603  */
50604 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
50605 
50606 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
50607 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
50608 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
50609  */
50610 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
50611 
50612 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
50613 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
50614 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
50615  */
50616 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
50617 
50618 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
50619 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
50620 /*! DLL_CTRL_GATE_UPDATE - DLL gate update
50621  */
50622 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
50623 
50624 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
50625 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
50626 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
50627  */
50628 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
50629 
50630 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
50631 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
50632 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
50633  */
50634 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
50635 
50636 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
50637 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
50638 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
50639  */
50640 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
50641 
50642 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
50643 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
50644 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
50645  */
50646 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
50647 
50648 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
50649 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
50650 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
50651  */
50652 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
50653 /*! @} */
50654 
50655 /*! @name DLL_STATUS - DLL Status */
50656 /*! @{ */
50657 
50658 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
50659 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
50660 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status
50661  */
50662 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
50663 
50664 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
50665 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
50666 /*! DLL_STS_REF_LOCK - Reference DLL lock status
50667  */
50668 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
50669 
50670 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
50671 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
50672 /*! DLL_STS_SLV_SEL - Slave delay line select status
50673  */
50674 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
50675 
50676 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
50677 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
50678 /*! DLL_STS_REF_SEL - Reference delay line select taps
50679  */
50680 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
50681 /*! @} */
50682 
50683 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
50684 /*! @{ */
50685 
50686 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
50687 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
50688 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
50689  */
50690 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
50691 
50692 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
50693 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
50694 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
50695  */
50696 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
50697 
50698 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
50699 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
50700 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
50701  */
50702 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
50703 
50704 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
50705 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
50706 /*! NXT_ERR - NXT error
50707  */
50708 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
50709 
50710 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
50711 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
50712 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
50713  */
50714 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
50715 
50716 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
50717 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
50718 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
50719  */
50720 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
50721 
50722 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
50723 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
50724 /*! TAP_SEL_PRE - TAP_SEL_PRE
50725  */
50726 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
50727 
50728 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
50729 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
50730 /*! PRE_ERR - PRE error
50731  */
50732 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
50733 /*! @} */
50734 
50735 /*! @name VEND_SPEC - Vendor Specific Register */
50736 /*! @{ */
50737 
50738 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
50739 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
50740 /*! VSELECT - Voltage selection
50741  *  0b1..Change the voltage to low voltage range, around 1.8 V
50742  *  0b0..Change the voltage to high voltage range, around 3.0 V
50743  */
50744 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
50745 
50746 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
50747 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
50748 /*! CONFLICT_CHK_EN - Conflict check enable
50749  *  0b0..Conflict check disable
50750  *  0b1..Conflict check enable
50751  */
50752 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
50753 
50754 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
50755 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
50756 /*! AC12_WR_CHKBUSY_EN - Check busy enable
50757  *  0b0..Do not check busy after auto CMD12 for write data packet
50758  *  0b1..Check busy after auto CMD12 for write data packet
50759  */
50760 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
50761 
50762 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
50763 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
50764 /*! FRC_SDCLK_ON - Force CLK
50765  *  0b0..CLK active or inactive is fully controlled by the hardware.
50766  *  0b1..Force CLK active
50767  */
50768 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
50769 
50770 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
50771 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
50772 /*! CRC_CHK_DIS - CRC Check Disable
50773  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
50774  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
50775  */
50776 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
50777 
50778 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
50779 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
50780 /*! CMD_BYTE_EN - Byte access
50781  *  0b0..Disable
50782  *  0b1..Enable
50783  */
50784 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
50785 /*! @} */
50786 
50787 /*! @name MMC_BOOT - MMC Boot */
50788 /*! @{ */
50789 
50790 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
50791 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
50792 /*! DTOCV_ACK - Boot ACK time out
50793  *  0b0000..SDCLK x 2^14
50794  *  0b0001..SDCLK x 2^15
50795  *  0b0010..SDCLK x 2^16
50796  *  0b0011..SDCLK x 2^17
50797  *  0b0100..SDCLK x 2^18
50798  *  0b0101..SDCLK x 2^19
50799  *  0b0110..SDCLK x 2^20
50800  *  0b0111..SDCLK x 2^21
50801  *  0b1110..SDCLK x 2^28
50802  *  0b1111..SDCLK x 2^29
50803  */
50804 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
50805 
50806 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
50807 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
50808 /*! BOOT_ACK - BOOT ACK
50809  *  0b0..No ack
50810  *  0b1..Ack
50811  */
50812 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
50813 
50814 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
50815 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
50816 /*! BOOT_MODE - Boot mode
50817  *  0b0..Normal boot
50818  *  0b1..Alternative boot
50819  */
50820 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
50821 
50822 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
50823 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
50824 /*! BOOT_EN - Boot enable
50825  *  0b0..Fast boot disable
50826  *  0b1..Fast boot enable
50827  */
50828 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
50829 
50830 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
50831 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
50832 /*! AUTO_SABG_EN - Auto stop at block gap
50833  */
50834 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
50835 
50836 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
50837 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
50838 /*! DISABLE_TIME_OUT - Time out
50839  *  0b0..Enable time out
50840  *  0b1..Disable time out
50841  */
50842 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
50843 
50844 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
50845 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
50846 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
50847  */
50848 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
50849 /*! @} */
50850 
50851 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
50852 /*! @{ */
50853 
50854 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
50855 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
50856 /*! CARD_INT_D3_TEST - Card interrupt detection test
50857  *  0b0..Check the card interrupt only when DATA3 is high.
50858  *  0b1..Check the card interrupt by ignoring the status of DATA3.
50859  */
50860 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
50861 
50862 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
50863 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
50864 /*! TUNING_8bit_EN - Tuning 8bit enable
50865  */
50866 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
50867 
50868 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
50869 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
50870 /*! TUNING_1bit_EN - Tuning 1bit enable
50871  */
50872 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
50873 
50874 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
50875 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
50876 /*! TUNING_CMD_EN - Tuning command enable
50877  *  0b0..Auto tuning circuit does not check the CMD line.
50878  *  0b1..Auto tuning circuit checks the CMD line.
50879  */
50880 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
50881 
50882 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
50883 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
50884 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
50885  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
50886  *  0b0..Disable
50887  */
50888 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
50889 /*! @} */
50890 
50891 /*! @name TUNING_CTRL - Tuning Control */
50892 /*! @{ */
50893 
50894 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0xFFU)
50895 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
50896 /*! TUNING_START_TAP - Tuning start
50897  */
50898 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
50899 
50900 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
50901 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
50902 /*! TUNING_COUNTER - Tuning counter
50903  */
50904 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
50905 
50906 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
50907 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
50908 /*! TUNING_STEP - TUNING_STEP
50909  */
50910 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
50911 
50912 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
50913 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
50914 /*! TUNING_WINDOW - Data window
50915  */
50916 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
50917 
50918 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
50919 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
50920 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable
50921  */
50922 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
50923 /*! @} */
50924 
50925 
50926 /*!
50927  * @}
50928  */ /* end of group USDHC_Register_Masks */
50929 
50930 
50931 /* USDHC - Peripheral instance base addresses */
50932 /** Peripheral USDHC1 base address */
50933 #define USDHC1_BASE                              (0x402C0000u)
50934 /** Peripheral USDHC1 base pointer */
50935 #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
50936 /** Peripheral USDHC2 base address */
50937 #define USDHC2_BASE                              (0x402C4000u)
50938 /** Peripheral USDHC2 base pointer */
50939 #define USDHC2                                   ((USDHC_Type *)USDHC2_BASE)
50940 /** Array initializer of USDHC peripheral base addresses */
50941 #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE, USDHC2_BASE }
50942 /** Array initializer of USDHC peripheral base pointers */
50943 #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1, USDHC2 }
50944 /** Interrupt vectors for the USDHC peripheral type */
50945 #define USDHC_IRQS                               { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
50946 
50947 /*!
50948  * @}
50949  */ /* end of group USDHC_Peripheral_Access_Layer */
50950 
50951 
50952 /* ----------------------------------------------------------------------------
50953    -- WDOG Peripheral Access Layer
50954    ---------------------------------------------------------------------------- */
50955 
50956 /*!
50957  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
50958  * @{
50959  */
50960 
50961 /** WDOG - Register Layout Typedef */
50962 typedef struct {
50963   __IO uint16_t WCR;                               /**< Watchdog Control Register, offset: 0x0 */
50964   __IO uint16_t WSR;                               /**< Watchdog Service Register, offset: 0x2 */
50965   __I  uint16_t WRSR;                              /**< Watchdog Reset Status Register, offset: 0x4 */
50966   __IO uint16_t WICR;                              /**< Watchdog Interrupt Control Register, offset: 0x6 */
50967   __IO uint16_t WMCR;                              /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
50968 } WDOG_Type;
50969 
50970 /* ----------------------------------------------------------------------------
50971    -- WDOG Register Masks
50972    ---------------------------------------------------------------------------- */
50973 
50974 /*!
50975  * @addtogroup WDOG_Register_Masks WDOG Register Masks
50976  * @{
50977  */
50978 
50979 /*! @name WCR - Watchdog Control Register */
50980 /*! @{ */
50981 
50982 #define WDOG_WCR_WDZST_MASK                      (0x1U)
50983 #define WDOG_WCR_WDZST_SHIFT                     (0U)
50984 /*! WDZST - WDZST
50985  *  0b0..Continue timer operation (Default).
50986  *  0b1..Suspend the watchdog timer.
50987  */
50988 #define WDOG_WCR_WDZST(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
50989 
50990 #define WDOG_WCR_WDBG_MASK                       (0x2U)
50991 #define WDOG_WCR_WDBG_SHIFT                      (1U)
50992 /*! WDBG - WDBG
50993  *  0b0..Continue WDOG timer operation (Default).
50994  *  0b1..Suspend the watchdog timer.
50995  */
50996 #define WDOG_WCR_WDBG(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
50997 
50998 #define WDOG_WCR_WDE_MASK                        (0x4U)
50999 #define WDOG_WCR_WDE_SHIFT                       (2U)
51000 /*! WDE - WDE
51001  *  0b0..Disable the Watchdog (Default).
51002  *  0b1..Enable the Watchdog.
51003  */
51004 #define WDOG_WCR_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
51005 
51006 #define WDOG_WCR_WDT_MASK                        (0x8U)
51007 #define WDOG_WCR_WDT_SHIFT                       (3U)
51008 /*! WDT - WDT
51009  *  0b0..No effect on WDOG_B (Default).
51010  *  0b1..Assert WDOG_B upon a Watchdog Time-out event.
51011  */
51012 #define WDOG_WCR_WDT(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
51013 
51014 #define WDOG_WCR_SRS_MASK                        (0x10U)
51015 #define WDOG_WCR_SRS_SHIFT                       (4U)
51016 /*! SRS - SRS
51017  *  0b0..Assert system reset signal.
51018  *  0b1..No effect on the system (Default).
51019  */
51020 #define WDOG_WCR_SRS(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
51021 
51022 #define WDOG_WCR_WDA_MASK                        (0x20U)
51023 #define WDOG_WCR_WDA_SHIFT                       (5U)
51024 /*! WDA - WDA
51025  *  0b0..Assert WDOG_B output.
51026  *  0b1..No effect on system (Default).
51027  */
51028 #define WDOG_WCR_WDA(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
51029 
51030 #define WDOG_WCR_SRE_MASK                        (0x40U)
51031 #define WDOG_WCR_SRE_SHIFT                       (6U)
51032 /*! SRE - software reset extension, an option way to generate software reset
51033  *  0b0..using original way to generate software reset (default)
51034  *  0b1..using new way to generate software reset.
51035  */
51036 #define WDOG_WCR_SRE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
51037 
51038 #define WDOG_WCR_WDW_MASK                        (0x80U)
51039 #define WDOG_WCR_WDW_SHIFT                       (7U)
51040 /*! WDW - WDW
51041  *  0b0..Continue WDOG timer operation (Default).
51042  *  0b1..Suspend WDOG timer operation.
51043  */
51044 #define WDOG_WCR_WDW(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
51045 
51046 #define WDOG_WCR_WT_MASK                         (0xFF00U)
51047 #define WDOG_WCR_WT_SHIFT                        (8U)
51048 /*! WT - WT
51049  *  0b00000000..- 0.5 Seconds (Default).
51050  *  0b00000001..- 1.0 Seconds.
51051  *  0b00000010..- 1.5 Seconds.
51052  *  0b00000011..- 2.0 Seconds.
51053  *  0b11111111..- 128 Seconds.
51054  */
51055 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
51056 /*! @} */
51057 
51058 /*! @name WSR - Watchdog Service Register */
51059 /*! @{ */
51060 
51061 #define WDOG_WSR_WSR_MASK                        (0xFFFFU)
51062 #define WDOG_WSR_WSR_SHIFT                       (0U)
51063 /*! WSR - WSR
51064  *  0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
51065  *  0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
51066  */
51067 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
51068 /*! @} */
51069 
51070 /*! @name WRSR - Watchdog Reset Status Register */
51071 /*! @{ */
51072 
51073 #define WDOG_WRSR_SFTW_MASK                      (0x1U)
51074 #define WDOG_WRSR_SFTW_SHIFT                     (0U)
51075 /*! SFTW - SFTW
51076  *  0b0..Reset is not the result of a software reset.
51077  *  0b1..Reset is the result of a software reset.
51078  */
51079 #define WDOG_WRSR_SFTW(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
51080 
51081 #define WDOG_WRSR_TOUT_MASK                      (0x2U)
51082 #define WDOG_WRSR_TOUT_SHIFT                     (1U)
51083 /*! TOUT - TOUT
51084  *  0b0..Reset is not the result of a WDOG timeout.
51085  *  0b1..Reset is the result of a WDOG timeout.
51086  */
51087 #define WDOG_WRSR_TOUT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
51088 
51089 #define WDOG_WRSR_POR_MASK                       (0x10U)
51090 #define WDOG_WRSR_POR_SHIFT                      (4U)
51091 /*! POR - POR
51092  *  0b0..Reset is not the result of a power on reset.
51093  *  0b1..Reset is the result of a power on reset.
51094  */
51095 #define WDOG_WRSR_POR(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
51096 /*! @} */
51097 
51098 /*! @name WICR - Watchdog Interrupt Control Register */
51099 /*! @{ */
51100 
51101 #define WDOG_WICR_WICT_MASK                      (0xFFU)
51102 #define WDOG_WICR_WICT_SHIFT                     (0U)
51103 /*! WICT - WICT
51104  *  0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
51105  *  0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
51106  *  0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
51107  *  0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
51108  */
51109 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
51110 
51111 #define WDOG_WICR_WTIS_MASK                      (0x4000U)
51112 #define WDOG_WICR_WTIS_SHIFT                     (14U)
51113 /*! WTIS - WTIS
51114  *  0b0..No interrupt has occurred (Default).
51115  *  0b1..Interrupt has occurred
51116  */
51117 #define WDOG_WICR_WTIS(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
51118 
51119 #define WDOG_WICR_WIE_MASK                       (0x8000U)
51120 #define WDOG_WICR_WIE_SHIFT                      (15U)
51121 /*! WIE - WIE
51122  *  0b0..Disable Interrupt (Default).
51123  *  0b1..Enable Interrupt.
51124  */
51125 #define WDOG_WICR_WIE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
51126 /*! @} */
51127 
51128 /*! @name WMCR - Watchdog Miscellaneous Control Register */
51129 /*! @{ */
51130 
51131 #define WDOG_WMCR_PDE_MASK                       (0x1U)
51132 #define WDOG_WMCR_PDE_SHIFT                      (0U)
51133 /*! PDE - PDE
51134  *  0b0..Power Down Counter of WDOG is disabled.
51135  *  0b1..Power Down Counter of WDOG is enabled (Default).
51136  */
51137 #define WDOG_WMCR_PDE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
51138 /*! @} */
51139 
51140 
51141 /*!
51142  * @}
51143  */ /* end of group WDOG_Register_Masks */
51144 
51145 
51146 /* WDOG - Peripheral instance base addresses */
51147 /** Peripheral WDOG1 base address */
51148 #define WDOG1_BASE                               (0x400B8000u)
51149 /** Peripheral WDOG1 base pointer */
51150 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
51151 /** Peripheral WDOG2 base address */
51152 #define WDOG2_BASE                               (0x400D0000u)
51153 /** Peripheral WDOG2 base pointer */
51154 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
51155 /** Array initializer of WDOG peripheral base addresses */
51156 #define WDOG_BASE_ADDRS                          { 0u, WDOG1_BASE, WDOG2_BASE }
51157 /** Array initializer of WDOG peripheral base pointers */
51158 #define WDOG_BASE_PTRS                           { (WDOG_Type *)0u, WDOG1, WDOG2 }
51159 /** Interrupt vectors for the WDOG peripheral type */
51160 #define WDOG_IRQS                                { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
51161 
51162 /*!
51163  * @}
51164  */ /* end of group WDOG_Peripheral_Access_Layer */
51165 
51166 
51167 /* ----------------------------------------------------------------------------
51168    -- XBARA Peripheral Access Layer
51169    ---------------------------------------------------------------------------- */
51170 
51171 /*!
51172  * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
51173  * @{
51174  */
51175 
51176 /** XBARA - Register Layout Typedef */
51177 typedef struct {
51178   __IO uint16_t SEL0;                              /**< Crossbar A Select Register 0, offset: 0x0 */
51179   __IO uint16_t SEL1;                              /**< Crossbar A Select Register 1, offset: 0x2 */
51180   __IO uint16_t SEL2;                              /**< Crossbar A Select Register 2, offset: 0x4 */
51181   __IO uint16_t SEL3;                              /**< Crossbar A Select Register 3, offset: 0x6 */
51182   __IO uint16_t SEL4;                              /**< Crossbar A Select Register 4, offset: 0x8 */
51183   __IO uint16_t SEL5;                              /**< Crossbar A Select Register 5, offset: 0xA */
51184   __IO uint16_t SEL6;                              /**< Crossbar A Select Register 6, offset: 0xC */
51185   __IO uint16_t SEL7;                              /**< Crossbar A Select Register 7, offset: 0xE */
51186   __IO uint16_t SEL8;                              /**< Crossbar A Select Register 8, offset: 0x10 */
51187   __IO uint16_t SEL9;                              /**< Crossbar A Select Register 9, offset: 0x12 */
51188   __IO uint16_t SEL10;                             /**< Crossbar A Select Register 10, offset: 0x14 */
51189   __IO uint16_t SEL11;                             /**< Crossbar A Select Register 11, offset: 0x16 */
51190   __IO uint16_t SEL12;                             /**< Crossbar A Select Register 12, offset: 0x18 */
51191   __IO uint16_t SEL13;                             /**< Crossbar A Select Register 13, offset: 0x1A */
51192   __IO uint16_t SEL14;                             /**< Crossbar A Select Register 14, offset: 0x1C */
51193   __IO uint16_t SEL15;                             /**< Crossbar A Select Register 15, offset: 0x1E */
51194   __IO uint16_t SEL16;                             /**< Crossbar A Select Register 16, offset: 0x20 */
51195   __IO uint16_t SEL17;                             /**< Crossbar A Select Register 17, offset: 0x22 */
51196   __IO uint16_t SEL18;                             /**< Crossbar A Select Register 18, offset: 0x24 */
51197   __IO uint16_t SEL19;                             /**< Crossbar A Select Register 19, offset: 0x26 */
51198   __IO uint16_t SEL20;                             /**< Crossbar A Select Register 20, offset: 0x28 */
51199   __IO uint16_t SEL21;                             /**< Crossbar A Select Register 21, offset: 0x2A */
51200   __IO uint16_t SEL22;                             /**< Crossbar A Select Register 22, offset: 0x2C */
51201   __IO uint16_t SEL23;                             /**< Crossbar A Select Register 23, offset: 0x2E */
51202   __IO uint16_t SEL24;                             /**< Crossbar A Select Register 24, offset: 0x30 */
51203   __IO uint16_t SEL25;                             /**< Crossbar A Select Register 25, offset: 0x32 */
51204   __IO uint16_t SEL26;                             /**< Crossbar A Select Register 26, offset: 0x34 */
51205   __IO uint16_t SEL27;                             /**< Crossbar A Select Register 27, offset: 0x36 */
51206   __IO uint16_t SEL28;                             /**< Crossbar A Select Register 28, offset: 0x38 */
51207   __IO uint16_t SEL29;                             /**< Crossbar A Select Register 29, offset: 0x3A */
51208   __IO uint16_t SEL30;                             /**< Crossbar A Select Register 30, offset: 0x3C */
51209   __IO uint16_t SEL31;                             /**< Crossbar A Select Register 31, offset: 0x3E */
51210   __IO uint16_t SEL32;                             /**< Crossbar A Select Register 32, offset: 0x40 */
51211   __IO uint16_t SEL33;                             /**< Crossbar A Select Register 33, offset: 0x42 */
51212   __IO uint16_t SEL34;                             /**< Crossbar A Select Register 34, offset: 0x44 */
51213   __IO uint16_t SEL35;                             /**< Crossbar A Select Register 35, offset: 0x46 */
51214   __IO uint16_t SEL36;                             /**< Crossbar A Select Register 36, offset: 0x48 */
51215   __IO uint16_t SEL37;                             /**< Crossbar A Select Register 37, offset: 0x4A */
51216   __IO uint16_t SEL38;                             /**< Crossbar A Select Register 38, offset: 0x4C */
51217   __IO uint16_t SEL39;                             /**< Crossbar A Select Register 39, offset: 0x4E */
51218   __IO uint16_t SEL40;                             /**< Crossbar A Select Register 40, offset: 0x50 */
51219   __IO uint16_t SEL41;                             /**< Crossbar A Select Register 41, offset: 0x52 */
51220   __IO uint16_t SEL42;                             /**< Crossbar A Select Register 42, offset: 0x54 */
51221   __IO uint16_t SEL43;                             /**< Crossbar A Select Register 43, offset: 0x56 */
51222   __IO uint16_t SEL44;                             /**< Crossbar A Select Register 44, offset: 0x58 */
51223   __IO uint16_t SEL45;                             /**< Crossbar A Select Register 45, offset: 0x5A */
51224   __IO uint16_t SEL46;                             /**< Crossbar A Select Register 46, offset: 0x5C */
51225   __IO uint16_t SEL47;                             /**< Crossbar A Select Register 47, offset: 0x5E */
51226   __IO uint16_t SEL48;                             /**< Crossbar A Select Register 48, offset: 0x60 */
51227   __IO uint16_t SEL49;                             /**< Crossbar A Select Register 49, offset: 0x62 */
51228   __IO uint16_t SEL50;                             /**< Crossbar A Select Register 50, offset: 0x64 */
51229   __IO uint16_t SEL51;                             /**< Crossbar A Select Register 51, offset: 0x66 */
51230   __IO uint16_t SEL52;                             /**< Crossbar A Select Register 52, offset: 0x68 */
51231   __IO uint16_t SEL53;                             /**< Crossbar A Select Register 53, offset: 0x6A */
51232   __IO uint16_t SEL54;                             /**< Crossbar A Select Register 54, offset: 0x6C */
51233   __IO uint16_t SEL55;                             /**< Crossbar A Select Register 55, offset: 0x6E */
51234   __IO uint16_t SEL56;                             /**< Crossbar A Select Register 56, offset: 0x70 */
51235   __IO uint16_t SEL57;                             /**< Crossbar A Select Register 57, offset: 0x72 */
51236   __IO uint16_t SEL58;                             /**< Crossbar A Select Register 58, offset: 0x74 */
51237   __IO uint16_t SEL59;                             /**< Crossbar A Select Register 59, offset: 0x76 */
51238   __IO uint16_t SEL60;                             /**< Crossbar A Select Register 60, offset: 0x78 */
51239   __IO uint16_t SEL61;                             /**< Crossbar A Select Register 61, offset: 0x7A */
51240   __IO uint16_t SEL62;                             /**< Crossbar A Select Register 62, offset: 0x7C */
51241   __IO uint16_t SEL63;                             /**< Crossbar A Select Register 63, offset: 0x7E */
51242   __IO uint16_t SEL64;                             /**< Crossbar A Select Register 64, offset: 0x80 */
51243   __IO uint16_t SEL65;                             /**< Crossbar A Select Register 65, offset: 0x82 */
51244   __IO uint16_t CTRL0;                             /**< Crossbar A Control Register 0, offset: 0x84 */
51245   __IO uint16_t CTRL1;                             /**< Crossbar A Control Register 1, offset: 0x86 */
51246 } XBARA_Type;
51247 
51248 /* ----------------------------------------------------------------------------
51249    -- XBARA Register Masks
51250    ---------------------------------------------------------------------------- */
51251 
51252 /*!
51253  * @addtogroup XBARA_Register_Masks XBARA Register Masks
51254  * @{
51255  */
51256 
51257 /*! @name SEL0 - Crossbar A Select Register 0 */
51258 /*! @{ */
51259 
51260 #define XBARA_SEL0_SEL0_MASK                     (0x7FU)
51261 #define XBARA_SEL0_SEL0_SHIFT                    (0U)
51262 #define XBARA_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
51263 
51264 #define XBARA_SEL0_SEL1_MASK                     (0x7F00U)
51265 #define XBARA_SEL0_SEL1_SHIFT                    (8U)
51266 #define XBARA_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
51267 /*! @} */
51268 
51269 /*! @name SEL1 - Crossbar A Select Register 1 */
51270 /*! @{ */
51271 
51272 #define XBARA_SEL1_SEL2_MASK                     (0x7FU)
51273 #define XBARA_SEL1_SEL2_SHIFT                    (0U)
51274 #define XBARA_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
51275 
51276 #define XBARA_SEL1_SEL3_MASK                     (0x7F00U)
51277 #define XBARA_SEL1_SEL3_SHIFT                    (8U)
51278 #define XBARA_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
51279 /*! @} */
51280 
51281 /*! @name SEL2 - Crossbar A Select Register 2 */
51282 /*! @{ */
51283 
51284 #define XBARA_SEL2_SEL4_MASK                     (0x7FU)
51285 #define XBARA_SEL2_SEL4_SHIFT                    (0U)
51286 #define XBARA_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
51287 
51288 #define XBARA_SEL2_SEL5_MASK                     (0x7F00U)
51289 #define XBARA_SEL2_SEL5_SHIFT                    (8U)
51290 #define XBARA_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
51291 /*! @} */
51292 
51293 /*! @name SEL3 - Crossbar A Select Register 3 */
51294 /*! @{ */
51295 
51296 #define XBARA_SEL3_SEL6_MASK                     (0x7FU)
51297 #define XBARA_SEL3_SEL6_SHIFT                    (0U)
51298 #define XBARA_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
51299 
51300 #define XBARA_SEL3_SEL7_MASK                     (0x7F00U)
51301 #define XBARA_SEL3_SEL7_SHIFT                    (8U)
51302 #define XBARA_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
51303 /*! @} */
51304 
51305 /*! @name SEL4 - Crossbar A Select Register 4 */
51306 /*! @{ */
51307 
51308 #define XBARA_SEL4_SEL8_MASK                     (0x7FU)
51309 #define XBARA_SEL4_SEL8_SHIFT                    (0U)
51310 #define XBARA_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
51311 
51312 #define XBARA_SEL4_SEL9_MASK                     (0x7F00U)
51313 #define XBARA_SEL4_SEL9_SHIFT                    (8U)
51314 #define XBARA_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
51315 /*! @} */
51316 
51317 /*! @name SEL5 - Crossbar A Select Register 5 */
51318 /*! @{ */
51319 
51320 #define XBARA_SEL5_SEL10_MASK                    (0x7FU)
51321 #define XBARA_SEL5_SEL10_SHIFT                   (0U)
51322 #define XBARA_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
51323 
51324 #define XBARA_SEL5_SEL11_MASK                    (0x7F00U)
51325 #define XBARA_SEL5_SEL11_SHIFT                   (8U)
51326 #define XBARA_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
51327 /*! @} */
51328 
51329 /*! @name SEL6 - Crossbar A Select Register 6 */
51330 /*! @{ */
51331 
51332 #define XBARA_SEL6_SEL12_MASK                    (0x7FU)
51333 #define XBARA_SEL6_SEL12_SHIFT                   (0U)
51334 #define XBARA_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
51335 
51336 #define XBARA_SEL6_SEL13_MASK                    (0x7F00U)
51337 #define XBARA_SEL6_SEL13_SHIFT                   (8U)
51338 #define XBARA_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
51339 /*! @} */
51340 
51341 /*! @name SEL7 - Crossbar A Select Register 7 */
51342 /*! @{ */
51343 
51344 #define XBARA_SEL7_SEL14_MASK                    (0x7FU)
51345 #define XBARA_SEL7_SEL14_SHIFT                   (0U)
51346 #define XBARA_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
51347 
51348 #define XBARA_SEL7_SEL15_MASK                    (0x7F00U)
51349 #define XBARA_SEL7_SEL15_SHIFT                   (8U)
51350 #define XBARA_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
51351 /*! @} */
51352 
51353 /*! @name SEL8 - Crossbar A Select Register 8 */
51354 /*! @{ */
51355 
51356 #define XBARA_SEL8_SEL16_MASK                    (0x7FU)
51357 #define XBARA_SEL8_SEL16_SHIFT                   (0U)
51358 #define XBARA_SEL8_SEL16(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
51359 
51360 #define XBARA_SEL8_SEL17_MASK                    (0x7F00U)
51361 #define XBARA_SEL8_SEL17_SHIFT                   (8U)
51362 #define XBARA_SEL8_SEL17(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
51363 /*! @} */
51364 
51365 /*! @name SEL9 - Crossbar A Select Register 9 */
51366 /*! @{ */
51367 
51368 #define XBARA_SEL9_SEL18_MASK                    (0x7FU)
51369 #define XBARA_SEL9_SEL18_SHIFT                   (0U)
51370 #define XBARA_SEL9_SEL18(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
51371 
51372 #define XBARA_SEL9_SEL19_MASK                    (0x7F00U)
51373 #define XBARA_SEL9_SEL19_SHIFT                   (8U)
51374 #define XBARA_SEL9_SEL19(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
51375 /*! @} */
51376 
51377 /*! @name SEL10 - Crossbar A Select Register 10 */
51378 /*! @{ */
51379 
51380 #define XBARA_SEL10_SEL20_MASK                   (0x7FU)
51381 #define XBARA_SEL10_SEL20_SHIFT                  (0U)
51382 #define XBARA_SEL10_SEL20(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
51383 
51384 #define XBARA_SEL10_SEL21_MASK                   (0x7F00U)
51385 #define XBARA_SEL10_SEL21_SHIFT                  (8U)
51386 #define XBARA_SEL10_SEL21(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
51387 /*! @} */
51388 
51389 /*! @name SEL11 - Crossbar A Select Register 11 */
51390 /*! @{ */
51391 
51392 #define XBARA_SEL11_SEL22_MASK                   (0x7FU)
51393 #define XBARA_SEL11_SEL22_SHIFT                  (0U)
51394 #define XBARA_SEL11_SEL22(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
51395 
51396 #define XBARA_SEL11_SEL23_MASK                   (0x7F00U)
51397 #define XBARA_SEL11_SEL23_SHIFT                  (8U)
51398 #define XBARA_SEL11_SEL23(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
51399 /*! @} */
51400 
51401 /*! @name SEL12 - Crossbar A Select Register 12 */
51402 /*! @{ */
51403 
51404 #define XBARA_SEL12_SEL24_MASK                   (0x7FU)
51405 #define XBARA_SEL12_SEL24_SHIFT                  (0U)
51406 #define XBARA_SEL12_SEL24(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
51407 
51408 #define XBARA_SEL12_SEL25_MASK                   (0x7F00U)
51409 #define XBARA_SEL12_SEL25_SHIFT                  (8U)
51410 #define XBARA_SEL12_SEL25(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
51411 /*! @} */
51412 
51413 /*! @name SEL13 - Crossbar A Select Register 13 */
51414 /*! @{ */
51415 
51416 #define XBARA_SEL13_SEL26_MASK                   (0x7FU)
51417 #define XBARA_SEL13_SEL26_SHIFT                  (0U)
51418 #define XBARA_SEL13_SEL26(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
51419 
51420 #define XBARA_SEL13_SEL27_MASK                   (0x7F00U)
51421 #define XBARA_SEL13_SEL27_SHIFT                  (8U)
51422 #define XBARA_SEL13_SEL27(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
51423 /*! @} */
51424 
51425 /*! @name SEL14 - Crossbar A Select Register 14 */
51426 /*! @{ */
51427 
51428 #define XBARA_SEL14_SEL28_MASK                   (0x7FU)
51429 #define XBARA_SEL14_SEL28_SHIFT                  (0U)
51430 #define XBARA_SEL14_SEL28(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
51431 
51432 #define XBARA_SEL14_SEL29_MASK                   (0x7F00U)
51433 #define XBARA_SEL14_SEL29_SHIFT                  (8U)
51434 #define XBARA_SEL14_SEL29(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
51435 /*! @} */
51436 
51437 /*! @name SEL15 - Crossbar A Select Register 15 */
51438 /*! @{ */
51439 
51440 #define XBARA_SEL15_SEL30_MASK                   (0x7FU)
51441 #define XBARA_SEL15_SEL30_SHIFT                  (0U)
51442 #define XBARA_SEL15_SEL30(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
51443 
51444 #define XBARA_SEL15_SEL31_MASK                   (0x7F00U)
51445 #define XBARA_SEL15_SEL31_SHIFT                  (8U)
51446 #define XBARA_SEL15_SEL31(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
51447 /*! @} */
51448 
51449 /*! @name SEL16 - Crossbar A Select Register 16 */
51450 /*! @{ */
51451 
51452 #define XBARA_SEL16_SEL32_MASK                   (0x7FU)
51453 #define XBARA_SEL16_SEL32_SHIFT                  (0U)
51454 #define XBARA_SEL16_SEL32(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
51455 
51456 #define XBARA_SEL16_SEL33_MASK                   (0x7F00U)
51457 #define XBARA_SEL16_SEL33_SHIFT                  (8U)
51458 #define XBARA_SEL16_SEL33(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
51459 /*! @} */
51460 
51461 /*! @name SEL17 - Crossbar A Select Register 17 */
51462 /*! @{ */
51463 
51464 #define XBARA_SEL17_SEL34_MASK                   (0x7FU)
51465 #define XBARA_SEL17_SEL34_SHIFT                  (0U)
51466 #define XBARA_SEL17_SEL34(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
51467 
51468 #define XBARA_SEL17_SEL35_MASK                   (0x7F00U)
51469 #define XBARA_SEL17_SEL35_SHIFT                  (8U)
51470 #define XBARA_SEL17_SEL35(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
51471 /*! @} */
51472 
51473 /*! @name SEL18 - Crossbar A Select Register 18 */
51474 /*! @{ */
51475 
51476 #define XBARA_SEL18_SEL36_MASK                   (0x7FU)
51477 #define XBARA_SEL18_SEL36_SHIFT                  (0U)
51478 #define XBARA_SEL18_SEL36(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
51479 
51480 #define XBARA_SEL18_SEL37_MASK                   (0x7F00U)
51481 #define XBARA_SEL18_SEL37_SHIFT                  (8U)
51482 #define XBARA_SEL18_SEL37(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
51483 /*! @} */
51484 
51485 /*! @name SEL19 - Crossbar A Select Register 19 */
51486 /*! @{ */
51487 
51488 #define XBARA_SEL19_SEL38_MASK                   (0x7FU)
51489 #define XBARA_SEL19_SEL38_SHIFT                  (0U)
51490 #define XBARA_SEL19_SEL38(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
51491 
51492 #define XBARA_SEL19_SEL39_MASK                   (0x7F00U)
51493 #define XBARA_SEL19_SEL39_SHIFT                  (8U)
51494 #define XBARA_SEL19_SEL39(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
51495 /*! @} */
51496 
51497 /*! @name SEL20 - Crossbar A Select Register 20 */
51498 /*! @{ */
51499 
51500 #define XBARA_SEL20_SEL40_MASK                   (0x7FU)
51501 #define XBARA_SEL20_SEL40_SHIFT                  (0U)
51502 #define XBARA_SEL20_SEL40(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
51503 
51504 #define XBARA_SEL20_SEL41_MASK                   (0x7F00U)
51505 #define XBARA_SEL20_SEL41_SHIFT                  (8U)
51506 #define XBARA_SEL20_SEL41(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
51507 /*! @} */
51508 
51509 /*! @name SEL21 - Crossbar A Select Register 21 */
51510 /*! @{ */
51511 
51512 #define XBARA_SEL21_SEL42_MASK                   (0x7FU)
51513 #define XBARA_SEL21_SEL42_SHIFT                  (0U)
51514 #define XBARA_SEL21_SEL42(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
51515 
51516 #define XBARA_SEL21_SEL43_MASK                   (0x7F00U)
51517 #define XBARA_SEL21_SEL43_SHIFT                  (8U)
51518 #define XBARA_SEL21_SEL43(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
51519 /*! @} */
51520 
51521 /*! @name SEL22 - Crossbar A Select Register 22 */
51522 /*! @{ */
51523 
51524 #define XBARA_SEL22_SEL44_MASK                   (0x7FU)
51525 #define XBARA_SEL22_SEL44_SHIFT                  (0U)
51526 #define XBARA_SEL22_SEL44(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
51527 
51528 #define XBARA_SEL22_SEL45_MASK                   (0x7F00U)
51529 #define XBARA_SEL22_SEL45_SHIFT                  (8U)
51530 #define XBARA_SEL22_SEL45(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
51531 /*! @} */
51532 
51533 /*! @name SEL23 - Crossbar A Select Register 23 */
51534 /*! @{ */
51535 
51536 #define XBARA_SEL23_SEL46_MASK                   (0x7FU)
51537 #define XBARA_SEL23_SEL46_SHIFT                  (0U)
51538 #define XBARA_SEL23_SEL46(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
51539 
51540 #define XBARA_SEL23_SEL47_MASK                   (0x7F00U)
51541 #define XBARA_SEL23_SEL47_SHIFT                  (8U)
51542 #define XBARA_SEL23_SEL47(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
51543 /*! @} */
51544 
51545 /*! @name SEL24 - Crossbar A Select Register 24 */
51546 /*! @{ */
51547 
51548 #define XBARA_SEL24_SEL48_MASK                   (0x7FU)
51549 #define XBARA_SEL24_SEL48_SHIFT                  (0U)
51550 #define XBARA_SEL24_SEL48(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
51551 
51552 #define XBARA_SEL24_SEL49_MASK                   (0x7F00U)
51553 #define XBARA_SEL24_SEL49_SHIFT                  (8U)
51554 #define XBARA_SEL24_SEL49(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
51555 /*! @} */
51556 
51557 /*! @name SEL25 - Crossbar A Select Register 25 */
51558 /*! @{ */
51559 
51560 #define XBARA_SEL25_SEL50_MASK                   (0x7FU)
51561 #define XBARA_SEL25_SEL50_SHIFT                  (0U)
51562 #define XBARA_SEL25_SEL50(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
51563 
51564 #define XBARA_SEL25_SEL51_MASK                   (0x7F00U)
51565 #define XBARA_SEL25_SEL51_SHIFT                  (8U)
51566 #define XBARA_SEL25_SEL51(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
51567 /*! @} */
51568 
51569 /*! @name SEL26 - Crossbar A Select Register 26 */
51570 /*! @{ */
51571 
51572 #define XBARA_SEL26_SEL52_MASK                   (0x7FU)
51573 #define XBARA_SEL26_SEL52_SHIFT                  (0U)
51574 #define XBARA_SEL26_SEL52(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
51575 
51576 #define XBARA_SEL26_SEL53_MASK                   (0x7F00U)
51577 #define XBARA_SEL26_SEL53_SHIFT                  (8U)
51578 #define XBARA_SEL26_SEL53(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
51579 /*! @} */
51580 
51581 /*! @name SEL27 - Crossbar A Select Register 27 */
51582 /*! @{ */
51583 
51584 #define XBARA_SEL27_SEL54_MASK                   (0x7FU)
51585 #define XBARA_SEL27_SEL54_SHIFT                  (0U)
51586 #define XBARA_SEL27_SEL54(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
51587 
51588 #define XBARA_SEL27_SEL55_MASK                   (0x7F00U)
51589 #define XBARA_SEL27_SEL55_SHIFT                  (8U)
51590 #define XBARA_SEL27_SEL55(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
51591 /*! @} */
51592 
51593 /*! @name SEL28 - Crossbar A Select Register 28 */
51594 /*! @{ */
51595 
51596 #define XBARA_SEL28_SEL56_MASK                   (0x7FU)
51597 #define XBARA_SEL28_SEL56_SHIFT                  (0U)
51598 #define XBARA_SEL28_SEL56(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
51599 
51600 #define XBARA_SEL28_SEL57_MASK                   (0x7F00U)
51601 #define XBARA_SEL28_SEL57_SHIFT                  (8U)
51602 #define XBARA_SEL28_SEL57(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
51603 /*! @} */
51604 
51605 /*! @name SEL29 - Crossbar A Select Register 29 */
51606 /*! @{ */
51607 
51608 #define XBARA_SEL29_SEL58_MASK                   (0x7FU)
51609 #define XBARA_SEL29_SEL58_SHIFT                  (0U)
51610 #define XBARA_SEL29_SEL58(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
51611 
51612 #define XBARA_SEL29_SEL59_MASK                   (0x7F00U)
51613 #define XBARA_SEL29_SEL59_SHIFT                  (8U)
51614 #define XBARA_SEL29_SEL59(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
51615 /*! @} */
51616 
51617 /*! @name SEL30 - Crossbar A Select Register 30 */
51618 /*! @{ */
51619 
51620 #define XBARA_SEL30_SEL60_MASK                   (0x7FU)
51621 #define XBARA_SEL30_SEL60_SHIFT                  (0U)
51622 #define XBARA_SEL30_SEL60(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
51623 
51624 #define XBARA_SEL30_SEL61_MASK                   (0x7F00U)
51625 #define XBARA_SEL30_SEL61_SHIFT                  (8U)
51626 #define XBARA_SEL30_SEL61(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
51627 /*! @} */
51628 
51629 /*! @name SEL31 - Crossbar A Select Register 31 */
51630 /*! @{ */
51631 
51632 #define XBARA_SEL31_SEL62_MASK                   (0x7FU)
51633 #define XBARA_SEL31_SEL62_SHIFT                  (0U)
51634 #define XBARA_SEL31_SEL62(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
51635 
51636 #define XBARA_SEL31_SEL63_MASK                   (0x7F00U)
51637 #define XBARA_SEL31_SEL63_SHIFT                  (8U)
51638 #define XBARA_SEL31_SEL63(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
51639 /*! @} */
51640 
51641 /*! @name SEL32 - Crossbar A Select Register 32 */
51642 /*! @{ */
51643 
51644 #define XBARA_SEL32_SEL64_MASK                   (0x7FU)
51645 #define XBARA_SEL32_SEL64_SHIFT                  (0U)
51646 #define XBARA_SEL32_SEL64(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
51647 
51648 #define XBARA_SEL32_SEL65_MASK                   (0x7F00U)
51649 #define XBARA_SEL32_SEL65_SHIFT                  (8U)
51650 #define XBARA_SEL32_SEL65(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
51651 /*! @} */
51652 
51653 /*! @name SEL33 - Crossbar A Select Register 33 */
51654 /*! @{ */
51655 
51656 #define XBARA_SEL33_SEL66_MASK                   (0x7FU)
51657 #define XBARA_SEL33_SEL66_SHIFT                  (0U)
51658 #define XBARA_SEL33_SEL66(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
51659 
51660 #define XBARA_SEL33_SEL67_MASK                   (0x7F00U)
51661 #define XBARA_SEL33_SEL67_SHIFT                  (8U)
51662 #define XBARA_SEL33_SEL67(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
51663 /*! @} */
51664 
51665 /*! @name SEL34 - Crossbar A Select Register 34 */
51666 /*! @{ */
51667 
51668 #define XBARA_SEL34_SEL68_MASK                   (0x7FU)
51669 #define XBARA_SEL34_SEL68_SHIFT                  (0U)
51670 #define XBARA_SEL34_SEL68(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
51671 
51672 #define XBARA_SEL34_SEL69_MASK                   (0x7F00U)
51673 #define XBARA_SEL34_SEL69_SHIFT                  (8U)
51674 #define XBARA_SEL34_SEL69(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
51675 /*! @} */
51676 
51677 /*! @name SEL35 - Crossbar A Select Register 35 */
51678 /*! @{ */
51679 
51680 #define XBARA_SEL35_SEL70_MASK                   (0x7FU)
51681 #define XBARA_SEL35_SEL70_SHIFT                  (0U)
51682 #define XBARA_SEL35_SEL70(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
51683 
51684 #define XBARA_SEL35_SEL71_MASK                   (0x7F00U)
51685 #define XBARA_SEL35_SEL71_SHIFT                  (8U)
51686 #define XBARA_SEL35_SEL71(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
51687 /*! @} */
51688 
51689 /*! @name SEL36 - Crossbar A Select Register 36 */
51690 /*! @{ */
51691 
51692 #define XBARA_SEL36_SEL72_MASK                   (0x7FU)
51693 #define XBARA_SEL36_SEL72_SHIFT                  (0U)
51694 #define XBARA_SEL36_SEL72(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
51695 
51696 #define XBARA_SEL36_SEL73_MASK                   (0x7F00U)
51697 #define XBARA_SEL36_SEL73_SHIFT                  (8U)
51698 #define XBARA_SEL36_SEL73(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
51699 /*! @} */
51700 
51701 /*! @name SEL37 - Crossbar A Select Register 37 */
51702 /*! @{ */
51703 
51704 #define XBARA_SEL37_SEL74_MASK                   (0x7FU)
51705 #define XBARA_SEL37_SEL74_SHIFT                  (0U)
51706 #define XBARA_SEL37_SEL74(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
51707 
51708 #define XBARA_SEL37_SEL75_MASK                   (0x7F00U)
51709 #define XBARA_SEL37_SEL75_SHIFT                  (8U)
51710 #define XBARA_SEL37_SEL75(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
51711 /*! @} */
51712 
51713 /*! @name SEL38 - Crossbar A Select Register 38 */
51714 /*! @{ */
51715 
51716 #define XBARA_SEL38_SEL76_MASK                   (0x7FU)
51717 #define XBARA_SEL38_SEL76_SHIFT                  (0U)
51718 #define XBARA_SEL38_SEL76(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
51719 
51720 #define XBARA_SEL38_SEL77_MASK                   (0x7F00U)
51721 #define XBARA_SEL38_SEL77_SHIFT                  (8U)
51722 #define XBARA_SEL38_SEL77(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
51723 /*! @} */
51724 
51725 /*! @name SEL39 - Crossbar A Select Register 39 */
51726 /*! @{ */
51727 
51728 #define XBARA_SEL39_SEL78_MASK                   (0x7FU)
51729 #define XBARA_SEL39_SEL78_SHIFT                  (0U)
51730 #define XBARA_SEL39_SEL78(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
51731 
51732 #define XBARA_SEL39_SEL79_MASK                   (0x7F00U)
51733 #define XBARA_SEL39_SEL79_SHIFT                  (8U)
51734 #define XBARA_SEL39_SEL79(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
51735 /*! @} */
51736 
51737 /*! @name SEL40 - Crossbar A Select Register 40 */
51738 /*! @{ */
51739 
51740 #define XBARA_SEL40_SEL80_MASK                   (0x7FU)
51741 #define XBARA_SEL40_SEL80_SHIFT                  (0U)
51742 #define XBARA_SEL40_SEL80(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
51743 
51744 #define XBARA_SEL40_SEL81_MASK                   (0x7F00U)
51745 #define XBARA_SEL40_SEL81_SHIFT                  (8U)
51746 #define XBARA_SEL40_SEL81(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
51747 /*! @} */
51748 
51749 /*! @name SEL41 - Crossbar A Select Register 41 */
51750 /*! @{ */
51751 
51752 #define XBARA_SEL41_SEL82_MASK                   (0x7FU)
51753 #define XBARA_SEL41_SEL82_SHIFT                  (0U)
51754 #define XBARA_SEL41_SEL82(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
51755 
51756 #define XBARA_SEL41_SEL83_MASK                   (0x7F00U)
51757 #define XBARA_SEL41_SEL83_SHIFT                  (8U)
51758 #define XBARA_SEL41_SEL83(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
51759 /*! @} */
51760 
51761 /*! @name SEL42 - Crossbar A Select Register 42 */
51762 /*! @{ */
51763 
51764 #define XBARA_SEL42_SEL84_MASK                   (0x7FU)
51765 #define XBARA_SEL42_SEL84_SHIFT                  (0U)
51766 #define XBARA_SEL42_SEL84(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
51767 
51768 #define XBARA_SEL42_SEL85_MASK                   (0x7F00U)
51769 #define XBARA_SEL42_SEL85_SHIFT                  (8U)
51770 #define XBARA_SEL42_SEL85(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
51771 /*! @} */
51772 
51773 /*! @name SEL43 - Crossbar A Select Register 43 */
51774 /*! @{ */
51775 
51776 #define XBARA_SEL43_SEL86_MASK                   (0x7FU)
51777 #define XBARA_SEL43_SEL86_SHIFT                  (0U)
51778 #define XBARA_SEL43_SEL86(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
51779 
51780 #define XBARA_SEL43_SEL87_MASK                   (0x7F00U)
51781 #define XBARA_SEL43_SEL87_SHIFT                  (8U)
51782 #define XBARA_SEL43_SEL87(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
51783 /*! @} */
51784 
51785 /*! @name SEL44 - Crossbar A Select Register 44 */
51786 /*! @{ */
51787 
51788 #define XBARA_SEL44_SEL88_MASK                   (0x7FU)
51789 #define XBARA_SEL44_SEL88_SHIFT                  (0U)
51790 #define XBARA_SEL44_SEL88(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
51791 
51792 #define XBARA_SEL44_SEL89_MASK                   (0x7F00U)
51793 #define XBARA_SEL44_SEL89_SHIFT                  (8U)
51794 #define XBARA_SEL44_SEL89(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
51795 /*! @} */
51796 
51797 /*! @name SEL45 - Crossbar A Select Register 45 */
51798 /*! @{ */
51799 
51800 #define XBARA_SEL45_SEL90_MASK                   (0x7FU)
51801 #define XBARA_SEL45_SEL90_SHIFT                  (0U)
51802 #define XBARA_SEL45_SEL90(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
51803 
51804 #define XBARA_SEL45_SEL91_MASK                   (0x7F00U)
51805 #define XBARA_SEL45_SEL91_SHIFT                  (8U)
51806 #define XBARA_SEL45_SEL91(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
51807 /*! @} */
51808 
51809 /*! @name SEL46 - Crossbar A Select Register 46 */
51810 /*! @{ */
51811 
51812 #define XBARA_SEL46_SEL92_MASK                   (0x7FU)
51813 #define XBARA_SEL46_SEL92_SHIFT                  (0U)
51814 #define XBARA_SEL46_SEL92(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
51815 
51816 #define XBARA_SEL46_SEL93_MASK                   (0x7F00U)
51817 #define XBARA_SEL46_SEL93_SHIFT                  (8U)
51818 #define XBARA_SEL46_SEL93(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
51819 /*! @} */
51820 
51821 /*! @name SEL47 - Crossbar A Select Register 47 */
51822 /*! @{ */
51823 
51824 #define XBARA_SEL47_SEL94_MASK                   (0x7FU)
51825 #define XBARA_SEL47_SEL94_SHIFT                  (0U)
51826 #define XBARA_SEL47_SEL94(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
51827 
51828 #define XBARA_SEL47_SEL95_MASK                   (0x7F00U)
51829 #define XBARA_SEL47_SEL95_SHIFT                  (8U)
51830 #define XBARA_SEL47_SEL95(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
51831 /*! @} */
51832 
51833 /*! @name SEL48 - Crossbar A Select Register 48 */
51834 /*! @{ */
51835 
51836 #define XBARA_SEL48_SEL96_MASK                   (0x7FU)
51837 #define XBARA_SEL48_SEL96_SHIFT                  (0U)
51838 #define XBARA_SEL48_SEL96(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
51839 
51840 #define XBARA_SEL48_SEL97_MASK                   (0x7F00U)
51841 #define XBARA_SEL48_SEL97_SHIFT                  (8U)
51842 #define XBARA_SEL48_SEL97(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
51843 /*! @} */
51844 
51845 /*! @name SEL49 - Crossbar A Select Register 49 */
51846 /*! @{ */
51847 
51848 #define XBARA_SEL49_SEL98_MASK                   (0x7FU)
51849 #define XBARA_SEL49_SEL98_SHIFT                  (0U)
51850 #define XBARA_SEL49_SEL98(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
51851 
51852 #define XBARA_SEL49_SEL99_MASK                   (0x7F00U)
51853 #define XBARA_SEL49_SEL99_SHIFT                  (8U)
51854 #define XBARA_SEL49_SEL99(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
51855 /*! @} */
51856 
51857 /*! @name SEL50 - Crossbar A Select Register 50 */
51858 /*! @{ */
51859 
51860 #define XBARA_SEL50_SEL100_MASK                  (0x7FU)
51861 #define XBARA_SEL50_SEL100_SHIFT                 (0U)
51862 #define XBARA_SEL50_SEL100(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
51863 
51864 #define XBARA_SEL50_SEL101_MASK                  (0x7F00U)
51865 #define XBARA_SEL50_SEL101_SHIFT                 (8U)
51866 #define XBARA_SEL50_SEL101(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
51867 /*! @} */
51868 
51869 /*! @name SEL51 - Crossbar A Select Register 51 */
51870 /*! @{ */
51871 
51872 #define XBARA_SEL51_SEL102_MASK                  (0x7FU)
51873 #define XBARA_SEL51_SEL102_SHIFT                 (0U)
51874 #define XBARA_SEL51_SEL102(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
51875 
51876 #define XBARA_SEL51_SEL103_MASK                  (0x7F00U)
51877 #define XBARA_SEL51_SEL103_SHIFT                 (8U)
51878 #define XBARA_SEL51_SEL103(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
51879 /*! @} */
51880 
51881 /*! @name SEL52 - Crossbar A Select Register 52 */
51882 /*! @{ */
51883 
51884 #define XBARA_SEL52_SEL104_MASK                  (0x7FU)
51885 #define XBARA_SEL52_SEL104_SHIFT                 (0U)
51886 #define XBARA_SEL52_SEL104(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
51887 
51888 #define XBARA_SEL52_SEL105_MASK                  (0x7F00U)
51889 #define XBARA_SEL52_SEL105_SHIFT                 (8U)
51890 #define XBARA_SEL52_SEL105(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
51891 /*! @} */
51892 
51893 /*! @name SEL53 - Crossbar A Select Register 53 */
51894 /*! @{ */
51895 
51896 #define XBARA_SEL53_SEL106_MASK                  (0x7FU)
51897 #define XBARA_SEL53_SEL106_SHIFT                 (0U)
51898 #define XBARA_SEL53_SEL106(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
51899 
51900 #define XBARA_SEL53_SEL107_MASK                  (0x7F00U)
51901 #define XBARA_SEL53_SEL107_SHIFT                 (8U)
51902 #define XBARA_SEL53_SEL107(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
51903 /*! @} */
51904 
51905 /*! @name SEL54 - Crossbar A Select Register 54 */
51906 /*! @{ */
51907 
51908 #define XBARA_SEL54_SEL108_MASK                  (0x7FU)
51909 #define XBARA_SEL54_SEL108_SHIFT                 (0U)
51910 #define XBARA_SEL54_SEL108(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
51911 
51912 #define XBARA_SEL54_SEL109_MASK                  (0x7F00U)
51913 #define XBARA_SEL54_SEL109_SHIFT                 (8U)
51914 #define XBARA_SEL54_SEL109(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
51915 /*! @} */
51916 
51917 /*! @name SEL55 - Crossbar A Select Register 55 */
51918 /*! @{ */
51919 
51920 #define XBARA_SEL55_SEL110_MASK                  (0x7FU)
51921 #define XBARA_SEL55_SEL110_SHIFT                 (0U)
51922 #define XBARA_SEL55_SEL110(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
51923 
51924 #define XBARA_SEL55_SEL111_MASK                  (0x7F00U)
51925 #define XBARA_SEL55_SEL111_SHIFT                 (8U)
51926 #define XBARA_SEL55_SEL111(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
51927 /*! @} */
51928 
51929 /*! @name SEL56 - Crossbar A Select Register 56 */
51930 /*! @{ */
51931 
51932 #define XBARA_SEL56_SEL112_MASK                  (0x7FU)
51933 #define XBARA_SEL56_SEL112_SHIFT                 (0U)
51934 #define XBARA_SEL56_SEL112(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
51935 
51936 #define XBARA_SEL56_SEL113_MASK                  (0x7F00U)
51937 #define XBARA_SEL56_SEL113_SHIFT                 (8U)
51938 #define XBARA_SEL56_SEL113(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
51939 /*! @} */
51940 
51941 /*! @name SEL57 - Crossbar A Select Register 57 */
51942 /*! @{ */
51943 
51944 #define XBARA_SEL57_SEL114_MASK                  (0x7FU)
51945 #define XBARA_SEL57_SEL114_SHIFT                 (0U)
51946 #define XBARA_SEL57_SEL114(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
51947 
51948 #define XBARA_SEL57_SEL115_MASK                  (0x7F00U)
51949 #define XBARA_SEL57_SEL115_SHIFT                 (8U)
51950 #define XBARA_SEL57_SEL115(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
51951 /*! @} */
51952 
51953 /*! @name SEL58 - Crossbar A Select Register 58 */
51954 /*! @{ */
51955 
51956 #define XBARA_SEL58_SEL116_MASK                  (0x7FU)
51957 #define XBARA_SEL58_SEL116_SHIFT                 (0U)
51958 #define XBARA_SEL58_SEL116(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
51959 
51960 #define XBARA_SEL58_SEL117_MASK                  (0x7F00U)
51961 #define XBARA_SEL58_SEL117_SHIFT                 (8U)
51962 #define XBARA_SEL58_SEL117(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
51963 /*! @} */
51964 
51965 /*! @name SEL59 - Crossbar A Select Register 59 */
51966 /*! @{ */
51967 
51968 #define XBARA_SEL59_SEL118_MASK                  (0x7FU)
51969 #define XBARA_SEL59_SEL118_SHIFT                 (0U)
51970 #define XBARA_SEL59_SEL118(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
51971 
51972 #define XBARA_SEL59_SEL119_MASK                  (0x7F00U)
51973 #define XBARA_SEL59_SEL119_SHIFT                 (8U)
51974 #define XBARA_SEL59_SEL119(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
51975 /*! @} */
51976 
51977 /*! @name SEL60 - Crossbar A Select Register 60 */
51978 /*! @{ */
51979 
51980 #define XBARA_SEL60_SEL120_MASK                  (0x7FU)
51981 #define XBARA_SEL60_SEL120_SHIFT                 (0U)
51982 #define XBARA_SEL60_SEL120(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
51983 
51984 #define XBARA_SEL60_SEL121_MASK                  (0x7F00U)
51985 #define XBARA_SEL60_SEL121_SHIFT                 (8U)
51986 #define XBARA_SEL60_SEL121(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
51987 /*! @} */
51988 
51989 /*! @name SEL61 - Crossbar A Select Register 61 */
51990 /*! @{ */
51991 
51992 #define XBARA_SEL61_SEL122_MASK                  (0x7FU)
51993 #define XBARA_SEL61_SEL122_SHIFT                 (0U)
51994 #define XBARA_SEL61_SEL122(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
51995 
51996 #define XBARA_SEL61_SEL123_MASK                  (0x7F00U)
51997 #define XBARA_SEL61_SEL123_SHIFT                 (8U)
51998 #define XBARA_SEL61_SEL123(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
51999 /*! @} */
52000 
52001 /*! @name SEL62 - Crossbar A Select Register 62 */
52002 /*! @{ */
52003 
52004 #define XBARA_SEL62_SEL124_MASK                  (0x7FU)
52005 #define XBARA_SEL62_SEL124_SHIFT                 (0U)
52006 #define XBARA_SEL62_SEL124(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
52007 
52008 #define XBARA_SEL62_SEL125_MASK                  (0x7F00U)
52009 #define XBARA_SEL62_SEL125_SHIFT                 (8U)
52010 #define XBARA_SEL62_SEL125(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
52011 /*! @} */
52012 
52013 /*! @name SEL63 - Crossbar A Select Register 63 */
52014 /*! @{ */
52015 
52016 #define XBARA_SEL63_SEL126_MASK                  (0x7FU)
52017 #define XBARA_SEL63_SEL126_SHIFT                 (0U)
52018 #define XBARA_SEL63_SEL126(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
52019 
52020 #define XBARA_SEL63_SEL127_MASK                  (0x7F00U)
52021 #define XBARA_SEL63_SEL127_SHIFT                 (8U)
52022 #define XBARA_SEL63_SEL127(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
52023 /*! @} */
52024 
52025 /*! @name SEL64 - Crossbar A Select Register 64 */
52026 /*! @{ */
52027 
52028 #define XBARA_SEL64_SEL128_MASK                  (0x7FU)
52029 #define XBARA_SEL64_SEL128_SHIFT                 (0U)
52030 #define XBARA_SEL64_SEL128(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
52031 
52032 #define XBARA_SEL64_SEL129_MASK                  (0x7F00U)
52033 #define XBARA_SEL64_SEL129_SHIFT                 (8U)
52034 #define XBARA_SEL64_SEL129(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
52035 /*! @} */
52036 
52037 /*! @name SEL65 - Crossbar A Select Register 65 */
52038 /*! @{ */
52039 
52040 #define XBARA_SEL65_SEL130_MASK                  (0x7FU)
52041 #define XBARA_SEL65_SEL130_SHIFT                 (0U)
52042 #define XBARA_SEL65_SEL130(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
52043 
52044 #define XBARA_SEL65_SEL131_MASK                  (0x7F00U)
52045 #define XBARA_SEL65_SEL131_SHIFT                 (8U)
52046 #define XBARA_SEL65_SEL131(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
52047 /*! @} */
52048 
52049 /*! @name CTRL0 - Crossbar A Control Register 0 */
52050 /*! @{ */
52051 
52052 #define XBARA_CTRL0_DEN0_MASK                    (0x1U)
52053 #define XBARA_CTRL0_DEN0_SHIFT                   (0U)
52054 /*! DEN0 - DMA Enable for XBAR_OUT0
52055  *  0b0..DMA disabled
52056  *  0b1..DMA enabled
52057  */
52058 #define XBARA_CTRL0_DEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
52059 
52060 #define XBARA_CTRL0_IEN0_MASK                    (0x2U)
52061 #define XBARA_CTRL0_IEN0_SHIFT                   (1U)
52062 /*! IEN0 - Interrupt Enable for XBAR_OUT0
52063  *  0b0..Interrupt disabled
52064  *  0b1..Interrupt enabled
52065  */
52066 #define XBARA_CTRL0_IEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
52067 
52068 #define XBARA_CTRL0_EDGE0_MASK                   (0xCU)
52069 #define XBARA_CTRL0_EDGE0_SHIFT                  (2U)
52070 /*! EDGE0 - Active edge for edge detection on XBAR_OUT0
52071  *  0b00..STS0 never asserts
52072  *  0b01..STS0 asserts on rising edges of XBAR_OUT0
52073  *  0b10..STS0 asserts on falling edges of XBAR_OUT0
52074  *  0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
52075  */
52076 #define XBARA_CTRL0_EDGE0(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
52077 
52078 #define XBARA_CTRL0_STS0_MASK                    (0x10U)
52079 #define XBARA_CTRL0_STS0_SHIFT                   (4U)
52080 /*! STS0 - Edge detection status for XBAR_OUT0
52081  *  0b0..Active edge not yet detected on XBAR_OUT0
52082  *  0b1..Active edge detected on XBAR_OUT0
52083  */
52084 #define XBARA_CTRL0_STS0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
52085 
52086 #define XBARA_CTRL0_DEN1_MASK                    (0x100U)
52087 #define XBARA_CTRL0_DEN1_SHIFT                   (8U)
52088 /*! DEN1 - DMA Enable for XBAR_OUT1
52089  *  0b0..DMA disabled
52090  *  0b1..DMA enabled
52091  */
52092 #define XBARA_CTRL0_DEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
52093 
52094 #define XBARA_CTRL0_IEN1_MASK                    (0x200U)
52095 #define XBARA_CTRL0_IEN1_SHIFT                   (9U)
52096 /*! IEN1 - Interrupt Enable for XBAR_OUT1
52097  *  0b0..Interrupt disabled
52098  *  0b1..Interrupt enabled
52099  */
52100 #define XBARA_CTRL0_IEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
52101 
52102 #define XBARA_CTRL0_EDGE1_MASK                   (0xC00U)
52103 #define XBARA_CTRL0_EDGE1_SHIFT                  (10U)
52104 /*! EDGE1 - Active edge for edge detection on XBAR_OUT1
52105  *  0b00..STS1 never asserts
52106  *  0b01..STS1 asserts on rising edges of XBAR_OUT1
52107  *  0b10..STS1 asserts on falling edges of XBAR_OUT1
52108  *  0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
52109  */
52110 #define XBARA_CTRL0_EDGE1(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
52111 
52112 #define XBARA_CTRL0_STS1_MASK                    (0x1000U)
52113 #define XBARA_CTRL0_STS1_SHIFT                   (12U)
52114 /*! STS1 - Edge detection status for XBAR_OUT1
52115  *  0b0..Active edge not yet detected on XBAR_OUT1
52116  *  0b1..Active edge detected on XBAR_OUT1
52117  */
52118 #define XBARA_CTRL0_STS1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
52119 /*! @} */
52120 
52121 /*! @name CTRL1 - Crossbar A Control Register 1 */
52122 /*! @{ */
52123 
52124 #define XBARA_CTRL1_DEN2_MASK                    (0x1U)
52125 #define XBARA_CTRL1_DEN2_SHIFT                   (0U)
52126 /*! DEN2 - DMA Enable for XBAR_OUT2
52127  *  0b0..DMA disabled
52128  *  0b1..DMA enabled
52129  */
52130 #define XBARA_CTRL1_DEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
52131 
52132 #define XBARA_CTRL1_IEN2_MASK                    (0x2U)
52133 #define XBARA_CTRL1_IEN2_SHIFT                   (1U)
52134 /*! IEN2 - Interrupt Enable for XBAR_OUT2
52135  *  0b0..Interrupt disabled
52136  *  0b1..Interrupt enabled
52137  */
52138 #define XBARA_CTRL1_IEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
52139 
52140 #define XBARA_CTRL1_EDGE2_MASK                   (0xCU)
52141 #define XBARA_CTRL1_EDGE2_SHIFT                  (2U)
52142 /*! EDGE2 - Active edge for edge detection on XBAR_OUT2
52143  *  0b00..STS2 never asserts
52144  *  0b01..STS2 asserts on rising edges of XBAR_OUT2
52145  *  0b10..STS2 asserts on falling edges of XBAR_OUT2
52146  *  0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
52147  */
52148 #define XBARA_CTRL1_EDGE2(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
52149 
52150 #define XBARA_CTRL1_STS2_MASK                    (0x10U)
52151 #define XBARA_CTRL1_STS2_SHIFT                   (4U)
52152 /*! STS2 - Edge detection status for XBAR_OUT2
52153  *  0b0..Active edge not yet detected on XBAR_OUT2
52154  *  0b1..Active edge detected on XBAR_OUT2
52155  */
52156 #define XBARA_CTRL1_STS2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
52157 
52158 #define XBARA_CTRL1_DEN3_MASK                    (0x100U)
52159 #define XBARA_CTRL1_DEN3_SHIFT                   (8U)
52160 /*! DEN3 - DMA Enable for XBAR_OUT3
52161  *  0b0..DMA disabled
52162  *  0b1..DMA enabled
52163  */
52164 #define XBARA_CTRL1_DEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
52165 
52166 #define XBARA_CTRL1_IEN3_MASK                    (0x200U)
52167 #define XBARA_CTRL1_IEN3_SHIFT                   (9U)
52168 /*! IEN3 - Interrupt Enable for XBAR_OUT3
52169  *  0b0..Interrupt disabled
52170  *  0b1..Interrupt enabled
52171  */
52172 #define XBARA_CTRL1_IEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
52173 
52174 #define XBARA_CTRL1_EDGE3_MASK                   (0xC00U)
52175 #define XBARA_CTRL1_EDGE3_SHIFT                  (10U)
52176 /*! EDGE3 - Active edge for edge detection on XBAR_OUT3
52177  *  0b00..STS3 never asserts
52178  *  0b01..STS3 asserts on rising edges of XBAR_OUT3
52179  *  0b10..STS3 asserts on falling edges of XBAR_OUT3
52180  *  0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
52181  */
52182 #define XBARA_CTRL1_EDGE3(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
52183 
52184 #define XBARA_CTRL1_STS3_MASK                    (0x1000U)
52185 #define XBARA_CTRL1_STS3_SHIFT                   (12U)
52186 /*! STS3 - Edge detection status for XBAR_OUT3
52187  *  0b0..Active edge not yet detected on XBAR_OUT3
52188  *  0b1..Active edge detected on XBAR_OUT3
52189  */
52190 #define XBARA_CTRL1_STS3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
52191 /*! @} */
52192 
52193 
52194 /*!
52195  * @}
52196  */ /* end of group XBARA_Register_Masks */
52197 
52198 
52199 /* XBARA - Peripheral instance base addresses */
52200 /** Peripheral XBARA1 base address */
52201 #define XBARA1_BASE                              (0x403BC000u)
52202 /** Peripheral XBARA1 base pointer */
52203 #define XBARA1                                   ((XBARA_Type *)XBARA1_BASE)
52204 /** Array initializer of XBARA peripheral base addresses */
52205 #define XBARA_BASE_ADDRS                         { 0u, XBARA1_BASE }
52206 /** Array initializer of XBARA peripheral base pointers */
52207 #define XBARA_BASE_PTRS                          { (XBARA_Type *)0u, XBARA1 }
52208 
52209 /*!
52210  * @}
52211  */ /* end of group XBARA_Peripheral_Access_Layer */
52212 
52213 
52214 /* ----------------------------------------------------------------------------
52215    -- XBARB Peripheral Access Layer
52216    ---------------------------------------------------------------------------- */
52217 
52218 /*!
52219  * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
52220  * @{
52221  */
52222 
52223 /** XBARB - Register Layout Typedef */
52224 typedef struct {
52225   __IO uint16_t SEL0;                              /**< Crossbar B Select Register 0, offset: 0x0 */
52226   __IO uint16_t SEL1;                              /**< Crossbar B Select Register 1, offset: 0x2 */
52227   __IO uint16_t SEL2;                              /**< Crossbar B Select Register 2, offset: 0x4 */
52228   __IO uint16_t SEL3;                              /**< Crossbar B Select Register 3, offset: 0x6 */
52229   __IO uint16_t SEL4;                              /**< Crossbar B Select Register 4, offset: 0x8 */
52230   __IO uint16_t SEL5;                              /**< Crossbar B Select Register 5, offset: 0xA */
52231   __IO uint16_t SEL6;                              /**< Crossbar B Select Register 6, offset: 0xC */
52232   __IO uint16_t SEL7;                              /**< Crossbar B Select Register 7, offset: 0xE */
52233 } XBARB_Type;
52234 
52235 /* ----------------------------------------------------------------------------
52236    -- XBARB Register Masks
52237    ---------------------------------------------------------------------------- */
52238 
52239 /*!
52240  * @addtogroup XBARB_Register_Masks XBARB Register Masks
52241  * @{
52242  */
52243 
52244 /*! @name SEL0 - Crossbar B Select Register 0 */
52245 /*! @{ */
52246 
52247 #define XBARB_SEL0_SEL0_MASK                     (0x3FU)
52248 #define XBARB_SEL0_SEL0_SHIFT                    (0U)
52249 #define XBARB_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
52250 
52251 #define XBARB_SEL0_SEL1_MASK                     (0x3F00U)
52252 #define XBARB_SEL0_SEL1_SHIFT                    (8U)
52253 #define XBARB_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
52254 /*! @} */
52255 
52256 /*! @name SEL1 - Crossbar B Select Register 1 */
52257 /*! @{ */
52258 
52259 #define XBARB_SEL1_SEL2_MASK                     (0x3FU)
52260 #define XBARB_SEL1_SEL2_SHIFT                    (0U)
52261 #define XBARB_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
52262 
52263 #define XBARB_SEL1_SEL3_MASK                     (0x3F00U)
52264 #define XBARB_SEL1_SEL3_SHIFT                    (8U)
52265 #define XBARB_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
52266 /*! @} */
52267 
52268 /*! @name SEL2 - Crossbar B Select Register 2 */
52269 /*! @{ */
52270 
52271 #define XBARB_SEL2_SEL4_MASK                     (0x3FU)
52272 #define XBARB_SEL2_SEL4_SHIFT                    (0U)
52273 #define XBARB_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
52274 
52275 #define XBARB_SEL2_SEL5_MASK                     (0x3F00U)
52276 #define XBARB_SEL2_SEL5_SHIFT                    (8U)
52277 #define XBARB_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
52278 /*! @} */
52279 
52280 /*! @name SEL3 - Crossbar B Select Register 3 */
52281 /*! @{ */
52282 
52283 #define XBARB_SEL3_SEL6_MASK                     (0x3FU)
52284 #define XBARB_SEL3_SEL6_SHIFT                    (0U)
52285 #define XBARB_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
52286 
52287 #define XBARB_SEL3_SEL7_MASK                     (0x3F00U)
52288 #define XBARB_SEL3_SEL7_SHIFT                    (8U)
52289 #define XBARB_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
52290 /*! @} */
52291 
52292 /*! @name SEL4 - Crossbar B Select Register 4 */
52293 /*! @{ */
52294 
52295 #define XBARB_SEL4_SEL8_MASK                     (0x3FU)
52296 #define XBARB_SEL4_SEL8_SHIFT                    (0U)
52297 #define XBARB_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
52298 
52299 #define XBARB_SEL4_SEL9_MASK                     (0x3F00U)
52300 #define XBARB_SEL4_SEL9_SHIFT                    (8U)
52301 #define XBARB_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
52302 /*! @} */
52303 
52304 /*! @name SEL5 - Crossbar B Select Register 5 */
52305 /*! @{ */
52306 
52307 #define XBARB_SEL5_SEL10_MASK                    (0x3FU)
52308 #define XBARB_SEL5_SEL10_SHIFT                   (0U)
52309 #define XBARB_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
52310 
52311 #define XBARB_SEL5_SEL11_MASK                    (0x3F00U)
52312 #define XBARB_SEL5_SEL11_SHIFT                   (8U)
52313 #define XBARB_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
52314 /*! @} */
52315 
52316 /*! @name SEL6 - Crossbar B Select Register 6 */
52317 /*! @{ */
52318 
52319 #define XBARB_SEL6_SEL12_MASK                    (0x3FU)
52320 #define XBARB_SEL6_SEL12_SHIFT                   (0U)
52321 #define XBARB_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
52322 
52323 #define XBARB_SEL6_SEL13_MASK                    (0x3F00U)
52324 #define XBARB_SEL6_SEL13_SHIFT                   (8U)
52325 #define XBARB_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
52326 /*! @} */
52327 
52328 /*! @name SEL7 - Crossbar B Select Register 7 */
52329 /*! @{ */
52330 
52331 #define XBARB_SEL7_SEL14_MASK                    (0x3FU)
52332 #define XBARB_SEL7_SEL14_SHIFT                   (0U)
52333 #define XBARB_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
52334 
52335 #define XBARB_SEL7_SEL15_MASK                    (0x3F00U)
52336 #define XBARB_SEL7_SEL15_SHIFT                   (8U)
52337 #define XBARB_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
52338 /*! @} */
52339 
52340 
52341 /*!
52342  * @}
52343  */ /* end of group XBARB_Register_Masks */
52344 
52345 
52346 /* XBARB - Peripheral instance base addresses */
52347 /** Peripheral XBARB2 base address */
52348 #define XBARB2_BASE                              (0x403C0000u)
52349 /** Peripheral XBARB2 base pointer */
52350 #define XBARB2                                   ((XBARB_Type *)XBARB2_BASE)
52351 /** Peripheral XBARB3 base address */
52352 #define XBARB3_BASE                              (0x403C4000u)
52353 /** Peripheral XBARB3 base pointer */
52354 #define XBARB3                                   ((XBARB_Type *)XBARB3_BASE)
52355 /** Array initializer of XBARB peripheral base addresses */
52356 #define XBARB_BASE_ADDRS                         { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
52357 /** Array initializer of XBARB peripheral base pointers */
52358 #define XBARB_BASE_PTRS                          { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
52359 
52360 /*!
52361  * @}
52362  */ /* end of group XBARB_Peripheral_Access_Layer */
52363 
52364 
52365 /* ----------------------------------------------------------------------------
52366    -- XTALOSC24M Peripheral Access Layer
52367    ---------------------------------------------------------------------------- */
52368 
52369 /*!
52370  * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer
52371  * @{
52372  */
52373 
52374 /** XTALOSC24M - Register Layout Typedef */
52375 typedef struct {
52376        uint8_t RESERVED_0[336];
52377   __IO uint32_t MISC0;                             /**< Miscellaneous Register 0, offset: 0x150 */
52378   __IO uint32_t MISC0_SET;                         /**< Miscellaneous Register 0, offset: 0x154 */
52379   __IO uint32_t MISC0_CLR;                         /**< Miscellaneous Register 0, offset: 0x158 */
52380   __IO uint32_t MISC0_TOG;                         /**< Miscellaneous Register 0, offset: 0x15C */
52381        uint8_t RESERVED_1[272];
52382   __IO uint32_t LOWPWR_CTRL;                       /**< XTAL OSC (LP) Control Register, offset: 0x270 */
52383   __IO uint32_t LOWPWR_CTRL_SET;                   /**< XTAL OSC (LP) Control Register, offset: 0x274 */
52384   __IO uint32_t LOWPWR_CTRL_CLR;                   /**< XTAL OSC (LP) Control Register, offset: 0x278 */
52385   __IO uint32_t LOWPWR_CTRL_TOG;                   /**< XTAL OSC (LP) Control Register, offset: 0x27C */
52386        uint8_t RESERVED_2[32];
52387   __IO uint32_t OSC_CONFIG0;                       /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */
52388   __IO uint32_t OSC_CONFIG0_SET;                   /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */
52389   __IO uint32_t OSC_CONFIG0_CLR;                   /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */
52390   __IO uint32_t OSC_CONFIG0_TOG;                   /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */
52391   __IO uint32_t OSC_CONFIG1;                       /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */
52392   __IO uint32_t OSC_CONFIG1_SET;                   /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */
52393   __IO uint32_t OSC_CONFIG1_CLR;                   /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */
52394   __IO uint32_t OSC_CONFIG1_TOG;                   /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */
52395   __IO uint32_t OSC_CONFIG2;                       /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */
52396   __IO uint32_t OSC_CONFIG2_SET;                   /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */
52397   __IO uint32_t OSC_CONFIG2_CLR;                   /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */
52398   __IO uint32_t OSC_CONFIG2_TOG;                   /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */
52399 } XTALOSC24M_Type;
52400 
52401 /* ----------------------------------------------------------------------------
52402    -- XTALOSC24M Register Masks
52403    ---------------------------------------------------------------------------- */
52404 
52405 /*!
52406  * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks
52407  * @{
52408  */
52409 
52410 /*! @name MISC0 - Miscellaneous Register 0 */
52411 /*! @{ */
52412 
52413 #define XTALOSC24M_MISC0_REFTOP_PWD_MASK         (0x1U)
52414 #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT        (0U)
52415 #define XTALOSC24M_MISC0_REFTOP_PWD(x)           (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
52416 
52417 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
52418 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
52419 /*! REFTOP_SELFBIASOFF
52420  *  0b0..Uses coarse bias currents for startup
52421  *  0b1..Uses bandgap-based bias currents for best performance.
52422  */
52423 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
52424 
52425 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK      (0x70U)
52426 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT     (4U)
52427 /*! REFTOP_VBGADJ
52428  *  0b000..Nominal VBG
52429  *  0b001..VBG+0.78%
52430  *  0b010..VBG+1.56%
52431  *  0b011..VBG+2.34%
52432  *  0b100..VBG-0.78%
52433  *  0b101..VBG-1.56%
52434  *  0b110..VBG-2.34%
52435  *  0b111..VBG-3.12%
52436  */
52437 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
52438 
52439 #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK       (0x80U)
52440 #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT      (7U)
52441 #define XTALOSC24M_MISC0_REFTOP_VBGUP(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
52442 
52443 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK   (0xC00U)
52444 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT  (10U)
52445 /*! STOP_MODE_CONFIG
52446  *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
52447  *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
52448  *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
52449  *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
52450  */
52451 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
52452 
52453 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK   (0x1000U)
52454 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT  (12U)
52455 /*! DISCON_HIGH_SNVS
52456  *  0b0..Turn on the switch
52457  *  0b1..Turn off the switch
52458  */
52459 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
52460 
52461 #define XTALOSC24M_MISC0_OSC_I_MASK              (0x6000U)
52462 #define XTALOSC24M_MISC0_OSC_I_SHIFT             (13U)
52463 /*! OSC_I
52464  *  0b00..Nominal
52465  *  0b01..Decrease current by 12.5%
52466  *  0b10..Decrease current by 25.0%
52467  *  0b11..Decrease current by 37.5%
52468  */
52469 #define XTALOSC24M_MISC0_OSC_I(x)                (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
52470 
52471 #define XTALOSC24M_MISC0_OSC_XTALOK_MASK         (0x8000U)
52472 #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT        (15U)
52473 #define XTALOSC24M_MISC0_OSC_XTALOK(x)           (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
52474 
52475 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK      (0x10000U)
52476 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT     (16U)
52477 #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
52478 
52479 #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK       (0x2000000U)
52480 #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT      (25U)
52481 /*! CLKGATE_CTRL
52482  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
52483  *  0b1..Prevent the logic from ever gating off the clock.
52484  */
52485 #define XTALOSC24M_MISC0_CLKGATE_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
52486 
52487 #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK      (0x1C000000U)
52488 #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT     (26U)
52489 /*! CLKGATE_DELAY
52490  *  0b000..0.5ms
52491  *  0b001..1.0ms
52492  *  0b010..2.0ms
52493  *  0b011..3.0ms
52494  *  0b100..4.0ms
52495  *  0b101..5.0ms
52496  *  0b110..6.0ms
52497  *  0b111..7.0ms
52498  */
52499 #define XTALOSC24M_MISC0_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
52500 
52501 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK    (0x20000000U)
52502 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT   (29U)
52503 /*! RTC_XTAL_SOURCE
52504  *  0b0..Internal ring oscillator
52505  *  0b1..RTC_XTAL
52506  */
52507 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
52508 
52509 #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK       (0x40000000U)
52510 #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT      (30U)
52511 #define XTALOSC24M_MISC0_XTAL_24M_PWD(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
52512 
52513 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK     (0x80000000U)
52514 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT    (31U)
52515 /*! VID_PLL_PREDIV
52516  *  0b0..Divide by 1
52517  *  0b1..Divide by 2
52518  */
52519 #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
52520 /*! @} */
52521 
52522 /*! @name MISC0_SET - Miscellaneous Register 0 */
52523 /*! @{ */
52524 
52525 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK     (0x1U)
52526 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT    (0U)
52527 #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
52528 
52529 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
52530 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
52531 /*! REFTOP_SELFBIASOFF
52532  *  0b0..Uses coarse bias currents for startup
52533  *  0b1..Uses bandgap-based bias currents for best performance.
52534  */
52535 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
52536 
52537 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK  (0x70U)
52538 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
52539 /*! REFTOP_VBGADJ
52540  *  0b000..Nominal VBG
52541  *  0b001..VBG+0.78%
52542  *  0b010..VBG+1.56%
52543  *  0b011..VBG+2.34%
52544  *  0b100..VBG-0.78%
52545  *  0b101..VBG-1.56%
52546  *  0b110..VBG-2.34%
52547  *  0b111..VBG-3.12%
52548  */
52549 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
52550 
52551 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK   (0x80U)
52552 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT  (7U)
52553 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
52554 
52555 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
52556 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
52557 /*! STOP_MODE_CONFIG
52558  *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
52559  *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
52560  *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
52561  *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
52562  */
52563 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
52564 
52565 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
52566 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
52567 /*! DISCON_HIGH_SNVS
52568  *  0b0..Turn on the switch
52569  *  0b1..Turn off the switch
52570  */
52571 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
52572 
52573 #define XTALOSC24M_MISC0_SET_OSC_I_MASK          (0x6000U)
52574 #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT         (13U)
52575 /*! OSC_I
52576  *  0b00..Nominal
52577  *  0b01..Decrease current by 12.5%
52578  *  0b10..Decrease current by 25.0%
52579  *  0b11..Decrease current by 37.5%
52580  */
52581 #define XTALOSC24M_MISC0_SET_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
52582 
52583 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK     (0x8000U)
52584 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT    (15U)
52585 #define XTALOSC24M_MISC0_SET_OSC_XTALOK(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
52586 
52587 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK  (0x10000U)
52588 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
52589 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
52590 
52591 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK   (0x2000000U)
52592 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT  (25U)
52593 /*! CLKGATE_CTRL
52594  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
52595  *  0b1..Prevent the logic from ever gating off the clock.
52596  */
52597 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
52598 
52599 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK  (0x1C000000U)
52600 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
52601 /*! CLKGATE_DELAY
52602  *  0b000..0.5ms
52603  *  0b001..1.0ms
52604  *  0b010..2.0ms
52605  *  0b011..3.0ms
52606  *  0b100..4.0ms
52607  *  0b101..5.0ms
52608  *  0b110..6.0ms
52609  *  0b111..7.0ms
52610  */
52611 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
52612 
52613 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
52614 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
52615 /*! RTC_XTAL_SOURCE
52616  *  0b0..Internal ring oscillator
52617  *  0b1..RTC_XTAL
52618  */
52619 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
52620 
52621 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK   (0x40000000U)
52622 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT  (30U)
52623 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
52624 
52625 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
52626 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
52627 /*! VID_PLL_PREDIV
52628  *  0b0..Divide by 1
52629  *  0b1..Divide by 2
52630  */
52631 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
52632 /*! @} */
52633 
52634 /*! @name MISC0_CLR - Miscellaneous Register 0 */
52635 /*! @{ */
52636 
52637 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK     (0x1U)
52638 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT    (0U)
52639 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
52640 
52641 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
52642 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
52643 /*! REFTOP_SELFBIASOFF
52644  *  0b0..Uses coarse bias currents for startup
52645  *  0b1..Uses bandgap-based bias currents for best performance.
52646  */
52647 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
52648 
52649 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK  (0x70U)
52650 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
52651 /*! REFTOP_VBGADJ
52652  *  0b000..Nominal VBG
52653  *  0b001..VBG+0.78%
52654  *  0b010..VBG+1.56%
52655  *  0b011..VBG+2.34%
52656  *  0b100..VBG-0.78%
52657  *  0b101..VBG-1.56%
52658  *  0b110..VBG-2.34%
52659  *  0b111..VBG-3.12%
52660  */
52661 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
52662 
52663 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK   (0x80U)
52664 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT  (7U)
52665 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
52666 
52667 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
52668 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
52669 /*! STOP_MODE_CONFIG
52670  *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
52671  *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
52672  *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
52673  *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
52674  */
52675 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
52676 
52677 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
52678 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
52679 /*! DISCON_HIGH_SNVS
52680  *  0b0..Turn on the switch
52681  *  0b1..Turn off the switch
52682  */
52683 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
52684 
52685 #define XTALOSC24M_MISC0_CLR_OSC_I_MASK          (0x6000U)
52686 #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT         (13U)
52687 /*! OSC_I
52688  *  0b00..Nominal
52689  *  0b01..Decrease current by 12.5%
52690  *  0b10..Decrease current by 25.0%
52691  *  0b11..Decrease current by 37.5%
52692  */
52693 #define XTALOSC24M_MISC0_CLR_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
52694 
52695 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK     (0x8000U)
52696 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT    (15U)
52697 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
52698 
52699 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK  (0x10000U)
52700 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
52701 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
52702 
52703 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK   (0x2000000U)
52704 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT  (25U)
52705 /*! CLKGATE_CTRL
52706  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
52707  *  0b1..Prevent the logic from ever gating off the clock.
52708  */
52709 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
52710 
52711 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK  (0x1C000000U)
52712 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
52713 /*! CLKGATE_DELAY
52714  *  0b000..0.5ms
52715  *  0b001..1.0ms
52716  *  0b010..2.0ms
52717  *  0b011..3.0ms
52718  *  0b100..4.0ms
52719  *  0b101..5.0ms
52720  *  0b110..6.0ms
52721  *  0b111..7.0ms
52722  */
52723 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
52724 
52725 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
52726 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
52727 /*! RTC_XTAL_SOURCE
52728  *  0b0..Internal ring oscillator
52729  *  0b1..RTC_XTAL
52730  */
52731 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
52732 
52733 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK   (0x40000000U)
52734 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT  (30U)
52735 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
52736 
52737 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
52738 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
52739 /*! VID_PLL_PREDIV
52740  *  0b0..Divide by 1
52741  *  0b1..Divide by 2
52742  */
52743 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
52744 /*! @} */
52745 
52746 /*! @name MISC0_TOG - Miscellaneous Register 0 */
52747 /*! @{ */
52748 
52749 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK     (0x1U)
52750 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT    (0U)
52751 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
52752 
52753 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
52754 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
52755 /*! REFTOP_SELFBIASOFF
52756  *  0b0..Uses coarse bias currents for startup
52757  *  0b1..Uses bandgap-based bias currents for best performance.
52758  */
52759 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
52760 
52761 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK  (0x70U)
52762 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
52763 /*! REFTOP_VBGADJ
52764  *  0b000..Nominal VBG
52765  *  0b001..VBG+0.78%
52766  *  0b010..VBG+1.56%
52767  *  0b011..VBG+2.34%
52768  *  0b100..VBG-0.78%
52769  *  0b101..VBG-1.56%
52770  *  0b110..VBG-2.34%
52771  *  0b111..VBG-3.12%
52772  */
52773 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
52774 
52775 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK   (0x80U)
52776 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT  (7U)
52777 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
52778 
52779 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
52780 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
52781 /*! STOP_MODE_CONFIG
52782  *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
52783  *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
52784  *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
52785  *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
52786  */
52787 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
52788 
52789 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
52790 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
52791 /*! DISCON_HIGH_SNVS
52792  *  0b0..Turn on the switch
52793  *  0b1..Turn off the switch
52794  */
52795 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
52796 
52797 #define XTALOSC24M_MISC0_TOG_OSC_I_MASK          (0x6000U)
52798 #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT         (13U)
52799 /*! OSC_I
52800  *  0b00..Nominal
52801  *  0b01..Decrease current by 12.5%
52802  *  0b10..Decrease current by 25.0%
52803  *  0b11..Decrease current by 37.5%
52804  */
52805 #define XTALOSC24M_MISC0_TOG_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
52806 
52807 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK     (0x8000U)
52808 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT    (15U)
52809 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
52810 
52811 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK  (0x10000U)
52812 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
52813 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
52814 
52815 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK   (0x2000000U)
52816 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT  (25U)
52817 /*! CLKGATE_CTRL
52818  *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
52819  *  0b1..Prevent the logic from ever gating off the clock.
52820  */
52821 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
52822 
52823 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK  (0x1C000000U)
52824 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
52825 /*! CLKGATE_DELAY
52826  *  0b000..0.5ms
52827  *  0b001..1.0ms
52828  *  0b010..2.0ms
52829  *  0b011..3.0ms
52830  *  0b100..4.0ms
52831  *  0b101..5.0ms
52832  *  0b110..6.0ms
52833  *  0b111..7.0ms
52834  */
52835 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
52836 
52837 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
52838 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
52839 /*! RTC_XTAL_SOURCE
52840  *  0b0..Internal ring oscillator
52841  *  0b1..RTC_XTAL
52842  */
52843 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
52844 
52845 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK   (0x40000000U)
52846 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT  (30U)
52847 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
52848 
52849 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
52850 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
52851 /*! VID_PLL_PREDIV
52852  *  0b0..Divide by 1
52853  *  0b1..Divide by 2
52854  */
52855 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
52856 /*! @} */
52857 
52858 /*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */
52859 /*! @{ */
52860 
52861 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK    (0x1U)
52862 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT   (0U)
52863 /*! RC_OSC_EN
52864  *  0b0..Use XTAL OSC to source the 24MHz clock
52865  *  0b1..Use RC OSC
52866  */
52867 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
52868 
52869 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK      (0x10U)
52870 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT     (4U)
52871 /*! OSC_SEL
52872  *  0b0..XTAL OSC
52873  *  0b1..RC OSC
52874  */
52875 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
52876 
52877 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK     (0x20U)
52878 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT    (5U)
52879 /*! LPBG_SEL
52880  *  0b0..Normal power bandgap
52881  *  0b1..Low power bandgap
52882  */
52883 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
52884 
52885 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK    (0x40U)
52886 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT   (6U)
52887 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
52888 
52889 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
52890 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
52891 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
52892 
52893 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK   (0x100U)
52894 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT  (8U)
52895 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
52896 
52897 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK   (0x200U)
52898 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT  (9U)
52899 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
52900 
52901 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK  (0x400U)
52902 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
52903 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
52904 
52905 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
52906 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
52907 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
52908 
52909 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
52910 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
52911 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
52912 
52913 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
52914 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
52915 /*! XTALOSC_PWRUP_DELAY
52916  *  0b00..0.25ms
52917  *  0b01..0.5ms
52918  *  0b10..1ms
52919  *  0b11..2ms
52920  */
52921 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
52922 
52923 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
52924 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
52925 /*! XTALOSC_PWRUP_STAT
52926  *  0b0..Not stable
52927  *  0b1..Stable and ready to use
52928  */
52929 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
52930 
52931 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK  (0x20000U)
52932 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
52933 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
52934 
52935 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK  (0x40000U)
52936 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
52937 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
52938 /*! @} */
52939 
52940 /*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */
52941 /*! @{ */
52942 
52943 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
52944 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
52945 /*! RC_OSC_EN
52946  *  0b0..Use XTAL OSC to source the 24MHz clock
52947  *  0b1..Use RC OSC
52948  */
52949 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
52950 
52951 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK  (0x10U)
52952 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
52953 /*! OSC_SEL
52954  *  0b0..XTAL OSC
52955  *  0b1..RC OSC
52956  */
52957 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
52958 
52959 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
52960 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
52961 /*! LPBG_SEL
52962  *  0b0..Normal power bandgap
52963  *  0b1..Low power bandgap
52964  */
52965 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
52966 
52967 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
52968 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
52969 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
52970 
52971 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
52972 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
52973 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
52974 
52975 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
52976 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
52977 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
52978 
52979 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
52980 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
52981 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
52982 
52983 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
52984 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
52985 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
52986 
52987 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
52988 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
52989 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
52990 
52991 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
52992 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
52993 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
52994 
52995 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
52996 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
52997 /*! XTALOSC_PWRUP_DELAY
52998  *  0b00..0.25ms
52999  *  0b01..0.5ms
53000  *  0b10..1ms
53001  *  0b11..2ms
53002  */
53003 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
53004 
53005 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
53006 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
53007 /*! XTALOSC_PWRUP_STAT
53008  *  0b0..Not stable
53009  *  0b1..Stable and ready to use
53010  */
53011 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
53012 
53013 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
53014 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
53015 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
53016 
53017 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
53018 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
53019 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
53020 /*! @} */
53021 
53022 /*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */
53023 /*! @{ */
53024 
53025 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
53026 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
53027 /*! RC_OSC_EN
53028  *  0b0..Use XTAL OSC to source the 24MHz clock
53029  *  0b1..Use RC OSC
53030  */
53031 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
53032 
53033 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK  (0x10U)
53034 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
53035 /*! OSC_SEL
53036  *  0b0..XTAL OSC
53037  *  0b1..RC OSC
53038  */
53039 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
53040 
53041 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
53042 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
53043 /*! LPBG_SEL
53044  *  0b0..Normal power bandgap
53045  *  0b1..Low power bandgap
53046  */
53047 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
53048 
53049 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
53050 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
53051 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
53052 
53053 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
53054 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
53055 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
53056 
53057 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
53058 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
53059 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
53060 
53061 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
53062 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
53063 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
53064 
53065 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
53066 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
53067 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
53068 
53069 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
53070 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
53071 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
53072 
53073 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
53074 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
53075 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
53076 
53077 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
53078 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
53079 /*! XTALOSC_PWRUP_DELAY
53080  *  0b00..0.25ms
53081  *  0b01..0.5ms
53082  *  0b10..1ms
53083  *  0b11..2ms
53084  */
53085 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
53086 
53087 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
53088 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
53089 /*! XTALOSC_PWRUP_STAT
53090  *  0b0..Not stable
53091  *  0b1..Stable and ready to use
53092  */
53093 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
53094 
53095 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
53096 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
53097 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
53098 
53099 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
53100 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
53101 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
53102 /*! @} */
53103 
53104 /*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */
53105 /*! @{ */
53106 
53107 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
53108 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
53109 /*! RC_OSC_EN
53110  *  0b0..Use XTAL OSC to source the 24MHz clock
53111  *  0b1..Use RC OSC
53112  */
53113 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
53114 
53115 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK  (0x10U)
53116 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
53117 /*! OSC_SEL
53118  *  0b0..XTAL OSC
53119  *  0b1..RC OSC
53120  */
53121 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
53122 
53123 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
53124 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
53125 /*! LPBG_SEL
53126  *  0b0..Normal power bandgap
53127  *  0b1..Low power bandgap
53128  */
53129 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
53130 
53131 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
53132 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
53133 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
53134 
53135 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
53136 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
53137 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
53138 
53139 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
53140 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
53141 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
53142 
53143 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
53144 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
53145 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
53146 
53147 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
53148 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
53149 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
53150 
53151 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
53152 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
53153 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
53154 
53155 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
53156 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
53157 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
53158 
53159 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
53160 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
53161 /*! XTALOSC_PWRUP_DELAY
53162  *  0b00..0.25ms
53163  *  0b01..0.5ms
53164  *  0b10..1ms
53165  *  0b11..2ms
53166  */
53167 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
53168 
53169 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
53170 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
53171 /*! XTALOSC_PWRUP_STAT
53172  *  0b0..Not stable
53173  *  0b1..Stable and ready to use
53174  */
53175 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
53176 
53177 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
53178 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
53179 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
53180 
53181 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
53182 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
53183 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
53184 /*! @} */
53185 
53186 /*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */
53187 /*! @{ */
53188 
53189 #define XTALOSC24M_OSC_CONFIG0_START_MASK        (0x1U)
53190 #define XTALOSC24M_OSC_CONFIG0_START_SHIFT       (0U)
53191 #define XTALOSC24M_OSC_CONFIG0_START(x)          (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
53192 
53193 #define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK       (0x2U)
53194 #define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT      (1U)
53195 #define XTALOSC24M_OSC_CONFIG0_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
53196 
53197 #define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK       (0x4U)
53198 #define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT      (2U)
53199 #define XTALOSC24M_OSC_CONFIG0_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
53200 
53201 #define XTALOSC24M_OSC_CONFIG0_INVERT_MASK       (0x8U)
53202 #define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT      (3U)
53203 #define XTALOSC24M_OSC_CONFIG0_INVERT(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
53204 
53205 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK  (0xFF0U)
53206 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
53207 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
53208 
53209 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK    (0xF000U)
53210 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT   (12U)
53211 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
53212 
53213 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK   (0xF0000U)
53214 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT  (16U)
53215 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
53216 
53217 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53218 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
53219 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
53220 /*! @} */
53221 
53222 /*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */
53223 /*! @{ */
53224 
53225 #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK    (0x1U)
53226 #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT   (0U)
53227 #define XTALOSC24M_OSC_CONFIG0_SET_START(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
53228 
53229 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK   (0x2U)
53230 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT  (1U)
53231 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
53232 
53233 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK   (0x4U)
53234 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT  (2U)
53235 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
53236 
53237 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK   (0x8U)
53238 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT  (3U)
53239 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
53240 
53241 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
53242 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
53243 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
53244 
53245 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
53246 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
53247 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
53248 
53249 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
53250 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
53251 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
53252 
53253 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53254 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
53255 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
53256 /*! @} */
53257 
53258 /*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */
53259 /*! @{ */
53260 
53261 #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK    (0x1U)
53262 #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT   (0U)
53263 #define XTALOSC24M_OSC_CONFIG0_CLR_START(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
53264 
53265 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK   (0x2U)
53266 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT  (1U)
53267 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
53268 
53269 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK   (0x4U)
53270 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT  (2U)
53271 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
53272 
53273 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK   (0x8U)
53274 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT  (3U)
53275 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
53276 
53277 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
53278 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
53279 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
53280 
53281 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
53282 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
53283 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
53284 
53285 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
53286 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
53287 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
53288 
53289 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53290 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
53291 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
53292 /*! @} */
53293 
53294 /*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */
53295 /*! @{ */
53296 
53297 #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK    (0x1U)
53298 #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT   (0U)
53299 #define XTALOSC24M_OSC_CONFIG0_TOG_START(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
53300 
53301 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK   (0x2U)
53302 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT  (1U)
53303 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
53304 
53305 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK   (0x4U)
53306 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT  (2U)
53307 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
53308 
53309 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK   (0x8U)
53310 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT  (3U)
53311 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
53312 
53313 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
53314 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
53315 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
53316 
53317 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
53318 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
53319 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
53320 
53321 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
53322 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
53323 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
53324 
53325 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53326 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
53327 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
53328 /*! @} */
53329 
53330 /*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */
53331 /*! @{ */
53332 
53333 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
53334 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
53335 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
53336 
53337 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
53338 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
53339 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
53340 /*! @} */
53341 
53342 /*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */
53343 /*! @{ */
53344 
53345 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
53346 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
53347 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
53348 
53349 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
53350 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
53351 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
53352 /*! @} */
53353 
53354 /*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */
53355 /*! @{ */
53356 
53357 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
53358 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
53359 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
53360 
53361 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
53362 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
53363 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
53364 /*! @} */
53365 
53366 /*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */
53367 /*! @{ */
53368 
53369 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
53370 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
53371 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
53372 
53373 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
53374 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
53375 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
53376 /*! @} */
53377 
53378 /*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */
53379 /*! @{ */
53380 
53381 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
53382 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
53383 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
53384 
53385 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK    (0x10000U)
53386 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT   (16U)
53387 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
53388 
53389 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK       (0x20000U)
53390 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT      (17U)
53391 #define XTALOSC24M_OSC_CONFIG2_MUX_1M(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
53392 
53393 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
53394 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
53395 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
53396 /*! @} */
53397 
53398 /*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */
53399 /*! @{ */
53400 
53401 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
53402 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
53403 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
53404 
53405 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
53406 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
53407 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
53408 
53409 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK   (0x20000U)
53410 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT  (17U)
53411 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
53412 
53413 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
53414 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
53415 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
53416 /*! @} */
53417 
53418 /*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */
53419 /*! @{ */
53420 
53421 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
53422 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
53423 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
53424 
53425 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
53426 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
53427 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
53428 
53429 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK   (0x20000U)
53430 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT  (17U)
53431 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
53432 
53433 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
53434 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
53435 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
53436 /*! @} */
53437 
53438 /*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */
53439 /*! @{ */
53440 
53441 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
53442 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
53443 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
53444 
53445 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
53446 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
53447 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
53448 
53449 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK   (0x20000U)
53450 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT  (17U)
53451 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
53452 
53453 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
53454 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
53455 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)
53456 /*! @} */
53457 
53458 
53459 /*!
53460  * @}
53461  */ /* end of group XTALOSC24M_Register_Masks */
53462 
53463 
53464 /* XTALOSC24M - Peripheral instance base addresses */
53465 /** Peripheral XTALOSC24M base address */
53466 #define XTALOSC24M_BASE                          (0x400D8000u)
53467 /** Peripheral XTALOSC24M base pointer */
53468 #define XTALOSC24M                               ((XTALOSC24M_Type *)XTALOSC24M_BASE)
53469 /** Array initializer of XTALOSC24M peripheral base addresses */
53470 #define XTALOSC24M_BASE_ADDRS                    { XTALOSC24M_BASE }
53471 /** Array initializer of XTALOSC24M peripheral base pointers */
53472 #define XTALOSC24M_BASE_PTRS                     { XTALOSC24M }
53473 
53474 /*!
53475  * @}
53476  */ /* end of group XTALOSC24M_Peripheral_Access_Layer */
53477 
53478 
53479 /*
53480 ** End of section using anonymous unions
53481 */
53482 
53483 #if defined(__ARMCC_VERSION)
53484   #if (__ARMCC_VERSION >= 6010050)
53485     #pragma clang diagnostic pop
53486   #else
53487     #pragma pop
53488   #endif
53489 #elif defined(__CWCC__)
53490   #pragma pop
53491 #elif defined(__GNUC__)
53492   /* leave anonymous unions enabled */
53493 #elif defined(__IAR_SYSTEMS_ICC__)
53494   #pragma language=default
53495 #else
53496   #error Not supported compiler type
53497 #endif
53498 
53499 /*!
53500  * @}
53501  */ /* end of group Peripheral_access_layer */
53502 
53503 
53504 /* ----------------------------------------------------------------------------
53505    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
53506    ---------------------------------------------------------------------------- */
53507 
53508 /*!
53509  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
53510  * @{
53511  */
53512 
53513 #if defined(__ARMCC_VERSION)
53514   #if (__ARMCC_VERSION >= 6010050)
53515     #pragma clang system_header
53516   #endif
53517 #elif defined(__IAR_SYSTEMS_ICC__)
53518   #pragma system_include
53519 #endif
53520 
53521 /**
53522  * @brief Mask and left-shift a bit field value for use in a register bit range.
53523  * @param field Name of the register bit field.
53524  * @param value Value of the bit field.
53525  * @return Masked and shifted value.
53526  */
53527 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
53528 /**
53529  * @brief Mask and right-shift a register value to extract a bit field value.
53530  * @param field Name of the register bit field.
53531  * @param value Value of the register.
53532  * @return Masked and shifted bit field value.
53533  */
53534 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
53535 
53536 /*!
53537  * @}
53538  */ /* end of group Bit_Field_Generic_Macros */
53539 
53540 
53541 /* ----------------------------------------------------------------------------
53542    -- SDK Compatibility
53543    ---------------------------------------------------------------------------- */
53544 
53545 /*!
53546  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
53547  * @{
53548  */
53549 
53550 /* No SDK compatibility issues. */
53551 
53552 /*!
53553  * @}
53554  */ /* end of group SDK_Compatibility_Symbols */
53555 
53556 
53557 #endif  /* _MIMXRT1052_H_ */
53558
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