imxrt/include/fsl_flexspi_nor_config.h

0001 /*
0002  * Copyright 2017-2020 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  *
0007  * Based on file for EVKBIMSRT1050 with values for other EVKs integrated.
0008  */
0009
0010 #ifndef __FSL_FLEXSPI_NOR_CONFIG__
0011 #define __FSL_FLEXSPI_NOR_CONFIG__
0012
0013 #include <stdint.h>
0014 #include <stdbool.h>
0015 #include "fsl_common.h"
0016
0017 /*! @name Driver version */
0018 /*@{*/
0019 /*! @brief XIP_BOARD driver version 2.0.1. */
0020 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
0021 /*@}*/
0022
0023 /* FLEXSPI memory config block related defintions */
0024 #define FLEXSPI_CFG_BLK_TAG     (0x42464346UL) // ascii "FCFB" Big Endian
0025 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
0026 #define FLEXSPI_CFG_BLK_SIZE    (512)
0027
0028 /* FLEXSPI Feature related definitions */
0029 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
0030
0031 /* Lookup table related defintions */
0032 #define CMD_INDEX_READ        0
0033 #define CMD_INDEX_READSTATUS  1
0034 #define CMD_INDEX_WRITEENABLE 2
0035 #define CMD_INDEX_WRITE       4
0036
0037 #define CMD_LUT_SEQ_IDX_READ        0
0038 #define CMD_LUT_SEQ_IDX_READSTATUS  1
0039 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3
0040 #define CMD_LUT_SEQ_IDX_WRITE       9
0041
0042 #define CMD_SDR        0x01
0043 #define CMD_DDR        0x21
0044 #define RADDR_SDR      0x02
0045 #define RADDR_DDR      0x22
0046 #define CADDR_SDR      0x03
0047 #define CADDR_DDR      0x23
0048 #define MODE1_SDR      0x04
0049 #define MODE1_DDR      0x24
0050 #define MODE2_SDR      0x05
0051 #define MODE2_DDR      0x25
0052 #define MODE4_SDR      0x06
0053 #define MODE4_DDR      0x26
0054 #define MODE8_SDR      0x07
0055 #define MODE8_DDR      0x27
0056 #define WRITE_SDR      0x08
0057 #define WRITE_DDR      0x28
0058 #define READ_SDR       0x09
0059 #define READ_DDR       0x29
0060 #define LEARN_SDR      0x0A
0061 #define LEARN_DDR      0x2A
0062 #define DATSZ_SDR      0x0B
0063 #define DATSZ_DDR      0x2B
0064 #define DUMMY_SDR      0x0C
0065 #define DUMMY_DDR      0x2C
0066 #define DUMMY_RWDS_SDR 0x0D
0067 #define DUMMY_RWDS_DDR 0x2D
0068 #define JMP_ON_CS      0x1F
0069 #define STOP           0
0070
0071 #define FLEXSPI_1PAD 0
0072 #define FLEXSPI_2PAD 1
0073 #define FLEXSPI_4PAD 2
0074 #define FLEXSPI_8PAD 3
0075
0076 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
0077     (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
0078      FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
0079
0080 //!@brief Definitions for FlexSPI Serial Clock Frequency
0081 typedef enum _FlexSpiSerialClockFreq
0082 {
0083     kFlexSpiSerialClk_30MHz  = 1,
0084     kFlexSpiSerialClk_50MHz  = 2,
0085     kFlexSpiSerialClk_60MHz  = 3,
0086 #if defined(MIMXRT1011_SERIES)
0087     kFlexSpiSerialClk_75MHz  = 4,
0088     kFlexSpiSerialClk_80MHz  = 5,
0089     kFlexSpiSerialClk_100MHz = 6,
0090     kFlexSpiSerialClk_120MHz = 7,
0091     kFlexSpiSerialClk_133MHz = 8,
0092 #elif defined(MIMXRT1015_SERIES) || defined(MIMXRT1021_SERIES) || defined(MIMXRT1024_SERIES)
0093     kFlexSpiSerialClk_75MHz  = 4,
0094     kFlexSpiSerialClk_80MHz  = 5,
0095     kFlexSpiSerialClk_100MHz = 6,
0096     kFlexSpiSerialClk_133MHz = 7,
0097 #elif defined(MIMXRT1052_SERIES)
0098     kFlexSpiSerialClk_75MHz  = 4,
0099     kFlexSpiSerialClk_80MHz  = 5,
0100     kFlexSpiSerialClk_100MHz = 6,
0101     kFlexSpiSerialClk_133MHz = 7,
0102     kFlexSpiSerialClk_166MHz = 8,
0103 #elif defined(MIMXRT1042_SERIES) || defined(MIMXRT1062_SERIES) || defined(MIMXRT1064_SERIES)
0104     kFlexSpiSerialClk_75MHz  = 4,
0105     kFlexSpiSerialClk_80MHz  = 5,
0106     kFlexSpiSerialClk_100MHz = 6,
0107     kFlexSpiSerialClk_120MHz = 7,
0108     kFlexSpiSerialClk_133MHz = 8,
0109     kFlexSpiSerialClk_166MHz = 9,
0110 #elif defined(MIMXRT1166_cm4_SERIES) || defined(MIMXRT1166_cm7_SERIES) || \
0111       defined(MIMXRT1176_cm4_SERIES) || defined(MIMXRT1176_cm7_SERIES)
0112     kFlexSpiSerialClk_80MHz  = 4,
0113     kFlexSpiSerialClk_100MHz = 5,
0114     kFlexSpiSerialClk_120MHz = 6,
0115     kFlexSpiSerialClk_133MHz = 7,
0116     kFlexSpiSerialClk_166MHz = 8,
0117     kFlexSpiSerialClk_200MHz = 9,
0118 #endif
0119 } flexspi_serial_clk_freq_t;
0120
0121 //!@brief FlexSPI clock configuration type
0122 enum
0123 {
0124     kFlexSpiClk_SDR, //!< Clock configure for SDR mode
0125     kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
0126 };
0127
0128 //!@brief FlexSPI Read Sample Clock Source definition
0129 typedef enum _FlashReadSampleClkSource
0130 {
0131     kFlexSPIReadSampleClk_LoopbackInternally      = 0,
0132     kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
0133     kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
0134     kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
0135 } flexspi_read_sample_clk_t;
0136
0137 //!@brief Misc feature bit definitions
0138 enum
0139 {
0140     kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
0141     kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
0142     kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
0143     kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
0144     kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
0145     kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
0146     kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
0147 };
0148
0149 //!@brief Flash Type Definition
0150 enum
0151 {
0152     kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
0153     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
0154     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
0155     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
0156     kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
0157 };
0158
0159 //!@brief Flash Pad Definitions
0160 enum
0161 {
0162     kSerialFlash_1Pad  = 1,
0163     kSerialFlash_2Pads = 2,
0164     kSerialFlash_4Pads = 4,
0165     kSerialFlash_8Pads = 8,
0166 };
0167
0168 //!@brief FlexSPI LUT Sequence structure
0169 typedef struct _lut_sequence
0170 {
0171     uint8_t seqNum; //!< Sequence Number, valid number: 1-16
0172     uint8_t seqId;  //!< Sequence Index, valid number: 0-15
0173     uint16_t reserved;
0174 } flexspi_lut_seq_t;
0175
0176 //!@brief Flash Configuration Command Type
0177 enum
0178 {
0179     kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
0180     kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
0181     kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
0182     kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
0183     kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
0184     kDeviceConfigCmdType_Reset,      //!< Reset device command
0185 };
0186
0187 //!@brief FlexSPI Memory Configuration Block
0188 typedef struct _FlexSPIConfig
0189 {
0190     uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
0191     uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
0192     uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
0193     uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
0194     uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
0195     uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
0196     uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
0197     //! Serial NAND, need to refer to datasheet
0198     uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
0199     uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
0200     //! Generic configuration, etc.
0201     uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
0202     //! DPI/QPI/OPI switch or reset command
0203     flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
0204     //! sequence number, [31:16] Reserved
0205     uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
0206     uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
0207     uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
0208     flexspi_lut_seq_t
0209         configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
0210     uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
0211     uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
0212     uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
0213     uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
0214     //! details
0215     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
0216     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
0217     uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
0218     //! Chapter for more details
0219     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
0220     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
0221     uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
0222     uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
0223     uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
0224     uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
0225     uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
0226     uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
0227     uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
0228     uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
0229     uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
0230     uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
0231     uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
0232     uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
0233     uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
0234     uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
0235     //! busy flag is 0 when flash device is busy
0236     uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
0237     flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
0238     uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
0239 } flexspi_mem_config_t;
0240
0241 /*  */
0242 #define NOR_CMD_INDEX_READ        CMD_INDEX_READ        //!< 0
0243 #define NOR_CMD_INDEX_READSTATUS  CMD_INDEX_READSTATUS  //!< 1
0244 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
0245 #define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
0246 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
0247 #define NOR_CMD_INDEX_CHIPERASE   5                     //!< 5
0248 #define NOR_CMD_INDEX_DUMMY       6                     //!< 6
0249 #define NOR_CMD_INDEX_ERASEBLOCK  7                     //!< 7
0250
0251 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
0252 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
0253     CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
0254 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
0255     2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
0256 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
0257     CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
0258 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
0259     4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
0260 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
0261 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK  8 //!< 8 Erase Block sequence id in lookupTable stored in config block
0262 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
0263     CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
0264 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
0265 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
0266 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
0267     14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
0268 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
0269     15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
0270
0271 /*
0272  *  Serial NOR configuration block
0273  */
0274 typedef struct _flexspi_nor_config
0275 {
0276     flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
0277     uint32_t pageSize;              //!< Page size of Serial NOR
0278     uint32_t sectorSize;            //!< Sector size of Serial NOR
0279     uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
0280     uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
0281     uint8_t isDataOrderSwapped;     //!< The data order is swapped in OPI DDR mode (only i.MXRT11*)
0282     uint8_t reserved0;              //!< Reserved for future use
0283     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
0284     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
0285     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
0286     uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
0287     uint32_t blockSize;             //!< Block size
0288     uint32_t FlashStateCtx;         //!< Flash State Context after being configured (only i.MXRT11*)
0289     uint32_t reserve2[10];          //!< Reserved for future use
0290 } flexspi_nor_config_t;
0291
0292 #ifdef __cplusplus
0293 extern "C" {
0294 #endif
0295
0296 #ifdef __cplusplus
0297 }
0298 #endif
0299 #endif /* __FSL_FLEXSPI_NOR_CONFIG__ */