boards/evkbimxrt1050/clock_config.c

0001 /*
0002  * Copyright 2017-2019 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007
0008 /*
0009  * How to setup clock using clock driver functions:
0010  *
0011  * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
0012  *
0013  * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
0014  *
0015  * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
0016  *
0017  * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
0018  *
0019  * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
0020  *
0021  */
0022
0023 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
0024 !!GlobalInfo
0025 product: Clocks v5.0
0026 processor: MIMXRT1052xxxxB
0027 package_id: MIMXRT1052DVL6B
0028 mcu_data: ksdk2_0
0029 processor_version: 0.0.0
0030 board: IMXRT1050-EVKB
0031  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
0032
0033 #ifndef __rtems__
0034 #include "clock_config.h"
0035 #else /* __rtems__ */
0036 #include <bspopts.h>
0037 #include "fsl_clock_config.h"
0038 #endif /* __rtems__ */
0039 #include "fsl_iomuxc.h"
0040
0041 /*******************************************************************************
0042  * Definitions
0043  ******************************************************************************/
0044
0045 /*******************************************************************************
0046  * Variables
0047  ******************************************************************************/
0048 /* System clock frequency. */
0049 #ifndef __rtems__
0050 extern uint32_t SystemCoreClock;
0051 #else /* __rtems__ */
0052 uint32_t SystemCoreClock;
0053 #endif /* __rtems__ */
0054
0055 /*******************************************************************************
0056  ************************ BOARD_InitBootClocks function ************************
0057  ******************************************************************************/
0058 void BOARD_InitBootClocks(void)
0059 {
0060     BOARD_BootClockRUN();
0061 }
0062
0063 /*******************************************************************************
0064  ********************** Configuration BOARD_BootClockRUN ***********************
0065  ******************************************************************************/
0066 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
0067 !!Configuration
0068 name: BOARD_BootClockRUN
0069 called_from_default_init: true
0070 outputs:
0071 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
0072 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
0073 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
0074 - {id: CLK_1M.outFreq, value: 1 MHz}
0075 - {id: CLK_24M.outFreq, value: 24 MHz}
0076 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
0077 - {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
0078 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
0079 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
0080 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
0081 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
0082 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
0083 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
0084 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
0085 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
0086 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
0087 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
0088 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
0089 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
0090 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
0091 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
0092 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
0093 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
0094 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
0095 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
0096 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
0097 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
0098 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
0099 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
0100 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
0101 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
0102 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
0103 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
0104 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
0105 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
0106 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
0107 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
0108 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
0109 settings:
0110 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
0111 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
0112 - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
0113 - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
0114 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
0115 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
0116 - {id: CCM.SEMC_PODF.scale, value: '8'}
0117 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
0118 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
0119 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
0120 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
0121 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
0122 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
0123 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
0124 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
0125 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
0126 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
0127 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
0128 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
0129 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
0130 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
0131 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
0132 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
0133 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
0134 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
0135 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
0136 - {id: CCM_ANALOG.PLL4.div, value: '47'}
0137 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
0138 - {id: CCM_ANALOG.PLL5.div, value: '40'}
0139 - {id: CCM_ANALOG.PLL5.num, value: '0'}
0140 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
0141 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
0142 sources:
0143 - {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
0144 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
0145  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
0146
0147 /*******************************************************************************
0148  * Variables for BOARD_BootClockRUN configuration
0149  ******************************************************************************/
0150 #ifndef __rtems__
0151 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
0152     .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
0153     .src         = 0,   /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
0154 };
0155 #else /* __rtems__ */
0156 /*
0157  * Moved to bsps/arm/imxrt/start/clock-arm-pll-config.c so an application can
0158  * overwrite it.
0159  */
0160 #endif /* __rtems__ */
0161 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
0162     .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
0163     .numerator   = 0, /* 30 bit numerator of fractional loop divider */
0164     .denominator = 1, /* 30 bit denominator of fractional loop divider */
0165     .src         = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
0166 };
0167 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
0168     .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
0169     .src         = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
0170 };
0171 /*******************************************************************************
0172  * Code for BOARD_BootClockRUN configuration
0173  ******************************************************************************/
0174 void BOARD_BootClockRUN(void)
0175 {
0176     /* Init RTC OSC clock frequency. */
0177     CLOCK_SetRtcXtalFreq(32768U);
0178     /* Enable 1MHz clock output. */
0179     XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
0180     /* Use free 1MHz clock output. */
0181     XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
0182     /* Set XTAL 24MHz clock frequency. */
0183     CLOCK_SetXtalFreq(24000000U);
0184     /* Enable XTAL 24MHz clock source. */
0185     CLOCK_InitExternalClk(0);
0186     /* Enable internal RC. */
0187     CLOCK_InitRcOsc24M();
0188     /* Switch clock source to external OSC. */
0189     CLOCK_SwitchOsc(kCLOCK_XtalOsc);
0190     /* Set Oscillator ready counter value. */
0191     CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
0192     /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
0193     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
0194     CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
0195     /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
0196     DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
0197     /* Waiting for DCDC_STS_DC_OK bit is asserted */
0198     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
0199     {
0200     }
0201     /* Set AHB_PODF. */
0202     CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
0203     /* Disable IPG clock gate. */
0204     CLOCK_DisableClock(kCLOCK_Adc1);
0205     CLOCK_DisableClock(kCLOCK_Adc2);
0206     CLOCK_DisableClock(kCLOCK_Xbar1);
0207     CLOCK_DisableClock(kCLOCK_Xbar2);
0208     CLOCK_DisableClock(kCLOCK_Xbar3);
0209     /* Set IPG_PODF. */
0210     CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
0211     /* Set ARM_PODF. */
0212     CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
0213     /* Set PERIPH_CLK2_PODF. */
0214     CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
0215     /* Disable PERCLK clock gate. */
0216     CLOCK_DisableClock(kCLOCK_Gpt1);
0217     CLOCK_DisableClock(kCLOCK_Gpt1S);
0218     CLOCK_DisableClock(kCLOCK_Gpt2);
0219     CLOCK_DisableClock(kCLOCK_Gpt2S);
0220     CLOCK_DisableClock(kCLOCK_Pit);
0221     /* Set PERCLK_PODF. */
0222     CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
0223     /* Disable USDHC1 clock gate. */
0224     CLOCK_DisableClock(kCLOCK_Usdhc1);
0225     /* Set USDHC1_PODF. */
0226     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
0227     /* Set Usdhc1 clock source. */
0228     CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
0229     /* Disable USDHC2 clock gate. */
0230     CLOCK_DisableClock(kCLOCK_Usdhc2);
0231     /* Set USDHC2_PODF. */
0232     CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
0233     /* Set Usdhc2 clock source. */
0234     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
0235 #ifndef __rtems__
0236 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
0237  * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
0238  * unchanged.
0239  * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
0240 #ifndef SKIP_SYSCLK_INIT
0241     /* Disable Semc clock gate. */
0242     CLOCK_DisableClock(kCLOCK_Semc);
0243     /* Set SEMC_PODF. */
0244     CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
0245     /* Set Semc alt clock source. */
0246     CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
0247     /* Set Semc clock source. */
0248     CLOCK_SetMux(kCLOCK_SemcMux, 0);
0249 #endif
0250 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
0251  * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
0252  * unchanged.
0253  * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
0254 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
0255     /* Disable Flexspi clock gate. */
0256     CLOCK_DisableClock(kCLOCK_FlexSpi);
0257     /* Set FLEXSPI_PODF. */
0258     CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
0259     /* Set Flexspi clock source. */
0260     CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
0261 #endif
0262 #endif /* __rtems__ */
0263     /* Disable CSI clock gate. */
0264     CLOCK_DisableClock(kCLOCK_Csi);
0265     /* Set CSI_PODF. */
0266     CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
0267     /* Set Csi clock source. */
0268     CLOCK_SetMux(kCLOCK_CsiMux, 0);
0269     /* Disable LPSPI clock gate. */
0270     CLOCK_DisableClock(kCLOCK_Lpspi1);
0271     CLOCK_DisableClock(kCLOCK_Lpspi2);
0272     CLOCK_DisableClock(kCLOCK_Lpspi3);
0273     CLOCK_DisableClock(kCLOCK_Lpspi4);
0274     /* Set LPSPI_PODF. */
0275     CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
0276     /* Set Lpspi clock source. */
0277     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
0278     /* Disable TRACE clock gate. */
0279     CLOCK_DisableClock(kCLOCK_Trace);
0280     /* Set TRACE_PODF. */
0281     CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
0282     /* Set Trace clock source. */
0283     CLOCK_SetMux(kCLOCK_TraceMux, 2);
0284     /* Disable SAI1 clock gate. */
0285     CLOCK_DisableClock(kCLOCK_Sai1);
0286     /* Set SAI1_CLK_PRED. */
0287     CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
0288     /* Set SAI1_CLK_PODF. */
0289     CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
0290     /* Set Sai1 clock source. */
0291     CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
0292     /* Disable SAI2 clock gate. */
0293     CLOCK_DisableClock(kCLOCK_Sai2);
0294     /* Set SAI2_CLK_PRED. */
0295     CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
0296     /* Set SAI2_CLK_PODF. */
0297     CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
0298     /* Set Sai2 clock source. */
0299     CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
0300     /* Disable SAI3 clock gate. */
0301     CLOCK_DisableClock(kCLOCK_Sai3);
0302     /* Set SAI3_CLK_PRED. */
0303     CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
0304     /* Set SAI3_CLK_PODF. */
0305     CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
0306     /* Set Sai3 clock source. */
0307     CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
0308     /* Disable Lpi2c clock gate. */
0309     CLOCK_DisableClock(kCLOCK_Lpi2c1);
0310     CLOCK_DisableClock(kCLOCK_Lpi2c2);
0311     CLOCK_DisableClock(kCLOCK_Lpi2c3);
0312     /* Set LPI2C_CLK_PODF. */
0313     CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
0314     /* Set Lpi2c clock source. */
0315     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
0316     /* Disable CAN clock gate. */
0317     CLOCK_DisableClock(kCLOCK_Can1);
0318     CLOCK_DisableClock(kCLOCK_Can2);
0319     CLOCK_DisableClock(kCLOCK_Can1S);
0320     CLOCK_DisableClock(kCLOCK_Can2S);
0321     /* Set CAN_CLK_PODF. */
0322     CLOCK_SetDiv(kCLOCK_CanDiv, 1);
0323     /* Set Can clock source. */
0324     CLOCK_SetMux(kCLOCK_CanMux, 2);
0325     /* Disable UART clock gate. */
0326     CLOCK_DisableClock(kCLOCK_Lpuart1);
0327     CLOCK_DisableClock(kCLOCK_Lpuart2);
0328     CLOCK_DisableClock(kCLOCK_Lpuart3);
0329     CLOCK_DisableClock(kCLOCK_Lpuart4);
0330     CLOCK_DisableClock(kCLOCK_Lpuart5);
0331     CLOCK_DisableClock(kCLOCK_Lpuart6);
0332     CLOCK_DisableClock(kCLOCK_Lpuart7);
0333     CLOCK_DisableClock(kCLOCK_Lpuart8);
0334     /* Set UART_CLK_PODF. */
0335     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
0336     /* Set Uart clock source. */
0337     CLOCK_SetMux(kCLOCK_UartMux, 0);
0338     /* Disable LCDIF clock gate. */
0339     CLOCK_DisableClock(kCLOCK_LcdPixel);
0340     /* Set LCDIF_PRED. */
0341     CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
0342     /* Set LCDIF_CLK_PODF. */
0343     CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
0344     /* Set Lcdif pre clock source. */
0345     CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
0346     /* Disable SPDIF clock gate. */
0347     CLOCK_DisableClock(kCLOCK_Spdif);
0348     /* Set SPDIF0_CLK_PRED. */
0349     CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
0350     /* Set SPDIF0_CLK_PODF. */
0351     CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
0352     /* Set Spdif clock source. */
0353     CLOCK_SetMux(kCLOCK_SpdifMux, 3);
0354     /* Disable Flexio1 clock gate. */
0355     CLOCK_DisableClock(kCLOCK_Flexio1);
0356     /* Set FLEXIO1_CLK_PRED. */
0357     CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
0358     /* Set FLEXIO1_CLK_PODF. */
0359     CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
0360     /* Set Flexio1 clock source. */
0361     CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
0362     /* Disable Flexio2 clock gate. */
0363     CLOCK_DisableClock(kCLOCK_Flexio2);
0364     /* Set FLEXIO2_CLK_PRED. */
0365     CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
0366     /* Set FLEXIO2_CLK_PODF. */
0367     CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
0368     /* Set Flexio2 clock source. */
0369     CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
0370     /* Set Pll3 sw clock source. */
0371     CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
0372     /* Init ARM PLL. */
0373     CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
0374 #ifndef __rtems__
0375     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
0376      * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
0377      * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
0378      * well.*/
0379 #ifndef SKIP_SYSCLK_INIT
0380     /* Init System PLL. */
0381     CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
0382     /* Init System pfd0. */
0383     CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
0384     /* Init System pfd1. */
0385     CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
0386     /* Init System pfd2. */
0387     CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
0388     /* Init System pfd3. */
0389     CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
0390     /* Disable pfd offset. */
0391     CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
0392 #endif
0393     /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
0394      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
0395      * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
0396      * well.*/
0397 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
0398     /* Init Usb1 PLL. */
0399     CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
0400     /* Init Usb1 pfd0. */
0401     CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
0402     /* Init Usb1 pfd1. */
0403     CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
0404     /* Init Usb1 pfd2. */
0405     CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
0406     /* Init Usb1 pfd3. */
0407     CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
0408     /* Disable Usb1 PLL output for USBPHY1. */
0409     CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
0410 #endif
0411 #endif /* __rtems__ */
0412     /* DeInit Audio PLL. */
0413     CLOCK_DeinitAudioPll();
0414     /* Bypass Audio PLL. */
0415     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
0416     /* Set divider for Audio PLL. */
0417     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
0418     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
0419     /* Enable Audio PLL output. */
0420     CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
0421     /* DeInit Video PLL. */
0422     CLOCK_DeinitVideoPll();
0423     /* Bypass Video PLL. */
0424     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
0425     /* Set divider for Video PLL. */
0426     CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
0427     /* Enable Video PLL output. */
0428     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
0429     /* DeInit Enet PLL. */
0430     CLOCK_DeinitEnetPll();
0431     /* Bypass Enet PLL. */
0432     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
0433     /* Set Enet output divider. */
0434     CCM_ANALOG->PLL_ENET =
0435         (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
0436     /* Enable Enet output. */
0437     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
0438     /* Enable Enet25M output. */
0439     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
0440     /* DeInit Usb2 PLL. */
0441     CLOCK_DeinitUsb2Pll();
0442     /* Bypass Usb2 PLL. */
0443     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
0444     /* Enable Usb2 PLL output. */
0445     CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
0446     /* Set preperiph clock source. */
0447     CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
0448     /* Set periph clock source. */
0449     CLOCK_SetMux(kCLOCK_PeriphMux, 0);
0450     /* Set periph clock2 clock source. */
0451     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
0452     /* Set per clock source. */
0453     CLOCK_SetMux(kCLOCK_PerclkMux, 0);
0454     /* Set lvds1 clock source. */
0455     CCM_ANALOG->MISC1 =
0456         (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
0457     /* Set clock out1 divider. */
0458     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
0459     /* Set clock out1 source. */
0460     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
0461     /* Set clock out2 divider. */
0462     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
0463     /* Set clock out2 source. */
0464     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
0465     /* Set clock out1 drives clock out1. */
0466     CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
0467     /* Disable clock out1. */
0468     CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
0469     /* Disable clock out2. */
0470     CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
0471     /* Set SAI1 MCLK1 clock source. */
0472     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
0473     /* Set SAI1 MCLK2 clock source. */
0474     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
0475     /* Set SAI1 MCLK3 clock source. */
0476     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
0477     /* Set SAI2 MCLK3 clock source. */
0478     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
0479     /* Set SAI3 MCLK3 clock source. */
0480     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
0481     /* Set MQS configuration. */
0482     IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
0483     /* Set ENET Tx clock source. */
0484     IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
0485     /* Set GPT1 High frequency reference clock source. */
0486     IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
0487     /* Set GPT2 High frequency reference clock source. */
0488     IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
0489     /* Set SystemCoreClock variable. */
0490     SystemCoreClock = 600000000U;
0491 }