imx/start/bspstarthooks.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
0029
0030 #include <bsp.h>
0031 #include <bsp/bootcard.h>
0032 #include <bsp/fdt.h>
0033 #include <bsp/linker-symbols.h>
0034 #include <bsp/start.h>
0035 #include <bsp/arm-cp15-start.h>
0036 #include <bsp/arm-a9mpcore-start.h>
0037
0038 #include <rtems/sysinit.h>
0039
0040 #include <libfdt.h>
0041
0042 BSP_START_DATA_SECTION static arm_cp15_start_section_config
0043 imx_mmu_config_table[] = {
0044   ARMV7_CP15_START_DEFAULT_SECTIONS,
0045   {
0046     .begin = 0x00a00000U,
0047     .end = 0x70000000U,
0048     .flags = ARMV7_MMU_DEVICE
0049   }
0050 };
0051
0052 BSP_START_DATA_SECTION static char memory_path[] = "/memory";
0053
0054 BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
0055 {
0056   const void *fdt;
0057   int node;
0058   uint32_t ctrl;
0059
0060   fdt = bsp_fdt_get();
0061   node = fdt_path_offset_namelen(
0062     fdt,
0063     memory_path,
0064     (int) sizeof(memory_path) - 1
0065   );
0066
0067   if (node >= 0) {
0068     int len;
0069     const void *val;
0070
0071     val = fdt_getprop(fdt, node, "reg", &len);
0072     if (len == 8) {
0073       uint32_t begin;
0074       uint32_t size;
0075
0076       begin = fdt32_to_cpu(((fdt32_t *) val)[0]);
0077       size = fdt32_to_cpu(((fdt32_t *) val)[1]);
0078
0079       /* The heap code does not like an end address of zero */
0080       if (begin + size == 0) {
0081         size -= 4;
0082       }
0083
0084       imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX].end =
0085         begin + size;
0086     }
0087   }
0088
0089   ctrl = arm_cp15_start_setup_mmu_and_cache(
0090     ARM_CP15_CTRL_A,
0091     ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
0092   );
0093
0094   arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
0095     ctrl,
0096     (uint32_t *) bsp_translation_table_base,
0097     ARM_MMU_DEFAULT_CLIENT_DOMAIN,
0098     &imx_mmu_config_table[0],
0099     RTEMS_ARRAY_SIZE(imx_mmu_config_table)
0100   );
0101 }
0102
0103 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
0104 {
0105 #ifdef RTEMS_SMP
0106   uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
0107
0108   arm_a9mpcore_start_enable_smp_in_auxiliary_control();
0109
0110   if (cpu_id != 0) {
0111     arm_a9mpcore_start_on_secondary_processor();
0112   }
0113 #endif
0114 }
0115
0116 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
0117 {
0118   bsp_start_copy_sections();
0119   setup_mmu_and_cache();
0120   bsp_start_clear_bss();
0121 }
0122
0123 static Memory_Area _Memory_Areas[1];
0124
0125 static void bsp_memory_initialize(void)
0126 {
0127   const arm_cp15_start_section_config *section;
0128
0129   section = &imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX];
0130   _Memory_Initialize(
0131     &_Memory_Areas[0],
0132     (void *) section->begin,
0133     (void *) section->end
0134   );
0135 }
0136
0137 RTEMS_SYSINIT_ITEM(
0138   bsp_memory_initialize,
0139   RTEMS_SYSINIT_MEMORY,
0140   RTEMS_SYSINIT_ORDER_MIDDLE
0141 );
0142
0143 static const Memory_Information _Memory_Information =
0144   MEMORY_INFORMATION_INITIALIZER(_Memory_Areas);
0145
0146 const Memory_Information *_Memory_Get(void)
0147 {
0148   return &_Memory_Information;
0149 }