imx/start/bspsmp.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2017 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <rtems/score/smpimpl.h>
0029
0030 #include <arm/freescale/imx/imx_srcreg.h>
0031 #include <arm/freescale/imx/imx_gpcreg.h>
0032
0033 #include <bsp/start.h>
0034
0035 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
0036 {
0037   bool started;
0038
0039   if (cpu_index == 1) {
0040     volatile imx_src *src = (volatile imx_src *) 0x30390000;
0041     volatile imx_gpc *gpc = (volatile imx_gpc *) 0x303a0000;
0042
0043     src->gpr3 = (uint32_t) _start;
0044     gpc->pgc_a7core0_ctrl |= IMX_GPC_PGC_CTRL_PCR;
0045     gpc->cpu_pgc_sw_pup_req |= IMX_GPC_CPU_PGC_CORE1_A7;
0046
0047     while ((gpc->cpu_pgc_pup_status1 & IMX_GPC_CPU_PGC_CORE1_A7) != 0) {
0048       /* Wait */
0049     }
0050
0051     gpc->pgc_a7core0_ctrl &= ~IMX_GPC_PGC_CTRL_PCR;
0052     src->a7rcr1 |= IMX_SRC_A7RCR1_A7_CORE1_ENABLE;
0053
0054     started = true;
0055   } else {
0056     started = false;
0057   }
0058
0059   return started;
0060 }