gumstix/start/start.S

0001 /*
0002  *  By Yang Xi <hiyangxi@gmail.com>.
0003  *  Based upon CSB337
0004  *
0005  *  The license and distribution terms for this file may be
0006  *  found in the file LICENSE in this distribution or at
0007  *  http://www.rtems.org/license/LICENSE.
0008  */
0009
0010 #include <rtems/asm.h>
0011 #include <rtems/score/cpu.h>
0012
0013 .text
0014 .globl  _start
0015 _start:
0016         /*
0017          * Since I don't plan to return to the bootloader,
0018          * I don't have to save the registers.
0019          */
0020
0021         /* Set end of interrupt stack area */
0022         ldr     r7, =_ISR_Stack_area_end
0023
0024         /* Enter FIQ mode and set up the FIQ stack pointer */
0025         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
0026         msr     cpsr, r0
0027         ldr     r1, =bsp_stack_fiq_size
0028         mov     sp, r7
0029         sub     r7, r7, r1
0030
0031         /* Enter ABT mode and set up the ABT stack pointer */
0032         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
0033         msr     cpsr, r0
0034         ldr     r1, =bsp_stack_abt_size
0035         mov     sp, r7
0036         sub     r7, r7, r1
0037
0038         /* Enter UND mode and set up the UND stack pointer */
0039         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
0040         msr     cpsr, r0
0041         ldr     r1, =bsp_stack_und_size
0042         mov     sp, r7
0043         sub     r7, r7, r1
0044
0045         /* Enter IRQ mode and set up the IRQ stack pointer */
0046         mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
0047         msr     cpsr, r0
0048         mov     sp, r7
0049
0050         /*
0051          * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
0052          * (interrupts are disabled).
0053          */
0054         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
0055         msr     cpsr, r0
0056         mov     sp, r7
0057
0058         /* Stay in SVC mode */
0059
0060         /* zero the bss */
0061         ldr     r1, =bsp_section_bss_end
0062         ldr     r0, =bsp_section_bss_begin
0063
0064 _bss_init:
0065         mov     r2, #0
0066         cmp     r0, r1
0067         strlot  r2, [r0], #4
0068         blo     _bss_init        /* loop while r0 < r1 */
0069
0070         /*
0071          * Initialize the MMU. After we return, the MMU is enabled,
0072          * and memory may be remapped. I hope we don't remap this
0073          * memory away.
0074          */
0075
0076     ldr     r0, =mem_map
0077     bl  mmu_init
0078
0079
0080
0081         /*
0082          * Initialize the exception vectors. This includes the
0083          * exceptions vectors (0x00000000-0x0000001c), and the
0084          * pointers to the exception handlers (0x00000020-0x0000003c).
0085          */
0086         mov     r0, #0
0087         adr     r1, vector_block
0088         ldmia   r1!, {r2-r9}
0089         stmia   r0!, {r2-r9}
0090         ldmia   r1!, {r2-r9}
0091         stmia   r0!, {r2-r9}
0092
0093
0094
0095         /* Now we are prepared to start the BSP's C code */
0096         mov     r0, #0
0097         bl      boot_card
0098
0099         /*
0100          * Theoretically, we could return to what started us up,
0101          * but we'd have to have saved the registers and stacks.
0102          * Instead, we'll just reset.
0103          */
0104         bl      bsp_reset
0105
0106         /* We shouldn't get here. If we do, hang */
0107 _hang:  b       _hang
0108
0109
0110 /*
0111  * This is the exception vector table and the pointers to
0112  * the functions that handle the exceptions. It's a total
0113  * of 16 words (64 bytes)
0114  */
0115 vector_block:
0116         ldr    pc, handler_addr_reset
0117         ldr    pc, handler_addr_undef
0118         ldr    pc, handler_addr_swi
0119         ldr    pc, handler_addr_prefetch
0120         ldr    pc, handler_addr_abort
0121         nop
0122         ldr    pc, handler_addr_irq
0123         ldr    pc, handler_addr_fiq
0124
0125 handler_addr_reset:
0126         .word  bsp_reset
0127
0128 handler_addr_undef:
0129         .word  _ARMV4_Exception_undef_default
0130
0131 handler_addr_swi:
0132         .word  _ARMV4_Exception_swi_default
0133
0134 handler_addr_prefetch:
0135         .word  _ARMV4_Exception_pref_abort_default
0136
0137 handler_addr_abort:
0138         .word  _ARMV4_Exception_data_abort_default
0139
0140 handler_addr_reserved:
0141         .word  0
0142
0143 handler_addr_irq:
0144         .word  _ARMV4_Exception_interrupt
0145
0146 handler_addr_fiq:
0147         .word  _ARMV4_Exception_fiq_default