gumstix/include/pxa255.h

0001 /*
0002  *  By Yang Xi <hiyangxi@gmail.com>.
0003  *
0004  *  The license and distribution terms for this file may be
0005  *  found in the file LICENSE in this distribution or at
0006  *  http://www.rtems.org/license/LICENSE.
0007  */
0008
0009 #ifndef __PXA_255_H__
0010 #define __PXA_255_H__
0011
0012 typedef unsigned int word_t;
0013
0014 /*Interrupt*/
0015
0016 #define PRIMARY_IRQS            32
0017 #define GPIO_IRQS               (85 - 2) /* The first two IRQs have level
0018                                             one interrupts */
0019 #define GPIO_IRQ                10
0020
0021 #define IRQS                    (PRIMARY_IRQS + GPIO_IRQS)
0022
0023 /* Interrupt Controller */
0024 #define INTERRUPT_OFFSET       0xd00000
0025 #define XSCALE_IRQ_OS_TIMER     26
0026 #define XSCALE_IRQ_PMU          12
0027 #define XSCALE_IRQ_STUART       20
0028 #define XSCALE_IRQ_NETWORK      16
0029
0030 #define PMU_IRQ             12
0031 #define CCNT_IRQ_ENABLE     1UL << 6
0032 #define PMN1_IRQ_ENABLE     1UL << 5
0033 #define PMN0_IRQ_ENABLE     1UL << 4
0034
0035 #define IODEVICE_VADDR      0x40000000
0036 #define XSCALE_INT              (IODEVICE_VADDR + INTERRUPT_OFFSET)
0037
0038 #define XSCALE_INT_ICMR         (*(volatile word_t *)(XSCALE_INT + 0x04))   /* Mask register */
0039 #define XSCALE_INT_ICLR         (*(volatile word_t *)(XSCALE_INT + 0x08))   /* FIQ / IRQ selection */
0040 #define XSCALE_INT_ICCR         (*(volatile word_t *)(XSCALE_INT + 0x14))   /* Control register */
0041 #define XSCALE_INT_ICIP         (*(volatile word_t *)(XSCALE_INT + 0x00))   /* IRQ pending */
0042 #define XSCALE_INT_ICFP         (*(volatile word_t *)(XSCALE_INT + 0x0c))   /* FIQ pending */
0043 #define XSCALE_INT_ICPR         (*(volatile word_t *)(XSCALE_INT + 0x10))   /* Pending (unmasked) */
0044
0045 /* GPIO */
0046 #define GPIO_OFFSET            0xe00000
0047 #define PXA_GPIO                (IODEVICE_VADDR + GPIO_OFFSET)
0048
0049 #define PXA_GEDR0       (*(volatile word_t *)(PXA_GPIO + 0x48))   /* GPIO edge detect 0 */
0050 #define PXA_GEDR1       (*(volatile word_t *)(PXA_GPIO + 0x4C))   /* GPIO edge detect 1 */
0051 #define PXA_GEDR2       (*(volatile word_t *)(PXA_GPIO + 0x50))   /* GPIO edge detect 2 */
0052
0053
0054 /* PXA2XX Timer */
0055
0056 #define TIMER_OFFSET           0x0a00000
0057 #define CLOCKS_OFFSET          0x1300000
0058 /*I change the TIMER_RATE to 36864,because when I use 3686400, the period will be calculate
0059   to 30000*/
0060 #define TIMER_RATE             36864
0061
0062 #define XSCALE_TIMERS           (IODEVICE_VADDR + TIMER_OFFSET)
0063
0064 /* Match registers */
0065 #define XSCALE_OS_TIMER_MR0     (*(volatile word_t *)(XSCALE_TIMERS + 0x00))
0066 #define XSCALE_OS_TIMER_MR1     (*(volatile word_t *)(XSCALE_TIMERS + 0x04))
0067 #define XSCALE_OS_TIMER_MR2     (*(volatile word_t *)(XSCALE_TIMERS + 0x08))
0068 #define XSCALE_OS_TIMER_MR3     (*(volatile word_t *)(XSCALE_TIMERS + 0x0c))
0069
0070 /* Interrupt enable register */
0071 #define XSCALE_OS_TIMER_IER     (*(volatile word_t *)(XSCALE_TIMERS + 0x1c))
0072 /* Watchdog match enable register */
0073 #define XSCALE_OS_TIMER_WMER    (*(volatile word_t *)(XSCALE_TIMERS + 0x18))
0074 /* Timer count register */
0075 #define XSCALE_OS_TIMER_TCR     (*(volatile word_t *)(XSCALE_TIMERS + 0x10))
0076 /* Timer status register */
0077 #define XSCALE_OS_TIMER_TSR     (*(volatile word_t *)(XSCALE_TIMERS + 0x14))
0078
0079 #define XSCALE_CLOCKS           (IODEVICE_VADDR + CLOCKS_VOFFSET)
0080
0081 #define XSCALE_CLOCKS_CCCR      (*(volatile word_t *)(XSCALE_CLOCKS + 0x00))
0082
0083 /*Use ffuart port as the console*/
0084 #define FFUART_BASE   0x40100000
0085
0086 /*Write to SKYEYE_MAGIC_ADDRESS to make SKYEYE  exit*/
0087
0088 #define SKYEYE_MAGIC_ADDRESS (*(volatile word_t *)(0xb0000000))
0089 #define SKYEYE_MAGIC_NUMBER  (0xf0f0f0f0)
0090
0091 /*PMC*/
0092 #define PMC_PMNC 0
0093 #define PMC_CCNT 1
0094 #define PMC_INTEN 2
0095 #define PMC_FLAG 3
0096 #define PMC_EVTSEL 4
0097 #define PMC_PMN0 5
0098 #define PMC_PMN1 6
0099 #define PMC_PMN2 7
0100 #define PMC_PMN3 8
0101
0102 #define PMC_PMNC_E (0x01)
0103 #define PMC_PMNC_PCR (0x01 << 1)
0104 #define PMC_PMNC_CCR (0x01 << 2)
0105 #define PMC_PMNC_CCD (0x01 << 3)
0106 #define PMC_PMNC_PCD (0x01 << 4)
0107
0108 /*LCD*/
0109 #define LCCR0  (*(volatile word_t *)(0x44000000))
0110 #define LCCR1  (*(volatile word_t *)(0x44000004))
0111 #define LCCR2  (*(volatile word_t *)(0x44000008))
0112 #define LCCR3  (*(volatile word_t *)(0x4400000C))
0113
0114 #define FDADR0  (*(volatile word_t *)(0x44000200))
0115 #define FSADR0  (*(volatile word_t *)(0x44000204))
0116 #define FIDR0   (*(volatile word_t *)(0x44000208))
0117 #define LDCMD0  (*(volatile word_t *)(0x4400020C))
0118
0119 #define FDADR1  (*(volatile word_t *)(0x44000210))
0120 #define FSADR1  (*(volatile word_t *)(0x44000214))
0121 #define FIDR1   (*(volatile word_t *)(0x44000218))
0122 #define LDCMD1  (*(volatile word_t *)(0x4400021C))
0123
0124 #define LCCR0_ENB       0x00000001
0125 #define LCCR1_PPL       0x000003FF
0126 #define LCCR2_LPP       0x000003FF
0127 #define LCCR3_BPP       0x07000000
0128 #endif