edb7312/start/start.S

0001 /*
0002  * Cirrus EP7312 Startup code
0003  *
0004  * Copyright (c) 2010 embedded brains GmbH & Co. KG
0005  *
0006  * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
0007  *
0008  * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
0009  *
0010  *  The license and distribution terms for this file may be
0011  *  found in the file LICENSE in this distribution or at
0012  *  http://www.rtems.org/license/LICENSE.
0013 */
0014
0015 #include <rtems/asm.h>
0016 #include <rtems/score/cpu.h>
0017
0018 .section ".bsp_start_text", "ax"
0019 .arm
0020
0021 /*******************************************************
0022  standard exception vectors table
0023  *** Must be located at address 0
0024 ********************************************************/
0025
0026 Vector_Init_Block:
0027         ldr    pc, handler_addr_reset
0028         ldr    pc, handler_addr_undef
0029         ldr    pc, handler_addr_swi
0030         ldr    pc, handler_addr_prefetch
0031         ldr    pc, handler_addr_abort
0032         nop
0033         ldr    pc, handler_addr_irq
0034         ldr    pc, handler_addr_fiq
0035
0036 handler_addr_reset:
0037         .word  _start
0038
0039 handler_addr_undef:
0040         .word  _ARMV4_Exception_undef_default
0041
0042 handler_addr_swi:
0043         .word  _ARMV4_Exception_swi_default
0044
0045 handler_addr_prefetch:
0046         .word  _ARMV4_Exception_pref_abort_default
0047
0048 handler_addr_abort:
0049         .word  _ARMV4_Exception_data_abort_default
0050
0051 handler_addr_reserved:
0052         .word  0
0053
0054 handler_addr_irq:
0055         .word  _ARMV4_Exception_interrupt
0056
0057 handler_addr_fiq:
0058         .word  _ARMV4_Exception_fiq_default
0059
0060     .globl  _start
0061 _start:
0062         /* Set end of interrupt stack area */
0063         ldr     r7, =_ISR_Stack_area_end
0064
0065         /* Enter FIQ mode and set up the FIQ stack pointer */
0066         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
0067         msr     cpsr, r0
0068         ldr     r1, =bsp_stack_fiq_size
0069         mov     sp, r7
0070         sub     r7, r7, r1
0071
0072         /* Enter ABT mode and set up the ABT stack pointer */
0073         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
0074         msr     cpsr, r0
0075         ldr     r1, =bsp_stack_abt_size
0076         mov     sp, r7
0077         sub     r7, r7, r1
0078
0079         /* Enter UND mode and set up the UND stack pointer */
0080         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
0081         msr     cpsr, r0
0082         ldr     r1, =bsp_stack_und_size
0083         mov     sp, r7
0084         sub     r7, r7, r1
0085
0086         /* Enter IRQ mode and set up the IRQ stack pointer */
0087         mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
0088         msr     cpsr, r0
0089         mov     sp, r7
0090
0091         /*
0092          * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
0093          * (interrupts are disabled).
0094          */
0095         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
0096         msr     cpsr, r0
0097         mov     sp, r7
0098
0099         /* Stay in SVC mode */
0100 /*
0101  * Here is the code to initialize the low-level BSP environment
0102  * (Chip Select, PLL, ....?)
0103  */
0104
0105 /* zero the bss */
0106         LDR     r1, =bsp_section_bss_end   /* get end of ZI region */
0107         LDR     r0, =bsp_section_bss_begin /* load base address of ZI region */
0108
0109 zi_init:
0110         MOV     r2, #0
0111         CMP     r0, r1             /* loop whilst r0 < r1 */
0112         STRLOT   r2, [r0], #4
0113         BLO     zi_init
0114
0115 /* --- Now we enter the C code */
0116
0117     mov     r0, #0
0118     bl  boot_card