edb7312/irq/irq.c

0001 /*
0002  * Cirrus EP7312 Intererrupt handler
0003  */
0004
0005 /*
0006  * Copyright (c) 2010 embedded brains GmbH & Co. KG
0007  *
0008  * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
0009  *
0010  * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
0011  *
0012  *  The license and distribution terms for this file may be
0013  *  found in the file LICENSE in this distribution or at
0014  *  http://www.rtems.org/license/LICENSE.
0015 */
0016
0017 #include <rtems/score/armv4.h>
0018
0019 #include <bsp.h>
0020 #include <bsp/irq.h>
0021 #include <bsp/irq-generic.h>
0022
0023 #include <ep7312.h>
0024
0025 void edb7312_interrupt_dispatch(rtems_vector_number vector)
0026 {
0027   bsp_interrupt_handler_dispatch(vector);
0028 }
0029
0030 rtems_status_code bsp_interrupt_get_attributes(
0031   rtems_vector_number         vector,
0032   rtems_interrupt_attributes *attributes
0033 )
0034 {
0035   return RTEMS_SUCCESSFUL;
0036 }
0037
0038 rtems_status_code bsp_interrupt_is_pending(
0039   rtems_vector_number vector,
0040   bool               *pending
0041 )
0042 {
0043   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0044   bsp_interrupt_assert(pending != NULL);
0045   *pending = false;
0046   return RTEMS_UNSATISFIED;
0047 }
0048
0049 rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
0050 {
0051   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0052   return RTEMS_UNSATISFIED;
0053 }
0054
0055 rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
0056 {
0057   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0058   return RTEMS_UNSATISFIED;
0059 }
0060
0061 rtems_status_code bsp_interrupt_vector_is_enabled(
0062   rtems_vector_number vector,
0063   bool               *enabled
0064 )
0065 {
0066   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0067   bsp_interrupt_assert(enabled != NULL);
0068   *enabled = false;
0069   return RTEMS_UNSATISFIED;
0070 }
0071
0072 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
0073 {
0074     bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0075
0076     if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
0077     {
0078         /* interrupt managed by INTMR1 and INTSR1 */
0079         *EP7312_INTMR1 |= (1 << vector);
0080     }
0081     else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
0082     {
0083         /* interrupt managed by INTMR2 and INTSR2 */
0084         *EP7312_INTMR2 |= (1 << (vector - 16));
0085     }
0086     else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
0087     {
0088         /* interrupt managed by INTMR2 and INTSR2 */
0089         *EP7312_INTMR2 |= (1 << (vector - 7));
0090     }
0091     else if(vector == BSP_DAIINT)
0092     {
0093         /* interrupt managed by INTMR3 and INTSR3 */
0094         *EP7312_INTMR3 |= (1 << (vector - 21));
0095     }
0096
0097     return RTEMS_SUCCESSFUL;
0098 }
0099
0100 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
0101 {
0102     bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0103
0104     if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
0105     {
0106         /* interrupt managed by INTMR1 and INTSR1 */
0107         *EP7312_INTMR1 &= ~(1 << vector);
0108     }
0109     else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
0110     {
0111         /* interrupt managed by INTMR2 and INTSR2 */
0112         *EP7312_INTMR2 &= ~(1 << (vector - 16));
0113     }
0114     else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
0115     {
0116         /* interrupt managed by INTMR2 and INTSR2 */
0117         *EP7312_INTMR2 &= ~(1 << (vector - 7));
0118     }
0119     else if(vector == BSP_DAIINT)
0120     {
0121         /* interrupt managed by INTMR3 and INTSR3 */
0122         *EP7312_INTMR3 &= ~(1 << (vector - 21));
0123     }
0124
0125     return RTEMS_SUCCESSFUL;
0126 }
0127
0128 rtems_status_code bsp_interrupt_set_priority(
0129   rtems_vector_number vector,
0130   uint32_t priority
0131 )
0132 {
0133   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0134   return RTEMS_UNSATISFIED;
0135 }
0136
0137 rtems_status_code bsp_interrupt_get_priority(
0138   rtems_vector_number vector,
0139   uint32_t *priority
0140 )
0141 {
0142   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0143   bsp_interrupt_assert(priority != NULL);
0144   return RTEMS_UNSATISFIED;
0145 }
0146
0147 void bsp_interrupt_facility_initialize(void)
0148 {
0149   uint32_t int_stat = 0;
0150
0151   /* mask all interrupts */
0152   *EP7312_INTMR1 = 0x0;
0153   *EP7312_INTMR2 = 0x0;
0154   *EP7312_INTMR3 = 0x0;
0155
0156   /* clear all pending interrupt status' */
0157   int_stat = *EP7312_INTSR1;
0158   if(int_stat & EP7312_INTR1_EXTFIQ)
0159   {
0160   }
0161   if(int_stat & EP7312_INTR1_BLINT)
0162   {
0163       *EP7312_BLEOI = 0xFFFFFFFF;
0164   }
0165   if(int_stat & EP7312_INTR1_WEINT)
0166   {
0167       *EP7312_TEOI = 0xFFFFFFFF;
0168   }
0169   if(int_stat & EP7312_INTR1_MCINT)
0170   {
0171   }
0172   if(int_stat & EP7312_INTR1_CSINT)
0173   {
0174       *EP7312_COEOI = 0xFFFFFFFF;
0175   }
0176   if(int_stat & EP7312_INTR1_EINT1)
0177   {
0178   }
0179   if(int_stat & EP7312_INTR1_EINT2)
0180   {
0181   }
0182   if(int_stat & EP7312_INTR1_EINT3)
0183   {
0184   }
0185   if(int_stat & EP7312_INTR1_TC1OI)
0186   {
0187       *EP7312_TC1EOI = 0xFFFFFFFF;
0188   }
0189   if(int_stat & EP7312_INTR1_TC2OI)
0190   {
0191       *EP7312_TC2EOI = 0xFFFFFFFF;
0192   }
0193   if(int_stat & EP7312_INTR1_RTCMI)
0194   {
0195       *EP7312_RTCEOI = 0xFFFFFFFF;
0196   }
0197   if(int_stat & EP7312_INTR1_TINT)
0198   {
0199       *EP7312_TEOI = 0xFFFFFFFF;
0200   }
0201   if(int_stat & EP7312_INTR1_URXINT1)
0202   {
0203   }
0204   if(int_stat & EP7312_INTR1_UTXINT1)
0205   {
0206   }
0207   if(int_stat & EP7312_INTR1_UMSINT)
0208   {
0209       *EP7312_UMSEOI = 0xFFFFFFFF;
0210   }
0211   if(int_stat & EP7312_INTR1_SSEOTI)
0212   {
0213       *EP7312_SYNCIO;
0214   }
0215   int_stat = *EP7312_INTSR1;
0216
0217   int_stat = *EP7312_INTSR2;
0218   if(int_stat & EP7312_INTR2_KBDINT)
0219   {
0220       *EP7312_KBDEOI = 0xFFFFFFFF;
0221   }
0222   if(int_stat & EP7312_INTR2_SS2RX)
0223   {
0224   }
0225   if(int_stat & EP7312_INTR2_SS2TX)
0226   {
0227   }
0228   if(int_stat & EP7312_INTR2_URXINT2)
0229   {
0230   }
0231   if(int_stat & EP7312_INTR2_UTXINT2)
0232   {
0233   }
0234   int_stat = *EP7312_INTSR2;
0235
0236   int_stat = *EP7312_INTSR3;
0237   if(int_stat & EP7312_INTR2_DAIINT)
0238   {
0239   }
0240   int_stat = *EP7312_INTSR3;
0241
0242   _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
0243 }