edb7312/include/uart.h

0001 /**
0002  *  @file
0003  *
0004  *  @ingroup arm_comm
0005  *
0006  *  @brief UART Support
0007  */
0008
0009 /*
0010  * This software is Copyright (C) 1998 by T.sqware - all rights limited
0011  * It is provided in to the public domain "as is", can be freely modified
0012  * as far as this copyight notice is kept unchanged, but does not imply
0013  * an endorsement by T.sqware of the product in which it is included.
0014  *
0015  * Copyright (c) Canon Research France SA.]
0016  * Emmanuel Raguet, mailto:raguet@crf.canon.fr
0017  *
0018  *  The license and distribution terms for this file may be
0019  *  found in the file LICENSE in this distribution or at
0020  *  http://www.rtems.org/license/LICENSE.
0021  */
0022
0023 #ifndef _BSPUART_H
0024 #define _BSPUART_H
0025
0026 #include <rtems/bspIo.h>
0027
0028 void BSP_uart_init(int uart, int baud, int hwFlow);
0029 void BSP_uart_set_baud(int aurt, int baud);
0030 void BSP_uart_intr_ctrl(int uart, int cmd);
0031 void BSP_uart_throttle(int uart);
0032 void BSP_uart_unthrottle(int uart);
0033 int  BSP_uart_polled_status(int uart);
0034 void BSP_uart_polled_write(int uart, int val);
0035 int  BSP_uart_polled_read(int uart);
0036 void BSP_uart_termios_set(int uart, void *ttyp);
0037 int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
0038 int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
0039 void BSP_uart_termios_isr_com1(void);
0040 void BSP_uart_termios_isr_com2(void);
0041 void BSP_uart_dbgisr_com1(void);
0042 void BSP_uart_dbgisr_com2(void);
0043 extern unsigned BSP_poll_char_via_serial(void);
0044 extern void BSP_output_char_via_serial(int val);
0045 extern int BSPConsolePort;
0046 extern int BSPBaseBaud;
0047 /*
0048  * Command values for BSP_uart_intr_ctrl(),
0049  * values are strange in order to catch errors
0050  * with assert
0051  */
0052 #define BSP_UART_INTR_CTRL_DISABLE  (0)
0053 #define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
0054 #define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
0055 #define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
0056
0057 /* Return values for uart_polled_status() */
0058 #define BSP_UART_STATUS_ERROR    (-1) /* No character */
0059 #define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
0060 #define BSP_UART_STATUS_CHAR     (1)  /* Character present */
0061 #define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
0062
0063 /* PC UART definitions */
0064 #define BSP_UART_COM1            (0)
0065 #define BSP_UART_COM2            (1)
0066
0067 /*
0068  * Base IO for UART
0069  */
0070
0071 #define COM1_BASE_IO    0x3F8
0072 #define COM2_BASE_IO    0x2F8
0073
0074 /*
0075  * Offsets from base
0076  */
0077
0078 /* DLAB 0 */
0079 #define RBR  RSRBR   /* Rx Buffer Register (read) */
0080 #define THR  RSTHR   /* Tx Buffer Register (write) */
0081 #define IER  RSIER   /* Interrupt Enable Register */
0082
0083 /* DLAB X */
0084 #define IIR  RSIIR   /* Interrupt Ident Register (read) */
0085 #define FCR  RSFCR   /* FIFO Control Register (write) */
0086 #define LCR  RSLCR   /* Line Control Register */
0087 #define LSR  RSLSR   /* Line Status Register */
0088
0089 /* DLAB 1 */
0090 #define DLL  RSDLL   /* Divisor Latch, LSB */
0091 #define DLM  RSDLH   /* Divisor Latch, MSB */
0092
0093 /* Uart control */
0094 #define CNT  RSCNT   /* General Control register */
0095
0096 /*
0097  * define bit for CNT
0098  */
0099 #define UART_ENABLE     1
0100 #define PAD_ENABLE  2
0101
0102 /*
0103  * Interrupt source definition via IIR
0104  */
0105 #define NO_MORE_INTR                1
0106 #define TRANSMITTER_HODING_REGISTER_EMPTY   2
0107 #define RECEIVER_DATA_AVAIL         4
0108 #define RECEIVER_ERROR              6
0109 #define CHARACTER_TIMEOUT_INDICATION        12
0110
0111 /*
0112  * Bits definition of IER
0113  */
0114 #define RECEIVE_ENABLE      0x1
0115 #define TRANSMIT_ENABLE     0x2
0116 #define RECEIVER_LINE_ST_ENABLE 0x4
0117 #define INTERRUPT_DISABLE   0x0
0118
0119 /*
0120  * Bits definition of the Line Status Register (LSR)
0121  */
0122 #define DR  0x01    /* Data Ready */
0123 #define OE  0x02    /* Overrun Error */
0124 #define PE  0x04    /* Parity Error */
0125 #define FE  0x08    /* Framing Error */
0126 #define BI  0x10    /* Break Interrupt */
0127 #define THRE    0x20    /* Transmitter Holding Register Empty */
0128 #define TEMT    0x40    /* Transmitter Empty */
0129 #define ERFIFO  0x80    /* Error receive Fifo */
0130
0131 /*
0132  * Bits definition of the Line Control Register (LCR)
0133  */
0134 #define CHR_5_BITS 0
0135 #define CHR_6_BITS 1
0136 #define CHR_7_BITS 2
0137 #define CHR_8_BITS 3
0138
0139 #define WL  0x03    /* Word length mask */
0140 #define STB 0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
0141 #define PEN 0x08    /* Parity Enabled */
0142 #define EPS 0x10    /* Even Parity Select, otherwise Odd */
0143 #define SP  0x20    /* Stick Parity */
0144 #define BCB 0x40    /* Break Control Bit */
0145 #define DLAB    0x80    /* Enable Divisor Latch Access */
0146
0147 /*
0148  * Bits definition of the FIFO Control Register : WD16C552 or NS16550
0149  */
0150
0151 #define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
0152 #define FIFO_EN     0x01    /* Enable the FIFO */
0153 #define XMIT_RESET  0x04    /* Transmit FIFO Reset */
0154 #define RCV_RESET   0x02    /* Receive FIFO Reset */
0155 #define FCR3        0x08    /* do not understand manual! */
0156
0157 #define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
0158 #define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
0159 #define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
0160 #define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 14 byte */
0161 #define TRIG_LEVEL          0xc0 /* Mask for the trigger level      */
0162
0163 #endif /* _BSPUART_H */