edb7312/include/ep7312.h

0001 /**
0002  * @file
0003  * @ingroup edb7312_registers
0004  * @brief Register declarations.
0005  */
0006
0007 /*
0008  * Cirrus EP7312 register declarations
0009  *
0010  * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
0011  *
0012  * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
0013  *
0014  *  The license and distribution terms for this file may be
0015  *  found in the file LICENSE in this distribution or at
0016  *  http://www.rtems.org/license/LICENSE.
0017  *
0018  *
0019  * Notes: The PLL registers (pll_ro and pll_wo) are either read only
0020  *        or write only. The data sheet says not to write the read
0021  *        only one or read the write only one. I'm not sure what will
0022  *        happen if you do.
0023 */
0024 #ifndef __EP7312_H__
0025 #define __EP7312_H__
0026
0027 #define EP7312_REG_BASE 0x80000000
0028
0029 /**
0030  * @defgroup edb7312_registers Register Definitions
0031  * @ingroup RTEMSBSPsARMEDB7312
0032  * @brief Cirrus EP7312 Register Definitions
0033  * @{
0034  */
0035
0036 #define EP7312_PADR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
0037 #define EP7312_PBDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001))
0038 #define EP7312_PDDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003))
0039 #define EP7312_PADDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040))
0040 #define EP7312_PBDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041))
0041 #define EP7312_PDDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043))
0042 #define EP7312_PEDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080))
0043 #define EP7312_PEDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0))
0044 #define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100))
0045 #define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140))
0046 #define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180))
0047 #define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0))
0048 #define EP7312_INTSR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240))
0049 #define EP7312_INTMR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280))
0050 #define EP7312_LCDCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0))
0051 #define EP7312_TC1D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300))
0052 #define EP7312_TC2D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340))
0053 #define EP7312_RTCDR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380))
0054 #define EP7312_RTCMR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0))
0055 #define EP7312_PMPCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400))
0056 #define EP7312_CODR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440))
0057 #define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480))
0058 #define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0))
0059 #define EP7312_SYNCIO  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500))
0060 #define EP7312_PALLSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540))
0061 #define EP7312_PALMSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580))
0062 #define EP7312_STFCLR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0))
0063 #define EP7312_BLEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600))
0064 #define EP7312_MCEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640))
0065 #define EP7312_TEOI    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680))
0066 #define EP7312_TC1EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0))
0067 #define EP7312_TC2EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700))
0068 #define EP7312_RTCEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740))
0069 #define EP7312_UMSEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780))
0070 #define EP7312_COEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0))
0071 #define EP7312_HALT    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800))
0072 #define EP7312_STDBY   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840))
0073 #define EP7312_FBADDR  ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000))
0074 #define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100))
0075 #define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140))
0076 #define EP7312_INTSR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240))
0077 #define EP7312_INTMR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280))
0078 #define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480))
0079 #define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0))
0080 #define EP7312_SS2DR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500))
0081 #define EP7312_SRXEOF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600))
0082 #define EP7312_SS2POP  ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0))
0083 #define EP7312_KBDEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700))
0084 #define EP7312_DAIR    ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000))
0085 #define EP7312_DAIDR0  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040))
0086 #define EP7312_DAIDR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080))
0087 #define EP7312_DAIDR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0))
0088 #define EP7312_DAISR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100))
0089 #define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200))
0090 #define EP7312_INTSR3  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240))
0091 #define EP7312_INTMR3  ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280))
0092 #define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0))
0093 #define EP7312_SDCONF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300))
0094 #define EP7312_SDRFPR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340))
0095 #define EP7312_UNIQID  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440))
0096 #define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600))
0097 #define EP7312_PLLW    ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610))
0098 #define EP7312_PLLR    ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8))
0099 #define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700))
0100 #define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704))
0101 #define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708))
0102 #define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C))
0103
0104 /* serial port bits */
0105
0106 /**
0107  * @name BITS in UBRLCR1
0108  * @{
0109  */
0110
0111 #define EP7312_UART_WRDLEN5    0x00000000
0112 #define EP7312_UART_WRDLEN6    0x00020000
0113 #define EP7312_UART_WRDLEN7    0x00040000
0114 #define EP7312_UART_WRDLEN8    0x00060000
0115 #define EP7312_UART_FIFOEN     0x00010000
0116 #define EP7312_UART_XSTOP      0x00008000
0117 #define EP7312_UART_EVENPRT    0x00004000
0118 #define EP7312_UART_PRTEN      0x00002000
0119 #define EP7312_UART_BREAK      0x00001000
0120
0121 /** @} */
0122
0123 /**
0124  * @name BITS in INTSR1
0125  * @{
0126  */
0127
0128 #define EP7312_UART_UTXINT1    0x00002000
0129 #define EP7312_UART_URXINT1    0x00001000
0130
0131 /** @} */
0132
0133 /**
0134  * @name BITS in UARTTDR1
0135  * @{
0136  */
0137
0138 #define EP7312_UART_FRMERR     0x00000100
0139 #define EP7312_UART_PARERR     0x00000200
0140 #define EP7312_UART_OVERR      0x00000400
0141
0142 /** @} */
0143
0144 /**
0145  * @name BITS in system status flag register 1
0146  * @{
0147  */
0148
0149 #define EP7312_UART_UBUSY1     0x00000800
0150 #define EP7312_UART_URXFE1     0x00400000
0151 #define EP7312_UART_UTXFF1     0x00800000
0152
0153 /** @} */
0154
0155 /* system configuration bits */
0156
0157 /**
0158  * @name  BITS in SYSCON1
0159  * @{
0160  */
0161
0162 #define EP7312_SYSCON1_UART1EN       0x00000100
0163 #define EP7312_SYSCON1_TC1_PRESCALE  0x00000010
0164 #define EP7312_SYSCON1_TC1_512KHZ    0x00000020
0165 #define EP7312_SYSCON1_TC2_PRESCALE  0x00000040
0166 #define EP7312_SYSCON1_TC2_512KHZ    0x00000080
0167
0168 /** @} */
0169
0170 /**
0171  * @name INTR1 (Interrupt 1) mask/status register bits
0172  * @{
0173  */
0174
0175 #define EP7312_INTR1_EXTFIQ  0x00000001
0176 #define EP7312_INTR1_BLINT   0x00000002
0177 #define EP7312_INTR1_WEINT   0x00000004
0178 #define EP7312_INTR1_MCINT   0x00000008
0179 #define EP7312_INTR1_CSINT   0x00000010
0180 #define EP7312_INTR1_EINT1   0x00000020
0181 #define EP7312_INTR1_EINT2   0x00000040
0182 #define EP7312_INTR1_EINT3   0x00000080
0183 #define EP7312_INTR1_TC1OI   0x00000100
0184 #define EP7312_INTR1_TC2OI   0x00000200
0185 #define EP7312_INTR1_RTCMI   0x00000400
0186 #define EP7312_INTR1_TINT    0x00000800
0187 #define EP7312_INTR1_URXINT1 0x00001000
0188 #define EP7312_INTR1_UTXINT1 0x00002000
0189 #define EP7312_INTR1_UMSINT  0x00004000
0190 #define EP7312_INTR1_SSEOTI  0x00008000
0191
0192 /** @} */
0193
0194 /**
0195  * @name INTR2 (Interrupt 2) mask/status register bits
0196  * @{
0197  */
0198
0199 #define EP7312_INTR2_KBDINT  0x00000001
0200 #define EP7312_INTR2_SS2RX   0x00000002
0201 #define EP7312_INTR2_SS2TX   0x00000004
0202 #define EP7312_INTR2_URXINT2 0x00001000
0203 #define EP7312_INTR2_UTXINT2 0x00002000
0204
0205 /** @} */
0206
0207 /**
0208  * @name INTR3 (Interrupt 3) mask/status register bits
0209  * @{
0210  */
0211
0212 #define EP7312_INTR2_DAIINT  0x00000001
0213
0214 /** @} */
0215
0216 /** @} */
0217
0218 #endif /* __EP7312_H__ */