edb7312/console/uart.c

0001 /*
0002  * Cirrus EP7312 Console Driver
0003  *
0004  * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010
0011 #include <bsp.h>                /* Must be before libio.h */
0012 #include <rtems/libio.h>
0013 #include <termios.h>
0014 #include <rtems/bspIo.h>
0015
0016 #include <ep7312.h>
0017 #include <libchip/serial.h>
0018 #include <libchip/sersupp.h>
0019
0020 #define NUM_DEVS 1
0021 int     uart_poll_read(int minor);
0022
0023 static int     uart_first_open(int major, int minor, void *arg);
0024 static int     uart_last_close(int major, int minor, void *arg);
0025 static int     uart_read(int minor);
0026 static ssize_t uart_write(int minor, const char *buf, size_t len);
0027 static void    uart_init(int minor);
0028 static void    uart_write_polled(int minor, char c);
0029 static int     uart_set_attributes(int minor, const struct termios *t);
0030
0031 unsigned long Console_Configuration_Count = NUM_DEVS;
0032
0033 const console_fns uart_fns =
0034 {
0035     libchip_serial_default_probe,
0036     uart_first_open,
0037     uart_last_close,
0038     uart_read,
0039     uart_write,
0040     uart_init,
0041     uart_write_polled,
0042     uart_set_attributes,
0043     FALSE
0044 };
0045 console_tbl Console_Configuration_Ports[] = {
0046     {
0047         "/dev/com0",                      /* sDeviceName */
0048         SERIAL_CUSTOM,                    /* deviceType */
0049         &uart_fns,                        /* pDeviceFns */
0050         NULL,                             /* deviceProbe */
0051         NULL,                             /* pDeviceFlow */
0052         16,                               /* ulMargin */
0053         8,                                /* ulHysteresis */
0054         NULL,                             /* pDeviceParams */
0055         (uint32_t)EP7312_UARTCR1,       /* ulCtrlPort1 */
0056         (uint32_t)EP7312_SYSFLG1,       /* ulCtrlPort2 */
0057         (uint32_t)EP7312_UARTDR1,       /* ulDataPort */
0058         0,                                /* getRegister */
0059         0,                                /* setRegister */
0060         0,                                /* getData */
0061         0,                                /* setData */
0062         0,                                /* ulClock */
0063         0                                 /* ulIntVector */
0064     }};
0065
0066 static int     uart_first_open(int major, int minor, void *arg) {return 0;}
0067 static int     uart_last_close(int major, int minor, void *arg) {return 0;}
0068 static int     uart_read(int minor)
0069 {
0070     return uart_poll_read(minor);
0071 }
0072
0073 static void    uart_write_polled(int minor, char c)
0074 {
0075     uart_write(minor, &c, 1);
0076 }
0077
0078 static int     uart_set_attributes(int minor, const struct termios *t)
0079 {
0080     return 0;
0081 }
0082
0083 int uart_poll_read(int minor)
0084 {
0085     volatile uint32_t   *data_reg;
0086     volatile uint32_t   *ctrl_reg2;
0087     char        c;
0088     int         err;
0089
0090     data_reg  = (uint32_t *)Console_Port_Tbl[minor]->ulDataPort;
0091     ctrl_reg2 = (uint32_t *)Console_Port_Tbl[minor]->ulCtrlPort2;
0092
0093     if ((*ctrl_reg2 & EP7312_UART_URXFE1) != 0) {
0094         return -1;
0095     }
0096
0097     err  = *data_reg;
0098     c    = err & 0xff;
0099     err &= (EP7312_UART_FRMERR | EP7312_UART_PARERR | EP7312_UART_OVERR);
0100
0101     return c;
0102 }
0103
0104 static ssize_t uart_do_write(
0105     volatile uint32_t *uartdr,
0106     const char *buf,
0107     size_t len,
0108     volatile uint32_t *sysflg
0109 )
0110 {
0111     size_t i;
0112
0113     for (i = 0; i < len; i++) {
0114         /* Wait for fifo to have room */
0115         while ((*sysflg & EP7312_UART_UTXFF1) != 0) {
0116             continue;
0117         }
0118
0119         *uartdr = buf[i];
0120     }
0121
0122     return len;
0123 }
0124
0125 static ssize_t uart_write(int minor, const char *buf, size_t len)
0126 {
0127     volatile uint32_t   *data_reg;
0128     volatile uint32_t   *ctrl_reg2;
0129
0130     data_reg  = (uint32_t *)Console_Port_Tbl[minor]->ulDataPort;
0131     ctrl_reg2 = (uint32_t *)Console_Port_Tbl[minor]->ulCtrlPort2;
0132
0133     return uart_do_write(data_reg, buf, len, ctrl_reg2);
0134 }
0135
0136 static void uart_init(int minor)
0137 {
0138     volatile uint32_t   *ctrl_reg1;
0139
0140     ctrl_reg1 = (uint32_t *)Console_Port_Tbl[minor]->ulCtrlPort1;
0141
0142     /*   *ctrl_reg = (BSP_UART_DATA8       |
0143                  BSP_UART_STOP1       |
0144                  BSP_UART_PARITY_NONE |
0145                  EP7312_UART_FIFOEN     |
0146                  BSP_UART_BAUD_9600);
0147     */
0148     *ctrl_reg1 = (EP7312_UART_WRDLEN8    |
0149                  EP7312_UART_FIFOEN     |
0150                  0x17);              /* 9600 baud */
0151
0152 }
0153
0154 /*
0155  * Debug IO support
0156  */
0157 static void _BSP_null_char(char c)
0158 {
0159   uart_do_write(EP7312_UARTDR1, &c, 1, EP7312_SYSFLG1);
0160 }
0161
0162 static int _BSP_get_char(void)
0163 {
0164   return uart_poll_read(0);
0165 }
0166
0167 BSP_output_char_function_type BSP_output_char = _BSP_null_char;
0168
0169 BSP_polling_getchar_function_type BSP_poll_char = _BSP_get_char;