csb337/start/start.S

0001 /*
0002  * Cogent CSB337 startup code
0003  *
0004  * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009 */
0010
0011 #include <rtems/asm.h>
0012 #include <rtems/score/cpu.h>
0013
0014 .text
0015 .globl  _start
0016 _start:
0017         /*
0018          * Since I don't plan to return to the bootloader,
0019          * I don't have to save the registers.
0020          */
0021
0022         /* Set end of interrupt stack area */
0023         ldr     r7, =_ISR_Stack_area_end
0024
0025         /* Enter FIQ mode and set up the FIQ stack pointer */
0026         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
0027         msr     cpsr, r0
0028         ldr     r1, =bsp_stack_fiq_size
0029         mov     sp, r7
0030         sub     r7, r7, r1
0031
0032         /* Enter ABT mode and set up the ABT stack pointer */
0033         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
0034         msr     cpsr, r0
0035         ldr     r1, =bsp_stack_abt_size
0036         mov     sp, r7
0037         sub     r7, r7, r1
0038
0039         /* Enter UND mode and set up the UND stack pointer */
0040         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
0041         msr     cpsr, r0
0042         ldr     r1, =bsp_stack_und_size
0043         mov     sp, r7
0044         sub     r7, r7, r1
0045
0046         /* Enter IRQ mode and set up the IRQ stack pointer */
0047         mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
0048         msr     cpsr, r0
0049         mov     sp, r7
0050
0051         /*
0052          * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
0053          * (interrupts are disabled).
0054          */
0055         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
0056         msr     cpsr, r0
0057         mov     sp, r7
0058
0059         /* Stay in SVC mode */
0060
0061         /* zero the bss */
0062         ldr     r1, =bsp_section_bss_end
0063         ldr     r0, =bsp_section_bss_begin
0064
0065 _bss_init:
0066         mov     r2, #0
0067         cmp     r0, r1
0068         strlot  r2, [r0], #4
0069         blo     _bss_init        /* loop while r0 < r1 */
0070
0071         /*
0072          * Initialize the MMU. After we return, the MMU is enabled,
0073          * and memory may be remapped. I hope we don't remap this
0074          * memory away.
0075          */
0076         ldr     r0, =mem_map
0077         bl      mmu_init
0078
0079         /*
0080          * Initialize the exception vectors. This includes the
0081          * exceptions vectors (0x00000000-0x0000001c), and the
0082          * pointers to the exception handlers (0x00000020-0x0000003c).
0083          */
0084         mov     r0, #0
0085         adr     r1, vector_block
0086         ldmia   r1!, {r2-r9}
0087         stmia   r0!, {r2-r9}
0088         ldmia   r1!, {r2-r9}
0089         stmia   r0!, {r2-r9}
0090
0091         /* Now we are prepared to start the BSP's C code */
0092         mov     r0, #0
0093         bl      boot_card
0094
0095         /*
0096          * Theoretically, we could return to what started us up,
0097          * but we'd have to have saved the registers and stacks.
0098          * Instead, we'll just reset.
0099          */
0100         bl      bsp_reset
0101
0102         /* We shouldn't get here. If we do, hang */
0103 _hang:  b       _hang
0104
0105
0106 /*
0107  * This is the exception vector table and the pointers to
0108  * the functions that handle the exceptions. It's a total
0109  * of 16 words (64 bytes)
0110  */
0111 vector_block:
0112         ldr    pc, handler_addr_reset
0113         ldr    pc, handler_addr_undef
0114         ldr    pc, handler_addr_swi
0115         ldr    pc, handler_addr_prefetch
0116         ldr    pc, handler_addr_abort
0117         nop
0118         ldr    pc, handler_addr_irq
0119         ldr    pc, handler_addr_fiq
0120
0121 handler_addr_reset:
0122         .word  bsp_reset
0123
0124 handler_addr_undef:
0125         .word  _ARMV4_Exception_undef_default
0126
0127 handler_addr_swi:
0128         .word  _ARMV4_Exception_swi_default
0129
0130 handler_addr_prefetch:
0131         .word  _ARMV4_Exception_pref_abort_default
0132
0133 handler_addr_abort:
0134         .word  _ARMV4_Exception_data_abort_default
0135
0136 handler_addr_reserved:
0137         .word  0
0138
0139 handler_addr_irq:
0140         .word  _ARMV4_Exception_interrupt
0141
0142 handler_addr_fiq:
0143         .word  _ARMV4_Exception_fiq_default