csb337/irq/irq.c

0001 /*
0002  * Atmel AT91RM9200 Interrupt handler
0003  *
0004  * Copyright (c) 2010 embedded brains GmbH & Co. KG
0005  *
0006  * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
0007  *
0008  *  The license and distribution terms for this file may be
0009  *  found in the file LICENSE in this distribution or at
0010  *  http://www.rtems.org/license/LICENSE.
0011  */
0012
0013 #include <rtems/score/armv4.h>
0014
0015 #include <bsp.h>
0016 #include <bsp/irq.h>
0017 #include <bsp/irq-generic.h>
0018
0019 #include <at91rm9200.h>
0020
0021 void bsp_interrupt_dispatch(void)
0022 {
0023   rtems_vector_number vector = AIC_CTL_REG(AIC_IVR);
0024
0025   bsp_interrupt_handler_dispatch(vector);
0026
0027   AIC_CTL_REG(AIC_EOICR) = 0;
0028 }
0029
0030 rtems_status_code bsp_interrupt_get_attributes(
0031   rtems_vector_number         vector,
0032   rtems_interrupt_attributes *attributes
0033 )
0034 {
0035   return RTEMS_SUCCESSFUL;
0036 }
0037
0038 rtems_status_code bsp_interrupt_is_pending(
0039   rtems_vector_number vector,
0040   bool               *pending
0041 )
0042 {
0043   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0044   bsp_interrupt_assert(pending != NULL);
0045   *pending = false;
0046   return RTEMS_UNSATISFIED;
0047 }
0048
0049 rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
0050 {
0051   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0052   return RTEMS_UNSATISFIED;
0053 }
0054
0055 rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
0056 {
0057   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0058   return RTEMS_UNSATISFIED;
0059 }
0060
0061 rtems_status_code bsp_interrupt_vector_is_enabled(
0062   rtems_vector_number vector,
0063   bool               *enabled
0064 )
0065 {
0066   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0067   bsp_interrupt_assert(enabled != NULL);
0068   *enabled = false;
0069   return RTEMS_UNSATISFIED;
0070 }
0071
0072 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
0073 {
0074   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0075   AIC_CTL_REG(AIC_IECR) = 1 << vector;
0076   return RTEMS_SUCCESSFUL;
0077 }
0078
0079 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
0080 {
0081   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0082   AIC_CTL_REG(AIC_IDCR) = 1 << vector;
0083   return RTEMS_SUCCESSFUL;
0084 }
0085
0086 rtems_status_code bsp_interrupt_set_priority(
0087   rtems_vector_number vector,
0088   uint32_t priority
0089 )
0090 {
0091   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0092   return RTEMS_UNSATISFIED;
0093 }
0094
0095 rtems_status_code bsp_interrupt_get_priority(
0096   rtems_vector_number vector,
0097   uint32_t *priority
0098 )
0099 {
0100   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0101   bsp_interrupt_assert(priority != NULL);
0102   return RTEMS_UNSATISFIED;
0103 }
0104
0105 void bsp_interrupt_facility_initialize(void)
0106 {
0107   unsigned long i = 0;
0108
0109   for (i = 0; i < 32; ++i) {
0110     AIC_SVR_REG(i<<2) = i;
0111   }
0112
0113   /* disable all interrupts */
0114   AIC_CTL_REG(AIC_IDCR) = 0xffffffff;
0115
0116   _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
0117 }