csb337/include/sed1356_16bit.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCSB337
0005  *
0006  * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637)
0007  *        16-Bit access mode
0008  */
0009
0010 /**
0011  * @defgroup csb337_sed1356 SED Video Controller.
0012  *
0013  * @ingroup RTEMSBSPsARMCSB337
0014  *
0015  * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637)
0016  *        16-Bit access mode
0017  */
0018
0019 /*
0020  * sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637)
0021  *            16-Bit access mode
0022  *
0023  *  Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/
0024  *  which includes this notice:
0025  *
0026  **************************************************************************
0027  *  General notice:
0028  *  This code is part of a boot-monitor package developed as a generic base
0029  *  platform for embedded system designs.  As such, it is likely to be
0030  *  distributed to various projects beyond the control of the original
0031  *  author.  Please notify the author of any enhancements made or bugs found
0032  *  so that all may benefit from the changes.  In addition, notification back
0033  *  to the author will allow the new user to pick up changes that may have
0034  *  been made by other users after this version of the code was distributed.
0035  *
0036  *  Note1: the majority of this code was edited with 4-space tabs.
0037  *  Note2: as more and more contributions are accepted, the term "author"
0038  *         is becoming a mis-representation of credit.
0039  *
0040  *  Original author:    Ed Sutter
0041  *  Email:              esutter@alcatel-lucent.com
0042  *  Phone:              908-582-2351
0043  **************************************************************************
0044  *
0045  *  Ed Sutter has been informed that this code is being used in RTEMS.
0046  *
0047  *  The code has been reformatted by Joel Sherrill from OAR Corporation and
0048  *  Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas
0049  *  Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards
0050  *  and to eliminate C++ style comments.
0051  */
0052
0053 #ifndef __sed1356_16bit_h
0054 #define __sed1356_16bit_h
0055
0056 #include "bits.h"
0057 /*------------------------------------------------------------------------
0058  * cpu specific code must define the following board specific macros.
0059  * in cpuio.h.  These examples assume the SED135x has been placed in
0060  * the correct endian mode via hardware.
0061  * #define SED_MEM_BASE   0xf0600000 <-- just example addresses,
0062  * #define SED_REG_BASE    0xf0400000 <-- define for each board
0063  * #define SED_STEP      1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry
0064  * #define SED_REG16(_x_)    *(vushortr *)(SED_REG_BASE + (_x_ * SED_STEP))  // Control/Status Registers
0065  * #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP)))))
0066  * #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_))
0067  * Big endian processors
0068  * #define H2SED(_x_)  ((((x) & 0xff00U) >> 8) | (((x) & 0x00ffU) << 8))
0069  * Little endian
0070  * #define H2SED(_x_)  (_x_)
0071  *
0072  */
0073
0074 /*
0075  * SED1356 registers - 16-Bit Access Mode.  The first register
0076  * referenced is the even addressed register.  The byte offsets
0077  * of the odd registers are shown in the comments
0078  */
0079 #define SED1356_REG_REV_and_MISC                 SED_REG16(0x00)
0080 #define SED1356_REG_GPIO_CFG                  SED_REG16(0x04)
0081 #define SED1356_REG_GPIO_CTL                    SED_REG16(0x08)
0082 #define SED1356_REG_MD_CFG_RD_LO_and_HI          SED_REG16(0x0c)
0083 #define SED1356_REG_MCLK_CFG                     SED_REG16(0x10)
0084 #define SED1356_REG_LCD_PCLK_CFG                 SED_REG16(0x14)
0085 #define SED1356_REG_CRT_PCLK_CFG                 SED_REG16(0x18)
0086 #define SED1356_REG_MEDIA_PCLK_CFG               SED_REG16(0x1c)
0087 #define SED1356_REG_WAIT_STATE                   SED_REG16(0x1e)
0088 #define SED1356_REG_MEM_CFG_and_REF_RATE           SED_REG16(0x20)
0089 #define SED1356_REG_MEM_TMG0_and_1               SED_REG16(0x2a)
0090 #define SED1356_REG_PANEL_TYPE_and_MOD_RATE       SED_REG16(0x30)
0091 /* LCD Control registers */
0092 #define SED1356_REG_LCD_HOR_DISP                 SED_REG16(0x32)
0093 #define SED1356_REG_LCD_HOR_NONDISP_and_START    SED_REG16(0x34)
0094 #define SED1356_REG_LCD_HOR_PULSE               SED_REG16(0x36)
0095 #define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI      SED_REG16(0x38)
0096 #define SED1356_REG_LCD_VER_NONDISP_and_START      SED_REG16(0x3a)
0097 #define SED1356_REG_LCD_VER_PULSE                SED_REG16(0x3c)
0098 #define SED1356_REG_LCD_DISP_MODE_and_MISC      SED_REG16(0x40)
0099 #define SED1356_REG_LCD_DISP_START_LO_and_MID    SED_REG16(0x42)
0100 #define SED1356_REG_LCD_DISP_START_HI           SED_REG16(0x44)
0101 #define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI    SED_REG16(0x46)
0102 #define SED1356_REG_LCD_PIXEL_PAN             SED_REG16(0x48)
0103 #define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI    SED_REG16(0x4a)
0104 /* CRT/TV Control registers */
0105 #define SED1356_REG_CRT_HOR_DISP                 SED_REG16(0x50)
0106 #define SED1356_REG_CRT_HOR_NONDISP_and_START    SED_REG16(0x52)
0107 #define SED1356_REG_CRT_HOR_PULSE               SED_REG16(0x54)
0108 #define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI      SED_REG16(0x56)
0109 #define SED1356_REG_CRT_VER_NONDISP_and_START    SED_REG16(0x58)
0110 #define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL    SED_REG16(0x5a)
0111 #define SED1356_REG_CRT_DISP_MODE          SED_REG16(0x60)
0112 #define SED1356_REG_CRT_DISP_START_LO_and_MID       SED_REG16(0x62)
0113 #define SED1356_REG_CRT_DISP_START_HI           SED_REG16(0x64)
0114 #define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI       SED_REG16(0x66)
0115 #define SED1356_REG_CRT_PIXEL_PAN             SED_REG16(0x68)
0116 #define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI      SED_REG16(0x6a)
0117 /* LCD Cursor Control Registers */
0118 #define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD  SED_REG16(0x70)
0119 #define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI     SED_REG16(0x72)
0120 #define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI    SED_REG16(0x74)
0121 #define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0  SED_REG16(0x76)
0122 #define SED1356_REG_LCD_CURSOR_RED_CLR_0      SED_REG16(0x78)
0123 #define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1  SED_REG16(0x7a)
0124 #define SED1356_REG_LCD_CURSOR_RED_CLR_1      SED_REG16(0x7c)
0125 #define SED1356_REG_LCD_CURSOR_FIFO_THRESH      SED_REG16(0x7e)
0126 /* CRT Cursor Control Registers */
0127 #define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD  SED_REG16(0x80)
0128 #define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI     SED_REG16(0x82)
0129 #define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI    SED_REG16(0x84)
0130 #define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0  SED_REG16(0x86)
0131 #define SED1356_REG_CRT_CURSOR_RED_CLR_0      SED_REG16(0x88)
0132 #define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1  SED_REG16(0x8a)
0133 #define SED1356_REG_CRT_CURSOR_RED_CLR_1      SED_REG16(0x8c)
0134 #define SED1356_REG_CRT_CURSOR_FIFO_THRESH      SED_REG16(0x8e)
0135 /* BitBlt Control Registers */
0136 #define SED1356_REG_BLT_CTL_0_and_1          SED_REG16(0x100)
0137 #define SED1356_REG_BLT_ROP_CODE_and_BLT_OP      SED_REG16(0x102)
0138 #define SED1356_REG_BLT_SRC_START_LO_and_MID    SED_REG16(0x104)
0139 #define SED1356_REG_BLT_SRC_START_HI        SED_REG16(0x106)
0140 #define SED1356_REG_BLT_DEST_START_LO_and_MID    SED_REG16(0x108)
0141 #define SED1356_REG_BLT_DEST_START_HI        SED_REG16(0x10a)
0142 #define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI    SED_REG16(0x10c)
0143 #define SED1356_REG_BLT_WID_LO_and_HI        SED_REG16(0x110)
0144 #define SED1356_REG_BLT_HGT_LO_and_HI        SED_REG16(0x112)
0145 #define SED1356_REG_BLT_BG_CLR_LO_and_HI      SED_REG16(0x114)
0146 #define SED1356_REG_BLT_FG_CLR_LO_and_HI      SED_REG16(0x118)
0147 /* Look-Up Table Control Registers */
0148 #define SED1356_REG_LUT_MODE            SED_REG16(0x1e0)
0149 #define SED1356_REG_LUT_ADD              SED_REG16(0x1e2)
0150 #define SED1356_REG_LUT_DATA            SED_REG16(0x1e4)
0151 /* Power and Miscellaneous Control Registers */
0152 #define SED1356_REG_PWR_CFG_and_STAT        SED_REG16(0x1f0)
0153 #define SED1356_REG_WATCHDOG_CTL          SED_REG16(0x1f4)
0154 #define SED1356_REG_DISP_MODE            SED_REG16(0x1fc)
0155
0156 /*
0157  * Bit Assignments - Little Endian, Use H2SED() macro to access
0158  *
0159  * SED1356_REG_REV_and_MISC - even
0160  */
0161 #define SED1356_REV_ID_MASK          0xfc /* ID bits - masks off the rev bits */
0162 #define SED1356_REV_ID_1356          BIT4
0163 #define SED1356_REV_ID_1355          BIT3
0164
0165 /* SED1356_REG_REV_and_MISC - odd */
0166 #define SED1356_MISC_HOST_DIS        BIT7 << 8  /* 0 = enable host access, 1 = disable */
0167
0168 /* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */
0169 #define SED1356_GPIO_GPIO3           BIT3    /* 0 = input, 1 = output, if configured as GPIO */
0170 #define SED1356_GPIO_GPIO2           BIT2
0171 #define SED1356_GPIO_GPIO1           BIT1
0172
0173 /* SED1356_REG_MCLK_CFG */
0174 #define SED1356_MCLK_DIV2          BIT4
0175 #define SED1356_MCLK_SRC_BCLK        BIT0
0176 #define SED1356_MCLK_SRC_CLKI        0x00
0177
0178 /* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG
0179  * and SED1356_REG_MEDIA_PCLK_CFG
0180  */
0181 #define SED1356_PCLK_X2            BIT7    /* SED1356_REG_CRT_PCLK_CFG only */
0182 #define SED1356_PCLK_DIV1          0x00 << 4
0183 #define SED1356_PCLK_DIV2          0x01 << 4
0184 #define SED1356_PCLK_DIV3          0x02 << 4
0185 #define SED1356_PCLK_DIV4          0x03 << 4
0186 #define SED1356_PCLK_SRC_CLKI        0x00
0187 #define SED1356_PCLK_SRC_BCLK        0x01
0188 #define SED1356_PCLK_SRC_CLKI2        0x02
0189 #define SED1356_PCLK_SRC_MCLK        0x03
0190
0191 /* SED1356_REG_MEM_CFG_and_REF_RATE - even */
0192 #define SED1356_MEM_CFG_2CAS_EDO      0x00
0193 #define SED1356_MEM_CFG_2CAS_FPM      0x01
0194 #define SED1356_MEM_CFG_2WE_EDO        0x02
0195 #define SED1356_MEM_CFG_2WE_FPM        0x03
0196 #define SED1356_MEM_CFG_MASK        0x03
0197
0198 /* SED1356_REG_MEM_CFG_and_REF_RATE - odd */
0199 #define SED1356_REF_TYPE_CBR        0x00 << 6 << 8
0200 #define SED1356_REF_TYPE_SELF        0x01 << 6 << 8
0201 #define SED1356_REF_TYPE_NONE        0x02 << 6 << 8
0202 #define SED1356_REF_TYPE_MASK        0x03 << 6 << 8
0203 #define SED1356_REF_RATE_64          0x00 << 0 << 8  /* MCLK / 64 */
0204 #define SED1356_REF_RATE_128        0x01 << 0 << 8  /* MCLK / 128 */
0205 #define SED1356_REF_RATE_256        0x02 << 0 << 8  /* MCLK / 256 */
0206 #define SED1356_REF_RATE_512        0x03 << 0 << 8  /* MCLK / 512 */
0207 #define SED1356_REF_RATE_1024        0x04 << 0 << 8  /* MCLK / 1024 */
0208 #define SED1356_REF_RATE_2048        0x05 << 0 << 8  /* MCLK / 2048 */
0209 #define SED1356_REF_RATE_4096        0x06 << 0 << 8  /* MCLK / 4096 */
0210 #define SED1356_REF_RATE_8192        0x07 << 0 << 8  /* MCLK / 8192 */
0211 #define SED1356_REF_RATE_MASK        0x07 << 0 << 8  /* MCLK / 8192 */
0212
0213 /* SED1356_REG_MEM_TMG0_and_1 - even */
0214 #define SED1356_MEM_TMG0_EDO50_MCLK40    0x01
0215 #define SED1356_MEM_TMG0_EDO50_MCLK33    0x01
0216 #define SED1356_MEM_TMG0_EDO60_MCLK33    0x01
0217 #define SED1356_MEM_TMG0_EDO50_MCLK30    0x12
0218 #define SED1356_MEM_TMG0_EDO60_MCLK30    0x01
0219 #define SED1356_MEM_TMG0_EDO70_MCLK30    0x00
0220 #define SED1356_MEM_TMG0_EDO50_MCLK25    0x12
0221 #define SED1356_MEM_TMG0_EDO60_MCLK25    0x12
0222 #define SED1356_MEM_TMG0_EDO70_MCLK25    0x01
0223 #define SED1356_MEM_TMG0_EDO80_MCLK25    0x00
0224 #define SED1356_MEM_TMG0_EDO50_MCLK20    0x12
0225 #define SED1356_MEM_TMG0_EDO60_MCLK20    0x12
0226 #define SED1356_MEM_TMG0_EDO70_MCLK20    0x12
0227 #define SED1356_MEM_TMG0_EDO80_MCLK20    0x01
0228 #define SED1356_MEM_TMG0_FPM50_MCLK25    0x12
0229 #define SED1356_MEM_TMG0_FPM60_MCLK25    0x01
0230 #define SED1356_MEM_TMG0_FPM50_MCLK20    0x12
0231 #define SED1356_MEM_TMG0_FPM60_MCLK20    0x12
0232 #define SED1356_MEM_TMG0_FPM70_MCLK20    0x11
0233 #define SED1356_MEM_TMG0_FPM80_MCLK20    0x01
0234
0235 /* SED1356_REG_MEM_TMG0_and_1 - odd */
0236 #define SED1356_MEM_TMG1_EDO50_MCLK40    0x01 << 8
0237 #define SED1356_MEM_TMG1_EDO50_MCLK33    0x01 << 8
0238 #define SED1356_MEM_TMG1_EDO60_MCLK33    0x01 << 8
0239 #define SED1356_MEM_TMG1_EDO50_MCLK30    0x02 << 8
0240 #define SED1356_MEM_TMG1_EDO60_MCLK30    0x01 << 8
0241 #define SED1356_MEM_TMG1_EDO70_MCLK30    0x00 << 8
0242 #define SED1356_MEM_TMG1_EDO50_MCLK25    0x02 << 8
0243 #define SED1356_MEM_TMG1_EDO60_MCLK25    0x02 << 8
0244 #define SED1356_MEM_TMG1_EDO70_MCLK25    0x01 << 8
0245 #define SED1356_MEM_TMG1_EDO80_MCLK25    0x01 << 8
0246 #define SED1356_MEM_TMG1_EDO50_MCLK20    0x02 << 8
0247 #define SED1356_MEM_TMG1_EDO60_MCLK20    0x02 << 8
0248 #define SED1356_MEM_TMG1_EDO70_MCLK20    0x02 << 8
0249 #define SED1356_MEM_TMG1_EDO80_MCLK20    0x01 << 8
0250 #define SED1356_MEM_TMG1_FPM50_MCLK25    0x02 << 8
0251 #define SED1356_MEM_TMG1_FPM60_MCLK25    0x01 << 8
0252 #define SED1356_MEM_TMG1_FPM50_MCLK20    0x02 << 8
0253 #define SED1356_MEM_TMG1_FPM60_MCLK20    0x02 << 8
0254 #define SED1356_MEM_TMG1_FPM70_MCLK20    0x02 << 8
0255 #define SED1356_MEM_TMG1_FPM80_MCLK20    0x01 << 8
0256
0257
0258 /* Bit definitions
0259  *
0260  * SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even
0261  */
0262 #define SED1356_PANEL_TYPE_EL      BIT7
0263 #define SED1356_PANEL_TYPE_4_9      (0x00 << 4)    /* Passive 4-Bit, TFT 9-Bit */
0264 #define SED1356_PANEL_TYPE_8_12      (0x01 << 4)    /* Passive 8-Bit, TFT 12-Bit */
0265 #define SED1356_PANEL_TYPE_16      (0x02 << 4)    /* Passive 16-Bit, or TFT 18-Bit */
0266 #define SED1356_PANEL_TYPE_MASK      (0x03 << 4)
0267 #define SED1356_PANEL_TYPE_FMT      BIT3      /* 0 = Passive Format 1, 1 = Passive Format 2 */
0268 #define SED1356_PANEL_TYPE_CLR      BIT2      /* 0 = Passive Mono, 1 = Passive Color */
0269 #define SED1356_PANEL_TYPE_DUAL      BIT1      /* 0 = Passive Single, 1 = Passive Dual */
0270 #define SED1356_PANEL_TYPE_TFT      BIT0      /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */
0271
0272 /* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE,
0273  * SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE
0274  */
0275 #define SED1356_PULSE_POL_HIGH      BIT7      /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
0276 #define SED1356_PULSE_POL_LOW      0x00      /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
0277 #define SED1356_PULSE_WID(_x_)      (_x_ & 0x0f)  /* Pulse Width in Pixels */
0278
0279 /* SED1356_LCD_DISP_MODE_and_MISC - even         */
0280 #define SED1356_LCD_DISP_BLANK      BIT7      /* 1 = Blank LCD Display */
0281 #define SED1356_LCD_DISP_SWIV_NORM    (0x00 << 4)    /* Used with SED1356_REG_DISP_MODE Bit 6 */
0282 #define SED1356_LCD_DISP_SWIV_90    (0x00 << 4)
0283 #define SED1356_LCD_DISP_SWIV_180    (0x01 << 4)
0284 #define SED1356_LCD_DISP_SWIV_270    (0x01 << 4)
0285 #define SED1356_LCD_DISP_SWIV_MASK    (0x01 << 4)
0286 #define SED1356_LCD_DISP_16BPP      0x05      /* Bit Per Pixel Selection */
0287 #define SED1356_LCD_DISP_15BPP      0x04
0288 #define SED1356_LCD_DISP_8BPP      0x03
0289 #define SED1356_LCD_DISP_4BPP      0x02
0290 #define SED1356_LCD_DISP_BPP_MASK    0x07
0291
0292 /* SED1356_LCD_DISP_MODE_and_MISC - odd */
0293 #define SED1356_LCD_MISC_DITH      BIT1 << 8    /* 1 = Dither Disable, Passive Panel Only */
0294 #define SED1356_LCD_MISC_DUAL      BIT0 << 8    /* 1 = Dual Panel Disable, Passive Panel Only */
0295
0296 /* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */
0297 #define SED1356_CRT_OUT_CHROM      BIT5 << 8    /* 1 = TV Chrominance Filter Enable */
0298 #define SED1356_CRT_OUT_LUM        BIT4 << 8    /* 1 = TV Luminance Filter Enable */
0299 #define SED1356_CRT_OUT_DAC_LVL      BIT3 << 8    /* 1 = 4.6ma IREF, 0 = 9.2 IREF */
0300 #define SED1356_CRT_OUT_SVIDEO      BIT1 << 8    /* 1 = S-Video Output, 0 = Composite Video Output */
0301 #define SED1356_CRT_OUT_PAL        BIT0 << 8    /* 1 = PAL Format Output, 0 = NTSC Format Output */
0302
0303 /* SED1356_REG_CRT_DISP_MODE */
0304 #define SED1356_CRT_DISP_BLANK      BIT7      /* 1 = Blank CRT Display */
0305 #define SED1356_CRT_DISP_16BPP      0x05      /* Bit Per Pixel Selection */
0306 #define SED1356_CRT_DISP_15BPP      0x04
0307 #define SED1356_CRT_DISP_8BPP      0x03
0308 #define SED1356_CRT_DISP_4BPP      0x02
0309 #define SED1356_CRT_DISP_BPP_MASK    0x07
0310
0311 /* SED1356_DISP_MODE         */
0312 #define SED1356_DISP_SWIV_NORM      (0x00 << 6)    /* Used with SED1356_LCD_DISP_MODE Bit 4 */
0313 #define SED1356_DISP_SWIV_90      (0x01 << 6)
0314 #define SED1356_DISP_SWIV_180      (0x00 << 6)
0315 #define SED1356_DISP_SWIV_270      (0x01 << 6)
0316 #define SED1356_DISP_MODE_OFF      0x00      /* All Displays Off */
0317 #define SED1356_DISP_MODE_LCD      0x01      /* LCD Only */
0318 #define SED1356_DISP_MODE_CRT      0x02      /* CRT Only */
0319 #define SED1356_DISP_MODE_LCD_CRT    0x03      /* Simultaneous LCD and CRT */
0320 #define SED1356_DISP_MODE_TV      0x04      /* TV Only, Flicker Filter Off */
0321 #define SED1356_DISP_MODE_TV_LCD    0x05      /* Simultaneous LCD and TV, Flicker Filter Off */
0322 #define SED1356_DISP_MODE_TV_FLICK    0x06      /* TV Only, Flicker Filter On */
0323 #define SED1356_DISP_MODE_TV_LCD_FLICK  0x07      /* Simultaneous LCD and TV, Flicker Filter On */
0324
0325 /* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */
0326 #define SED1356_PWR_PCLK        BIT1      /* SED1356_REG_PWR_STAT only */
0327 #define SED1356_PWR_MCLK        BIT0
0328
0329 /* SED1356_REG_VER_NONDISP */
0330 #define SED1356_VER_NONDISP        BIT7      /* vertical retrace status 1 = in retrace */
0331
0332 /* Display size defines */
0333 extern long PIXELS_PER_ROW;
0334 extern long PIXELS_PER_COL;
0335 #define BYTES_PER_PIXEL    2
0336 extern long COLS_PER_SCREEN;
0337 extern long ROWS_PER_SCREEN;
0338
0339 /* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the  */
0340 /* LCD Interface, while the LSB of GREEN is loaded as 0 */
0341 #define RED_SUBPIXEL(n)    ((n & 0x1f) << 11)
0342 #define GREEN_SUBPIXEL(n)  ((n & 0x1f) << 5)
0343 #define BLUE_SUBPIXEL(n)  ((n & 0x1f) << 0)
0344
0345 /* define a simple VGA style 16-color pallette */
0346 #if 0
0347 #define  LU_BLACK    (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
0348 #define  LU_BLUE      (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f))
0349 #define  LU_GREEN    (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00))
0350 #define  LU_CYAN      (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f))
0351 #define  LU_RED      (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
0352 #define  LU_VIOLET    (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f))
0353 #define  LU_YELLOW    (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00))
0354 #define  LU_GREY      (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f))
0355 #define  LU_WHITE    (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17))
0356 #define  LU_BRT_BLUE    (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f))
0357 #define  LU_BRT_GREEN  (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00))
0358 #define  LU_BRT_CYAN    (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f))
0359 #define  LU_BRT_RED    (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
0360 #define  LU_BRT_VIOLET  (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f))
0361 #define  LU_BRT_YELLOW  (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00))
0362 #define  LU_BRT_WHITE  (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f))
0363 /*    RED,  GREEN, BLUE    Entry */
0364   { 0x00,  0x00, 0x00, },  /* LU_BLACK     */
0365   { 0x00,  0x00, 0xA0, },  /* LU_BLUE       */
0366   { 0x00,  0xA0, 0x00, },  /* LU_GREEN     */
0367   { 0x00,  0xA0, 0xA0, },  /* LU_CYAN       */
0368   { 0xA0,  0x00, 0x00, },  /* LU_RED       */
0369   { 0xA0,  0x00, 0xA0, },  /* LU_VIOLET     */
0370   { 0xA0,  0xA0, 0x00, },  /* LU_YELLOW     */
0371   { 0xA0,  0xA0, 0xA0, },  /* LU_WHITE     */
0372   { 0x50,  0x50, 0x50, },  /* LU_GREY       */
0373   { 0x50,  0x50, 0xF0, },  /* LU_BRT_BLUE     */
0374   { 0x50,  0xF0, 0x50, },  /* LU_BRT_GREEN   */
0375   { 0x50,  0xF0, 0xF0, },  /* LU_BRT_CYAN     */
0376   { 0xF0,  0x50, 0x50, },  /* LU_BRT_RED     */
0377   { 0xF0,  0x50, 0xF0, },  /* LU_BRT_VIOLET   */
0378   { 0xF0,  0xF0, 0x50, },  /* LU_BRT_YELLOW   */
0379   { 0xF0,  0xF0, 0xF0, },  /* LU_BRT_WHITE   */
0380 #endif
0381
0382 #define BLUE      (0x14 << 0)
0383 #define GREEN      (0x14 << 6)
0384 #define RED        (0x14 << 11)
0385
0386 #define HALF_BLUE    (0x0a << 0)
0387 #define HALF_GREEN    (0x0a << 6)
0388 #define HALF_RED    (0x0a << 11)
0389
0390
0391 #define BRT_BLUE     (0x1e << 0)
0392 #define BRT_GREEN    (0x1e << 6)
0393 #define BRT_RED      (0x1e << 11)
0394
0395 #define  LU_BLACK    0
0396 #define  LU_BLUE      (BLUE)
0397 #define  LU_GREEN    (GREEN)
0398 #define  LU_CYAN      (GREEN | BLUE)
0399 #define  LU_RED      (RED)
0400 #define  LU_VIOLET    (RED | BLUE)
0401 #define  LU_YELLOW    (RED | GREEN)
0402 #define  LU_WHITE    (RED | GREEN | BLUE)
0403 #define  LU_GREY      (HALF_RED | HALF_GREEN | HALF_BLUE)
0404 #define  LU_BRT_BLUE    (HALF_RED | HALF_GREEN | BRT_BLUE)
0405 #define  LU_BRT_GREEN  (HALF_RED | BRT_GREEN | HALF_BLUE)
0406 #define  LU_BRT_CYAN    (HALF_RED | BRT_GREEN | BRT_BLUE)
0407 #define  LU_BRT_RED    (BRT_RED | HALF_GREEN | HALF_BLUE)
0408 #define  LU_BRT_VIOLET  (BRT_RED | HALF_GREEN | BRT_BLUE)
0409 #define  LU_BRT_YELLOW  (BRT_RED | BRT_GREEN | HALF_BLUE)
0410 #define  LU_BRT_WHITE  (BRT_RED | BRT_GREEN | BRT_BLUE)
0411
0412 const ushort vga_lookup[] = {
0413 LU_BLACK,        /* 0 */
0414 LU_BLUE,        /* 1 */
0415 LU_GREEN,        /* 2 */
0416 LU_CYAN,        /* 3 */
0417 LU_RED,          /* 4 */
0418 LU_VIOLET,        /* 5 */
0419 LU_YELLOW,        /* 6 */
0420 LU_WHITE,        /* 7 */
0421 LU_GREY,        /* 8 */
0422 LU_BRT_BLUE,      /* 9 */
0423 LU_BRT_GREEN,      /* 10 */
0424 LU_BRT_CYAN,      /* 11 */
0425 LU_BRT_RED,        /* 12 */
0426 LU_BRT_VIOLET,      /* 13 */
0427 LU_BRT_YELLOW,      /* 14 */
0428 LU_BRT_WHITE      /* 15 */
0429 };
0430
0431 /* default foreground and background colors */
0432 #define SED_BG_DEF      1
0433 #define SED_FG_DEF      14
0434
0435 /*   Draw defines */
0436 #define TOP            0
0437 #define BOTTOM          (PIXELS_PER_COL-1)
0438 #define LEFT          0
0439 #define RIGHT          (PIXELS_PER_ROW-1)
0440 #define CENTER_X        (PIXELS_PER_ROW/2)
0441 #define CENTER_Y        (PIXELS_PER_COL/2)
0442
0443
0444 /* Vertical and Horizontal Pulse, Start and Non-Display values vary depending
0445  * upon the mode.  The following section gives some insight into how the
0446  * values are arrived at.
0447  * ms = milliseconds, us = microseconds, ns = nanoseconds
0448  * Mhz = Megaherz, Khz = Kiloherz, Hz = Herz
0449  *
0450  * ***************************************************************************************************
0451  * CRT Mode is 640x480 @ 72Hz VESA compatible timing.  PCLK = 31.5Mhz (31.75ns)
0452  * ***************************************************************************************************
0453  *
0454  *                               CRT MODE HORIZONTAL TIMING PARAMETERS
0455  *
0456  *                                       |<-------Tha------->|
0457  *                                       |___________________|                     ______
0458  * Display Enable   _____________________|                   |____________________|
0459  *                                       |                   |
0460  * Horizontal Pulse __           ________|___________________|________          __________
0461  *                    |_________|        |                   |        |________|
0462  *                    |<- Thp ->|        |                   |        |
0463  *                    |         |<-Thbp->|                   |        |
0464  *                    |                                      |<-Thfp->|
0465  *                    |<----------------------Tht-------------------->|
0466  *
0467  * Tha  - Active Display Time                      = 640 pixels
0468  * Thp  - Horizontal Pulse       = 1.27us/31.75ns  =  40 pixels
0469  * Thbp - Horizontal Front Porch = 1.016us/31.75ns =  32 pixels
0470  * Thfp - Horizontal Back Porch  = 3.8us/31.75ns   = 120 pixels
0471  * Tht  - Total Horizontal Time                    = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz
0472  *
0473  * Correlation between horizontal timing parameters and SED registers
0474  */
0475 #define SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register           = (Thp/8) - 1 */
0476 #define SED_HOR_PULSE_START_CRT  0x02 /* Horizontal Pulse Start Position Register    = ((Thfp + 2)/8) - 1 */
0477 #define SED_HOR_NONDISP_CRT    0x17 /* Horizontal Non-Display Period Register     = ((Thp + Thfp + Thbp)/8) - 1 */
0478 /*
0479  *                                CRT MODE VERTICAL TIMING PARAMTERS
0480  *
0481  *                                       |<-------Tva------->|
0482  *                                       |___________________|                     ______
0483  * Display Enable   _____________________|                   |_____________________|
0484  *                                       |                   |
0485  * Vertical Pulse   __           ________|___________________|________          __________
0486  *                    |_________|        |                   |        |________|
0487  *                    |<- Tvp ->|        |                   |        |
0488  *                    |         |<-Tvbp->|                   |        |
0489  *                    |                                      |<-Tvfp->|
0490  *                    |<----------------------Tvt-------------------->|
0491  *
0492  * Tva  - Active Display Time   = 480 lines
0493  * Tvp  - Vertical Pulse        =  3 lines
0494  * Tvfp - Vertical Front Porch  =   9 lines
0495  * Tvbp - Vertical Back Porch   =  28 lines
0496  * Tvt  - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz
0497  *
0498  * Correlation between vertical timing parameters and SED registers
0499  */
0500 #define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register    = Tvp - 1
0501 #define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1
0502 #define SED_VER_NONDISP_CRT    0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
0503 /*
0504  *****************************************************************************************************
0505  * DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing.   PCLK = 25.175Mhz (39.722ns)
0506  *****************************************************************************************************
0507  *
0508  *                              LCD MODE HORIZONTAL TIMING PARAMTERS
0509  *
0510  *                                       |<-------Tha------->|
0511  *                                       |___________________|                     ______
0512  * Display Enable   _____________________|                   |____________________|
0513  *                                       |                   |
0514  * Horizontal Pulse __           ________|___________________|________          __________
0515  *                    |_________|        |                   |        |________|
0516  *                    |<- Thp ->|        |                   |        |
0517  *                    |         |<-Thbp->|                   |        |
0518  *                    |                                      |<-Thfp->|
0519  *                    |<----------------------Tht-------------------->|
0520  *
0521  * Tha  - Active Display Time                     = 640 pixels
0522  * Thp  - Horizontal Pulse       = 3.8us/39.72ns  =  96 pixels
0523  * Thfp - Horizontal Front Porch = .595us/39.72ns =  16 pixels
0524  * Thbp - Horizontal Backporch   = 1.9us/39.72ns  =  48 pixels
0525  * Tht  - Total Horizontal Time  =                = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz
0526  *
0527  * Correlation between horizontal timing parameters and SED registers
0528  *#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register       = (Thp/8) - 1
0529  *#define SED_HOR_PULSE_START_LCD  0x02 // HRTC/FPLINE Start Position Register    = (Thfp/8) - 2
0530  *#define SED_HOR_NONDISP_LCD   0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1
0531  */
0532 extern long SED_HOR_PULSE_WIDTH_LCD;
0533 extern long SED_HOR_PULSE_START_LCD;
0534 extern long SED_HOR_NONDISP_LCD;
0535
0536 /*
0537  *
0538  *                              LCD MODE VERTICAL TIMING PARAMTERS
0539  *
0540  *                                       |<-------Tva------->|
0541  *                                       |___________________|                     ______
0542  * Display Enable   _____________________|                   |_____________________|
0543  *                                       |                   |
0544  * Vertical Pulse   __           ________|___________________|________          __________
0545  *                    |_________|        |                   |        |________|
0546  *                    |<- Tvp ->|        |                   |        |
0547  *                    |         |<-Tvbp->|                   |        |
0548  *                    |                                      |<-Tvfp->|
0549  *                    |<----------------------Tvt-------------------->|
0550  *
0551  * Tva  - Active Display Time   = 480 lines
0552  * Tvp  - Vertical Pulse        = 2 lines
0553  * Tvfp - Vertical Front Porch  = 10 lines
0554  * Tvbp - Vertical Backporch    = 33 lines
0555  * Tvt  - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz
0556  *
0557  * Correlation between vertical timing parameters and SED registers
0558  *#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register    = Tvp - 1
0559  *#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1
0560  *#define SED_VER_NONDISP_LCD   0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
0561  */
0562 extern long SED_VER_PULSE_WIDTH_LCD;
0563 extern long SED_VER_PULSE_START_LCD;
0564 extern long SED_VER_NONDISP_LCD;
0565
0566 #endif