csb337/include/at91rm9200_pmc.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup csb337_at91rm9200
0005  *
0006  * @brief AT91RM9200 Power Management and Clock definitions
0007  */
0008
0009 /*
0010  * AT91RM9200 Power Management and Clock definitions
0011  *
0012  * Copyright (c) 2002 by Cogent Computer Systems
0013  * Written by Mike Kelly <mike@cogcomp.com>
0014  *
0015  *  The license and distribution terms for this file may be
0016  *  found in the file LICENSE in this distribution or at
0017  *  http://www.rtems.org/license/LICENSE.
0018  */
0019 #ifndef __AT91RM9200_PMC_H__
0020 #define __AT91RM9200_PMC_H__
0021
0022 #include <bits.h>
0023
0024 /***********************************************************************
0025  *       Power Management and Clock Control Register Offsets
0026  ***********************************************************************/
0027 int at91rm9200_get_mainclk(void);
0028 int at91rm9200_get_slck(void);
0029 int at91rm9200_get_mck(void);
0030
0031
0032 #define PMC_SCER  0x00    /* System Clock Enable Register */
0033 #define PMC_SCDR  0x04    /* System Clock Disable Register */
0034 #define PMC_SCSR  0x08    /* System Clock Status Register */
0035 #define PMC_PCER  0x10    /* Peripheral Clock Enable Register */
0036 #define PMC_PCDR  0x14    /* Peripheral Clock Disable Register */
0037 #define PMC_PCSR  0x18    /* Peripheral Clock Status Register */
0038 #define PMC_MOR   0x20    /* Main Oscillator Register */
0039 #define PMC_MCFR  0x24    /* Main Clock  Frequency Register */
0040 #define PMC_PLLAR       0x28    /* PLL A Register */
0041 #define PMC_PLLBR       0x2C    /* PLL B Register */
0042 #define PMC_MCKR  0x30    /* Master Clock Register */
0043 #define PMC_PCKR0       0x40    /* Programmable Clock Register 0 */
0044 #define PMC_PCKR1       0x44    /* Programmable Clock Register 1 */
0045 #define PMC_PCKR2       0x48    /* Programmable Clock Register 2 */
0046 #define PMC_PCKR3       0x4C    /* Programmable Clock Register 3 */
0047 #define PMC_PCKR4       0x50    /* Programmable Clock Register 4 */
0048 #define PMC_PCKR5       0x54    /* Programmable Clock Register 5 */
0049 #define PMC_PCKR6       0x58    /* Programmable Clock Register 6 */
0050 #define PMC_PCKR7       0x5C    /* Programmable Clock Register 7 */
0051 #define PMC_IER   0x60    /* Interrupt Enable Register */
0052 #define PMC_IDR   0x64    /* Interrupt Disable Register */
0053 #define PMC_SR    0x68    /* Status Register */
0054 #define PMC_IMR   0x6C    /* Interrupt Mask Register */
0055
0056 /* Bit Defines */
0057
0058 /* PMC_SCDR - System Clock Disable Register */
0059 /* PMC_SCSR - System Clock Status Register */
0060 /* PMC_SCER - System Clock Enable Register */
0061 #define PMC_SCR_PCK7        BIT15
0062 #define PMC_SCR_PCK6        BIT14
0063 #define PMC_SCR_PCK5        BIT13
0064 #define PMC_SCR_PCK4        BIT12
0065 #define PMC_SCR_PCK3        BIT11
0066 #define PMC_SCR_PCK2        BIT10
0067 #define PMC_SCR_PCK1        BIT9
0068 #define PMC_SCR_PCK0        BIT8
0069 #define PMC_SCR_UHP           BIT4
0070 #define PMC_SCR_MCKUDP      BIT2
0071 #define PMC_SCR_UDP         BIT1
0072 #define PMC_SCR_PCK         BIT0
0073
0074 /* PMC_PCER - Peripheral Clock Enable Register */
0075 /* PMC_PCDR - Peripheral Clock Disable Register */
0076 /* PMC_PCSR - Peripheral Clock Status Register */
0077 #define PMC_PCR_PID_EMAC    BIT24     /* Ethernet Peripheral Clock */
0078 #define PMC_PCR_PID_UHP     BIT23     /* USB Host Ports Peripheral Clock */
0079 #define PMC_PCR_PID_TC5     BIT22     /* Timer/Counter 5 Peripheral Clock */
0080 #define PMC_PCR_PID_TC4     BIT21     /* Timer/Counter 4 Peripheral Clock */
0081 #define PMC_PCR_PID_TC3     BIT20     /* Timer/Counter 3 Peripheral Clock */
0082 #define PMC_PCR_PID_TC2     BIT19     /* Timer/Counter 2 Peripheral Clock */
0083 #define PMC_PCR_PID_TC1     BIT18     /* Timer/Counter 1 Peripheral Clock */
0084 #define PMC_PCR_PID_TC0     BIT17     /* Timer/Counter 0 Peripheral Clock */
0085 #define PMC_PCR_PID_SSC2    BIT16     /* Synchronous Serial 2 Peripheral Clock */
0086 #define PMC_PCR_PID_SSC1    BIT15     /* Synchronous Serial 1 Peripheral Clock */
0087 #define PMC_PCR_PID_SSC0    BIT14     /* Synchronous Serial 0 Peripheral Clock */
0088 #define PMC_PCR_PID_SPI     BIT13     /* Serial Peripheral Interface Peripheral Clock */
0089 #define PMC_PCR_PID_TWI     BIT12     /* Two-Wire Interface Peripheral Clock */
0090 #define PMC_PCR_PID_UDP     BIT11     /* USB Device Port Peripheral Clock */
0091 #define PMC_PCR_PID_MCI     BIT10     /* MMC/SD Card Peripheral Clock */
0092 #define PMC_PCR_PID_US3     BIT9      /* USART 3 Peripheral Clock */
0093 #define PMC_PCR_PID_US2     BIT8      /* USART 2 Peripheral Clock */
0094 #define PMC_PCR_PID_US1     BIT7      /* USART 1 Peripheral Clock */
0095 #define PMC_PCR_PID_US0     BIT6      /* USART 0 Peripheral Clock */
0096 #define PMC_PCR_PID_PIOD    BIT5      /* Parallel I/O D Peripheral Clock */
0097 #define PMC_PCR_PID_PIOC    BIT4      /* Parallel I/O C Peripheral Clock */
0098 #define PMC_PCR_PID_PIOB    BIT3      /* Parallel I/O B Peripheral Clock */
0099 #define PMC_PCR_PID_PIOA    BIT2      /* Parallel I/O A Peripheral Clock */
0100
0101 /* PMC_MOR - Main Oscillator Register */
0102 #define PMC_MOR_MOSCEN      BIT0
0103
0104 /* PMC_MCFR - Main Clock  Frequency Register */
0105 #define PMC_MCFR_MAINRDY    BIT16
0106
0107 /* PMC_PLLAR - PLL A Register */
0108 #define PMC_PLLAR_MUST_SET        BIT29           /* This bit must be set according to the docs */
0109 #define PMC_PLLAR_MUL(_x_)        ((_x_ & 0x7ff) << 16)   /* Multiplier    */
0110 #define PMC_PLLAR_MUL_MASK        (0x7ff << 16)   /* Multiplier mask */
0111
0112 #define PMC_PLLAR_OUT_80_160    (0 << 14)             /* select when PLL frequency is 80-160 Mhz */
0113 #define PMC_PLLAR_OUT_150_240   (2 << 14)             /* select when PLL frequency is 150-240 Mhz */
0114 #define PMC_PLLAR_DIV(_x_)        ((_x_ & 0xff) << 0)       /* Divider */
0115 #define PMC_PLLAR_DIV_MASK        (0xff)    /* Divider mask */
0116
0117 /* PMC_PLLBR - PLL B Register */
0118 #define PMC_PLLBR_USB_96M         BIT28           /* Set when PLL is 96Mhz to divide it by 2 for USB */
0119 #define PMC_PLLBR_MUL(_x_)        ((_x_ & 0x7ff) << 16)   /* Multiplier    */
0120 #define PMC_PLLBR_MUL_MASK      (0x7ff << 16)   /* Multiplier mask */
0121 #define PMC_PLLBR_OUT_80_160    (0 << 14)         /* select when PLL frequency is 80-160 Mhz */
0122 #define PMC_PLLBR_OUT_150_240   (2 << 14)        /* select when PLL frequency is 150-240 Mhz */
0123 #define PMC_PLLBR_DIV(_x_)      ((_x_ & 0xff) << 0)       /* Divider */
0124 #define PMC_PLLBR_DIV_MASK      (0xff)    /* Divider mask */
0125
0126 /* PMC_MCKR - Master Clock Register */
0127 #define PMC_MCKR_MDIV_MASK      (3 << 8)        /* for masking out the MDIV field */
0128 #define PMC_MCKR_MDIV_1     (0 << 8)        /* MCK = Core/1 */
0129 #define PMC_MCKR_MDIV_2     (1 << 8)        /* MCK = Core/2 */
0130 #define PMC_MCKR_MDIV_3     (2 << 8)        /* MCK = Core/3 */
0131 #define PMC_MCKR_MDIV_4     (3 << 8)        /* MCK = Core/4 */
0132 #define PMC_MCKR_PRES_MASK        (7 << 2)        /* for masking out the PRES field */
0133 #define PMC_MCKR_PRES_1     (0 << 2)        /* Core = CSS/1 */
0134 #define PMC_MCKR_PRES_2     (1 << 2)        /* Core = CSS/2 */
0135 #define PMC_MCKR_PRES_4     (2 << 2)        /* Core = CSS/4 */
0136 #define PMC_MCKR_PRES_8     (3 << 2)        /* Core = CSS/8 */
0137 #define PMC_MCKR_PRES_16    (4 << 2)        /* Core = CSS/16 */
0138 #define PMC_MCKR_PRES_32    (5 << 2)        /* Core = CSS/32 */
0139 #define PMC_MCKR_PRES_64    (6 << 2)        /* Core = CSS/64 */
0140 #define PMC_MCKR_CSS_MASK         (3 << 0)        /* for masking out the CSS field */
0141 #define PMC_MCKR_CSS_SLOW         (0 << 0)        /* Core Source = Slow Clock */
0142 #define PMC_MCKR_CSS_MAIN         (1 << 0)        /* Core Source = Main Oscillator */
0143 #define PMC_MCKR_CSS_PLLA         (2 << 0)        /* Core Source = PLL A */
0144 #define PMC_MCKR_CSS_PLLB         (3 << 0)        /* Core Source = PLL B */
0145
0146 /* PMC_PCKR0 - 7 - Programmable Clock Register 0 */
0147 #define PMC_PCKR_PRES_1     (0 << 2)        /* Peripheral Clock = CSS/1 */
0148 #define PMC_PCKR_PRES_2     (1 << 2)        /* Peripheral Clock = CSS/2 */
0149 #define PMC_PCKR_PRES_4     (2 << 2)        /* Peripheral Clock = CSS/4 */
0150 #define PMC_PCKR_PRES_8     (3 << 2)        /* Peripheral Clock = CSS/8 */
0151 #define PMC_PCKR_PRES_16    (4 << 2)        /* Peripheral Clock = CSS/16 */
0152 #define PMC_PCKR_PRES_32    (5 << 2)        /* Peripheral Clock = CSS/32 */
0153 #define PMC_PCKR_PRES_64    (6 << 2)        /* Peripheral Clock = CSS/64 */
0154 #define PMC_PCKR_CSS_SLOW         (0 << 0)        /* Peripheral Clock Source = Slow Clock */
0155 #define PMC_PCKR_CSS_MAIN         (1 << 0)        /* Peripheral Clock Source = Main Oscillator */
0156 #define PMC_PCKR_CSS_PLLA         (2 << 0)        /* Peripheral Clock Source = PLL A */
0157 #define PMC_PCKR_CSS_PLLB         (3 << 0)        /* Peripheral Clock Source = PLL B */
0158
0159 /* PMC_IER - Interrupt Enable Register */
0160 /* PMC_IDR - Interrupt Disable Register */
0161 /* PMC_SR - Status Register */
0162 /* PMC_IMR - Interrupt Mask Register */
0163 #define PMC_INT_PCK7_RDY    BIT15
0164 #define PMC_INT_PCK6_RDY    BIT14
0165 #define PMC_INT_PCK5_RDY    BIT13
0166 #define PMC_INT_PCK4_RDY    BIT12
0167 #define PMC_INT_PCK3_RDY    BIT11
0168 #define PMC_INT_PCK2_RDY    BIT10
0169 #define PMC_INT_PCK1_RDY    BIT9
0170 #define PMC_INT_PCK0_RDY    BIT8
0171 #define PMC_INT_MCK_RDY     BIT3
0172 #define PMC_INT_LOCKB       BIT2
0173 #define PMC_INT_LCKA        BIT1
0174 #define PMC_INT_MOSCS       BIT0
0175
0176
0177 #endif