csb337/include/at91rm9200_mem.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup csb337_at91rm9200
0005  *
0006  * @brief AT91RM9200 Memory Controller definitions
0007  */
0008
0009 /*
0010  * AT91RM9200 Memory Controller definitions
0011  *
0012  * Copyright (c) 2002 by Cogent Computer Systems
0013  * Written by Mike Kelly <mike@cogcomp.com>
0014  *
0015  *  The license and distribution terms for this file may be
0016  *  found in the file LICENSE in this distribution or at
0017  *  http://www.rtems.org/license/LICENSE.
0018  */
0019 #ifndef AT91RM9200_MEM_H
0020 #define AT91RM9200_MEM_H
0021
0022 /**********************************************************************
0023  *       External Bus Interface Unit
0024  **********************************************************************/
0025 #define EBI_CSA             0x00    /* Chip Select Assignment Register */
0026 #define EBI_CFGR            0x04    /* Configuration Register */
0027
0028 /* Bit Defines */
0029 /* EBI_CSA - Chip Select Assignment Register */
0030 #define EBI_CSA_CS4_CF        BIT4    /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */
0031 #define EBI_CSA_CS3_SMM       BIT3    /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */
0032 #define EBI_CSA_CS1_SDRAM     BIT1    /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */
0033 #define EBI_CSA_CS0_BF        BIT0    /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */
0034
0035 /* EBI_CFGR     - Configuration Register */
0036 #define EBI_CFGR_DBPU         BIT0    /* 1 = Disable D0-15 pullups         */
0037
0038 /***************************************************************************
0039  * Static Memory Interface Unit
0040  ***************************************************************************/
0041 #define SMC_CSR0            0x00    /* Chip Select Register 0  */
0042 #define SMC_CSR1            0x04    /* Chip Select Register 1  */
0043 #define SMC_CSR2            0x08    /* Chip Select Register 2  */
0044 #define SMC_CSR3            0x0C    /* Chip Select Register 3  */
0045 #define SMC_CSR4            0x10    /* Chip Select Register 4  */
0046 #define SMC_CSR5            0x14    /* Chip Select Register 5  */
0047 #define SMC_CSR6            0x18    /* Chip Select Register 6  */
0048 #define SMC_CSR7            0x1C    /* Chip Select Register 7  */
0049
0050 /* Bit Defines */
0051 /* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */
0052 #define SMC_CSR_RWHOLD(_x_)        ((_x_ & 0x3) << 28)     /* Hold CS after R/W strobes */
0053 #define SMC_CSR_RWSETUP(_x_)    ((_x_ & 0x3) << 24)     /* Setup CS before R/W strobes */
0054 #define SMC_CSR_ACSS_0        (0 << 16)           /* Setup/Hold Address 0 clocks before/after CS */
0055 #define SMC_CSR_ACSS_1        (1 << 16)           /* Setup/Hold Address 1 clock before/after CS */
0056 #define SMC_CSR_ACSS_2        (2 << 16)           /* Setup/Hold Address 2 clocks before/after CS */
0057 #define SMC_CSR_ACSS_3        (3 << 16)           /* Setup/Hold Address 3 clocks before/after CS */
0058 #define SMC_CSR_DRP_NORMAL    0                 /* 0 = normal read protocol */
0059 #define SMC_CSR_DRP_EARLY     BIT15          /* 1 = early read protocol */
0060 #define SMC_CSR_DBW_16        (1 << 13)           /* CS DataBus Width = 16-Bits */
0061 #define SMC_CSR_DBW_8         (2 << 13)           /* CS DataBus Width = 8 Bits */
0062 #define SMC_CSR_BAT_16_1      0                 /* Single 16-Bit device (when DBW is 16) */
0063 #define SMC_CSR_BAT_16_2      BIT12          /* Dual 8-Bit devices (when DBW is 16) */
0064 #define SMC_CSR_TDF(_x_)      ((_x_ & 0xf) << 8)    /* Intercycle Data Float Time */
0065 #define SMC_CSR_WSEN          BIT7           /* 1 = wait states are enabled */
0066 #define SMC_CSR_NWS(_x_)      ((_x_ & 0x7f) << 0)     /* Wait States + 1 */
0067
0068 /* ***************************************************************************** */
0069 /* SDRAM Memory Interface Unit */
0070 /* ***************************************************************************** */
0071 #define SDRC_MR             0x00       /* Mode Register */
0072 #define SDRC_TR             0x04       /* Refresh Timer Register */
0073 #define SDRC_CR             0x08       /* Configuration Register */
0074 #define SDRC_SRR            0x0C       /* Self Refresh Register */
0075 #define SDRC_LPR            0x10       /* Low Power Register */
0076 #define SDRC_IER            0x14       /* Interrupt Enable Register */
0077 #define SDRC_IDR            0x18       /* Interrupt Disable Register */
0078 #define SDRC_IMR            0x1C       /* Interrupt Mask Register */
0079 #define SDRC_ISR            0x20       /* Interrupt Status Register */
0080
0081 /* Bit Defines */
0082 /* SDRC_MR - Mode Register */
0083 #define SDRC_MR_DBW_16        BIT4       /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */
0084 #define SDRC_MR_NORM          (0 << 0)   /* Normal Mode - All accesses to SDRAM are decoded normally */
0085 #define SDRC_MR_NOP         (1 << 0)   /* NOP Command is sent to SDRAM */
0086 #define SDRC_MR_PRE         (2 << 0)   /* Precharge All Command is sent to SDRAM */
0087 #define SDRC_MR_MRS         (3 << 0)   /* Mode Register Set Command is sent to SDRAM */
0088 #define SDRC_MR_REF         (4 << 0)   /* Refresh Command is sent to SDRAM */
0089
0090 /* SDRC_TR - Refresh Timer Register */
0091 #define SDRC_TR_COUNT(_x_)    ((_x_ & 0xfff) << 0)
0092
0093 /* SDRC_CR - Configuration Register */
0094 #define SDRC_CR_TXSR(_x_)     ((_x_ & 0xf) << 27)     /* CKE to ACT Time */
0095 #define SDRC_CR_TRAS(_x_)     ((_x_ & 0xf) << 23)     /* ACT to PRE Time */
0096 #define SDRC_CR_TRCD(_x_)     ((_x_ & 0xf) << 19)     /* RAS to CAS Time */
0097 #define SDRC_CR_TRP(_x_)      ((_x_ & 0xf) << 15)     /* PRE to ACT Time */
0098 #define SDRC_CR_TRC(_x_)      ((_x_ & 0xf) << 11)     /* REF to ACT Time */
0099 #define SDRC_CR_TWR(_x_)      ((_x_ & 0xf) << 7)      /* Write Recovery Time */
0100 #define SDRC_CR_CAS_2         (2 << 5)   /* Cas Delay = 2, this is the only supported value */
0101 #define SDRC_CR_NB_2          0        /* 2 Banks per device */
0102 #define SDRC_CR_NB_4          BIT4       /* 4 Banks per device */
0103 #define SDRC_CR_NR_11         (0 << 2)   /* Number of rows = 11 */
0104 #define SDRC_CR_NR_12         (1 << 2)   /* Number of rows = 12 */
0105 #define SDRC_CR_NR_13         (2 << 2)   /* Number of rows = 13 */
0106 #define SDRC_CR_NC_8          (0 << 0)   /* Number of columns = 8 */
0107 #define SDRC_CR_NC_9          (1 << 0)   /* Number of columns = 9 */
0108 #define SDRC_CR_NC_10         (2 << 0)   /* Number of columns = 10 */
0109 #define SDRC_CR_NC_11         (3 << 0)   /* Number of columns = 11 */
0110
0111 /* SDRC_SRR - Self Refresh Register */
0112 #define SDRC_SRR_SRCB         BIT0       /* 1 = Enter Self Refresh */
0113
0114 /* SDRC_LPR - Low Power Register */
0115 #define SDRC_LPR_LPCB         BIT0       /* 1 = De-assert CKE between accesses */
0116
0117 /* SDRC_IER - Interrupt Enable Register */
0118 /* SDRC_IDR - Interrupt Disable Register */
0119 /* SDRC_ISR - Interrupt Mask Register */
0120 /* SDRC_IMR - Interrupt Mask Register */
0121 #define SDRC_INT_RES          BIT0       /* Refresh Error Status */
0122
0123 #endif