LXR |
|
|
|
|||
File indexing completed on 2025-05-11 08:22:49
0001 /** 0002 * @file 0003 * 0004 * @ingroup csb337_at91rm9200 0005 * 0006 * @brief Atmel AT91RM9200 EMAC Register definitions 0007 */ 0008 0009 /* 0010 * Atmel AT91RM9200 EMAC Register definitions 0011 * 0012 * Copyright (c) 2003 by Cogent Computer Systems 0013 * Written by Mike Kelly <mike@cogcomp.com> 0014 * 0015 * The license and distribution terms for this file may be 0016 * found in the file LICENSE in this distribution or at 0017 * http://www.rtems.org/license/LICENSE. 0018 */ 0019 #ifndef __AT91RM9200_EMAC_H__ 0020 #define __AT91RM9200_EMAC_H__ 0021 0022 #include <bits.h> 0023 0024 /*Register offsets */ 0025 #define EMAC_CTL 0x00 /* Network Control Register */ 0026 #define EMAC_CFG 0x04 /* Network Configuration Register */ 0027 #define EMAC_SR 0x08 /* Network Status Register */ 0028 #define EMAC_TAR 0x0C /* Transmit Address Register */ 0029 #define EMAC_TCR 0x10 /* Transmit Control Register */ 0030 #define EMAC_TSR 0x14 /* Transmit Status Register */ 0031 #define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ 0032 #define EMAC_RSR 0x20 /* Receive Status Register */ 0033 #define EMAC_ISR 0x24 /* Interrupt Enable Register */ 0034 #define EMAC_IER 0x28 /* Interrupt Enable Register */ 0035 #define EMAC_IDR 0x2C /* Interrupt Disable Register */ 0036 #define EMAC_IMR 0x30 /* Interrupt Mask Register */ 0037 #define EMAC_MAN 0x34 /* PHY Maintenance Register */ 0038 #define EMAC_FRA 0x40 /* Frames Transmitted OK Register */ 0039 #define EMAC_SCOL 0x44 /* Single Collision Frame Register */ 0040 #define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */ 0041 #define EMAC_OK 0x4C /* Frames Received OK Register */ 0042 #define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */ 0043 #define EMAC_ALE 0x54 /* Alignment Error Register */ 0044 #define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */ 0045 #define EMAC_LCOL 0x5C /* Late Collision Register */ 0046 #define EMAC_ECOL 0x60 /* Excessive Collision Register */ 0047 #define EMAC_CSE 0x64 /* Carrier Sense Error Register */ 0048 #define EMAC_TUE 0x68 /* Transmit Underrun Error Register */ 0049 #define EMAC_CDE 0x6C /* Code Error Register */ 0050 #define EMAC_ELR 0x70 /* Excessive Length Error Register */ 0051 #define EMAC_RJB 0x74 /* Receive Jabber Register */ 0052 #define EMAC_USF 0x78 /* Undersize Frame Register */ 0053 #define EMAC_SQEE 0x7C /* SQE Test Error Register */ 0054 #define EMAC_DRFC 0x80 /* Discarded RX Frame Register */ 0055 #define EMAC_HSH 0x90 /* Hash Address High[63:32] */ 0056 #define EMAC_HSL 0x94 /* Hash Address Low[31:0] */ 0057 #define EMAC_SA1L 0x98 /* Specific Addr 1 Low, First 4 bytes */ 0058 #define EMAC_SA1H 0x9C /* Specific Addr 1 High, Last 2 bytes */ 0059 #define EMAC_SA2L 0xA0 /* Specific Addr 2 Low, First 4 bytes */ 0060 #define EMAC_SA2H 0xA4 /* Specific Addr 2 High, Last 2 bytes */ 0061 #define EMAC_SA3L 0xA8 /* Specific Addr 3 Low, First 4 bytes */ 0062 #define EMAC_SA3H 0xAC /* Specific Addr 3 High, Last 2 bytes */ 0063 #define EMAC_SA4L 0xB0 /* Specific Addr 4 Low, First 4 bytes */ 0064 #define EMAC_SA4H 0xB4 /* Specific Addr 4 High, Last 2 bytesr */ 0065 0066 /* Control Register, EMAC_CTL, Offset 0x0 */ 0067 #define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */ 0068 #define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */ 0069 #define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */ 0070 #define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */ 0071 #define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */ 0072 #define EMAC_CTL_CSR BIT5 /* Write 1 to clear stats registers. */ 0073 #define EMAC_CTL_ISR BIT6 /* Write to increment stats registers */ 0074 #define EMAC_CTL_WES BIT7 /* 1 = Enable writing to stats regs */ 0075 #define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames */ 0076 0077 /* Configuration Register, EMAC_CFG, Offset 0x4 */ 0078 #define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (not functional?) */ 0079 #define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */ 0080 #define EMAC_CFG_BR BIT2 /* write 0 */ 0081 #define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */ 0082 #define EMAC_CFG_NBC BIT5 /* 1 = disable reception of bcast frms */ 0083 #define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */ 0084 #define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */ 0085 #define EMAC_CFG_BIG BIT8 /* 1 = enable reception 1522 byte frms */ 0086 #define EMAC_CFG_EAE BIT9 /* write 0 */ 0087 #define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */ 0088 #define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */ 0089 #define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */ 0090 #define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */ 0091 #define EMAC_CFG_CLK_MASK (3 << 10) /* MII Clock mask */ 0092 #define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */ 0093 #define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */ 0094 0095 /* Status Register, EMAC_SR, Offset 0x8 */ 0096 #define EMAC_LINK BIT0 /* Link pin */ 0097 #define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */ 0098 #define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle */ 0099 0100 /* Transmit Control Register, EMAC_TCR, Offset 0x10 */ 0101 #define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Tx frame len minus CRC */ 0102 #define EMAC_TCR_NCRC BIT15 /* Do'nt append CRC on Tx */ 0103 0104 /* Transmit Status Register, EMAC_TSR, Offset 0x14 */ 0105 #define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */ 0106 #define EMAC_TSR_COL BIT1 /* 1 = Collision occured */ 0107 #define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */ 0108 #define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */ 0109 #define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ 0110 #define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ 0111 #define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ 0112 0113 /* Receive Status Register, EMAC_RSR, Offset 0x20 */ 0114 #define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ 0115 #define EMAC_RSR_REC BIT1 /* 1 = Frame received */ 0116 #define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */ 0117 0118 /* 0119 * Interrupt Status Register, EMAC_ISR, Offsen 0x24 0120 * Interrupt Enable Register, EMAC_IER, Offset 0x28 0121 * Interrupt Disable Register, EMAC_IDR, Offset 0x2c 0122 * Interrupt Mask Register, EMAC_IMR, Offset 0x30 0123 */ 0124 #define EMAC_INT_DONE BIT0 /* Phy management done */ 0125 #define EMAC_INT_RCOM BIT1 /* Receive complete */ 0126 #define EMAC_INT_RBNA BIT2 /* Receive buffer not available */ 0127 #define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */ 0128 #define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */ 0129 #define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */ 0130 #define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */ 0131 #define EMAC_INT_TCOM BIT7 /* Transmit complete */ 0132 #define EMAC_INT_TIDLE BIT8 /* Transmit idle */ 0133 #define EMAC_INT_LINK BIT9 /* Link pin changed value */ 0134 #define EMAC_INT_ROVR BIT10 /* Receive overrun */ 0135 #define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */ 0136 0137 /* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */ 0138 #define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0)/* PHY data register */ 0139 #define EMAC_MAN_CODE (0x2 << 16) /* IEEE Code */ 0140 #define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */ 0141 #define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */ 0142 #define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ 0143 #define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ 0144 #define EMAC_MAN_HIGH BIT30 /* Must be set */ 0145 #define EMAC_MAN_LOW BIT31 0146 0147 /* 0148 * Bit assignments for Receive Buffer Descriptor 0149 * Address - Word 0 0150 */ 0151 #define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base addr of the rx buf */ 0152 #define RXBUF_ADD_WRAP BIT1 /* set indicates last buf */ 0153 #define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer */ 0154 0155 /* Status - Word 1 */ 0156 #define RXBUF_STAT_BCAST BIT31 /* Global bcast addr detected */ 0157 #define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */ 0158 #define RXBUF_STAT_UNI BIT29 /* Unicast hash match */ 0159 #define RXBUF_STAT_EXT BIT28 /* External address (optional) */ 0160 #define RXBUF_STAT_UNK BIT27 /* Unknown source address */ 0161 #define RXBUF_STAT_LOC1 BIT26 /* Local address 1 match */ 0162 #define RXBUF_STAT_LOC2 BIT25 /* Local address 2 match */ 0163 #define RXBUF_STAT_LOC3 BIT24 /* Local address 3 match */ 0164 #define RXBUF_STAT_LOC4 BIT23 /* Local address 4 match */ 0165 #define RXBUF_STAT_LEN_MASK 0x7ff /* Len of frame including FCS */ 0166 0167 #endif /* __AT91RM9200_EMAC_H__ */ 0168
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
|