csb337/include/at91rm9200_dbgu.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup csb337_at91rm9200
0005  *
0006  * @brief Atmel AT91RM9200_DBGU Register definitions
0007  */
0008
0009 /*
0010  * Atmel AT91RM9200_DBGU Register definitions
0011  *
0012  * Copyright (c) 2003 by Cogent Computer Systems
0013  * Written by Mike Kelly <mike@cogcomp.com>
0014  *
0015  *  The license and distribution terms for this file may be
0016  *  found in the file LICENSE in this distribution or at
0017  *  http://www.rtems.org/license/LICENSE.
0018  */
0019 #ifndef __AT91RM9200_DBGU_H__
0020 #define __AT91RM9200_DBGU_H__
0021
0022 #include "bits.h"
0023
0024 /* Register Offsets */
0025 #define DBGU_CR         0x00            /* Control Register */
0026 #define DBGU_MR         0x04            /* Mode Register */
0027 #define DBGU_IER        0x08            /* Interrupt Enable Register */
0028 #define DBGU_IDR        0x0C            /* Interrupt Disable Register */
0029 #define DBGU_IMR        0x10            /* Interrupt Mask Register */
0030 #define DBGU_SR         0x14            /* Channel Status Register */
0031 #define DBGU_RHR        0x18            /* Receiver Holding Register */
0032 #define DBGU_THR        0x1C            /* Transmitter Holding Register */
0033 #define DBGU_BRGR       0x20            /* Baud Rate Generator Register */
0034 #define DBGU_C1R        0x40            /* Chip ID1 Register */
0035 #define DBGU_C2R        0x44            /* Chip ID2 Register */
0036 #define DBGU_FNTR       0x48            /* Force NTRST Register */
0037
0038 /* Bit Defines */
0039 /* Control Register, DBGU_CR, Offset 0x00 */
0040 #define DBGU_CR_RSTRX   BIT2            /* 1 = Reset and disable receiver */
0041 #define DBGU_CR_RSTTX   BIT3            /* 1 = Reset and disable transmitter */
0042 #define DBGU_CR_RXEN    BIT4            /* 1 = Receiver enable */
0043 #define DBGU_CR_RXDIS   BIT5            /* 1 = Receiver disable */
0044 #define DBGU_CR_TXEN    BIT6            /* 1 = Transmitter enable */
0045 #define DBGU_CR_TXDIS   BIT7            /* 1 = Transmitter disable */
0046 #define DBGU_CR_RSTSTA  BIT8            /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
0047
0048 /* Mode Register. DBGU_MR. Offset 0x04 */
0049 #define DBGU_MR_PAR_EVEN    (0x0 <<  9) /* Even Parity */
0050 #define DBGU_MR_PAR_ODD     (0x1 <<  9) /* Odd Parity */
0051 #define DBGU_MR_PAR_SPACE   (0x2 <<  9) /* Parity forced to 0 (Space) */
0052 #define DBGU_MR_PAR_MARK    (0x3 <<  9) /* Parity forced to 1 (Mark) */
0053 #define DBGU_MR_PAR_NONE    (0x4 <<  9) /* No Parity */
0054 #define DBGU_MR_PAR_MDROP   (0x6 <<  9) /* Multi-drop mode */
0055 #define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */
0056 #define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */
0057 #define DBGU_MR_CHMODE_LOC  (0x2 << 14) /* Local Loopback: TXD drives RXD */
0058 #define DBGU_MR_CHMODE_REM  (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
0059
0060 /* Interrupt Enable Register, DBGU_IER, Offset 0x08 */
0061 /* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */
0062 /* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */
0063 /* Channel Status Register, DBGU_SR, Offset 0x14 */
0064 #define DBGU_INT_RXRDY      BIT0        /* RXRDY Interrupt */
0065 #define DBGU_INT_TXRDY      BIT1        /* TXRDY Interrupt */
0066 #define DBGU_INT_ENDRX      BIT3        /* End of Receive Transfer Interrupt */
0067 #define DBGU_INT_ENDTX      BIT4        /* End of Transmit Interrupt */
0068 #define DBGU_INT_OVRE       BIT5        /* Overrun Interrupt */
0069 #define DBGU_INT_FRAME      BIT6        /* Framing Error Interrupt */
0070 #define DBGU_INT_PARE       BIT7        /* Parity Error Interrupt */
0071 #define DBGU_INT_TXEMPTY    BIT9        /* TXEMPTY Interrupt */
0072 #define DBGU_INT_TXBUFE     BIT11       /* TXBUFE Interrupt */
0073 #define DBGU_INT_RXBUFF     BIT12       /* RXBUFF Interrupt */
0074 #define DBGU_INT_COMM_TX    BIT30       /* COMM_TX Interrupt */
0075 #define DBGU_INT_COMM_RX    BIT31       /* COMM_RX Interrupt */
0076 #define DBGU_INT_ALL        0xC0001AFB  /* all assigned bits */
0077
0078 /* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */
0079 #define DBGU_FNTR_NTRST         BIT0    /* 1 = Force NTRST low in JTAG */
0080
0081 typedef struct {
0082     volatile uint32_t cr;
0083     volatile uint32_t mr;
0084     volatile uint32_t ier;
0085     volatile uint32_t idr;
0086     volatile uint32_t imr;
0087     volatile uint32_t sr;
0088     volatile uint32_t rhr;
0089     volatile uint32_t thr;
0090     volatile uint32_t brgr;
0091     volatile uint32_t _res0[7];
0092     volatile uint32_t cidr;
0093     volatile uint32_t exid;
0094     volatile uint32_t fnr;
0095 } at91rm9200_dbgu_regs_t;
0096
0097 #endif /* __AT91RM9200_DBGU_H__ */