csb336/start/start.S

0001 /*
0002  * Cogent CSB336 startup code
0003  *
0004  * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
0005  *
0006  * The license and distribution terms for this file may be
0007  * found in the file LICENSE in this distribution or at
0008  * http://www.rtems.org/license/LICENSE.
0009  */
0010
0011 #include <rtems/asm.h>
0012 #include <rtems/score/cpu.h>
0013
0014 .section .bsp_start_text,"ax"
0015          .code 32
0016 _start_jump_at_origin:
0017         ldr     pc, _start_address
0018 _start_address:
0019         .word   _start
0020
0021 .text
0022 .globl  _start
0023 _start:
0024         /*
0025          * Since I don't plan to return to the bootloader,
0026          * I don't have to save the registers.
0027          */
0028
0029         /* Set end of interrupt stack area */
0030         ldr     r7, =_ISR_Stack_area_end
0031
0032         /* Enter FIQ mode and set up the FIQ stack pointer */
0033         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
0034         msr     cpsr, r0
0035         ldr     r1, =bsp_stack_fiq_size
0036         mov     sp, r7
0037         sub     r7, r7, r1
0038
0039         /* Enter ABT mode and set up the ABT stack pointer */
0040         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
0041         msr     cpsr, r0
0042         ldr     r1, =bsp_stack_abt_size
0043         mov     sp, r7
0044         sub     r7, r7, r1
0045
0046         /* Enter UND mode and set up the UND stack pointer */
0047         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
0048         msr     cpsr, r0
0049         ldr     r1, =bsp_stack_und_size
0050         mov     sp, r7
0051         sub     r7, r7, r1
0052
0053         /* Enter IRQ mode and set up the IRQ stack pointer */
0054         mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
0055         msr     cpsr, r0
0056         mov     sp, r7
0057
0058         /*
0059          * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
0060          * (interrupts are disabled).
0061          */
0062         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
0063         msr     cpsr, r0
0064         mov     sp, r7
0065
0066         /* Stay in SVC mode */
0067
0068         /* zero the bss */
0069         ldr     r1, =bsp_section_bss_end
0070         ldr     r0, =bsp_section_bss_begin
0071
0072 _bss_init:
0073         mov     r2, #0
0074         cmp     r0, r1
0075         strlot  r2, [r0], #4
0076         blo     _bss_init        /* loop while r0 < r1 */
0077
0078         /*
0079          * Initialize the MMU. After we return, the MMU is enabled,
0080          * and memory may be remapped. I hope we don't remap this
0081          * memory away.
0082          */
0083         ldr     r0, =mem_map
0084         bl      mmu_init
0085
0086         /*
0087          * Initialize the exception vectors. This includes the
0088          * exceptions vectors (0x00000000-0x0000001c), and the
0089          * pointers to the exception handlers (0x00000020-0x0000003c).
0090          */
0091         mov     r0, #0
0092         adr     r1, vector_block
0093         ldmia   r1!, {r2-r9}
0094         stmia   r0!, {r2-r9}
0095         ldmia   r1!, {r2-r9}
0096         stmia   r0!, {r2-r9}
0097
0098         /* Now we are prepared to start the BSP's C code */
0099         mov     r0, #0
0100         bl      boot_card
0101
0102         /*
0103          * Theoretically, we could return to what started us up,
0104          * but we'd have to have saved the registers and stacks.
0105          * Instead, we'll just reset.
0106          */
0107         bl      bsp_reset
0108
0109         /* We shouldn't get here. If we do, hang */
0110 _hang:  b       _hang
0111
0112
0113 /*
0114  * This is the exception vector table and the pointers to
0115  * the functions that handle the exceptions. It's a total
0116  * of 16 words (64 bytes)
0117  */
0118 vector_block:
0119         ldr    pc, handler_addr_reset
0120         ldr    pc, handler_addr_undef
0121         ldr    pc, handler_addr_swi
0122         ldr    pc, handler_addr_prefetch
0123         ldr    pc, handler_addr_abort
0124         nop
0125         ldr    pc, handler_addr_irq
0126         ldr    pc, handler_addr_fiq
0127
0128 handler_addr_reset:
0129         .word  bsp_reset
0130
0131 handler_addr_undef:
0132         .word  _ARMV4_Exception_undef_default
0133
0134 handler_addr_swi:
0135         .word  _ARMV4_Exception_swi_default
0136
0137 handler_addr_prefetch:
0138         .word  _ARMV4_Exception_pref_abort_default
0139
0140 handler_addr_abort:
0141         .word  _ARMV4_Exception_data_abort_default
0142
0143 handler_addr_reserved:
0144         .word  0
0145
0146 handler_addr_irq:
0147         .word  _ARMV4_Exception_interrupt
0148
0149 handler_addr_fiq:
0150         .word  _ARMV4_Exception_fiq_default