csb336/start/memmap.c

0001 /*
0002  *  CSB336 Memory Map
0003  *
0004  *  Copyright (c) 2004 by Cogent Computer Systems
0005  *  Written by Jay Monkman <jtm@lopingdog.com>
0006  *
0007  *  The license and distribution terms for this file may be
0008  *  found in the file LICENSE in this distribution or at
0009  *  http://www.rtems.org/license/LICENSE.
0010  */
0011 #include <rtems.h>
0012 #include <libcpu/mmu.h>
0013
0014 /* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than
0015  * that, you'll have TLB lookups, which could hurt performance.
0016  */
0017 mmu_sect_map_t mem_map[] = {
0018 /*  <phys addr>  <virt addr> <size> <flags> */
0019     {0x08200000, 0x00000000,   1,    MMU_CACHE_WBACK},     /* Mirror of SDRAM */
0020     {0x00100000, 0x00100000,   1,    MMU_CACHE_NONE},     /* Bootstrap ROM */
0021     {0x00200000, 0x00200000,   2,    MMU_CACHE_NONE},     /* Internal Regs + eSRAM */
0022
0023     {0x08000000, 0x08000000,   1,    MMU_CACHE_NONE},     /* SDRAM */
0024     {0x08100000, 0x08100000,   1,    MMU_CACHE_WTHROUGH}, /* SDRAM */
0025     {0x08200000, 0x08200000,  30,    MMU_CACHE_WBACK},    /* SDRAM */
0026
0027     {0x10000000, 0x10000000,   8,    MMU_CACHE_NONE},     /* CS0 - Flash */
0028     {0x12000000, 0x12000000,   1,    MMU_CACHE_NONE},     /* CS1 - enet */
0029     {0x13000000, 0x13000000,   1,    MMU_CACHE_NONE},     /* CS2 - */
0030     {0x14000000, 0x14000000,   1,    MMU_CACHE_NONE},     /* CS3 - */
0031     {0x15000000, 0x15000000,   1,    MMU_CACHE_NONE},     /* CS4 - */
0032     {0x16000000, 0x16000000,   1,    MMU_CACHE_NONE},     /* CS5 - */
0033     {0x50000000, 0x50000000,   1,    MMU_CACHE_NONE},     /* ARM Test Regs */
0034     {0x00000000, 0x00000000,   0,    0}                   /* The end */
0035 };