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0023 #ifndef LIBBSP_ARM_BEAGLE_I2C_H
0024 #define LIBBSP_ARM_BEAGLE_I2C_H
0025
0026 #include <rtems.h>
0027 #include <bsp.h>
0028 #include <dev/i2c/i2c.h>
0029 #include <ofw/ofw.h>
0030
0031 #ifdef __cplusplus
0032 extern "C" {
0033 #endif
0034
0035 #define BBB_I2C_SYSCLK 48000000
0036 #define BBB_I2C_INTERNAL_CLK 12000000
0037
0038 #define BBB_I2C_0_BUS_PATH "/dev/i2c-0"
0039 #define BBB_I2C_1_BUS_PATH "/dev/i2c-1"
0040 #define BBB_I2C_2_BUS_PATH "/dev/i2c-2"
0041
0042 typedef enum {
0043 I2C0,
0044 I2C1,
0045 I2C2,
0046 I2C_COUNT
0047 } bbb_i2c_id_t;
0048
0049 typedef struct i2c_regs {
0050 uint32_t BBB_I2C_REVNB_LO;
0051 uint32_t BBB_I2C_REVNB_HI;
0052 uint32_t dummy1[ 2 ];
0053 uint32_t BBB_I2C_SYSC;
0054 uint32_t dummy2[ 4 ];
0055 uint32_t BBB_I2C_IRQSTATUS_RAW;
0056 uint32_t BBB_I2C_IRQSTATUS;
0057 uint32_t BBB_I2C_IRQENABLE_SET;
0058 uint32_t BBB_I2C_IRQENABLE_CLR;
0059 uint32_t BBB_I2C_WE;
0060 uint32_t BBB_I2C_DMARXENABLE_SET;
0061 uint32_t BBB_I2C_DMATXENABLE_SET;
0062 uint32_t BBB_I2C_DMARXENABLE_CLR;
0063 uint32_t BBB_I2C_DMATXENABLE_CLR;
0064 uint32_t BBB_I2C_DMARXWAKE_EN;
0065 uint32_t BBB_I2C_DMATXWAKE_EN;
0066 uint32_t dummy3[ 16 ];
0067 uint32_t BBB_I2C_SYSS;
0068 uint32_t BBB_I2C_BUF;
0069 uint32_t BBB_I2C_CNT;
0070 uint32_t BBB_I2C_DATA;
0071 uint32_t dummy4;
0072 uint32_t BBB_I2C_CON;
0073 uint32_t BBB_I2C_OA;
0074 uint32_t BBB_I2C_SA;
0075 uint32_t BBB_I2C_PSC;
0076 uint32_t BBB_I2C_SCLL;
0077 uint32_t BBB_I2C_SCLH;
0078 uint32_t BBB_I2C_SYSTEST;
0079 uint32_t BBB_I2C_BUFSTAT;
0080 uint32_t BBB_I2C_OA1;
0081 uint32_t BBB_I2C_OA2;
0082 uint32_t BBB_I2C_OA3;
0083 uint32_t BBB_I2C_ACTOA;
0084 uint32_t BBB_I2C_SBLOCK;
0085 } bbb_i2c_regs;
0086
0087 void beagle_i2c_init( phandle_t node );
0088
0089 #ifdef __cplusplus
0090 }
0091 #endif
0092
0093 #endif