beagle/include/bsp.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMBeagle
0005  *
0006  * @brief Global BSP definitions.
0007  */
0008
0009 /*
0010  * Copyright (c) 2012 Claas Ziemke. All rights reserved.
0011  *
0012  *  Claas Ziemke
0013  *  Kernerstrasse 11
0014  *  70182 Stuttgart
0015  *  Germany
0016  *  <claas.ziemke@gmx.net>
0017  *
0018  * The license and distribution terms for this file may be
0019  * found in the file LICENSE in this distribution or at
0020  * http://www.rtems.org/license/LICENSE.
0021  *
0022  * Modified by Ben Gras <beng@shrike-systems.com> to add lots
0023  * of beagleboard/beaglebone definitions, delete lpc32xx specific
0024  * ones, and merge with some other header files.
0025  */
0026
0027 #ifndef LIBBSP_ARM_BEAGLE_BSP_H
0028 #define LIBBSP_ARM_BEAGLE_BSP_H
0029
0030 /**
0031  * @defgroup RTEMSBSPsARMBeagle Beaglebone
0032  *
0033  * @ingroup RTEMSBSPsARM
0034  *
0035  * @brief Beaglebone Board Support Package.
0036  *
0037  * @{
0038  */
0039
0040 #include <bspopts.h>
0041 #include <stdint.h>
0042 #include <bsp/start.h>
0043 #include <bsp/default-initial-extension.h>
0044 #include <bsp/beagleboneblack.h>
0045
0046 #include <rtems.h>
0047 #include <rtems/irq-extension.h>
0048
0049 #include <libcpu/omap3.h>
0050 #include <libcpu/am335x.h>
0051
0052 #include <ofw/ofw.h>
0053
0054 #define BSP_FEATURE_IRQ_EXTENSION
0055
0056 /* UART base clock frequency */
0057 #define UART_CLOCK     48000000
0058
0059 /* Access memory-mapped I/O devices */
0060 #define mmio_read(a)    (*(volatile uint32_t *)(a))
0061 #define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
0062 #define mmio_set(a,v)   mmio_write((a), mmio_read((a)) | (v))
0063 #define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
0064
0065 #define REG16(x)(*((volatile uint16_t *)(x)))
0066 #define REG(x)(*((volatile uint32_t *)(x)))
0067 #define BIT(x)(0x1 << (x))
0068 // Start and End included
0069 #define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1))
0070
0071 #define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
0072
0073 int beagle_get_node_unit(phandle_t node);
0074
0075 /* Write a uint32_t value to a memory address. */
0076 static inline void
0077 write32(uint32_t address, uint32_t value)
0078 {
0079     REG(address) = value;
0080 }
0081
0082 /* Read an uint32_t from a memory address */
0083 static inline uint32_t
0084 read32(uint32_t address)
0085 {
0086     return REG(address);
0087 }
0088
0089 /* Set a 32 bits value depending on a mask */
0090 static inline void
0091 set32(uint32_t address, uint32_t mask, uint32_t value)
0092 {
0093     uint32_t val;
0094     val = read32(address);
0095     /* clear the bits */
0096     val &= ~(mask);
0097     /* apply the value using the mask */
0098     val |= (value & mask);
0099     write32(address, val);
0100 }
0101
0102 /* Write a uint16_t value to a memory address. */
0103 static inline void
0104 write16(uint32_t address, uint16_t value)
0105 {
0106     REG16(address) = value;
0107 }
0108
0109 /* Read an uint16_t from a memory address */
0110 static inline uint16_t
0111 read16(uint32_t address)
0112 {
0113     return REG16(address);
0114 }
0115
0116 /* Data synchronization barrier */
0117 static inline void dsb(void)
0118 {
0119     __asm__ volatile("dsb" : : : "memory");
0120 }
0121
0122 /* Instruction synchronization barrier */
0123 static inline void isb(void)
0124 {
0125     __asm__ volatile("isb" : : : "memory");
0126 }
0127
0128 /* flush data cache */
0129 static inline void flush_data_cache(void)
0130 {
0131     __asm__ volatile(
0132         "mov r0, #0\n"
0133         "mcr p15, #0, r0, c7, c10, #4\n"
0134         : /* No outputs */
0135         : /* No inputs */
0136         : "r0","memory"
0137     );
0138 }
0139
0140 #define __arch_getb(a)      (*(volatile unsigned char *)(a))
0141 #define __arch_getw(a)      (*(volatile unsigned short *)(a))
0142 #define __arch_getl(a)      (*(volatile unsigned int *)(a))
0143
0144 #define __arch_putb(v,a)    (*(volatile unsigned char *)(a) = (v))
0145 #define __arch_putw(v,a)    (*(volatile unsigned short *)(a) = (v))
0146 #define __arch_putl(v,a)    (*(volatile unsigned int *)(a) = (v))
0147
0148 #define writeb(v,c) ({ unsigned char  __v = v; __arch_putb(__v,c); __v; })
0149 #define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
0150 #define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
0151
0152 #define readb(c)  ({ unsigned char  __v = __arch_getb(c); __v; })
0153 #define readw(c)  ({ unsigned short __v = __arch_getw(c); __v; })
0154 #define readl(c)  ({ unsigned int __v = __arch_getl(c); __v; })
0155
0156 #define SYSTEM_CLOCK_12       12000000
0157 #define SYSTEM_CLOCK_13       13000000
0158 #define SYSTEM_CLOCK_192      19200000
0159 #define SYSTEM_CLOCK_96       96000000
0160
0161 #if !defined(IS_DM3730) && !defined(IS_AM335X)
0162 #error Unrecognized BSP configured.
0163 #endif
0164
0165 #if IS_DM3730
0166 #define BSP_DEVICEMEM_START 0x48000000
0167 #define BSP_DEVICEMEM_END   0x5F000000
0168 #endif
0169
0170 #if IS_AM335X
0171 #define BSP_DEVICEMEM_START 0x44000000
0172 #define BSP_DEVICEMEM_END   0x57000000
0173 #endif
0174
0175 /* per-target uart config */
0176 #if IS_AM335X
0177 #define BSP_CONSOLE_UART        1
0178 #define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_1
0179 #define BSP_CONSOLE_UART_IRQ    OMAP3_UART1_IRQ
0180 #define BEAGLE_BASE_UART_1      0x44E09000
0181 #define BEAGLE_BASE_UART_2      0x48022000
0182 #define BEAGLE_BASE_UART_3      0x48024000
0183 #endif
0184
0185 /* per-target uart config */
0186 #if IS_DM3730
0187 #define BSP_CONSOLE_UART        3
0188 #define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_3
0189 #define BSP_CONSOLE_UART_IRQ    OMAP3_UART3_IRQ
0190 #define BEAGLE_BASE_UART_1      0x4806A000
0191 #define BEAGLE_BASE_UART_2      0x4806C000
0192 #define BEAGLE_BASE_UART_3      0x49020000
0193 #endif
0194
0195 /* GPIO pin config */
0196 #if IS_AM335X
0197 #define BSP_GPIO_PIN_COUNT 128
0198 #define BSP_GPIO_PINS_PER_BANK 32
0199 #endif
0200
0201 #if IS_DM3730
0202 #define BSP_GPIO_PIN_COUNT 192
0203 #define BSP_GPIO_PINS_PER_BANK 32
0204 #endif
0205
0206 #if BSP_START_COPY_FDT_FROM_U_BOOT
0207 #define BSP_FDT_IS_SUPPORTED
0208 #endif
0209
0210 /* i2c stuff */
0211 typedef struct {
0212     uint32_t rx_or_tx;
0213     uint32_t stat;
0214     uint32_t ctrl;
0215     uint32_t clk_hi;
0216     uint32_t clk_lo;
0217     uint32_t adr;
0218     uint32_t rxfl;
0219     uint32_t txfl;
0220     uint32_t rxb;
0221     uint32_t txb;
0222     uint32_t s_tx;
0223     uint32_t s_txfl;
0224 } beagle_i2c;
0225
0226 /* sctlr */
0227 /* Read System Control Register */
0228 static inline uint32_t read_sctlr(void)
0229 {
0230     uint32_t ctl;
0231
0232     __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
0233         : [ctl] "=r" (ctl));
0234     return ctl;
0235 }
0236
0237 /* Write System Control Register */
0238 static inline void write_sctlr(uint32_t ctl)
0239 {
0240     __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
0241         : : [ctl] "r" (ctl));
0242     isb();
0243 }
0244
0245 /* Read Auxiliary Control Register */
0246 static inline uint32_t read_actlr(void)
0247 {
0248     uint32_t ctl;
0249
0250     __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
0251             : [ctl] "=r" (ctl));
0252     return ctl;
0253 }
0254
0255 /* Write Auxiliary Control Register */
0256 static inline void write_actlr(uint32_t ctl)
0257 {
0258     __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
0259         : : [ctl] "r" (ctl));
0260     isb();
0261 }
0262
0263 /* Write Translation Table Base Control Register */
0264 static inline void write_ttbcr(uint32_t bcr)
0265 {
0266         __asm__ volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
0267                         : : [bcr] "r" (bcr));
0268
0269         isb();
0270 }
0271
0272 /* Read Domain Access Control Register */
0273 static inline uint32_t read_dacr(void)
0274 {
0275         uint32_t dacr;
0276
0277         __asm__ volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
0278                         : [dacr] "=r" (dacr));
0279
0280         return dacr;
0281 }
0282
0283
0284 /* Write Domain Access Control Register */
0285 static inline void write_dacr(uint32_t dacr)
0286 {
0287         __asm__ volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
0288                         : : [dacr] "r" (dacr));
0289
0290         isb();
0291 }
0292
0293 static inline void refresh_tlb(void)
0294 {
0295     dsb();
0296
0297     /* Invalidate entire unified TLB */
0298     __asm__ volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
0299         : : [zero] "r" (0));
0300
0301     /* Invalidate all instruction caches to PoU.
0302      * Also flushes branch target cache. */
0303     __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 0"
0304         : : [zero] "r" (0));
0305
0306     /* Invalidate entire branch predictor array */
0307     __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 6"
0308         : : [zero] "r" (0)); /* flush BTB */
0309
0310     dsb();
0311     isb();
0312 }
0313
0314 /* Read Translation Table Base Register 0 */
0315 static inline uint32_t read_ttbr0(void)
0316 {
0317     uint32_t bar;
0318
0319     __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
0320         : [bar] "=r" (bar));
0321
0322     return bar & ARM_TTBR_ADDR_MASK;
0323 }
0324
0325
0326 /* Read Translation Table Base Register 0 */
0327 static inline uint32_t read_ttbr0_unmasked(void)
0328 {
0329     uint32_t bar;
0330
0331     __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
0332         : [bar] "=r" (bar));
0333
0334     return bar;
0335 }
0336
0337 /* Write Translation Table Base Register 0 */
0338 static inline void write_ttbr0(uint32_t bar)
0339 {
0340     dsb();
0341     isb();
0342     /* In our setup TTBR contains the base address *and* the flags
0343        but other pieces of the kernel code expect ttbr to be the
0344        base address of the l1 page table. We therefore add the
0345        flags here and remove them in the read_ttbr0 */
0346     uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
0347     __asm__ volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
0348         : : [bar] "r" (v));
0349
0350     refresh_tlb();
0351 }
0352
0353 /**
0354  * @brief Beagleboard specific set up of the MMU.
0355  *
0356  * Provide in the application to override.
0357  */
0358 BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
0359
0360 /* @} */
0361
0362 #endif /* LIBBSP_ARM_BEAGLE_BSP_H */