atsam/start/sdram-config.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bspopts.h>
0029 #include <chip.h>
0030 #include <include/board_memories.h>
0031
0032 #if defined ATSAM_SDRAM_IS42S16100E_7BLI
0033
0034 #if ATSAM_MCK != 123000000
0035 #error Please check SDRAM settings for this clock frequency.
0036 #endif
0037
0038 const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
0039   /* FIXME: a lot of these values should be calculated using CPU frequency */
0040   .sdramc_tr = 1562,
0041   .sdramc_cr =
0042       SDRAMC_CR_NC_COL8      /* 8 column bits */
0043     | SDRAMC_CR_NR_ROW11     /* 12 row bits (4K) */
0044     | SDRAMC_CR_CAS_LATENCY3 /* CAS Latency 3 */
0045     | SDRAMC_CR_NB_BANK2     /* 2 banks */
0046     | SDRAMC_CR_DBW          /* 16 bit */
0047     | SDRAMC_CR_TWR(5)
0048     | SDRAMC_CR_TRC_TRFC(13) /* 63ns   min */
0049     | SDRAMC_CR_TRP(5)       /* Command period (PRE to ACT) 21 ns min */
0050     | SDRAMC_CR_TRCD(5)      /* Active Command to R/W Cmd delay time 21ns min */
0051     | SDRAMC_CR_TRAS(9)      /* Command period (ACT to PRE)  42ns min */
0052     | SDRAMC_CR_TXSR(15U),   /* Exit self-refresh to active time  70ns Min */
0053   .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
0054   .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2),
0055   .sdramc_lpr = 0
0056 };
0057
0058 #elif defined ATSAM_SDRAM_IS42S16320F_7BL
0059
0060 #if ATSAM_MCK != 123000000
0061 #error Please check SDRAM settings for this clock frequency.
0062 #endif
0063
0064 #define CLOCK_CYCLES_FROM_NS_MAX(ns) \
0065     (((ns) * (ATSAM_MCK / 1000ul / 1000ul)) / 1000ul)
0066 #define CLOCK_CYCLES_FROM_NS_MIN(ns) (CLOCK_CYCLES_FROM_NS_MAX(ns) + 1)
0067
0068 const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
0069   /* 8k refresh cycles every 64ms => 7.8125us */
0070   .sdramc_tr = CLOCK_CYCLES_FROM_NS_MAX(7812ul),
0071   .sdramc_cr =
0072       SDRAMC_CR_NC_COL10
0073     | SDRAMC_CR_NR_ROW13
0074     | SDRAMC_CR_CAS_LATENCY3
0075     | SDRAMC_CR_NB_BANK4
0076     | SDRAMC_CR_DBW
0077     /* t_WR = 30ns min (t_RC - t_RP - t_RCD;
0078      * see data sheet November 2015 page 55);
0079      * add some security margin */
0080     | SDRAMC_CR_TWR(CLOCK_CYCLES_FROM_NS_MIN(40))
0081     | SDRAMC_CR_TRC_TRFC(CLOCK_CYCLES_FROM_NS_MIN(60))
0082     | SDRAMC_CR_TRP(CLOCK_CYCLES_FROM_NS_MIN(15))
0083     | SDRAMC_CR_TRCD(CLOCK_CYCLES_FROM_NS_MIN(15))
0084     | SDRAMC_CR_TRAS(CLOCK_CYCLES_FROM_NS_MIN(37))
0085     | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)),
0086   .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
0087   .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
0088       SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14)),
0089   .sdramc_lpr = 0
0090 };
0091
0092 #elif defined ATSAM_SDRAM_MT48LC16M16A2P_6A
0093
0094 /*
0095  * Refresh: 7.81 us
0096  * TWR: 12 ns
0097  * TRC_TRFC: 60 ns
0098  * TRP: 15 ns
0099  * TRCD: 18 ns
0100  * TRAS: 42 ns
0101  * TXSR: 67 ns
0102  * TMRD: 2 clock cycles
0103  */
0104
0105 #if ATSAM_MCK == 60000000
0106 const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
0107   .sdramc_tr = 0x1D4,
0108   .sdramc_cr =
0109       SDRAMC_CR_NC_COL9
0110     | SDRAMC_CR_NR_ROW13
0111     | SDRAMC_CR_NB_BANK4
0112     | SDRAMC_CR_CAS_LATENCY3
0113     | SDRAMC_CR_DBW
0114     | SDRAMC_CR_TWR(3)
0115     | SDRAMC_CR_TRC_TRFC(8)
0116     | SDRAMC_CR_TRP(3)
0117     | SDRAMC_CR_TRCD(3)
0118     | SDRAMC_CR_TRAS(5)
0119     | SDRAMC_CR_TXSR(9),
0120   .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
0121   .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
0122       SDRAMC_CFR1_TMRD(2),
0123   .sdramc_lpr = 0
0124 };
0125
0126 #elif ATSAM_MCK == 123000000
0127 const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
0128   .sdramc_tr = 960,
0129   .sdramc_cr =
0130       SDRAMC_CR_NC_COL9
0131     | SDRAMC_CR_NR_ROW13
0132     | SDRAMC_CR_NB_BANK4
0133     | SDRAMC_CR_CAS_LATENCY3
0134     | SDRAMC_CR_DBW
0135     | SDRAMC_CR_TWR(2)
0136     | SDRAMC_CR_TRC_TRFC(8)
0137     | SDRAMC_CR_TRP(2)
0138     | SDRAMC_CR_TRCD(3)
0139     | SDRAMC_CR_TRAS(6)
0140     | SDRAMC_CR_TXSR(9),
0141   .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
0142   .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
0143       SDRAMC_CFR1_TMRD(2),
0144   .sdramc_lpr = 0
0145 };
0146
0147 #else /* ATSAM_MCK unknown */
0148 #error Please check SDRAM settings for this frequency.
0149 #endif
0150
0151 #elif defined ATSAM_SDRAM_CUSTOM
0152 /*
0153  * Custom SDRAM defined. Provide only a dummy BOARD_Sdram_Config. This config
0154  * won't work and is only there so that test applications can link. The
0155  * application has to overwrite this BOARD_Sdram_Config!
0156  */
0157 const struct BOARD_Sdram_Config BOARD_Sdram_Config = {};
0158 #else
0159   #error SDRAM not supported.
0160 #endif