atsam/start/pmc-config.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2017 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp/atsam-clock-config.h>
0029 #include <bspopts.h>
0030 #include <chip.h>
0031
0032 #if ATSAM_MCK == 123000000
0033 /* PLLA/HCLK/MCK clock is set to 492/246/123MHz */
0034 const struct atsam_clock_config atsam_clock_config = {
0035   .pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x28U) |
0036       CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)),
0037   .mckr_init = (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK |
0038       PMC_MCKR_MDIV_PCK_DIV2),
0039   .mck_freq = 123*1000*1000
0040 };
0041 #elif ATSAM_MCK == 150000000
0042 /* PLLA/HCLK/MCK clock is set to 300/300/150MHz */
0043 const struct atsam_clock_config atsam_clock_config = {
0044   .pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) |
0045       CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)),
0046   .mckr_init = (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK |
0047       PMC_MCKR_MDIV_PCK_DIV2),
0048   .mck_freq = 150*1000*1000
0049 };
0050 #elif ATSAM_MCK == 60000000
0051 /* PLLA/HCLK/MCK clock is set to 60/60/60MHz */
0052 const struct atsam_clock_config atsam_clock_config = {
0053   .pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x4U) |
0054       CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)),
0055   .mckr_init = (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK |
0056       PMC_MCKR_MDIV_EQ_PCK),
0057   .mck_freq = 60*1000*1000
0058 };
0059 #error Unknown ATSAM_MCK.
0060 #endif