atsam/start/bspstarthooks.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp.h>
0029 #include <bsp/start.h>
0030 #include <bsp/pin-config.h>
0031 #include <bsp/atsam-clock-config.h>
0032
0033 #include <chip.h>
0034 #include <include/board_lowlevel.h>
0035 #include <include/board_memories.h>
0036
0037 #define SIZE_0K 0
0038 #define SIZE_32K (32 * 1024)
0039 #define SIZE_64K (64 * 1024)
0040 #define SIZE_128K (128 * 1024)
0041
0042 #define ITCMCR_SZ_0K 0x0
0043 #define ITCMCR_SZ_32K 0x6
0044 #define ITCMCR_SZ_64K 0x7
0045 #define ITCMCR_SZ_128K 0x8
0046
0047 static BSP_START_TEXT_SECTION void efc_send_command(uint32_t eefc)
0048 {
0049   EFC->EEFC_FCR = eefc | EEFC_FCR_FKEY_PASSWD;
0050 }
0051
0052 static BSP_START_TEXT_SECTION void tcm_enable(void)
0053 {
0054   SCB->ITCMCR |= SCB_ITCMCR_EN_Msk;
0055   SCB->DTCMCR |= SCB_DTCMCR_EN_Msk;
0056 }
0057
0058 static BSP_START_TEXT_SECTION void tcm_disable(void)
0059 {
0060   SCB->ITCMCR &= ~SCB_ITCMCR_EN_Msk;
0061   SCB->DTCMCR &= ~SCB_DTCMCR_EN_Msk;
0062 }
0063
0064 static BSP_START_TEXT_SECTION bool tcm_setup_and_check_if_do_efc_config(
0065   uintptr_t tcm_size,
0066   uint32_t itcmcr_sz
0067 )
0068 {
0069   if (tcm_size == SIZE_0K && itcmcr_sz == ITCMCR_SZ_0K) {
0070     tcm_disable();
0071     return false;
0072   } else if (tcm_size == SIZE_32K && itcmcr_sz == ITCMCR_SZ_32K) {
0073     tcm_enable();
0074     return false;
0075   } else if (tcm_size == SIZE_64K && itcmcr_sz == ITCMCR_SZ_64K) {
0076     tcm_enable();
0077     return false;
0078   } else if (tcm_size == SIZE_128K && itcmcr_sz == ITCMCR_SZ_128K) {
0079     tcm_enable();
0080     return false;
0081   } else {
0082     return true;
0083   }
0084 }
0085
0086 static bool ATSAM_START_SRAM_SECTION sdram_settings_unchanged(void)
0087 {
0088   return (
0089     (SDRAMC->SDRAMC_CR == BOARD_Sdram_Config.sdramc_cr) &&
0090     (SDRAMC->SDRAMC_TR == BOARD_Sdram_Config.sdramc_tr) &&
0091     (SDRAMC->SDRAMC_MDR == BOARD_Sdram_Config.sdramc_mdr) &&
0092     (SDRAMC->SDRAMC_CFR1 == BOARD_Sdram_Config.sdramc_cfr1)
0093   );
0094 }
0095
0096 static void ATSAM_START_SRAM_SECTION setup_CPU_and_SDRAM(void)
0097 {
0098   SystemInit();
0099   if (!PMC_IsPeriphEnabled(ID_SDRAMC) || !sdram_settings_unchanged()) {
0100     BOARD_ConfigureSdram();
0101   }
0102 }
0103
0104 static void configure_tcm(void)
0105 {
0106   uintptr_t tcm_size;
0107   uint32_t itcmcr_sz;
0108
0109   tcm_size = (uintptr_t) atsam_memory_dtcm_size;
0110   itcmcr_sz = (SCB->ITCMCR & SCB_ITCMCR_SZ_Msk) >> SCB_ITCMCR_SZ_Pos;
0111
0112   if (tcm_setup_and_check_if_do_efc_config(tcm_size, itcmcr_sz)) {
0113     if (tcm_size == SIZE_128K) {
0114       efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
0115       efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
0116       tcm_enable();
0117     } else if (tcm_size == SIZE_64K) {
0118       efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
0119       efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
0120       tcm_enable();
0121     } else if (tcm_size == SIZE_32K) {
0122       efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
0123       efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
0124       tcm_enable();
0125     } else {
0126       efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
0127       efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
0128       tcm_disable();
0129     }
0130   }
0131 }
0132
0133 void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
0134 {
0135   system_init_flash(BOARD_MCK);
0136
0137   PIO_Configure(&atsam_pin_config[0], atsam_pin_config_count);
0138   MATRIX->CCFG_SYSIO = atsam_matrix_ccfg_sysio;
0139
0140   configure_tcm();
0141 #if ATSAM_CHANGE_CLOCK_FROM_SRAM != 0
0142   /* Early copy of .fast_text section for CPU and SDRAM setup. */
0143   bsp_start_memcpy_libc(
0144     bsp_section_fast_text_begin,
0145     bsp_section_fast_text_load_begin,
0146     (size_t) bsp_section_fast_text_size
0147   );
0148 #endif
0149   setup_CPU_and_SDRAM();
0150
0151   if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
0152     SCB_EnableICache();
0153   }
0154
0155   if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
0156     SCB_EnableDCache();
0157   }
0158
0159   _SetupMemoryRegion();
0160 }
0161
0162 void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
0163 {
0164   bsp_start_copy_sections_compact();
0165   SCB_CleanDCache();
0166   SCB_InvalidateICache();
0167   bsp_start_clear_bss();
0168 }