atsam/spi/atsam_spi_init.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp/atsam-spi.h>
0029 #include <bsp/spi.h>
0030
0031 /** SPI0 MISO pin */
0032 #define PIN_SPI0_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
0033 /** SPI0 MOSI pin */
0034 #define PIN_SPI0_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
0035 /** SPI0 CS0 pin */
0036 #define PIN_SPI0_NPCS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT}
0037 /** SPI0 CS1_1 pin */
0038 #define PIN_SPI0_NPCS1_1 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
0039 /** SPI0 CS1_2 pin */
0040 #define PIN_SPI0_NPCS1_2 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
0041 /** SPI0 CS2 pin */
0042 #define PIN_SPI0_NPCS2 {PIO_PD12C_SPI0_NPCS2, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
0043 /** SPI0 CS3 pin */
0044 #define PIN_SPI0_NPCS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
0045 /** SPI0 Clock pin */
0046 #define PIN_SPI0_CLOCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
0047
0048 /** SPI1 MISO pin */
0049 #define PIN_SPI1_MISO {PIO_PC26C_SPI1_MISO, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0050 /** SPI1 MOSI pin */
0051 #define PIN_SPI1_MOSI {PIO_PC27C_SPI1_MOSI, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0052 /** SPI1 CS0 pin */
0053 #define PIN_SPI1_NPCS0 {PIO_PC25C_SPI1_NPCS0, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0054 /** SPI1 CS1_1 pin */
0055 #define PIN_SPI1_NPCS1_1 {PIO_PC28C_SPI1_NPCS1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0056 /** SPI1 CS1_2 pin */
0057 #define PIN_SPI1_NPCS1_2 {PIO_PD0C_SPI1_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
0058 /** SPI1 CS2_1 pin */
0059 #define PIN_SPI1_NPCS2_1 {PIO_PC29C_SPI1_NPCS2, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0060 /** SPI1 CS2_2 pin */
0061 #define PIN_SPI1_NPCS2_2 {PIO_PD1C_SPI1_NPCS2, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
0062 /** SPI1 CS3_1 pin */
0063 #define PIN_SPI1_NPCS3_1 {PIO_PC30C_SPI1_NPCS3, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0064 /** SPI1 CS3_2 pin */
0065 #define PIN_SPI1_NPCS3_2 {PIO_PD2C_SPI1_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
0066 /** SPI1 Clock pin */
0067 #define PIN_SPI1_CLOCK {PIO_PC24C_SPI1_SPCK, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
0068
0069 int atsam_register_spi_0(void)
0070 {
0071   static const Pin pins[] = {
0072     PIN_SPI0_MISO,
0073     PIN_SPI0_MOSI,
0074     PIN_SPI0_NPCS0,
0075     PIN_SPI0_NPCS1_1,
0076     PIN_SPI0_NPCS1_2,
0077     PIN_SPI0_NPCS2,
0078     PIN_SPI0_NPCS3,
0079     PIN_SPI0_CLOCK
0080   };
0081
0082   static const atsam_spi_config config = {
0083     .spi_peripheral_id = ID_SPI0,
0084     .spi_regs = SPI0,
0085     .pins = pins,
0086     .pin_count = RTEMS_ARRAY_SIZE(pins),
0087     .chip_select_decode = false
0088   };
0089
0090   return spi_bus_register_atsam(
0091     ATSAM_SPI_0_BUS_PATH,
0092     &config
0093   );
0094 }
0095
0096 int atsam_register_spi_1(void)
0097 {
0098   static const Pin pins[] = {
0099     PIN_SPI1_MISO,
0100     PIN_SPI1_MOSI,
0101     PIN_SPI1_NPCS0,
0102     PIN_SPI1_NPCS1_1,
0103     PIN_SPI1_NPCS1_2,
0104     PIN_SPI1_NPCS2_1,
0105     PIN_SPI1_NPCS2_2,
0106     PIN_SPI1_NPCS3_1,
0107     PIN_SPI1_NPCS3_2,
0108     PIN_SPI1_CLOCK
0109   };
0110
0111   static const atsam_spi_config config = {
0112     .spi_peripheral_id = ID_SPI1,
0113     .spi_regs = SPI1,
0114     .pins = pins,
0115     .pin_count = RTEMS_ARRAY_SIZE(pins),
0116     .chip_select_decode = false
0117   };
0118
0119   return spi_bus_register_atsam(
0120     ATSAM_SPI_1_BUS_PATH,
0121     &config
0122   );
0123 }