libchip/include/usbhs.h

0001 /* ---------------------------------------------------------------------------- */
0002 /*                  Atmel Microcontroller Software Support                      */
0003 /*                       SAM Software Package License                           */
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0005 /* Copyright (c) 2015, Atmel Corporation                                        */
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0029
0030 /** \file */
0031
0032 #ifndef USBHS_H
0033 #define USBHS_H
0034 /** addtogroup usbd_hal
0035  *@{
0036  */
0037
0038 #define  USB_DEVICE_HS_SUPPORT
0039
0040 //! Control endpoint size
0041 #define  USB_DEVICE_EP_CTRL_SIZE       64
0042
0043 /** Indicates chip has an UDP High Speed. */
0044 #define CHIP_USB_UDP
0045
0046 /** Indicates chip has an internal pull-up. */
0047 #define CHIP_USB_PULLUP_INTERNAL
0048
0049 /** Number of USB endpoints */
0050 #define CHIP_USB_NUMENDPOINTS   10
0051
0052 /** Endpoints max packet size */
0053 #define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \
0054     ((ep == 0) ? 64 : 1024)
0055
0056 /** Endpoints Number of Bank */
0057 #define CHIP_USB_ENDPOINTS_BANKS(ep)            ((ep==0)?1:((ep<=2)?3:2))
0058
0059
0060 #define CHIP_USB_ENDPOINTS_HBW(ep)               ((((ep)>=1) &&((ep)<=2))?true:false)
0061
0062 /** Endpoints DMA support */
0063 #define CHIP_USB_ENDPOINTS_DMA(ep)              ((((ep)>=1)&&((ep)<=7))?true:false)
0064
0065 /** Max size of the FMA FIFO */
0066 #define DMA_MAX_FIFO_SIZE     (65536/1)
0067 /** fifo space size in DW */
0068 #define EPT_VIRTUAL_SIZE      8192
0069
0070
0071 //! @name USBHS Host IP properties
0072 //!
0073 //! @{
0074 //! Get maximal number of endpoints
0075 #define uhd_get_pipe_max_nbr()                (9)
0076 #define USBHS_EPT_NUM                        (uhd_get_pipe_max_nbr()+1)
0077 //! Get maximal number of banks of endpoints
0078 #define uhd_get_pipe_bank_max_nbr(ep)         ((ep == 0) ? 1 : ((ep <= 2) ? 3 : 2))
0079 //! Get maximal size of endpoint (3X, 1024/64)
0080 #define uhd_get_pipe_size_max(ep)             (((ep) == 0) ? 64 : 1024)
0081 //! Get DMA support of endpoints
0082 #define Is_uhd_pipe_dma_supported(ep)         ((((ep) >= 1) && ((ep) <= 7)) ? true : false)
0083 //! Get High Band Width support of endpoints
0084 #define Is_uhd_pipe_high_bw_supported(ep)     (((ep) >= 2) ? true : false)
0085 //! @}
0086
0087 typedef enum {
0088     HOST_MODE = 0,
0089     DEVICE_MODE = 1
0090 } USB_Mode_t;
0091
0092 //! Maximum transfer size on USB DMA
0093 #define UHD_PIPE_MAX_TRANS 0x8000
0094
0095 /**
0096 =================================
0097         USBHS_CTRL
0098 =================================
0099 **/
0100
0101 /**
0102  * \brief Freeze or unfreeze USB clock
0103  * \param pUsbhs   Pointer to an USBHS instance.
0104  * \param Enable Enable or disable
0105  */
0106 __STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs)
0107 {
0108     pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
0109 }
0110
0111 /**
0112  * \brief Freeze or unfreeze USB clock
0113  * \param pUsbhs   Pointer to an USBHS instance.
0114  * \param Enable Enable or disable
0115  */
0116 __STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs)
0117 {
0118     pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK);
0119 }
0120 /**
0121  * \brief Freeze or unfreeze USB clock
0122  * \param pUsbhs   Pointer to an USBHS instance.
0123  * \param Enable Enable or disable
0124  */
0125 __STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable)
0126 {
0127
0128     if (!Enable)
0129         pUsbhs->USBHS_CTRL |= (1 << 8);
0130     else
0131         pUsbhs->USBHS_CTRL &= ~((uint32_t)(1 << 8));
0132 }
0133
0134 /**
0135  * \brief Enables or disables USB
0136  * \param pUsbhs   Pointer to an USBHS instance.
0137  * \param Enable Enable or disable
0138  */
0139
0140 __STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable)
0141 {
0142     if (Enable)
0143         pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE;
0144     else
0145         pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE);
0146 }
0147
0148
0149 /**
0150  * \brief Device or Host Mode
0151  * \param pUsbhs   Pointer to an USBHS instance.
0152  * \param Mode   Device or Host Mode
0153  */
0154
0155 __STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode)
0156 {
0157     if (Mode)
0158         pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE;
0159     else
0160         pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE);
0161 }
0162
0163 /********************* USBHS_SR  *****************/
0164
0165 /**
0166  * \brief Check if clock is usable or not
0167  * \param pUsbhs   Pointer to an USBHS instance.
0168  * \return 1 if USB clock is usable
0169  */
0170
0171 __STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs)
0172 {
0173     return ((pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14);
0174 }
0175
0176
0177 /**
0178  * \brief Raise interrupt for endpoint.
0179  * \param pUsbhs   Pointer to an USBHS instance.
0180  * \return USB status
0181  */
0182
0183 __STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs)
0184 {
0185     return (pUsbhs->USBHS_SR);
0186 }
0187
0188 /**
0189  * \brief Enable or disable USB address
0190  * \param pUsbhs   Pointer to an USBHS instance.
0191  * \return USB speed status
0192  */
0193
0194 __STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs)
0195 {
0196     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk));
0197 }
0198
0199
0200 /**
0201  * \brief Enable or disable USB address
0202  * \param pUsbhs   Pointer to an USBHS instance.
0203  * \return USB speed status
0204  */
0205
0206 __STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs)
0207 {
0208     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ?
0209            true : false;
0210 }
0211
0212
0213 /**
0214  * \brief Enable or disable USB address
0215  * \param pUsbhs   Pointer to an USBHS instance.
0216  * \return USB speed status
0217  */
0218
0219 __STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs)
0220 {
0221     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ?
0222            true : false;
0223 }
0224
0225 /**
0226  * \brief Enable or disable USB address
0227  * \param pUsbhs   Pointer to an USBHS instance.
0228  * \return USB speed status
0229  */
0230
0231 __STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs)
0232 {
0233     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ?
0234            true : false;
0235 }
0236 /********************* USBHS_SCR  *****************/
0237
0238 /**
0239  * \brief Raise interrupt for endpoint.
0240  * \param pUsbhs   Pointer to an USBHS instance.
0241  * \param AckType Interrupt Acknowledge type
0242  */
0243
0244 __STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType)
0245 {
0246     pUsbhs->USBHS_SCR |= AckType;
0247 }
0248
0249 /********************* USBHS_SFR  *****************/
0250
0251 /**
0252  * \brief Raise interrupt for endpoint.
0253  * \param pUsbhs   Pointer to an USBHS instance.
0254  * \param SetStatus Set USB status
0255  */
0256
0257 __STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus)
0258 {
0259     pUsbhs->USBHS_SFR |= SetStatus;
0260 }
0261
0262
0263 /*--------------------------------------------------------
0264 * =========== USB Device functions ======================
0265 *---------------------------------------------------------*/
0266
0267 /**
0268  * \brief Enable or disable USB address
0269  * \param pUsbhs   Pointer to an USBHS instance.
0270  * \param SetStatus Set USB status
0271  */
0272
0273 __STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable)
0274 {
0275     if (Enable)
0276         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
0277     else
0278         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN);
0279 }
0280
0281 /**
0282  * \brief Configure USB address and enable or disable it
0283  * \param pUsbhs   Pointer to an USBHS instance.
0284  * \param Addr   USB device status
0285  */
0286
0287 __STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr)
0288 {
0289     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr);
0290     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
0291 }
0292
0293 /**
0294  * \brief Get USB address
0295  * \param pUsbhs   Pointer to an USBHS instance.
0296  */
0297
0298 __STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs)
0299 {
0300     return (pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk);
0301 }
0302
0303 /**
0304  * \brief Attach or detach USB.
0305  * \param pUsbhs   Pointer to an USBHS instance.
0306  * \param Enable Attachs or detach USB device
0307  */
0308
0309 __STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable)
0310 {
0311     if (Enable)
0312         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
0313     else
0314         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH);
0315
0316 }
0317
0318 /**
0319  * \brief Force Low Speed mode
0320  * \param pUsbhs   Pointer to an USBHS instance.
0321  * \param Enable Enables the Full speed
0322  */
0323
0324 __STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable)
0325 {
0326     if (Enable)
0327         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS;
0328     else
0329         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS);
0330 }
0331
0332 /**
0333  * \brief Disable/Enables High Speed mode
0334  * \param pUsbhs   Pointer to an USBHS instance.
0335  * \param Enable Enables/disable option
0336  */
0337
0338 __STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable)
0339 {
0340     uint32_t cfg = pUsbhs->USBHS_DEVCTRL;
0341     cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk);
0342
0343     if (Enable)
0344         pUsbhs->USBHS_DEVCTRL |= cfg;
0345     else
0346         pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS);
0347
0348 }
0349
0350 /**
0351  * \brief Set Remote WakeUp mode
0352  * \param pUsbhs   Pointer to an USBHS instance.
0353  */
0354
0355 __STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs)
0356 {
0357     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
0358 }
0359
0360 /**
0361  * \brief Disable/Enables Test mode
0362  * \param pUsbhs   Pointer to an USBHS instance.
0363  * \param mode Enables/disable option
0364  */
0365
0366 __STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode)
0367 {
0368     pUsbhs->USBHS_DEVCTRL |= mode;
0369 }
0370
0371
0372 /**
0373  * \brief Disable/Enables HS Test mode
0374  * \param pUsbhs   Pointer to an USBHS instance.
0375  */
0376
0377 __STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs)
0378 {
0379     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED;
0380 }
0381
0382 /**
0383  * \brief Read status for an interrupt
0384  * \param pUsbhs   Pointer to an USBHS instance.
0385  * \param IntType Interrupt type
0386  */
0387
0388 __STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType)
0389 {
0390     return (pUsbhs->USBHS_DEVISR & IntType);
0391 }
0392
0393 /**
0394  * \brief Read status for an Endpoint
0395  * \param pUsbhs   Pointer to an USBHS instance.
0396  * \param EpNum  Endpoint
0397  */
0398
0399 __STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum)
0400 {
0401     return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_PEP_0 << EpNum));
0402 }
0403
0404 /**
0405  * \brief Read status for a DMA Endpoint
0406  * \param pUsbhs   Pointer to an USBHS instance.
0407  * \param DmaNum  DMA Endpoint
0408  */
0409 __STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum)
0410 {
0411     return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_DMA_1 << DmaNum));
0412 }
0413
0414 /**
0415  * \brief Acknowledge interrupt for endpoint.
0416  * \param pUsbhs   Pointer to an USBHS instance.
0417  * \param IntType Interrupt Type
0418  */
0419
0420 __STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType)
0421 {
0422     pUsbhs->USBHS_DEVICR |=  IntType;
0423 }
0424
0425 /**
0426  * \brief Raise interrupt for endpoint.
0427  * \param pUsbhs   Pointer to an USBHS instance.
0428  * \param IntType Interrupt Type
0429  */
0430
0431
0432 __STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType)
0433 {
0434     pUsbhs->USBHS_DEVIFR |=  IntType;
0435 }
0436
0437 /**
0438  * \brief Raise DMA interrupt for endpoint.
0439  * \param pUsbhs   Pointer to an USBHS instance.
0440  * \param IntType Interrupt Type
0441  */
0442 __STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma)
0443 {
0444     assert(Dma < USBHSDEVDMA_NUMBER);
0445     pUsbhs->USBHS_DEVIFR |=  (USBHS_DEVIFR_DMA_1 << Dma);
0446 }
0447
0448 /**
0449  * \brief check for interrupt of endpoint.
0450  * \param pUsbhs   Pointer to an USBHS instance.
0451  * \param IntType Interrupt Type
0452  */
0453
0454 __STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType)
0455 {
0456     return (pUsbhs->USBHS_DEVIMR &  IntType);
0457 }
0458
0459 /**
0460  * \brief Check if endpoint's interrupt is enabled for a given endpoint number
0461  * \param pUsbhs   Pointer to an USBHS instance.
0462  * \param EpNum Endpoint number
0463  */
0464
0465 __STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum)
0466 {
0467     return (pUsbhs->USBHS_DEVIMR &  (USBHS_DEVIMR_PEP_0 << EpNum));
0468 }
0469
0470
0471 /**
0472  * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint
0473  * DMA number
0474  * \param pUsbhs   Pointer to an USBHS instance.
0475  * \param DmaNum Endpoint's DMA number
0476  */
0477
0478 __STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum)
0479 {
0480     return (pUsbhs->USBHS_DEVIMR &  (USBHS_DEVIMR_DMA_1 << DmaNum));
0481 }
0482
0483
0484 /**
0485  * \brief Enables Interrupt
0486  * \param pUsbhs   Pointer to an USBHS instance.
0487  * \param IntType Interrupt Type
0488  */
0489 __STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType)
0490 {
0491     pUsbhs->USBHS_DEVIER |=  IntType;
0492 }
0493
0494 /**
0495  * \brief Enables interrupt for a given endpoint.
0496  * \param pUsbhs   Pointer to an USBHS instance.
0497  * \param DmaNum Endpoint's DMA number
0498  */
0499 __STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum)
0500 {
0501     pUsbhs->USBHS_DEVIER |=  (USBHS_DEVIER_PEP_0 << EpNum);
0502 }
0503
0504 /**
0505  * \brief Enables DMA interrupt for a given endpoint.
0506  * \param pUsbhs   Pointer to an USBHS instance.
0507  * \param DmaEp  Endpoint's DMA interrupt number
0508  */
0509
0510 __STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp)
0511 {
0512     assert(DmaEp < USBHSDEVDMA_NUMBER);
0513     pUsbhs->USBHS_DEVIER |=  (USBHS_DEVIER_DMA_1 << DmaEp);
0514 }
0515
0516 /**
0517 * \brief Disables interrupt for endpoint.
0518 * \param pUsbhs   Pointer to an USBHS instance.
0519 * \param IntType Int type
0520 */
0521
0522 __STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType)
0523 {
0524     pUsbhs->USBHS_DEVIDR |=  IntType;
0525 }
0526
0527 /**
0528 * \brief Disables interrupt for endpoint.
0529 * \param pUsbhs  Pointer to an USBHS instance.
0530 * \param Ep    Endpoint number
0531 */
0532
0533 __STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep)
0534 {
0535     pUsbhs->USBHS_DEVIDR |=  (USBHS_DEVIDR_PEP_0 << Ep);
0536 }
0537
0538 /**
0539 * \brief Disables DMA interrupt for endpoint.
0540 * \param pUsbhs  Pointer to an USBHS instance.
0541 * \param DmaEp Endpoint's DMA number
0542 */
0543 __STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp)
0544 {
0545     assert(DmaEp < USBHSDEVDMA_NUMBER);
0546     pUsbhs->USBHS_DEVIDR |=  (USBHS_DEVIDR_DMA_1 << DmaEp);
0547 }
0548
0549
0550 /**
0551 * \brief Enables or disables endpoint.
0552 * \param pUsbhs  Pointer to an USBHS instance.
0553 * \param Enable Enable/disable endpoint
0554 */
0555
0556 __STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
0557 {
0558     if (Enable)
0559         pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep);
0560     else
0561         pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep);
0562
0563 }
0564
0565
0566 /**
0567 * \brief Rests Endpoint
0568 * \param pUsbhs  Pointer to an USBHS instance.
0569 * \param Ep    Endpoint Number
0570 */
0571
0572 __STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep)
0573 {
0574     pUsbhs->USBHS_DEVEPT |=  (USBHS_DEVEPT_EPRST0 << Ep);
0575     pUsbhs->USBHS_DEVEPT &=  ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep);
0576 }
0577
0578 /**
0579 * \brief Checks if Endpoint is enable
0580 * \param pUsbhs  Pointer to an USBHS instance.
0581 * \param Ep    Endpoint Number
0582 */
0583
0584 __STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep)
0585 {
0586     return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep));
0587 }
0588
0589 /**
0590 * \brief Get MicrFrame number
0591 * \param pUsbhs  Pointer to an USBHS instance.
0592 * \retruns Micro frame number
0593 */
0594 __STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs)
0595 {
0596     return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk);
0597 }
0598
0599
0600 /**
0601 * \brief Get Frame number
0602 * \param pUsbhs  Pointer to an USBHS instance.
0603 * \retruns frame number
0604 */
0605 __STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs)
0606 {
0607     return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk)
0608              >> USBHS_DEVFNUM_FNUM_Pos);
0609 }
0610
0611 /**
0612 * \brief Get Frame number CRC error
0613 * \param pUsbhs  Pointer to an USBHS instance.
0614 * \retruns Frame number error status
0615 */
0616 __STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs)
0617 {
0618     return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15);
0619 }
0620
0621 /*-----------------------------------------
0622 * =========== USB Device's Endpoint functions ========
0623 *------------------------------------------*/
0624
0625 /**
0626  * Set Endpoints configuration
0627  * Bank size, type and direction
0628  */
0629 __STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep,
0630                                         const uint8_t Type, const uint8_t Dir,
0631                                         const uint8_t Size, const uint8_t Bank)
0632 {
0633
0634     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
0635         ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk);
0636     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
0637         ((Dir << 8) & USBHS_DEVEPTCFG_EPDIR);
0638     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
0639         (((Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk);
0640     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
0641         (((Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk);
0642 }
0643
0644
0645 /**
0646  * Enable or disable Auto switch of banks
0647  */
0648 __STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep,
0649         uint8_t Enable)
0650 {
0651     if (Enable)
0652         pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_AUTOSW;
0653     else
0654         pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW);
0655 }
0656
0657
0658 /**
0659  * Allocate Endpoint memory
0660  */
0661 __STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep)
0662 {
0663     pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_ALLOC;
0664 }
0665
0666
0667 /**
0668  * Free allocated Endpoint memory
0669  */
0670 __STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep)
0671 {
0672     pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC);
0673 }
0674
0675
0676 /**
0677  * Get Endpoint configuration
0678  */
0679 __STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep,
0680         uint32_t IntType)
0681 {
0682     return ((pUsbhs->USBHS_DEVEPTCFG[Ep]) & IntType);
0683 }
0684
0685 /**
0686  * Get Endpoint Type
0687  */
0688 __STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep)
0689 {
0690     return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk)
0691             >> USBHS_DEVEPTCFG_EPTYPE_Pos);
0692 }
0693
0694 /**
0695  * Get Endpoint Size
0696  */
0697 __STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep)
0698 {
0699     return (8 << ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk)
0700                     >> USBHS_DEVEPTCFG_EPSIZE_Pos));
0701 }
0702
0703
0704 /**
0705  * Sets ISO endpoint's Number of Transfer for High Speed
0706  */
0707 __STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep,
0708                                        uint8_t nbTrans)
0709 {
0710     pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans);
0711 }
0712
0713 /**
0714  * Check for interrupt types enabled for a given endpoint
0715  */
0716 __STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep,
0717         uint32_t EpIntType)
0718 {
0719     return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType);
0720 }
0721
0722
0723 /**
0724  * Enables an interrupt type for a given endpoint
0725  */
0726 __STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
0727         uint32_t EpInt)
0728 {
0729     pUsbhs->USBHS_DEVEPTIER[Ep] |=  EpInt;
0730 }
0731
0732 /**
0733  * Enables an interrupt type for a given endpoint
0734  */
0735 __STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep)
0736 {
0737     return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK);
0738 }
0739
0740 /**
0741  * Enables an interrupt type for a given endpoint
0742  */
0743 __STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep)
0744 {
0745     pUsbhs->USBHS_DEVEPTIER[Ep] =  USBHS_DEVEPTIER_KILLBKS;
0746 }
0747 /**
0748  * Disables an interrupt type for a given endpoint
0749  */
0750 __STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
0751         uint32_t EpInt)
0752 {
0753     pUsbhs->USBHS_DEVEPTIDR[Ep] |=  EpInt;
0754 }
0755
0756 /**
0757  * Clears register/acknowledge for a given endpoint
0758  */
0759 __STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep,
0760         uint32_t EpInt)
0761 {
0762     pUsbhs->USBHS_DEVEPTICR[Ep] |=  EpInt;
0763 }
0764
0765 /**
0766  * Sets/Raise register for a given endpoint
0767  */
0768 __STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
0769 {
0770     pUsbhs->USBHS_DEVEPTIFR[Ep] |=  EpInt;
0771 }
0772
0773 /**
0774  * Gets interrupt status for a given EP
0775  */
0776 __STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep,
0777         uint32_t EpInt)
0778 {
0779     return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt);
0780 }
0781
0782 /**
0783  * Check if given endpoint's bank is free
0784  */
0785 __STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep)
0786 {
0787     if ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk))
0788         return false;
0789     else
0790         return true;
0791 }
0792
0793 /**
0794  * Read endpoint's bank number in use
0795  */
0796 __STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep)
0797 {
0798     return ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)
0799              >> USBHS_DEVEPTISR_NBUSYBK_Pos);
0800 }
0801
0802
0803 /**
0804  * Read endpoint's byte count of the FIFO
0805  */
0806 __STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep)
0807 {
0808     return (uint16_t)((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk)
0809                        >> USBHS_DEVEPTISR_BYCT_Pos);
0810 }
0811
0812 /*--------------------------------------------------------
0813 * =========== USB Device's Ep's DMA functions =========
0814 *---------------------------------------------------------*/
0815
0816 /**
0817 * \brief Sets DMA next descriptor address
0818 * \param pUsbDma  USBHS device DMA instance
0819 * \param Desc NDA address
0820 */
0821 __STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc)
0822 {
0823     pUsbDma->USBHS_DEVDMANXTDSC = Desc;
0824 }
0825
0826 /**
0827 * \brief Gets DMA next descriptor address
0828 * \param pUsbDma  USBHS device DMA instance
0829 * \return Next DMA descriptor
0830 */
0831 __STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma)
0832 {
0833     return (pUsbDma->USBHS_DEVDMANXTDSC);
0834 }
0835
0836 /**
0837 * \brief Sets USBHS's DMA Buffer addresse
0838 * \param pUsbDma  USBHS device DMA instance
0839 * \param Addr  DMA's buffer Addrs
0840 */
0841 __STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr)
0842 {
0843     pUsbDma->USBHS_DEVDMAADDRESS = Addr;
0844 }
0845
0846
0847 /**
0848 * \brief Gets USBHS's DMA Buffer addresse
0849 * \param pUsbDma  USBHS device DMA instance
0850 * \return DMA addrs
0851 */
0852 __STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma)
0853 {
0854     return (pUsbDma->USBHS_DEVDMAADDRESS);
0855 }
0856
0857 /**
0858 * \brief Setup the USBHS DMA
0859 * \param pUsbDma  USBHS device DMA instance
0860 * \param Cfg  DMA's configuration
0861 */
0862 __STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg)
0863 {
0864     pUsbDma->USBHS_DEVDMACONTROL |= Cfg;
0865 }
0866
0867 /**
0868 * \brief Get DMA configuration
0869 * \param pUsbDma  USBHS device DMA instance
0870 * \return DMA control setup
0871 */
0872 __STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma)
0873 {
0874     return (pUsbDma->USBHS_DEVDMACONTROL);
0875 }
0876
0877
0878 /**
0879 * \brief Set DMA status
0880 * \param pUsbDma  USBHS device DMA instance
0881 * \Status Set DMA status
0882 */
0883 __STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status)
0884 {
0885     pUsbDma->USBHS_DEVDMASTATUS = Status;
0886 }
0887
0888
0889 /**
0890 * \brief Get Dma Status
0891 * \param pUsbDma  USBHS device DMA instance
0892 * \return Dma status
0893 */
0894 __STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma)
0895 {
0896     return (pUsbDma->USBHS_DEVDMASTATUS);
0897 }
0898
0899
0900 /**
0901 * \brief Get DMA buffer's count
0902 * \param pUsbDma  USBHS device DMA instance
0903 * \return Buffer count
0904 */
0905 __STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma)
0906 {
0907     return ((pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk)
0908              >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
0909 }
0910
0911
0912 /*--------------------------------------------------------
0913 * =========== USB Host Functions  ========================
0914 *---------------------------------------------------------*/
0915
0916 /** Number of USB endpoints */
0917 #define CHIP_USB_NUMPIPE            10
0918 /** Number of USB endpoints */
0919 #define CHIP_USB_DMA_NUMPIPE        7
0920
0921 /** Endpoints max paxcket size */
0922 #define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \
0923     ((ep == 0) ? 64 : 1024)
0924
0925 /** Endpoints Number of Bank */
0926 #define CHIP_USB_PIPE_BANKS(ep)                 ((ep==0)?1:((ep<=2)?3:2))
0927
0928
0929 #define CHIP_USB_PIPE_HBW(ep)                   ((((ep)>=1) &&((ep)<=2))?true:false)
0930
0931 /** Endpoints DMA support */
0932 #define CHIP_USB_PIPE_DMA(ep)                   ((((ep)>=1)&&((ep)<=7))?true:false)
0933
0934 /**
0935 * \brief Sets USB host's speed to Normal , it sets to HS from FS
0936 * \param pUsbhs  USBHS host instance
0937 */
0938 __STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs)
0939 {
0940     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
0941     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL;
0942 }
0943
0944 /**
0945 * \brief Sets USB host's speed to Low speed
0946 * \param pUsbhs  USBHS host instance
0947 */
0948 __STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs)
0949 {
0950     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
0951     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER;
0952 }
0953
0954 /**
0955 * \brief Sets USB host's speed to forced Full speed
0956 * \param pUsbhs  USBHS host instance
0957 */
0958 __STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs)
0959 {
0960     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
0961     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS;
0962 }
0963
0964 /**
0965 * \brief Sets USB host sends reste signal on USB Bus
0966 * \param pUsbhs  USBHS host instance
0967 */
0968 __STATIC_INLINE void USBHS_Reset(void)
0969 {
0970     USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET;
0971 }
0972
0973 /**
0974 * \brief Sets USB host sends reste signal on USB Bus
0975 * \param pUsbhs  USBHS host instance
0976 */
0977 __STATIC_INLINE void USBHS_StopReset(void)
0978 {
0979     USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET;
0980 }
0981
0982 /**
0983 * \brief Sets USB host send Resume on USB bus
0984 * \param pUsbhs  USBHS host instance
0985 */
0986 __STATIC_INLINE void USBHS_Resume(void)
0987 {
0988     USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME;
0989 }
0990
0991 /**
0992 * \brief Sets USB host Enable the Generation of  Start of Frame
0993 * \param pUsbhs  USBHS host instance
0994 */
0995 __STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs)
0996 {
0997     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE;
0998 }
0999
1000 /**
1001 * \brief Sets USB host Enable the Generation of  Start of Frame
1002 * \param pUsbhs  USBHS host instance
1003 */
1004 __STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs)
1005 {
1006     return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8;
1007 }
1008 /**
1009 * \brief Sets USB host disable the Generation of  Start of Frame
1010 * \param pUsbhs  USBHS host instance
1011 */
1012 __STATIC_INLINE void USBHS_DisableSOF(void)
1013 {
1014     USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE;
1015 }
1016
1017 /**
1018 * \brief Gets USB host interrupt status
1019 * \param pUsbhs  USBHS host instance
1020 */
1021 __STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType)
1022 {
1023     return (pUsbhs->USBHS_HSTISR & IntType);
1024 }
1025
1026
1027 /**
1028  * \brief Gets USB host interrupt status
1029  * \param pUsbhs  USBHS host instance
1030  */
1031 __STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
1032 {
1033     assert(PipeInt < CHIP_USB_NUMPIPE);
1034     return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_PEP_0 << PipeInt));
1035 }
1036
1037
1038 /**
1039  * \brief Gets USB host interrupt status
1040  * \param pUsbhs  USBHS host instance
1041  */
1042 __STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs,
1043         uint8_t PipeInt)
1044 {
1045     assert(PipeInt);
1046     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1047     return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_DMA_1 << PipeInt));
1048 }
1049
1050 /**
1051  * \brief Gets USB host interrupt status
1052  * \param pUsbhs  USBHS host instance
1053  */
1054 __STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType)
1055 {
1056     pUsbhs->USBHS_HSTICR = IntType;
1057 }
1058
1059 /**
1060  * \brief Gets USB host interrupt status
1061  * \param pUsbhs  USBHS host instance
1062  */
1063 __STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType)
1064 {
1065     pUsbhs->USBHS_HSTIFR = IntType;
1066 }
1067
1068 /**
1069  * \brief Gets USB host interrupt status
1070  * \param pUsbhs  USBHS host instance
1071  */
1072 __STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt)
1073 {
1074     assert(PipeInt);
1075     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1076     pUsbhs->USBHS_HSTIFR =  (USBHS_HSTIFR_DMA_1 << PipeInt);
1077 }
1078
1079 /*** Interrupt Mask ****/
1080 /**
1081  * \brief Gets USB host interrupt status
1082  * \param pUsbhs  USBHS host instance
1083  */
1084 __STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType)
1085 {
1086     return (pUsbhs->USBHS_HSTIMR & IntType);
1087 }
1088
1089 /**
1090  * \brief Gets USB host interrupt status
1091  * \param pUsbhs  USBHS host instance
1092  */
1093 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs,
1094         uint8_t PipeInt)
1095 {
1096     assert(PipeInt < CHIP_USB_NUMPIPE);
1097     return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt));
1098 }
1099
1100 /**
1101  * \brief Gets USB host interrupt status
1102  * \param pUsbhs  USBHS host instance
1103  */
1104 __STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs,
1105         uint8_t PipeInt)
1106 {
1107     assert(PipeInt);
1108     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1109     return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt));
1110 }
1111
1112 /*** Interrupt Disable ****/
1113 /**
1114  * \brief Gets USB host interrupt status
1115  * \param pUsbhs  USBHS host instance
1116  */
1117 __STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType)
1118 {
1119     pUsbhs->USBHS_HSTIDR = IntType;
1120 }
1121
1122 /**
1123  * \brief Gets USB host interrupt status
1124  * \param pUsbhs  USBHS host instance
1125  */
1126 __STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
1127 {
1128     assert(PipeInt < CHIP_USB_NUMPIPE);
1129     pUsbhs->USBHS_HSTIDR  = (USBHS_HSTIDR_PEP_0 << PipeInt);
1130 }
1131
1132 /**
1133  * \brief Gets USB host interrupt status
1134  * \param pUsbhs  USBHS host instance
1135  */
1136 __STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
1137 {
1138     assert(PipeInt);
1139     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1140     pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt);
1141 }
1142
1143 /*** Interrupt Enable ****/
1144
1145 /**
1146  * \brief Gets USB host interrupt status
1147  * \param pUsbhs  USBHS host instance
1148  */
1149 __STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType)
1150 {
1151     pUsbhs->USBHS_HSTIER = IntType;
1152 }
1153
1154 /**
1155  * \brief Gets USB host interrupt status
1156  * \param pUsbhs  USBHS host instance
1157  */
1158 __STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
1159 {
1160     assert(PipeInt < CHIP_USB_NUMPIPE);
1161     pUsbhs->USBHS_HSTIER = (USBHS_HSTIER_PEP_0 << PipeInt);
1162 }
1163
1164 /**
1165  * \brief Gets USB host interrupt status
1166  * \param pUsbhs  USBHS host instance
1167  */
1168 __STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
1169 {
1170     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
1171     pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt);
1172 }
1173
1174 /**
1175  * \brief Gets USB host interrupt status
1176  * \param pUsbhs  USBHS host instance
1177  */
1178 __STATIC_INLINE uint16_t USBHS_HostGetSOF(void)
1179 {
1180     return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >>
1181              USBHS_HSTFNUM_FNUM_Pos);
1182 }
1183
1184 /**
1185  * \brief Gets USB host interrupt status
1186  * \param pUsbhs  USBHS host instance
1187  */
1188 __STATIC_INLINE uint16_t USBHS_HostGetFramePos(void)
1189 {
1190     return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >>
1191              USBHS_HSTFNUM_FLENHIGH_Pos);
1192 }
1193
1194
1195 /**
1196  * \brief Gets USB host interrupt status
1197  * \param pUsbhs  USBHS host instance
1198  */
1199 __STATIC_INLINE uint16_t USBHS_HostGetMSOF(void)
1200 {
1201     return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >>
1202              USBHS_HSTFNUM_MFNUM_Pos);
1203 }
1204
1205 __STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe,
1206                                        uint8_t Addr)
1207 {
1208     assert(Pipe < CHIP_USB_NUMPIPE);
1209
1210     if (Pipe < 4)
1211         pUsbhs->USBHS_HSTADDR1 |= (Addr << (8 * Pipe));
1212     else if ((Pipe < 8) && (Pipe >= 4))
1213         pUsbhs->USBHS_HSTADDR2 |= (Addr << (8 * (Pipe - 4)));
1214     else
1215         pUsbhs->USBHS_HSTADDR3 |= (Addr << (8 * (Pipe - 8)));
1216
1217 }
1218
1219 __STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe)
1220 {
1221     assert(Pipe < CHIP_USB_NUMPIPE);
1222
1223     if (Pipe < 4)
1224         return (pUsbhs->USBHS_HSTADDR1 >>  (8 * Pipe));
1225     else if ((Pipe < 8) && (Pipe >= 4))
1226         return (pUsbhs->USBHS_HSTADDR2  >>  (8 * (Pipe - 4)));
1227     else
1228         return (pUsbhs->USBHS_HSTADDR3  >> (8 * (Pipe - 8)));
1229
1230 }
1231
1232 /**
1233  * \brief Gets USB host interrupt status
1234  * \param pUsbhs  USBHS host instance
1235  */
1236 __STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
1237 {
1238     assert(Pipe < CHIP_USB_NUMPIPE);
1239     pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe);
1240 }
1241
1242 /**
1243  * \brief Gets USB host interrupt status
1244  * \param pUsbhs  USBHS host instance
1245  */
1246 __STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe)
1247 {
1248     assert(Pipe < CHIP_USB_NUMPIPE);
1249     pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe);
1250 }
1251
1252 /**
1253  * \brief Gets USB host interrupt status
1254  * \param pUsbhs  USBHS host instance
1255  */
1256 __STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
1257 {
1258     assert(Pipe < CHIP_USB_NUMPIPE);
1259     return (pUsbhs->USBHS_HSTPIP & (USBHS_HSTPIP_PEN0 << Pipe));
1260 }
1261 /**
1262  * \brief Gets USB host interrupt status
1263  * \param pUsbhs  USBHS host instance
1264  */
1265 __STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe)
1266 {
1267     assert(Pipe < CHIP_USB_NUMPIPE);
1268     pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe);
1269     pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe);
1270 }
1271
1272 /**
1273  * \brief Gets USB host interrupt status
1274  * \param pUsbhs  USBHS host instance
1275  */
1276 __STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe,
1277         uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken,
1278         uint8_t pipeEpNum, uint8_t PipeIntFreq)
1279 {
1280     assert(Pipe < CHIP_USB_NUMPIPE);
1281     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= (pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(
1282                                            pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) |
1283                                        USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq));
1284 }
1285
1286 /**
1287  * \brief Gets USB host interrupt status
1288  * \param pUsbhs  USBHS host instance
1289  */
1290 __STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe)
1291 {
1292     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC;
1293
1294 }
1295
1296 /**
1297  * \brief Gets USB host interrupt status
1298  * \param pUsbhs  USBHS host instance
1299  */
1300 __STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe)
1301 {
1302     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC;
1303
1304 }
1305
1306
1307 /**
1308  * \brief Gets USB host interrupt status
1309  * \param pUsbhs  USBHS host instance
1310  */
1311 __STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe)
1312 {
1313     return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >>
1314                   USBHS_HSTPIPCFG_PSIZE_Pos));
1315
1316 }
1317
1318 /**
1319 * \brief Gets USB host interrupt status
1320 * \param pUsbhs  USBHS host instance
1321 */
1322 __STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe,
1323                                         uint32_t Token)
1324 {
1325     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk;
1326     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token;
1327
1328 }
1329
1330
1331 /**
1332  * \brief Gets USB host interrupt status
1333  * \param pUsbhs  USBHS host instance
1334  */
1335 __STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe)
1336 {
1337     return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk);
1338
1339 }
1340
1341
1342 /**
1343  * \brief Gets USB host interrupt status
1344  * \param pUsbhs  USBHS host instance
1345  */
1346 __STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe,
1347         uint8_t PipeType)
1348 {
1349     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk;
1350     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType;
1351
1352 }
1353
1354 /**
1355  * \brief Gets USB host interrupt status
1356  * \param pUsbhs  USBHS host instance
1357  */
1358 __STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe)
1359 {
1360     return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk);
1361
1362 }
1363
1364 __STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe)
1365 {
1366
1367     if (USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN)
1368         return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >>
1369                   USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80);
1370     else
1371         return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >>
1372                   USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00);
1373 }
1374
1375
1376
1377 /**
1378  * \brief Gets USB host interrupt status
1379  * \param pUsbhs  USBHS host instance
1380  */
1381 __STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
1382 {
1383     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW;
1384 }
1385
1386 /**
1387  * \brief Gets USB host interrupt status
1388  * \param pUsbhs  USBHS host instance
1389  */
1390 __STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
1391 {
1392     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW;
1393 }
1394
1395 /**
1396  * \brief Gets USB host interrupt status
1397  * \param pUsbhs  USBHS host instance
1398  */
1399 __STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe,
1400         uint8_t Freq)
1401 {
1402     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq);
1403 }
1404
1405
1406 /**
1407  * \brief Gets USB host interrupt status
1408  * \param pUsbhs  USBHS host instance
1409  */
1410 __STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe)
1411 {
1412     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN;
1413 }
1414
1415
1416 /**
1417  * \brief Gets USB host interrupt status
1418  * \param pUsbhs  USBHS host instance
1419  */
1420 __STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe)
1421 {
1422     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >>
1423              USBHS_HSTPIPISR_DTSEQ_Pos);
1424 }
1425
1426
1427 /**
1428  * \brief Gets USB host interrupt status
1429  * \param pUsbhs  USBHS host instance
1430  */
1431 __STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe)
1432 {
1433     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >>
1434              USBHS_HSTPIPISR_NBUSYBK_Pos);
1435 }
1436
1437
1438 /**
1439  * \brief Gets USB host interrupt status
1440  * \param pUsbhs  USBHS host instance
1441  */
1442 __STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe)
1443 {
1444     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >>
1445              USBHS_HSTPIPISR_CURRBK_Pos);
1446 }
1447
1448
1449 /**
1450  * \brief Gets USB host interrupt status
1451  * \param pUsbhs  USBHS host instance
1452  */
1453 __STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe)
1454 {
1455     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >>
1456              USBHS_HSTPIPISR_PBYCT_Pos);
1457 }
1458
1459 /**
1460  * \brief Gets USB host interrupt status
1461  * \param pUsbhs  USBHS host instance
1462  */
1463 __STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe)
1464 {
1465     return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK);
1466 }
1467
1468 /**
1469  * \brief Gets USB host interrupt status
1470  * \param pUsbhs  USBHS host instance
1471  */
1472 __STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe,
1473         uint32_t intType)
1474 {
1475     return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType);
1476 }
1477
1478 /**
1479  * \brief Gets USB host interrupt status
1480  * \param pUsbhs  USBHS host instance
1481  */
1482 __STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1483         uint32_t intType)
1484 {
1485     pUsbhs->USBHS_HSTPIPICR[Pipe] = intType;
1486 }
1487
1488 /**
1489  * \brief Gets USB host interrupt status
1490  * \param pUsbhs  USBHS host instance
1491  */
1492 __STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1493         uint32_t intType)
1494 {
1495     pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType;
1496 }
1497
1498 /**
1499  * \brief Gets USB host interrupt status
1500  * \param pUsbhs  USBHS host instance
1501  */
1502 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs,
1503         uint8_t Pipe, uint32_t intType)
1504 {
1505     return (pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType);
1506 }
1507
1508 /**
1509  * \brief Gets USB host interrupt status
1510  * \param pUsbhs  USBHS host instance
1511  */
1512 __STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1513         uint32_t intType)
1514 {
1515     pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType;
1516 }
1517
1518 /**
1519  * \brief Gets USB host interrupt status
1520  * \param pUsbhs  USBHS host instance
1521  */
1522 __STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
1523         uint32_t intType)
1524 {
1525     pUsbhs->USBHS_HSTPIPIER[Pipe] = intType;
1526 }
1527
1528 /**
1529  * \brief Gets USB host interrupt status
1530  * \param pUsbhs  USBHS host instance
1531  */
1532 __STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe)
1533 {
1534     pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE;
1535 }
1536
1537 /**
1538  * \brief Gets USB host interrupt status
1539  * \param pUsbhs  USBHS host instance
1540  */
1541 __STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe)
1542 {
1543     pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE;
1544 }
1545
1546 /**
1547  * \brief Gets USB host interrupt status
1548  * \param pUsbhs  USBHS host instance
1549  */
1550 __STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe)
1551 {
1552     return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8);
1553 }
1554
1555 /**
1556  * \brief Gets USB host interrupt status
1557  * \param pUsbhs  USBHS host instance
1558  */
1559 __STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq)
1560 {
1561     pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq - 1);
1562 }
1563
1564
1565 /**
1566  * \brief Gets USB host interrupt status
1567  * \param pUsbhs  USBHS host instance
1568  */
1569 __STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
1570 {
1571     pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err;
1572 }
1573
1574 /**
1575  * \brief Gets USB host interrupt status
1576  * \param pUsbhs  USBHS host instance
1577  */
1578 __STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe,
1579         uint8_t Err)
1580 {
1581     return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err);
1582 }
1583
1584
1585 /**
1586  * \brief Gets USB host interrupt status
1587  * \param pUsbhs  USBHS host instance
1588  */
1589 __STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe,
1590                                         uint8_t Err)
1591 {
1592     pUsbhs->USBHS_HSTPIPERR[Pipe] = Err;
1593 }
1594
1595
1596 __STATIC_INLINE  uint8_t USBHS_GetInterruptPipeNum(void)
1597 {
1598     uint32_t status = USBHS->USBHS_HSTISR;
1599     uint32_t mask = USBHS->USBHS_HSTIMR;
1600     return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM));
1601 }
1602
1603 static inline uint8_t USBHS_GetInterruptPipeDmaNum(void)
1604 {
1605     uint32_t status = USBHS->USBHS_HSTISR;
1606     uint32_t mask = USBHS->USBHS_HSTIMR;
1607     return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM - 1))) + 1);
1608 }
1609 /*--------------------------------------------------------
1610 * =========== USB Host's pipe DMA functions =========
1611 *---------------------------------------------------------*/
1612
1613 /**
1614 * \brief Sets DMA next descriptor address
1615 * \param pUsbDma  USBHS device DMA instance
1616 * \param Desc NDA addrs
1617 */
1618 __STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc)
1619 {
1620     pUsbDma->USBHS_HSTDMANXTDSC = Desc;
1621 }
1622
1623 /**
1624 * \brief Gets DMA next descriptor address
1625 * \param pUsbDma  USBHS device DMA instance
1626 * \return Next DMA descriptor
1627 */
1628 __STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma)
1629 {
1630     return (pUsbDma->USBHS_HSTDMANXTDSC);
1631 }
1632
1633 /**
1634 * \brief Sets USBHS's DMA Buffer addresse
1635 * \param pUsbDma  USBHS device DMA instance
1636 * \param Addr  DMA's buffer Addrs
1637 */
1638 __STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma,
1639         uint32_t Addr)
1640 {
1641     pUsbDma->USBHS_HSTDMAADDRESS = Addr;
1642 }
1643
1644
1645 /**
1646 * \brief Gets USBHS's DMA Buffer addresse
1647 * \param pUsbDma  USBHS device DMA instance
1648 * \return DMA addrs
1649 */
1650 __STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma)
1651 {
1652     return (pUsbDma->USBHS_HSTDMAADDRESS);
1653 }
1654
1655 /**
1656 * \brief Setup the USBHS DMA
1657 * \param pUsbDma  USBHS device DMA instance
1658 * \param Cfg  DMA's configuration
1659 */
1660 __STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg)
1661 {
1662     pUsbDma->USBHS_HSTDMACONTROL |= Cfg;
1663 }
1664
1665 /**
1666 * \brief Get DMA configuration
1667 * \param pUsbDma  USBHS device DMA instance
1668 * \return DMA control setup
1669 */
1670 __STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma)
1671 {
1672     return (pUsbDma->USBHS_HSTDMACONTROL);
1673 }
1674
1675
1676 /**
1677 * \brief Set DMA status
1678 * \param pUsbDma  USBHS device DMA instance
1679 * \Status Set DMA status
1680 */
1681 __STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma,
1682         uint32_t Status)
1683 {
1684     pUsbDma->USBHS_HSTDMASTATUS = Status;
1685 }
1686
1687
1688 /**
1689 * \brief Get Dma Status
1690 * \param pUsbDma  USBHS device DMA instance
1691 * \return Dma status
1692 */
1693 __STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma)
1694 {
1695     return (pUsbDma->USBHS_HSTDMASTATUS);
1696 }
1697
1698 /**@}*/
1699 #endif /* #ifndef USBHS_H */