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0001 /* ---------------------------------------------------------------------------- */
0002 /*                  Atmel Microcontroller Software Support                      */
0003 /*                       SAM Software Package License                           */
0004 /* ---------------------------------------------------------------------------- */
0005 /* Copyright (c) 2015, Atmel Corporation                                        */
0006 /*                                                                              */
0007 /* All rights reserved.                                                         */
0008 /*                                                                              */
0009 /* Redistribution and use in source and binary forms, with or without           */
0010 /* modification, are permitted provided that the following condition is met:    */
0011 /*                                                                              */
0012 /* - Redistributions of source code must retain the above copyright notice,     */
0013 /* this list of conditions and the disclaimer below.                            */
0014 /*                                                                              */
0015 /* Atmel's name may not be used to endorse or promote products derived from     */
0016 /* this software without specific prior written permission.                     */
0017 /*                                                                              */
0018 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
0019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
0020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
0021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
0022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
0023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
0024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
0025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
0026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
0027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
0028 /* ---------------------------------------------------------------------------- */
0029 
0030 /** \file */
0031 
0032 /** \addtogroup gmac_module
0033  * @{
0034  * Provides the interface to configure and use the GMAC peripheral.
0035  *
0036  * \section gmac_usage Usage
0037  * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls
0038  *   are also available, such as:
0039  *   - GMAC_SetSpeed(): Setup GMAC working clock.
0040  *   - GMAC_FullDuplexEnable(): Working in full duplex or not.
0041  *   - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF).
0042  *   - ...
0043  * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls
0044  *   can modify with:
0045  *   - GMAC_ReceiveEnable(): Enable/Disable Rx.
0046  *   - GMAC_TransmitEnable(): Enable/Disable Tx.
0047  *   - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving.
0048  *   - ...
0049  * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(),
0050  *   GMAC_GetItMask() and GMAC_GetItStatus().
0051  * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus()
0052  *   GMAC_ClearTxStatus() and GMAC_ClearRxStatus().
0053  * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(),
0054  *   GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define
0055  *   by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor.
0056  * - Manage PHY through GMAC is performed by
0057  *   - GMAC_ManagementEnable(): Enable/Disable PHY management.
0058  *   - GMAC_PHYMaintain(): Execute PHY management commands.
0059  *   - GMAC_PHYData(): Return PHY management data.
0060  *   - GMAC_IsIdle(): Check if PHY is idle.
0061  * - Setup GMAC parameters with following functions:
0062  *   - GMAC_SetHash(): Set Hash value.
0063  *   - GMAC_SetAddress(): Set MAC address.
0064  * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()
0065  * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable()
0066  *
0067  * For more accurate information, please look at the GMAC section of the
0068  * Datasheet.
0069  *
0070  * \sa \ref gmacd_module
0071  *
0072  * Related files:\n
0073  * gmac.c\n
0074  * gmac.h.\n
0075  *
0076  *   \defgroup gmac_defines GMAC Defines
0077  *   \defgroup gmac_structs GMAC Data Structs
0078  *   \defgroup gmac_functions GMAC Functions
0079  */
0080 /**@}*/
0081 
0082 #ifndef _GMAC_H
0083 #define _GMAC_H
0084 
0085 /*----------------------------------------------------------------------------
0086  *        Headers
0087  *----------------------------------------------------------------------------*/
0088 #include "chip.h"
0089 
0090 #include <stdint.h>
0091 
0092 #ifdef __cplusplus
0093 extern "C" {
0094 #endif
0095 
0096 /*----------------------------------------------------------------------------
0097  *        Defines
0098  *----------------------------------------------------------------------------*/
0099 /** \addtogroup gmac_defines
0100         @{*/
0101 
0102 #define NUM_GMAC_QUEUES 3
0103 /// Board GMAC base address
0104 
0105 #define GMAC_DUPLEX_HALF 0
0106 #define GMAC_DUPLEX_FULL 1
0107 
0108 //
0109 #define GMAC_SPEED_10M      0
0110 #define GMAC_SPEED_100M     1
0111 #define GMAC_SPEED_1000M    2
0112 
0113 /*------------------------------------------------------------------------------
0114                             Definitions
0115 ------------------------------------------------------------------------------
0116 */
0117 /// The buffer addresses written into the descriptors must be aligned so the
0118 /// last few bits are zero.  These bits have special meaning for the GMAC
0119 /// peripheral and cannot be used as part of the address.
0120 #define GMAC_ADDRESS_MASK   ((unsigned int)0xFFFFFFFC)
0121 #define GMAC_LENGTH_FRAME   ((unsigned int)0x3FFF)    /// Length of frame mask
0122 
0123 // receive buffer descriptor bits
0124 #define GMAC_RX_OWNERSHIP_BIT   (1u <<  0)
0125 #define GMAC_RX_WRAP_BIT        (1u <<  1)
0126 #define GMAC_RX_SOF_BIT         (1u << 14)
0127 #define GMAC_RX_EOF_BIT         (1u << 15)
0128 
0129 // Transmit buffer descriptor bits
0130 #define GMAC_TX_LAST_BUFFER_BIT (1u << 15)
0131 #define GMAC_TX_WRAP_BIT        (1u << 30)
0132 #define GMAC_TX_USED_BIT        (1u << 31)
0133 #define GMAC_TX_RLE_BIT         (1u << 29) /// Retry Limit Exceeded
0134 #define GMAC_TX_UND_BIT         (1u << 28) /// Tx Buffer Under-run
0135 #define GMAC_TX_ERR_BIT         (1u << 27) /// Exhausted in mid-frame
0136 #define GMAC_TX_ERR_BITS  \
0137     (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
0138 
0139 // Interrupt bits
0140 #define GMAC_INT_RX_BITS  \
0141     (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)
0142 #define GMAC_INT_TX_ERR_BITS  \
0143     (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP)
0144 #define GMAC_INT_TX_BITS  \
0145     (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)
0146 // Interrupt Status bits
0147 #define GMAC_INT_RX_STATUS_BITS  \
0148     (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR)
0149 #define GMAC_INT_TX_STATUS_ERR_BITS  \
0150     (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP)
0151 
0152 // Rx descriptor status flags
0153 #define   GMAC_RXDESC_ST_CKSUM_RESULT_NOT_CHECKED        (0)
0154 #define   GMAC_RXDESC_ST_CKSUM_RESULT_IP_CHECKED         (1)
0155 #define   GMAC_RXDESC_ST_CKSUM_RESULT_IP_AND_TCP_CHECKED (2)
0156 #define   GMAC_RXDESC_ST_CKSUM_RESULT_IP_AND_UDP_CHECKED (3)
0157 
0158 /*----------------------------------------------------------------------------
0159  *        Types
0160  *----------------------------------------------------------------------------*/
0161 /** \addtogroup gmac_structs
0162         @{*/
0163 
0164 /* This is the list of GMAC queue */
0165 typedef enum  {
0166     GMAC_QUE_0 = 0,
0167     GMAC_QUE_1 = 1,
0168     GMAC_QUE_2 = 2
0169 } gmacQueList_t;
0170 
0171 /** Receive buffer descriptor struct */
0172 typedef struct _GmacRxDescriptor {
0173     union _GmacRxAddr {
0174         uint32_t val;
0175         struct _GmacRxAddrBM {
0176             uint32_t bOwnership: 1,  /**< User clear, GMAC set this to one once
0177                                          it has successfully written a frame to
0178                                          memory */
0179                      bWrap: 1,      /**< Marks last descriptor in receive buffer */
0180                      addrDW: 30;    /**< Address in number of DW */
0181         } bm;
0182     } addr;                    /**< Address, Wrap & Ownership */
0183     union _GmacRxStatus {
0184         uint32_t val;
0185         struct _GmacRxStatusBM {
0186             uint32_t len: 12,               /** Length of frame including FCS */
0187                      offset: 2,              /** Receive buffer offset,
0188                                                 bits 13:12 of frame length for jumbo
0189                                                 frame */
0190                      bSof: 1,               /** Start of frame */
0191                      bEof: 1,               /** End of frame */
0192                      bCFI: 1,               /** Concatenation Format Indicator */
0193                      vlanPriority: 3,       /** VLAN priority (if VLAN detected) */
0194                      bPriorityDetected: 1,  /** Priority tag detected */
0195                      bVlanDetected: 1,      /**< VLAN tag detected */
0196                      typeIDMatchOrCksumResult: 2,
0197                      bTypeIDMatchFoundOrCksumSNAPState: 1,
0198                      specAddrMatchRegister: 2,
0199                      bSpecAddrMatchFound: 1,
0200                      reserved: 1,
0201                      bUniHashMatch: 1,      /**< Unicast hash match */
0202                      bMultiHashMatch: 1,    /**< Multicast hash match */
0203                      bBroadcastDetected: 1;  /**< Global all ones broadcast
0204                                                  address detected */
0205         } bm;
0206     } status;
0207 } sGmacRxDescriptor;    /* GCC */
0208 
0209 /** Transmit buffer descriptor struct */
0210 typedef struct _GmacTxDescriptor {
0211     uint32_t addr;
0212     union _GmacTxStatus {
0213         uint32_t val;
0214         struct _GmacTxStatusBM {
0215             uint32_t len: 11,       /**< Length of buffer */
0216                      reserved: 4,
0217                      bLastBuffer: 1, /**< Last buffer (in the current frame) */
0218                      bNoCRC: 1,     /**< No CRC */
0219                      reserved1: 10,
0220                      bExhausted: 1, /**< Buffer exhausted in mid frame */
0221                      bUnderrun: 1,  /**< Transmit under run */
0222                      bError: 1,     /**< Retry limit exceeded, error detected */
0223                      bWrap: 1,      /**< Marks last descriptor in TD list */
0224                      bUsed: 1;       /**< User clear, GMAC sets this once a frame
0225                                          has been successfully transmitted */
0226         } bm;
0227     } status;
0228 } sGmacTxDescriptor;     /* GCC */
0229 
0230 /**     @}*/
0231 
0232 //-----------------------------------------------------------------------------
0233 //         PHY Exported functions
0234 //-----------------------------------------------------------------------------
0235 extern uint8_t GMAC_IsIdle(Gmac *pGmac);
0236 extern void GMAC_PHYMaintain(Gmac      *pGmac,
0237                              uint8_t   bPhyAddr,
0238                              uint8_t   bRegAddr,
0239                              uint8_t   bRW,
0240                              uint16_t  wData);
0241 extern uint16_t GMAC_PHYData(Gmac *pGmac);
0242 extern void GMAC_ClearStatistics(Gmac *pGmac);
0243 extern void GMAC_IncreaseStatistics(Gmac *pGmac);
0244 extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);
0245 extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck);
0246 extern void GMAC_EnableMdio(Gmac *pGmac);
0247 extern void GMAC_DisableMdio(Gmac *pGmac);
0248 extern void GMAC_EnableMII(Gmac *pGmac);
0249 extern void GMAC_EnableRMII(Gmac *pGmac);
0250 extern void GMAC_EnableGMII(Gmac *pGmac);
0251 extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);
0252 extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources,
0253                           gmacQueList_t queueIdx);
0254 extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
0255 extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources,
0256                            gmacQueList_t queueIdx);
0257 extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
0258 extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx);
0259 extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx);
0260 extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);
0261 extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);
0262 extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);
0263 extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);
0264 extern void GMAC_ReceiveEnable(Gmac *pGmac, uint8_t bEnaDis);
0265 extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);
0266 extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);
0267 extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr,
0268                             gmacQueList_t queueIdx);
0269 extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
0270 extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr,
0271                             gmacQueList_t queueIdx);
0272 extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
0273 extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);
0274 extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);
0275 extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);
0276 extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT,
0277                               uint32_t dwMacB);
0278 extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);
0279 extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);
0280 extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg,
0281                               gmacQueList_t queueIdx);
0282 extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx);
0283 extern uint32_t GMAC_GetConfigure(Gmac *pGmac);
0284 extern void GMAC_TransmissionStart(Gmac *pGmac);
0285 extern void GMAC_TransmissionHalt(Gmac *pGmac);
0286 extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);
0287 
0288 void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx);
0289 
0290 void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx,
0291                             uint32_t regVal);
0292 
0293 void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx);
0294 
0295 void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx,
0296                              uint32_t regVal);
0297 
0298 void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx,
0299                            uint16_t etherType);
0300 
0301 void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg,
0302                           uint16_t c1Reg);
0303 
0304 void GMAC_EnableCbsQueA(Gmac *pGmac);
0305 
0306 void GMAC_DisableCbsQueA(Gmac *pGmac);
0307 
0308 void GMAC_EnableCbsQueB(Gmac *pGmac);
0309 
0310 void GMAC_DisableCbsQueB(Gmac *pGmac);
0311 
0312 void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA);
0313 
0314 void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB);
0315 
0316 void GMAC_SetTsuTmrIncReg(Gmac *pGmac, uint32_t nanoSec);
0317 
0318 uint16_t GMAC_GetPtpEvtMsgRxdMsbSec(Gmac *pGmac);
0319 
0320 uint32_t GMAC_GetPtpEvtMsgRxdLsbSec(Gmac *pGmac);
0321 
0322 uint32_t GMAC_GetPtpEvtMsgRxdNanoSec(Gmac *pGmac);
0323 
0324 void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31,
0325                         uint32_t nanosec);
0326 
0327 void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec);
0328 
0329 void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31);
0330 
0331 void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47);
0332 
0333 uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac);
0334 
0335 uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac);
0336 
0337 uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac);
0338 
0339 uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac);
0340 
0341 uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac);
0342 
0343 uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac);
0344 
0345 uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac);
0346 
0347 uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac);
0348 
0349 #ifdef __cplusplus
0350 }
0351 #endif
0352 
0353 #endif // #ifndef GMAC_H
0354
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