libchip/include/afec.h

0001 /* ---------------------------------------------------------------------------- */
0002 /*                  Atmel Microcontroller Software Support                      */
0003 /*                       SAM Software Package License                           */
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0005 /* Copyright (c) 2015, Atmel Corporation                                        */
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0029
0030 /**
0031  *  \file
0032  *
0033  *  \section Purpose
0034  *
0035  *  Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral.
0036  *
0037  *  \section Usage
0038  *
0039  *  -# Configurate the pins for AFEC.
0040  *  -# Initialize the AFEC with AFEC_Initialize().
0041  *  -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming().
0042  *  -# Select the active channel using AFEC_EnableChannel().
0043  *  -# Start the conversion with AFEC_StartConversion().
0044  *  -# Wait the end of the conversion by polling status with AFEC_GetStatus().
0045  *  -# Finally, get the converted data using AFEC_GetConvertedData() or
0046  * AFEC_GetLastConvertedData().
0047  *
0048 */
0049 #ifndef _AFEC_
0050 #define _AFEC_
0051
0052 /*----------------------------------------------------------------------------
0053  *        Headers
0054  *----------------------------------------------------------------------------*/
0055 #include <assert.h>
0056 #include <stdint.h>
0057
0058 /*------------------------------------------------------------------------------
0059  *         Definitions
0060  *------------------------------------------------------------------------------*/
0061
0062 /* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */
0063 #define AFEC_MR_SETTLING_Pos 20
0064 #define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos)
0065 /**< \brief (AFEC_MR) Trigger Selection */
0066 #define   AFEC_MR_SETTLING_AST3 (0x0u << 20)
0067 /**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */
0068 #define   AFEC_MR_SETTLING_AST5 (0x1u << 20)
0069 /**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */
0070 #define   AFEC_MR_SETTLING_AST9 (0x2u << 20)
0071 /**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/
0072 #define   AFEC_MR_SETTLING_AST17 (0x3u << 20)
0073 /**< \brief (AFEC_MR) ADC_SETTLING_AST17  17 periods of AFEClock*/
0074
0075 /***************************** Single Trigger Mode ****************************/
0076 #define AFEC_EMR_STM_Pos 25
0077 #define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos)
0078 /**< \brief (AFEC_EMR) Single Trigger Mode */
0079 #define   AFEC_EMR_STM_MULTI_TRIG (0x0u << 25)
0080 /**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to
0081     get an averaged result. */
0082 #define   AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25)
0083 /**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required
0084     to get an averaged value. */
0085
0086 /***************************** TAG of the AFEC_LDCR Register ******************/
0087 #define AFEC_EMR_TAG_Pos 24
0088 #define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos)
0089 /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */
0090 #define   AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24)
0091 /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero
0092 in AFEC_LDCR. */
0093 #define   AFEC_EMR_TAG_APPENDS (0x1u << 24)
0094 /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel
0095 number to the conversion result in AFEC_LDCR register. */
0096
0097 /***************************** Compare All Channels ******************/
0098 #define AFEC_EMR_CMPALL_Pos 9
0099 #define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos)
0100 /**< \brief (AFEC_EMR) Compare All Channels */
0101 #define   AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9)
0102 /**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in
0103 CMPSEL field is compared. */
0104 #define   AFEC_EMR_CMPALL_ALL_CHANNELS_COMP  (0x1u << 9)
0105 /**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */
0106
0107 #define AFEC_ACR_PGA0_ON     (0x1u << 2)
0108 #define AFEC_ACR_PGA1_ON     (0x1u << 3)
0109
0110 #ifdef __cplusplus
0111 extern "C" {
0112 #endif
0113
0114 /*------------------------------------------------------------------------------
0115  *         Macros function of register access
0116  *------------------------------------------------------------------------------*/
0117
0118 #define AFEC_GetModeReg(pAFEC)                ((pAFEC)->AFEC_MR)
0119 #define AFEC_SetModeReg(pAFEC, mode)          ((pAFEC)->AFEC_MR = mode)
0120
0121 #define AFEC_GetExtModeReg(pAFEC)             ((pAFEC)->AFEC_EMR)
0122 #define AFEC_SetExtModeReg(pAFEC, mode)       ((pAFEC)->AFEC_EMR = mode)
0123
0124 #define AFEC_StartConversion(pAFEC)           ((pAFEC)->AFEC_CR = AFEC_CR_START)
0125
0126 #define AFEC_EnableChannel(pAFEC, dwChannel)    {\
0127         (pAFEC)->AFEC_CHER = (1 << (dwChannel));\
0128     }
0129
0130 #define AFEC_DisableChannel(pAFEC, dwChannel)  {\
0131         (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\
0132     }
0133
0134 #define AFEC_EnableIt(pAFEC, dwMode)            {\
0135         (pAFEC)->AFEC_IER = (dwMode);\
0136     }
0137
0138 #define AFEC_DisableIt(pAFEC, dwMode)           {\
0139         (pAFEC)->AFEC_IDR = (dwMode);\
0140     }
0141
0142 #define AFEC_SetChannelGain(pAFEC,dwMode)       {\
0143         (pAFEC)->AFEC_CGR = dwMode;\
0144     }
0145
0146 #define AFEC_EnableDataReadyIt(pAFEC)         ((pAFEC)->AFEC_IER = AFEC_IER_DRDY)
0147
0148 #define AFEC_GetStatus(pAFEC)                 ((pAFEC)->AFEC_ISR)
0149
0150 #define AFEC_GetCompareMode(pAFEC)            (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk))
0151
0152 #define AFEC_GetChannelStatus(pAFEC)          ((pAFEC)->AFEC_CHSR)
0153
0154 #define AFEC_GetInterruptMaskStatus(pAFEC)    ((pAFEC)->AFEC_IMR)
0155
0156 #define AFEC_GetLastConvertedData(pAFEC)      ((pAFEC)->AFEC_LCDR)
0157
0158 /*------------------------------------------------------------------------------
0159  *         Exported functions
0160  *------------------------------------------------------------------------------*/
0161 extern void AFEC_Initialize(Afec *pAFEC, uint32_t dwId);
0162 extern uint32_t AFEC_SetClock(Afec *pAFEC, uint32_t dwPres, uint32_t dwMck);
0163 extern void AFEC_SetTiming(Afec *pAFEC, uint32_t dwStartup,
0164                             uint32_t dwTracking,
0165                             uint32_t dwSettling);
0166 extern void AFEC_SetTrigger(Afec *pAFEC, uint32_t dwTrgSel);
0167 extern void AFEC_SetAnalogChange(Afec *pAFE, uint8_t bEnDis);
0168 extern void AFEC_SetSleepMode(Afec *pAFEC, uint8_t bEnDis);
0169 extern void AFEC_SetFastWakeup(Afec *pAFEC, uint8_t bEnDis);
0170 extern void AFEC_SetSequenceMode(Afec *pAFEC, uint8_t bEnDis);
0171 extern void AFEC_SetSequence(Afec *pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2);
0172 extern void AFEC_SetSequenceByList(Afec *pAFEC, uint8_t ucChList[],
0173                                     uint8_t ucNumCh);
0174 extern void AFEC_SetTagEnable(Afec *pAFEC, uint8_t bEnDis);
0175 extern void AFEC_SetCompareChannel(Afec *pAFEC, uint32_t dwChannel);
0176 extern void AFEC_SetCompareMode(Afec *pAFEC, uint32_t dwMode);
0177 extern void AFEC_SetComparisonWindow(Afec *pAFEC, uint32_t dwHi_Lo);
0178 extern uint8_t AFEC_CheckConfiguration(Afec *pAFEC, uint32_t dwMcK);
0179 extern uint32_t AFEC_GetConvertedData(Afec *pAFEC, uint32_t dwChannel);
0180 extern void AFEC_SetStartupTime(Afec *pAFEC, uint32_t dwUs);
0181 extern void AFEC_SetTrackingTime(Afec *pAFEC, uint32_t dwNs);
0182 extern void AFEC_SetAnalogOffset(Afec *pAFE, uint32_t dwChannel,
0183                                   uint32_t aoffset);
0184 extern void AFEC_SetAnalogControl(Afec *pAFE, uint32_t control);
0185 #ifdef __cplusplus
0186 }
0187 #endif
0188
0189 #endif /* #ifndef _AFEC_ */
0190