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File indexing completed on 2025-05-11 08:22:44
0001 /* ---------------------------------------------------------------------------- */ 0002 /* Atmel Microcontroller Software Support */ 0003 /* SAM Software Package License */ 0004 /* ---------------------------------------------------------------------------- */ 0005 /* Copyright (c) 2015, Atmel Corporation */ 0006 /* */ 0007 /* All rights reserved. */ 0008 /* */ 0009 /* Redistribution and use in source and binary forms, with or without */ 0010 /* modification, are permitted provided that the following condition is met: */ 0011 /* */ 0012 /* - Redistributions of source code must retain the above copyright notice, */ 0013 /* this list of conditions and the disclaimer below. */ 0014 /* */ 0015 /* Atmel's name may not be used to endorse or promote products derived from */ 0016 /* this software without specific prior written permission. */ 0017 /* */ 0018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 0019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 0020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 0021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 0022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 0023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 0024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 0025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 0026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 0027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 0028 /* ---------------------------------------------------------------------------- */ 0029 0030 #ifndef _GMII_DEFINE_H 0031 #define _GMII_DEFINE_H 0032 0033 0034 /*--------------------------------------------------------------------------- 0035 * Definitions 0036 *---------------------------------------------------------------------------*/ 0037 0038 //IEEE defined Registers 0039 #define GMII_BMCR 0x0 // Basic Mode Control Register 0040 #define GMII_BMSR 0x1 // Basic Mode Status Register 0041 #define GMII_PHYID1R 0x2 // PHY Identifier Register 1 0042 #define GMII_PHYID2R 0x3 // PHY Identifier Register 2 0043 #define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register 0044 #define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register 0045 #define GMII_ANER 0x6 // Auto-negotiation Expansion Register 0046 #define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register 0047 #define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register 0048 #define GMII_AFEC0R 0x11 // AFE Control 0 Register 0049 #define GMII_AFEC3R 0x14 // AFE Control 3 Register 0050 #define GMII_RXERCR 0x15 // RXER Counter Register 0051 #define GMII_OMSSR 0x17 // Operation Mode Strap Status Register 0052 #define GMII_ECR 0x18 // Expanded Control Register 0053 #define GMII_ICSR 0x1B // Interrupt Control/Status Register 0054 #define GMII_FC 0x1C // Function Control 0055 #define GMII_LCSR 0x1D // LinkMD(R) Control/Status Register 0056 #define GMII_PC1R 0x1E // PHY Control 1 Register 0057 #define GMII_PC2R 0x1F // PHY Control 2 Register 0058 0059 // PHY ID Identifier Register 0060 #define GMII_LSB_MASK 0x0U 0061 // definitions: MII_PHYID1 0062 #define GMII_OUI_MSB 0x0022 0063 // definitions: MII_PHYID2 0064 #define GMII_OUI_LSB 0x1572 // KSZ8061 PHY Id2 0065 0066 // Basic Mode Control Register (BMCR) 0067 // Bit definitions: MII_BMCR 0068 #define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation 0069 #define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation 0070 #define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps 0071 #define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable 0072 #define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation 0073 #define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation 0074 #define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation 0075 #define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation 0076 // Reserved 7 // Read as 0, ignore on write 0077 #define GMII_SPEED_SELECT_MSB (1 << 6) // 0078 // Reserved 5 to 0 // Read as 0, ignore on write 0079 0080 0081 // Basic Mode Status Register (BMSR) 0082 // Bit definitions: MII_BMSR 0083 #define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable 0084 #define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable 0085 #define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable 0086 #define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable 0087 #define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable 0088 // Reserved 10 to 9 // Read as 0, ignore on write 0089 #define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15 0090 // Reserved 7 0091 #define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression 0092 #define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete 0093 #define GMII_REMOTE_FAULT (1 << 4) // Remote Fault 0094 #define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability 0095 #define GMII_LINK_STATUS (1 << 2) // Link Status 0096 #define GMII_JABBER_DETECT (1 << 1) // Jabber Detect 0097 #define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability 0098 0099 // Auto-negotiation Advertisement Register (ANAR) 0100 // Auto-negotiation Link Partner Ability Register (ANLPAR) 0101 // Bit definitions: MII_ANAR, MII_ANLPAR 0102 #define GMII_NP (1 << 15) // Next page Indication 0103 // Reserved 7 0104 #define GMII_RF (1 << 13) // Remote Fault 0105 // Reserved 12 // Write as 0, ignore on read 0106 #define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) 0107 // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) 0108 #define GMII_T4 (1 << 9) // 100BASE-T4 Support 0109 #define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support 0110 #define GMII_TX_HDX (1 << 7) // 100BASE-TX Support 0111 #define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support 0112 #define GMII_10_HDX (1 << 5) // 10BASE-T Support 0113 // Selector 4 to 0 // Protocol Selection Bits 0114 #define GMII_AN_IEEE_802_3 0x00001 0115 0116 #endif // #ifndef _MII_DEFINE_H
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