altera-cyclone-v/start/bspstarthooks.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMCycV
0007  */
0008
0009 /*
0010  * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
0035
0036 #include <bsp.h>
0037 #include <bsp/start.h>
0038 #include <bsp/arm-cp15-start.h>
0039 #include <bsp/arm-a9mpcore-start.h>
0040 #include <bsp/linker-symbols.h>
0041 #include <bsp/alt_address_space.h>
0042 #include <bsp/socal/socal.h>
0043 #include <bsp/socal/alt_sdr.h>
0044 #include <bsp/socal/hps.h>
0045
0046 /* 1 MB reset default value for address filtering start */
0047 #define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
0048
0049 BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
0050 {
0051   arm_a9mpcore_start_hook_0();
0052 }
0053
0054 BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
0055 {
0056   uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
0057     ARM_CP15_CTRL_A | ARM_CP15_CTRL_M,
0058     ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
0059   );
0060
0061   arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
0062     ctrl,
0063     (uint32_t *) bsp_translation_table_base,
0064     ARM_MMU_DEFAULT_CLIENT_DOMAIN,
0065     &arm_cp15_start_mmu_config_table[0],
0066     arm_cp15_start_mmu_config_table_size
0067   );
0068 }
0069
0070 BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
0071 {
0072   uint32_t addr_filt_start;
0073   uint32_t addr_filt_end;
0074
0075   /* Disable ECC. Preloader respectively UBoot enable ECC.
0076      But they do run without interrupts. Our BSP will enable interrupts
0077      and get spurious ECC error interrupts. Thus we disasable ECC
0078      until we either know about a better handling or Altera has modified
0079      it's SDRAM settings to not create possibly false ECC errors */
0080   uint32_t ctlcfg = alt_read_word( ALT_SDR_CTL_CTLCFG_ADDR );
0081   ctlcfg &= ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK;
0082   alt_write_word( ALT_SDR_CTL_CTLCFG_ADDR, ctlcfg );
0083
0084   /* Perform L3 remap register programming first by setting the desired new MPU
0085      address space 0 mapping. Assume BOOTROM in order to be able to boot the
0086      second core. */
0087   alt_addr_space_remap(
0088     ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,
0089     ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM,
0090     ALT_ADDR_SPACE_H2F_ACCESSIBLE,
0091     ALT_ADDR_SPACE_LWH2F_ACCESSIBLE );
0092
0093   /* Next, adjust the L2 cache address filtering range. Set the start address
0094    * to the default reset value and retain the existing end address
0095    * configuration. */
0096   alt_l2_addr_filter_cfg_get( &addr_filt_start, &addr_filt_end );
0097
0098   if ( addr_filt_start != BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET ) {
0099     alt_l2_addr_filter_cfg_set( BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET,
0100                                 addr_filt_end );
0101   }
0102
0103   arm_a9mpcore_start_hook_1();
0104   bsp_start_copy_sections();
0105   setup_mmu_and_cache();
0106 #ifndef RTEMS_SMP
0107   /* Enable unified L2 cache */
0108   rtems_cache_enable_data();
0109 #endif
0110   bsp_start_clear_bss();
0111 }