altera-cyclone-v/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMCycV
0007  */
0008
0009 /*
0010  * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #include <bsp/bootcard.h>
0035 #include <bsp/fdt.h>
0036 #include <bsp/irq-generic.h>
0037 #include <bsp/linker-symbols.h>
0038
0039 #include <bsp/alt_clock_manager.h>
0040
0041 #include <libfdt.h>
0042
0043 #ifdef BSP_FDT_IS_SUPPORTED
0044 uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
0045 {
0046   return intr[1] + 32;
0047 }
0048
0049 static void set_clock(
0050   const void *fdt,
0051   int parent,
0052   ALT_CLK_t clk,
0053   const char *name
0054 )
0055 {
0056   int node;
0057   int len;
0058   const uint32_t *val;
0059
0060   node = fdt_subnode_offset(fdt, parent, name);
0061   val = fdt_getprop(fdt, node, "clock-frequency", &len);
0062
0063   if (val != NULL && len >= 4) {
0064     alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
0065   }
0066 }
0067
0068 static void set_clock_by_output_name(
0069   const void *fdt,
0070   ALT_CLK_t clk,
0071   const char *clock_output_name
0072 )
0073 {
0074   int node;
0075   int len;
0076   const uint32_t *val;
0077
0078   node = fdt_node_offset_by_prop_value(
0079     fdt,
0080     -1,
0081     "clock-output-names",
0082     clock_output_name,
0083     strlen(clock_output_name) + 1
0084   );
0085   val = fdt_getprop(fdt, node, "clock-frequency", &len);
0086
0087   if (val != NULL && len >= 4) {
0088     alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
0089   }
0090 }
0091
0092 static void update_clocks(void)
0093 {
0094   const void *fdt;
0095   int parent;
0096
0097   fdt = bsp_fdt_get();
0098
0099   /* Try to set by node name */
0100   parent = fdt_node_offset_by_compatible(fdt, -1, "altr,clk-mgr");
0101   parent = fdt_subnode_offset(fdt, parent, "clocks");
0102   set_clock(fdt, parent, ALT_CLK_OSC1, "osc1");
0103   set_clock(fdt, parent, ALT_CLK_IN_PIN_OSC2, "osc2");
0104   set_clock(fdt, parent, ALT_CLK_F2H_PERIPH_REF, "f2s_periph_ref_clk");
0105   set_clock(fdt, parent, ALT_CLK_F2H_SDRAM_REF, "f2s_sdram_ref_clk");
0106
0107   /* Try to set by "clock-output-names" property value */
0108   set_clock_by_output_name(fdt, ALT_CLK_OSC1, "hps_0_eosc1-clk");
0109   set_clock_by_output_name(fdt, ALT_CLK_IN_PIN_OSC2, "hps_0_eosc2-clk");
0110   set_clock_by_output_name(fdt, ALT_CLK_F2H_PERIPH_REF, "hps_0_f2s_periph_ref_clk-clk");
0111   set_clock_by_output_name(fdt, ALT_CLK_F2H_SDRAM_REF, "hps_0_f2s_sdram_ref_clk-clk");
0112 }
0113 #endif
0114
0115 #ifdef ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
0116 uint32_t altera_cyclone_v_a9mpcore_periphclk;
0117 #endif
0118
0119 void bsp_start(void)
0120 {
0121 #ifdef BSP_FDT_IS_SUPPORTED
0122   update_clocks();
0123 #endif
0124 #ifdef ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
0125   alt_clk_freq_get(ALT_CLK_MPU_PERIPH, &altera_cyclone_v_a9mpcore_periphclk);
0126 #endif
0127   bsp_interrupt_initialize();
0128   rtems_cache_coherent_add_area(
0129     bsp_section_nocacheheap_begin,
0130     (uintptr_t) bsp_section_nocacheheap_size
0131   );
0132 }